1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8795 switch driver 4 * 5 * Copyright (C) 2017 Microchip Technology Inc. 6 * Tristram Ha <Tristram.Ha@microchip.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/gpio.h> 13 #include <linux/if_vlan.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_data/microchip-ksz.h> 17 #include <linux/phy.h> 18 #include <linux/etherdevice.h> 19 #include <linux/if_bridge.h> 20 #include <linux/micrel_phy.h> 21 #include <net/dsa.h> 22 #include <net/switchdev.h> 23 #include <linux/phylink.h> 24 25 #include "ksz_common.h" 26 #include "ksz8795_reg.h" 27 #include "ksz8.h" 28 29 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 30 { 31 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 32 } 33 34 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 35 bool set) 36 { 37 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 38 bits, set ? bits : 0); 39 } 40 41 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data) 42 { 43 const u16 *regs; 44 u16 ctrl_addr; 45 int ret = 0; 46 47 regs = dev->info->regs; 48 49 mutex_lock(&dev->alu_mutex); 50 51 ctrl_addr = IND_ACC_TABLE(table) | addr; 52 ret = ksz_write8(dev, regs[REG_IND_BYTE], data); 53 if (!ret) 54 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 55 56 mutex_unlock(&dev->alu_mutex); 57 58 return ret; 59 } 60 61 int ksz8_reset_switch(struct ksz_device *dev) 62 { 63 if (ksz_is_ksz88x3(dev)) { 64 /* reset switch */ 65 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 66 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 67 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 68 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 69 } else { 70 /* reset switch */ 71 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 72 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 73 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 74 } 75 76 return 0; 77 } 78 79 static int ksz8863_change_mtu(struct ksz_device *dev, int frame_size) 80 { 81 u8 ctrl2 = 0; 82 83 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE) 84 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE; 85 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 86 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE; 87 88 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE | 89 KSZ8863_HUGE_PACKET_ENABLE, ctrl2); 90 } 91 92 static int ksz8795_change_mtu(struct ksz_device *dev, int frame_size) 93 { 94 u8 ctrl1 = 0, ctrl2 = 0; 95 int ret; 96 97 if (frame_size > KSZ8_LEGAL_PACKET_SIZE) 98 ctrl2 |= SW_LEGAL_PACKET_DISABLE; 99 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 100 ctrl1 |= SW_HUGE_PACKET; 101 102 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1); 103 if (ret) 104 return ret; 105 106 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2); 107 } 108 109 int ksz8_change_mtu(struct ksz_device *dev, int port, int mtu) 110 { 111 u16 frame_size; 112 113 if (!dsa_is_cpu_port(dev->ds, port)) 114 return 0; 115 116 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 117 118 switch (dev->chip_id) { 119 case KSZ8795_CHIP_ID: 120 case KSZ8794_CHIP_ID: 121 case KSZ8765_CHIP_ID: 122 return ksz8795_change_mtu(dev, frame_size); 123 case KSZ8830_CHIP_ID: 124 return ksz8863_change_mtu(dev, frame_size); 125 } 126 127 return -EOPNOTSUPP; 128 } 129 130 static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue) 131 { 132 u8 hi, lo; 133 134 /* Number of queues can only be 1, 2, or 4. */ 135 switch (queue) { 136 case 4: 137 case 3: 138 queue = PORT_QUEUE_SPLIT_4; 139 break; 140 case 2: 141 queue = PORT_QUEUE_SPLIT_2; 142 break; 143 default: 144 queue = PORT_QUEUE_SPLIT_1; 145 } 146 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo); 147 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi); 148 lo &= ~PORT_QUEUE_SPLIT_L; 149 if (queue & PORT_QUEUE_SPLIT_2) 150 lo |= PORT_QUEUE_SPLIT_L; 151 hi &= ~PORT_QUEUE_SPLIT_H; 152 if (queue & PORT_QUEUE_SPLIT_4) 153 hi |= PORT_QUEUE_SPLIT_H; 154 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo); 155 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi); 156 157 /* Default is port based for egress rate limit. */ 158 if (queue != PORT_QUEUE_SPLIT_1) 159 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED, 160 true); 161 } 162 163 void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 164 { 165 const u32 *masks; 166 const u16 *regs; 167 u16 ctrl_addr; 168 u32 data; 169 u8 check; 170 int loop; 171 172 masks = dev->info->masks; 173 regs = dev->info->regs; 174 175 ctrl_addr = addr + dev->info->reg_mib_cnt * port; 176 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 177 178 mutex_lock(&dev->alu_mutex); 179 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 180 181 /* It is almost guaranteed to always read the valid bit because of 182 * slow SPI speed. 183 */ 184 for (loop = 2; loop > 0; loop--) { 185 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 186 187 if (check & masks[MIB_COUNTER_VALID]) { 188 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 189 if (check & masks[MIB_COUNTER_OVERFLOW]) 190 *cnt += MIB_COUNTER_VALUE + 1; 191 *cnt += data & MIB_COUNTER_VALUE; 192 break; 193 } 194 } 195 mutex_unlock(&dev->alu_mutex); 196 } 197 198 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 199 u64 *dropped, u64 *cnt) 200 { 201 const u32 *masks; 202 const u16 *regs; 203 u16 ctrl_addr; 204 u32 data; 205 u8 check; 206 int loop; 207 208 masks = dev->info->masks; 209 regs = dev->info->regs; 210 211 addr -= dev->info->reg_mib_cnt; 212 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 213 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 214 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 215 216 mutex_lock(&dev->alu_mutex); 217 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 218 219 /* It is almost guaranteed to always read the valid bit because of 220 * slow SPI speed. 221 */ 222 for (loop = 2; loop > 0; loop--) { 223 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 224 225 if (check & masks[MIB_COUNTER_VALID]) { 226 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 227 if (addr < 2) { 228 u64 total; 229 230 total = check & MIB_TOTAL_BYTES_H; 231 total <<= 32; 232 *cnt += total; 233 *cnt += data; 234 if (check & masks[MIB_COUNTER_OVERFLOW]) { 235 total = MIB_TOTAL_BYTES_H + 1; 236 total <<= 32; 237 *cnt += total; 238 } 239 } else { 240 if (check & masks[MIB_COUNTER_OVERFLOW]) 241 *cnt += MIB_PACKET_DROPPED + 1; 242 *cnt += data & MIB_PACKET_DROPPED; 243 } 244 break; 245 } 246 } 247 mutex_unlock(&dev->alu_mutex); 248 } 249 250 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 251 u64 *dropped, u64 *cnt) 252 { 253 u32 *last = (u32 *)dropped; 254 const u16 *regs; 255 u16 ctrl_addr; 256 u32 data; 257 u32 cur; 258 259 regs = dev->info->regs; 260 261 addr -= dev->info->reg_mib_cnt; 262 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 263 KSZ8863_MIB_PACKET_DROPPED_RX_0; 264 ctrl_addr += port; 265 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 266 267 mutex_lock(&dev->alu_mutex); 268 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 269 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 270 mutex_unlock(&dev->alu_mutex); 271 272 data &= MIB_PACKET_DROPPED; 273 cur = last[addr]; 274 if (data != cur) { 275 last[addr] = data; 276 if (data < cur) 277 data += MIB_PACKET_DROPPED + 1; 278 data -= cur; 279 *cnt += data; 280 } 281 } 282 283 void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 284 u64 *dropped, u64 *cnt) 285 { 286 if (ksz_is_ksz88x3(dev)) 287 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 288 else 289 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 290 } 291 292 void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 293 { 294 if (ksz_is_ksz88x3(dev)) 295 return; 296 297 /* enable the port for flush/freeze function */ 298 if (freeze) 299 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 300 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 301 302 /* disable the port after freeze is done */ 303 if (!freeze) 304 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 305 } 306 307 void ksz8_port_init_cnt(struct ksz_device *dev, int port) 308 { 309 struct ksz_port_mib *mib = &dev->ports[port].mib; 310 u64 *dropped; 311 312 if (!ksz_is_ksz88x3(dev)) { 313 /* flush all enabled port MIB counters */ 314 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 315 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 316 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 317 } 318 319 mib->cnt_ptr = 0; 320 321 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 322 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 323 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 324 &mib->counters[mib->cnt_ptr]); 325 ++mib->cnt_ptr; 326 } 327 328 /* last one in storage */ 329 dropped = &mib->counters[dev->info->mib_cnt]; 330 331 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 332 while (mib->cnt_ptr < dev->info->mib_cnt) { 333 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 334 dropped, &mib->counters[mib->cnt_ptr]); 335 ++mib->cnt_ptr; 336 } 337 } 338 339 static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 340 { 341 const u16 *regs; 342 u16 ctrl_addr; 343 344 regs = dev->info->regs; 345 346 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 347 348 mutex_lock(&dev->alu_mutex); 349 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 350 ksz_read64(dev, regs[REG_IND_DATA_HI], data); 351 mutex_unlock(&dev->alu_mutex); 352 } 353 354 static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 355 { 356 const u16 *regs; 357 u16 ctrl_addr; 358 359 regs = dev->info->regs; 360 361 ctrl_addr = IND_ACC_TABLE(table) | addr; 362 363 mutex_lock(&dev->alu_mutex); 364 ksz_write64(dev, regs[REG_IND_DATA_HI], data); 365 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 366 mutex_unlock(&dev->alu_mutex); 367 } 368 369 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 370 { 371 int timeout = 100; 372 const u32 *masks; 373 const u16 *regs; 374 375 masks = dev->info->masks; 376 regs = dev->info->regs; 377 378 do { 379 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 380 timeout--; 381 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 382 383 /* Entry is not ready for accessing. */ 384 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) { 385 return -EAGAIN; 386 /* Entry is ready for accessing. */ 387 } else { 388 ksz_read8(dev, regs[REG_IND_DATA_8], data); 389 390 /* There is no valid entry in the table. */ 391 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) 392 return -ENXIO; 393 } 394 return 0; 395 } 396 397 int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr, 398 u8 *fid, u8 *src_port, u8 *timestamp, u16 *entries) 399 { 400 u32 data_hi, data_lo; 401 const u8 *shifts; 402 const u32 *masks; 403 const u16 *regs; 404 u16 ctrl_addr; 405 u8 data; 406 int rc; 407 408 shifts = dev->info->shifts; 409 masks = dev->info->masks; 410 regs = dev->info->regs; 411 412 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 413 414 mutex_lock(&dev->alu_mutex); 415 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 416 417 rc = ksz8_valid_dyn_entry(dev, &data); 418 if (rc == -EAGAIN) { 419 if (addr == 0) 420 *entries = 0; 421 } else if (rc == -ENXIO) { 422 *entries = 0; 423 /* At least one valid entry in the table. */ 424 } else { 425 u64 buf = 0; 426 int cnt; 427 428 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 429 data_hi = (u32)(buf >> 32); 430 data_lo = (u32)buf; 431 432 /* Check out how many valid entry in the table. */ 433 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 434 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 435 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 436 shifts[DYNAMIC_MAC_ENTRIES]; 437 *entries = cnt + 1; 438 439 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 440 shifts[DYNAMIC_MAC_FID]; 441 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 442 shifts[DYNAMIC_MAC_SRC_PORT]; 443 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >> 444 shifts[DYNAMIC_MAC_TIMESTAMP]; 445 446 mac_addr[5] = (u8)data_lo; 447 mac_addr[4] = (u8)(data_lo >> 8); 448 mac_addr[3] = (u8)(data_lo >> 16); 449 mac_addr[2] = (u8)(data_lo >> 24); 450 451 mac_addr[1] = (u8)data_hi; 452 mac_addr[0] = (u8)(data_hi >> 8); 453 rc = 0; 454 } 455 mutex_unlock(&dev->alu_mutex); 456 457 return rc; 458 } 459 460 int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 461 struct alu_struct *alu) 462 { 463 u32 data_hi, data_lo; 464 const u8 *shifts; 465 const u32 *masks; 466 u64 data; 467 468 shifts = dev->info->shifts; 469 masks = dev->info->masks; 470 471 ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 472 data_hi = data >> 32; 473 data_lo = (u32)data; 474 if (data_hi & (masks[STATIC_MAC_TABLE_VALID] | 475 masks[STATIC_MAC_TABLE_OVERRIDE])) { 476 alu->mac[5] = (u8)data_lo; 477 alu->mac[4] = (u8)(data_lo >> 8); 478 alu->mac[3] = (u8)(data_lo >> 16); 479 alu->mac[2] = (u8)(data_lo >> 24); 480 alu->mac[1] = (u8)data_hi; 481 alu->mac[0] = (u8)(data_hi >> 8); 482 alu->port_forward = 483 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 484 shifts[STATIC_MAC_FWD_PORTS]; 485 alu->is_override = 486 (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 487 data_hi >>= 1; 488 alu->is_static = true; 489 alu->is_use_fid = 490 (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 491 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 492 shifts[STATIC_MAC_FID]; 493 return 0; 494 } 495 return -ENXIO; 496 } 497 498 void ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 499 struct alu_struct *alu) 500 { 501 u32 data_hi, data_lo; 502 const u8 *shifts; 503 const u32 *masks; 504 u64 data; 505 506 shifts = dev->info->shifts; 507 masks = dev->info->masks; 508 509 data_lo = ((u32)alu->mac[2] << 24) | 510 ((u32)alu->mac[3] << 16) | 511 ((u32)alu->mac[4] << 8) | alu->mac[5]; 512 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 513 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 514 515 if (alu->is_override) 516 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 517 if (alu->is_use_fid) { 518 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 519 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 520 } 521 if (alu->is_static) 522 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 523 else 524 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 525 526 data = (u64)data_hi << 32 | data_lo; 527 ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 528 } 529 530 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 531 u8 *member, u8 *valid) 532 { 533 const u8 *shifts; 534 const u32 *masks; 535 536 shifts = dev->info->shifts; 537 masks = dev->info->masks; 538 539 *fid = vlan & masks[VLAN_TABLE_FID]; 540 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 541 shifts[VLAN_TABLE_MEMBERSHIP_S]; 542 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 543 } 544 545 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 546 u16 *vlan) 547 { 548 const u8 *shifts; 549 const u32 *masks; 550 551 shifts = dev->info->shifts; 552 masks = dev->info->masks; 553 554 *vlan = fid; 555 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 556 if (valid) 557 *vlan |= masks[VLAN_TABLE_VALID]; 558 } 559 560 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 561 { 562 const u8 *shifts; 563 u64 data; 564 int i; 565 566 shifts = dev->info->shifts; 567 568 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 569 addr *= 4; 570 for (i = 0; i < 4; i++) { 571 dev->vlan_cache[addr + i].table[0] = (u16)data; 572 data >>= shifts[VLAN_TABLE]; 573 } 574 } 575 576 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 577 { 578 int index; 579 u16 *data; 580 u16 addr; 581 u64 buf; 582 583 data = (u16 *)&buf; 584 addr = vid / 4; 585 index = vid & 3; 586 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 587 *vlan = data[index]; 588 } 589 590 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 591 { 592 int index; 593 u16 *data; 594 u16 addr; 595 u64 buf; 596 597 data = (u16 *)&buf; 598 addr = vid / 4; 599 index = vid & 3; 600 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 601 data[index] = vlan; 602 dev->vlan_cache[vid].table[0] = vlan; 603 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 604 } 605 606 int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 607 { 608 u8 restart, speed, ctrl, link; 609 int processed = true; 610 const u16 *regs; 611 u8 val1, val2; 612 u16 data = 0; 613 u8 p = phy; 614 int ret; 615 616 regs = dev->info->regs; 617 618 switch (reg) { 619 case MII_BMCR: 620 ret = ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 621 if (ret) 622 return ret; 623 624 ret = ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 625 if (ret) 626 return ret; 627 628 ret = ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 629 if (ret) 630 return ret; 631 632 if (restart & PORT_PHY_LOOPBACK) 633 data |= BMCR_LOOPBACK; 634 if (ctrl & PORT_FORCE_100_MBIT) 635 data |= BMCR_SPEED100; 636 if (ksz_is_ksz88x3(dev)) { 637 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 638 data |= BMCR_ANENABLE; 639 } else { 640 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 641 data |= BMCR_ANENABLE; 642 } 643 if (restart & PORT_POWER_DOWN) 644 data |= BMCR_PDOWN; 645 if (restart & PORT_AUTO_NEG_RESTART) 646 data |= BMCR_ANRESTART; 647 if (ctrl & PORT_FORCE_FULL_DUPLEX) 648 data |= BMCR_FULLDPLX; 649 if (speed & PORT_HP_MDIX) 650 data |= KSZ886X_BMCR_HP_MDIX; 651 if (restart & PORT_FORCE_MDIX) 652 data |= KSZ886X_BMCR_FORCE_MDI; 653 if (restart & PORT_AUTO_MDIX_DISABLE) 654 data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX; 655 if (restart & PORT_TX_DISABLE) 656 data |= KSZ886X_BMCR_DISABLE_TRANSMIT; 657 if (restart & PORT_LED_OFF) 658 data |= KSZ886X_BMCR_DISABLE_LED; 659 break; 660 case MII_BMSR: 661 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 662 if (ret) 663 return ret; 664 665 data = BMSR_100FULL | 666 BMSR_100HALF | 667 BMSR_10FULL | 668 BMSR_10HALF | 669 BMSR_ANEGCAPABLE; 670 if (link & PORT_AUTO_NEG_COMPLETE) 671 data |= BMSR_ANEGCOMPLETE; 672 if (link & PORT_STAT_LINK_GOOD) 673 data |= BMSR_LSTATUS; 674 break; 675 case MII_PHYSID1: 676 data = KSZ8795_ID_HI; 677 break; 678 case MII_PHYSID2: 679 if (ksz_is_ksz88x3(dev)) 680 data = KSZ8863_ID_LO; 681 else 682 data = KSZ8795_ID_LO; 683 break; 684 case MII_ADVERTISE: 685 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 686 if (ret) 687 return ret; 688 689 data = ADVERTISE_CSMA; 690 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 691 data |= ADVERTISE_PAUSE_CAP; 692 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 693 data |= ADVERTISE_100FULL; 694 if (ctrl & PORT_AUTO_NEG_100BTX) 695 data |= ADVERTISE_100HALF; 696 if (ctrl & PORT_AUTO_NEG_10BT_FD) 697 data |= ADVERTISE_10FULL; 698 if (ctrl & PORT_AUTO_NEG_10BT) 699 data |= ADVERTISE_10HALF; 700 break; 701 case MII_LPA: 702 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 703 if (ret) 704 return ret; 705 706 data = LPA_SLCT; 707 if (link & PORT_REMOTE_SYM_PAUSE) 708 data |= LPA_PAUSE_CAP; 709 if (link & PORT_REMOTE_100BTX_FD) 710 data |= LPA_100FULL; 711 if (link & PORT_REMOTE_100BTX) 712 data |= LPA_100HALF; 713 if (link & PORT_REMOTE_10BT_FD) 714 data |= LPA_10FULL; 715 if (link & PORT_REMOTE_10BT) 716 data |= LPA_10HALF; 717 if (data & ~LPA_SLCT) 718 data |= LPA_LPACK; 719 break; 720 case PHY_REG_LINK_MD: 721 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1); 722 if (ret) 723 return ret; 724 725 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2); 726 if (ret) 727 return ret; 728 729 if (val1 & PORT_START_CABLE_DIAG) 730 data |= PHY_START_CABLE_DIAG; 731 732 if (val1 & PORT_CABLE_10M_SHORT) 733 data |= PHY_CABLE_10M_SHORT; 734 735 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M, 736 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1)); 737 738 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M, 739 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) | 740 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2)); 741 break; 742 case PHY_REG_PHY_CTRL: 743 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 744 if (ret) 745 return ret; 746 747 if (link & PORT_MDIX_STATUS) 748 data |= KSZ886X_CTRL_MDIX_STAT; 749 break; 750 default: 751 processed = false; 752 break; 753 } 754 if (processed) 755 *val = data; 756 757 return 0; 758 } 759 760 int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 761 { 762 u8 restart, speed, ctrl, data; 763 const u16 *regs; 764 u8 p = phy; 765 int ret; 766 767 regs = dev->info->regs; 768 769 switch (reg) { 770 case MII_BMCR: 771 772 /* Do not support PHY reset function. */ 773 if (val & BMCR_RESET) 774 break; 775 ret = ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 776 if (ret) 777 return ret; 778 779 data = speed; 780 if (val & KSZ886X_BMCR_HP_MDIX) 781 data |= PORT_HP_MDIX; 782 else 783 data &= ~PORT_HP_MDIX; 784 785 if (data != speed) { 786 ret = ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data); 787 if (ret) 788 return ret; 789 } 790 791 ret = ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 792 if (ret) 793 return ret; 794 795 data = ctrl; 796 if (ksz_is_ksz88x3(dev)) { 797 if ((val & BMCR_ANENABLE)) 798 data |= PORT_AUTO_NEG_ENABLE; 799 else 800 data &= ~PORT_AUTO_NEG_ENABLE; 801 } else { 802 if (!(val & BMCR_ANENABLE)) 803 data |= PORT_AUTO_NEG_DISABLE; 804 else 805 data &= ~PORT_AUTO_NEG_DISABLE; 806 807 /* Fiber port does not support auto-negotiation. */ 808 if (dev->ports[p].fiber) 809 data |= PORT_AUTO_NEG_DISABLE; 810 } 811 812 if (val & BMCR_SPEED100) 813 data |= PORT_FORCE_100_MBIT; 814 else 815 data &= ~PORT_FORCE_100_MBIT; 816 if (val & BMCR_FULLDPLX) 817 data |= PORT_FORCE_FULL_DUPLEX; 818 else 819 data &= ~PORT_FORCE_FULL_DUPLEX; 820 821 if (data != ctrl) { 822 ret = ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data); 823 if (ret) 824 return ret; 825 } 826 827 ret = ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 828 if (ret) 829 return ret; 830 831 data = restart; 832 if (val & KSZ886X_BMCR_DISABLE_LED) 833 data |= PORT_LED_OFF; 834 else 835 data &= ~PORT_LED_OFF; 836 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT) 837 data |= PORT_TX_DISABLE; 838 else 839 data &= ~PORT_TX_DISABLE; 840 if (val & BMCR_ANRESTART) 841 data |= PORT_AUTO_NEG_RESTART; 842 else 843 data &= ~(PORT_AUTO_NEG_RESTART); 844 if (val & BMCR_PDOWN) 845 data |= PORT_POWER_DOWN; 846 else 847 data &= ~PORT_POWER_DOWN; 848 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX) 849 data |= PORT_AUTO_MDIX_DISABLE; 850 else 851 data &= ~PORT_AUTO_MDIX_DISABLE; 852 if (val & KSZ886X_BMCR_FORCE_MDI) 853 data |= PORT_FORCE_MDIX; 854 else 855 data &= ~PORT_FORCE_MDIX; 856 if (val & BMCR_LOOPBACK) 857 data |= PORT_PHY_LOOPBACK; 858 else 859 data &= ~PORT_PHY_LOOPBACK; 860 861 if (data != restart) { 862 ret = ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL], 863 data); 864 if (ret) 865 return ret; 866 } 867 break; 868 case MII_ADVERTISE: 869 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 870 if (ret) 871 return ret; 872 873 data = ctrl; 874 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 875 PORT_AUTO_NEG_100BTX_FD | 876 PORT_AUTO_NEG_100BTX | 877 PORT_AUTO_NEG_10BT_FD | 878 PORT_AUTO_NEG_10BT); 879 if (val & ADVERTISE_PAUSE_CAP) 880 data |= PORT_AUTO_NEG_SYM_PAUSE; 881 if (val & ADVERTISE_100FULL) 882 data |= PORT_AUTO_NEG_100BTX_FD; 883 if (val & ADVERTISE_100HALF) 884 data |= PORT_AUTO_NEG_100BTX; 885 if (val & ADVERTISE_10FULL) 886 data |= PORT_AUTO_NEG_10BT_FD; 887 if (val & ADVERTISE_10HALF) 888 data |= PORT_AUTO_NEG_10BT; 889 890 if (data != ctrl) { 891 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 892 if (ret) 893 return ret; 894 } 895 break; 896 case PHY_REG_LINK_MD: 897 if (val & PHY_START_CABLE_DIAG) 898 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true); 899 break; 900 default: 901 break; 902 } 903 904 return 0; 905 } 906 907 void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 908 { 909 u8 data; 910 911 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 912 data &= ~PORT_VLAN_MEMBERSHIP; 913 data |= (member & dev->port_mask); 914 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data); 915 } 916 917 void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port) 918 { 919 u8 learn[DSA_MAX_PORTS]; 920 int first, index, cnt; 921 struct ksz_port *p; 922 const u16 *regs; 923 924 regs = dev->info->regs; 925 926 if ((uint)port < dev->info->port_cnt) { 927 first = port; 928 cnt = port + 1; 929 } else { 930 /* Flush all ports. */ 931 first = 0; 932 cnt = dev->info->port_cnt; 933 } 934 for (index = first; index < cnt; index++) { 935 p = &dev->ports[index]; 936 if (!p->on) 937 continue; 938 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]); 939 if (!(learn[index] & PORT_LEARN_DISABLE)) 940 ksz_pwrite8(dev, index, regs[P_STP_CTRL], 941 learn[index] | PORT_LEARN_DISABLE); 942 } 943 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 944 for (index = first; index < cnt; index++) { 945 p = &dev->ports[index]; 946 if (!p->on) 947 continue; 948 if (!(learn[index] & PORT_LEARN_DISABLE)) 949 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]); 950 } 951 } 952 953 int ksz8_fdb_dump(struct ksz_device *dev, int port, 954 dsa_fdb_dump_cb_t *cb, void *data) 955 { 956 int ret = 0; 957 u16 i = 0; 958 u16 entries = 0; 959 u8 timestamp = 0; 960 u8 fid; 961 u8 member; 962 struct alu_struct alu; 963 964 do { 965 alu.is_static = false; 966 ret = ksz8_r_dyn_mac_table(dev, i, alu.mac, &fid, &member, 967 ×tamp, &entries); 968 if (!ret && (member & BIT(port))) { 969 ret = cb(alu.mac, alu.fid, alu.is_static, data); 970 if (ret) 971 break; 972 } 973 i++; 974 } while (i < entries); 975 if (i >= entries) 976 ret = 0; 977 978 return ret; 979 } 980 981 int ksz8_mdb_add(struct ksz_device *dev, int port, 982 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 983 { 984 struct alu_struct alu; 985 int index; 986 int empty = 0; 987 988 alu.port_forward = 0; 989 for (index = 0; index < dev->info->num_statics; index++) { 990 if (!ksz8_r_sta_mac_table(dev, index, &alu)) { 991 /* Found one already in static MAC table. */ 992 if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) && 993 alu.fid == mdb->vid) 994 break; 995 /* Remember the first empty entry. */ 996 } else if (!empty) { 997 empty = index + 1; 998 } 999 } 1000 1001 /* no available entry */ 1002 if (index == dev->info->num_statics && !empty) 1003 return -ENOSPC; 1004 1005 /* add entry */ 1006 if (index == dev->info->num_statics) { 1007 index = empty - 1; 1008 memset(&alu, 0, sizeof(alu)); 1009 memcpy(alu.mac, mdb->addr, ETH_ALEN); 1010 alu.is_static = true; 1011 } 1012 alu.port_forward |= BIT(port); 1013 if (mdb->vid) { 1014 alu.is_use_fid = true; 1015 1016 /* Need a way to map VID to FID. */ 1017 alu.fid = mdb->vid; 1018 } 1019 ksz8_w_sta_mac_table(dev, index, &alu); 1020 1021 return 0; 1022 } 1023 1024 int ksz8_mdb_del(struct ksz_device *dev, int port, 1025 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 1026 { 1027 struct alu_struct alu; 1028 int index; 1029 1030 for (index = 0; index < dev->info->num_statics; index++) { 1031 if (!ksz8_r_sta_mac_table(dev, index, &alu)) { 1032 /* Found one already in static MAC table. */ 1033 if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) && 1034 alu.fid == mdb->vid) 1035 break; 1036 } 1037 } 1038 1039 /* no available entry */ 1040 if (index == dev->info->num_statics) 1041 goto exit; 1042 1043 /* clear port */ 1044 alu.port_forward &= ~BIT(port); 1045 if (!alu.port_forward) 1046 alu.is_static = false; 1047 ksz8_w_sta_mac_table(dev, index, &alu); 1048 1049 exit: 1050 return 0; 1051 } 1052 1053 int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag, 1054 struct netlink_ext_ack *extack) 1055 { 1056 if (ksz_is_ksz88x3(dev)) 1057 return -ENOTSUPP; 1058 1059 /* Discard packets with VID not enabled on the switch */ 1060 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 1061 1062 /* Discard packets with VID not enabled on the ingress port */ 1063 for (port = 0; port < dev->phy_port_cnt; ++port) 1064 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER, 1065 flag); 1066 1067 return 0; 1068 } 1069 1070 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state) 1071 { 1072 if (ksz_is_ksz88x3(dev)) { 1073 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID, 1074 0x03 << (4 - 2 * port), state); 1075 } else { 1076 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); 1077 } 1078 } 1079 1080 int ksz8_port_vlan_add(struct ksz_device *dev, int port, 1081 const struct switchdev_obj_port_vlan *vlan, 1082 struct netlink_ext_ack *extack) 1083 { 1084 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1085 struct ksz_port *p = &dev->ports[port]; 1086 u16 data, new_pvid = 0; 1087 u8 fid, member, valid; 1088 1089 if (ksz_is_ksz88x3(dev)) 1090 return -ENOTSUPP; 1091 1092 /* If a VLAN is added with untagged flag different from the 1093 * port's Remove Tag flag, we need to change the latter. 1094 * Ignore VID 0, which is always untagged. 1095 * Ignore CPU port, which will always be tagged. 1096 */ 1097 if (untagged != p->remove_tag && vlan->vid != 0 && 1098 port != dev->cpu_port) { 1099 unsigned int vid; 1100 1101 /* Reject attempts to add a VLAN that requires the 1102 * Remove Tag flag to be changed, unless there are no 1103 * other VLANs currently configured. 1104 */ 1105 for (vid = 1; vid < dev->info->num_vlans; ++vid) { 1106 /* Skip the VID we are going to add or reconfigure */ 1107 if (vid == vlan->vid) 1108 continue; 1109 1110 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0], 1111 &fid, &member, &valid); 1112 if (valid && (member & BIT(port))) 1113 return -EINVAL; 1114 } 1115 1116 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1117 p->remove_tag = untagged; 1118 } 1119 1120 ksz8_r_vlan_table(dev, vlan->vid, &data); 1121 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1122 1123 /* First time to setup the VLAN entry. */ 1124 if (!valid) { 1125 /* Need to find a way to map VID to FID. */ 1126 fid = 1; 1127 valid = 1; 1128 } 1129 member |= BIT(port); 1130 1131 ksz8_to_vlan(dev, fid, member, valid, &data); 1132 ksz8_w_vlan_table(dev, vlan->vid, data); 1133 1134 /* change PVID */ 1135 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1136 new_pvid = vlan->vid; 1137 1138 if (new_pvid) { 1139 u16 vid; 1140 1141 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1142 vid &= ~VLAN_VID_MASK; 1143 vid |= new_pvid; 1144 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1145 1146 ksz8_port_enable_pvid(dev, port, true); 1147 } 1148 1149 return 0; 1150 } 1151 1152 int ksz8_port_vlan_del(struct ksz_device *dev, int port, 1153 const struct switchdev_obj_port_vlan *vlan) 1154 { 1155 u16 data, pvid; 1156 u8 fid, member, valid; 1157 1158 if (ksz_is_ksz88x3(dev)) 1159 return -ENOTSUPP; 1160 1161 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1162 pvid = pvid & 0xFFF; 1163 1164 ksz8_r_vlan_table(dev, vlan->vid, &data); 1165 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1166 1167 member &= ~BIT(port); 1168 1169 /* Invalidate the entry if no more member. */ 1170 if (!member) { 1171 fid = 0; 1172 valid = 0; 1173 } 1174 1175 ksz8_to_vlan(dev, fid, member, valid, &data); 1176 ksz8_w_vlan_table(dev, vlan->vid, data); 1177 1178 if (pvid == vlan->vid) 1179 ksz8_port_enable_pvid(dev, port, false); 1180 1181 return 0; 1182 } 1183 1184 int ksz8_port_mirror_add(struct ksz_device *dev, int port, 1185 struct dsa_mall_mirror_tc_entry *mirror, 1186 bool ingress, struct netlink_ext_ack *extack) 1187 { 1188 if (ingress) { 1189 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1190 dev->mirror_rx |= BIT(port); 1191 } else { 1192 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1193 dev->mirror_tx |= BIT(port); 1194 } 1195 1196 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 1197 1198 /* configure mirror port */ 1199 if (dev->mirror_rx || dev->mirror_tx) 1200 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1201 PORT_MIRROR_SNIFFER, true); 1202 1203 return 0; 1204 } 1205 1206 void ksz8_port_mirror_del(struct ksz_device *dev, int port, 1207 struct dsa_mall_mirror_tc_entry *mirror) 1208 { 1209 u8 data; 1210 1211 if (mirror->ingress) { 1212 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1213 dev->mirror_rx &= ~BIT(port); 1214 } else { 1215 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1216 dev->mirror_tx &= ~BIT(port); 1217 } 1218 1219 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1220 1221 if (!dev->mirror_rx && !dev->mirror_tx) 1222 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1223 PORT_MIRROR_SNIFFER, false); 1224 } 1225 1226 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 1227 { 1228 struct ksz_port *p = &dev->ports[port]; 1229 1230 if (!p->interface && dev->compat_interface) { 1231 dev_warn(dev->dev, 1232 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1233 "Please update your device tree.\n", 1234 port); 1235 p->interface = dev->compat_interface; 1236 } 1237 } 1238 1239 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1240 { 1241 struct dsa_switch *ds = dev->ds; 1242 const u32 *masks; 1243 u8 member; 1244 1245 masks = dev->info->masks; 1246 1247 /* enable broadcast storm limit */ 1248 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1249 1250 if (!ksz_is_ksz88x3(dev)) 1251 ksz8795_set_prio_queue(dev, port, 4); 1252 1253 /* disable DiffServ priority */ 1254 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false); 1255 1256 /* replace priority */ 1257 ksz_port_cfg(dev, port, P_802_1P_CTRL, 1258 masks[PORT_802_1P_REMAPPING], false); 1259 1260 /* enable 802.1p priority */ 1261 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true); 1262 1263 if (cpu_port) { 1264 if (!ksz_is_ksz88x3(dev)) 1265 ksz8795_cpu_interface_select(dev, port); 1266 1267 member = dsa_user_ports(ds); 1268 } else { 1269 member = BIT(dsa_upstream_port(ds, port)); 1270 } 1271 1272 ksz8_cfg_port_member(dev, port, member); 1273 } 1274 1275 void ksz8_config_cpu_port(struct dsa_switch *ds) 1276 { 1277 struct ksz_device *dev = ds->priv; 1278 struct ksz_port *p; 1279 const u32 *masks; 1280 const u16 *regs; 1281 u8 remote; 1282 int i; 1283 1284 masks = dev->info->masks; 1285 regs = dev->info->regs; 1286 1287 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 1288 1289 p = &dev->ports[dev->cpu_port]; 1290 p->on = 1; 1291 1292 ksz8_port_setup(dev, dev->cpu_port, true); 1293 1294 for (i = 0; i < dev->phy_port_cnt; i++) { 1295 p = &dev->ports[i]; 1296 1297 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1298 1299 /* Last port may be disabled. */ 1300 if (i == dev->phy_port_cnt) 1301 break; 1302 p->on = 1; 1303 } 1304 for (i = 0; i < dev->phy_port_cnt; i++) { 1305 p = &dev->ports[i]; 1306 if (!p->on) 1307 continue; 1308 if (!ksz_is_ksz88x3(dev)) { 1309 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 1310 if (remote & KSZ8_PORT_FIBER_MODE) 1311 p->fiber = 1; 1312 } 1313 if (p->fiber) 1314 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1315 PORT_FORCE_FLOW_CTRL, true); 1316 else 1317 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1318 PORT_FORCE_FLOW_CTRL, false); 1319 } 1320 } 1321 1322 static int ksz8_handle_global_errata(struct dsa_switch *ds) 1323 { 1324 struct ksz_device *dev = ds->priv; 1325 int ret = 0; 1326 1327 /* KSZ87xx Errata DS80000687C. 1328 * Module 2: Link drops with some EEE link partners. 1329 * An issue with the EEE next page exchange between the 1330 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in 1331 * the link dropping. 1332 */ 1333 if (dev->info->ksz87xx_eee_link_erratum) 1334 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0); 1335 1336 return ret; 1337 } 1338 1339 int ksz8_enable_stp_addr(struct ksz_device *dev) 1340 { 1341 struct alu_struct alu; 1342 1343 /* Setup STP address for STP operation. */ 1344 memset(&alu, 0, sizeof(alu)); 1345 ether_addr_copy(alu.mac, eth_stp_addr); 1346 alu.is_static = true; 1347 alu.is_override = true; 1348 alu.port_forward = dev->info->cpu_ports; 1349 1350 ksz8_w_sta_mac_table(dev, 0, &alu); 1351 1352 return 0; 1353 } 1354 1355 int ksz8_setup(struct dsa_switch *ds) 1356 { 1357 struct ksz_device *dev = ds->priv; 1358 int i; 1359 1360 ds->mtu_enforcement_ingress = true; 1361 1362 /* We rely on software untagging on the CPU port, so that we 1363 * can support both tagged and untagged VLANs 1364 */ 1365 ds->untag_bridge_pvid = true; 1366 1367 /* VLAN filtering is partly controlled by the global VLAN 1368 * Enable flag 1369 */ 1370 ds->vlan_filtering_is_global = true; 1371 1372 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true); 1373 1374 /* Enable automatic fast aging when link changed detected. */ 1375 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 1376 1377 /* Enable aggressive back off algorithm in half duplex mode. */ 1378 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1, 1379 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 1380 1381 /* 1382 * Make sure unicast VLAN boundary is set as default and 1383 * enable no excessive collision drop. 1384 */ 1385 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2, 1386 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 1387 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 1388 1389 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 1390 1391 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1392 1393 if (!ksz_is_ksz88x3(dev)) 1394 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); 1395 1396 for (i = 0; i < (dev->info->num_vlans / 4); i++) 1397 ksz8_r_vlan_entries(dev, i); 1398 1399 return ksz8_handle_global_errata(ds); 1400 } 1401 1402 void ksz8_get_caps(struct ksz_device *dev, int port, 1403 struct phylink_config *config) 1404 { 1405 config->mac_capabilities = MAC_10 | MAC_100; 1406 1407 /* Silicon Errata Sheet (DS80000830A): 1408 * "Port 1 does not respond to received flow control PAUSE frames" 1409 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3 1410 * switches. 1411 */ 1412 if (!ksz_is_ksz88x3(dev) || port) 1413 config->mac_capabilities |= MAC_SYM_PAUSE; 1414 1415 /* Asym pause is not supported on KSZ8863 and KSZ8873 */ 1416 if (!ksz_is_ksz88x3(dev)) 1417 config->mac_capabilities |= MAC_ASYM_PAUSE; 1418 } 1419 1420 u32 ksz8_get_port_addr(int port, int offset) 1421 { 1422 return PORT_CTRL_ADDR(port, offset); 1423 } 1424 1425 int ksz8_switch_init(struct ksz_device *dev) 1426 { 1427 dev->cpu_port = fls(dev->info->cpu_ports) - 1; 1428 dev->phy_port_cnt = dev->info->port_cnt - 1; 1429 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports; 1430 1431 return 0; 1432 } 1433 1434 void ksz8_switch_exit(struct ksz_device *dev) 1435 { 1436 ksz8_reset_switch(dev); 1437 } 1438 1439 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 1440 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 1441 MODULE_LICENSE("GPL"); 1442