1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * The VLAN and bridge model the GSWIP hardware uses does not directly 10 * matches the model DSA uses. 11 * 12 * The hardware has 64 possible table entries for bridges with one VLAN 13 * ID, one flow id and a list of ports for each bridge. All entries which 14 * match the same flow ID are combined in the mac learning table, they 15 * act as one global bridge. 16 * The hardware does not support VLAN filter on the port, but on the 17 * bridge, this driver converts the DSA model to the hardware. 18 * 19 * The CPU gets all the exception frames which do not match any forwarding 20 * rule and the CPU port is also added to all bridges. This makes it possible 21 * to handle all the special cases easily in software. 22 * At the initialization the driver allocates one bridge table entry for 23 * each switch port which is used when the port is used without an 24 * explicit bridge. This prevents the frames from being forwarded 25 * between all LAN ports by default. 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 #include <linux/etherdevice.h> 31 #include <linux/firmware.h> 32 #include <linux/if_bridge.h> 33 #include <linux/if_vlan.h> 34 #include <linux/iopoll.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/module.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/of_platform.h> 40 #include <linux/phy.h> 41 #include <linux/phylink.h> 42 #include <linux/platform_device.h> 43 #include <linux/regmap.h> 44 #include <linux/reset.h> 45 #include <net/dsa.h> 46 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 47 48 #include "lantiq_pce.h" 49 50 /* GSWIP MDIO Registers */ 51 #define GSWIP_MDIO_GLOB 0x00 52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 53 #define GSWIP_MDIO_CTRL 0x08 54 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 55 #define GSWIP_MDIO_CTRL_RD BIT(11) 56 #define GSWIP_MDIO_CTRL_WR BIT(10) 57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 60 #define GSWIP_MDIO_READ 0x09 61 #define GSWIP_MDIO_WRITE 0x0A 62 #define GSWIP_MDIO_MDC_CFG0 0x0B 63 #define GSWIP_MDIO_MDC_CFG1 0x0C 64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 88 GSWIP_MDIO_PHY_FCONRX_MASK | \ 89 GSWIP_MDIO_PHY_FCONTX_MASK | \ 90 GSWIP_MDIO_PHY_LINK_MASK | \ 91 GSWIP_MDIO_PHY_SPEED_MASK | \ 92 GSWIP_MDIO_PHY_FDUP_MASK) 93 94 /* GSWIP MII Registers */ 95 #define GSWIP_MII_CFGp(p) (0x2 * (p)) 96 #define GSWIP_MII_CFG_EN BIT(14) 97 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 98 #define GSWIP_MII_CFG_MODE_MIIP 0x0 99 #define GSWIP_MII_CFG_MODE_MIIM 0x1 100 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 101 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 102 #define GSWIP_MII_CFG_MODE_RGMII 0x4 103 #define GSWIP_MII_CFG_MODE_MASK 0xf 104 #define GSWIP_MII_CFG_RATE_M2P5 0x00 105 #define GSWIP_MII_CFG_RATE_M25 0x10 106 #define GSWIP_MII_CFG_RATE_M125 0x20 107 #define GSWIP_MII_CFG_RATE_M50 0x30 108 #define GSWIP_MII_CFG_RATE_AUTO 0x40 109 #define GSWIP_MII_CFG_RATE_MASK 0x70 110 #define GSWIP_MII_PCDU0 0x01 111 #define GSWIP_MII_PCDU1 0x03 112 #define GSWIP_MII_PCDU5 0x05 113 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 114 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 115 116 /* GSWIP Core Registers */ 117 #define GSWIP_SWRES 0x000 118 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 119 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 120 #define GSWIP_VERSION 0x013 121 #define GSWIP_VERSION_REV_SHIFT 0 122 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 123 #define GSWIP_VERSION_MOD_SHIFT 8 124 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 125 #define GSWIP_VERSION_2_0 0x100 126 #define GSWIP_VERSION_2_1 0x021 127 #define GSWIP_VERSION_2_2 0x122 128 #define GSWIP_VERSION_2_2_ETC 0x022 129 130 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 131 #define GSWIP_BM_RAM_ADDR 0x044 132 #define GSWIP_BM_RAM_CTRL 0x045 133 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 134 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 135 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 136 #define GSWIP_BM_QUEUE_GCTRL 0x04A 137 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 138 /* buffer management Port Configuration Register */ 139 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 140 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 141 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 142 /* buffer management Port Control Register */ 143 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 144 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 145 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 146 147 /* PCE */ 148 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 149 #define GSWIP_PCE_TBL_MASK 0x448 150 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 151 #define GSWIP_PCE_TBL_ADDR 0x44E 152 #define GSWIP_PCE_TBL_CTRL 0x44F 153 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 154 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 155 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 156 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 157 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 158 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 159 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 160 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 161 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 162 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 163 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 164 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 165 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 166 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 167 #define GSWIP_PCE_GCTRL_0 0x456 168 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ 169 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 170 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 171 #define GSWIP_PCE_GCTRL_1 0x457 172 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 173 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 174 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 175 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ 176 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ 177 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ 178 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 179 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 180 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 181 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 182 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 183 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 184 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) 185 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ 186 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ 187 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ 188 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ 189 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ 190 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) 191 192 #define GSWIP_MAC_FLEN 0x8C5 193 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 194 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 195 196 /* Ethernet Switch Fetch DMA Port Control Register */ 197 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 198 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 199 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 200 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 201 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 202 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 203 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 204 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 205 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 206 207 /* Ethernet Switch Store DMA Port Control Register */ 208 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 209 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 210 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 211 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */ 212 213 #define GSWIP_TABLE_ACTIVE_VLAN 0x01 214 #define GSWIP_TABLE_VLAN_MAPPING 0x02 215 #define GSWIP_TABLE_MAC_BRIDGE 0x0b 216 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ 217 218 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 219 220 struct gswip_hw_info { 221 int max_ports; 222 int cpu_port; 223 }; 224 225 struct xway_gphy_match_data { 226 char *fe_firmware_name; 227 char *ge_firmware_name; 228 }; 229 230 struct gswip_gphy_fw { 231 struct clk *clk_gate; 232 struct reset_control *reset; 233 u32 fw_addr_offset; 234 char *fw_name; 235 }; 236 237 struct gswip_vlan { 238 struct net_device *bridge; 239 u16 vid; 240 u8 fid; 241 }; 242 243 struct gswip_priv { 244 __iomem void *gswip; 245 __iomem void *mdio; 246 __iomem void *mii; 247 const struct gswip_hw_info *hw_info; 248 const struct xway_gphy_match_data *gphy_fw_name_cfg; 249 struct dsa_switch *ds; 250 struct device *dev; 251 struct regmap *rcu_regmap; 252 struct gswip_vlan vlans[64]; 253 int num_gphy_fw; 254 struct gswip_gphy_fw *gphy_fw; 255 u32 port_vlan_filter; 256 }; 257 258 struct gswip_pce_table_entry { 259 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index 260 u16 table; // PCE_TBL_CTRL.ADDR = pData->table 261 u16 key[8]; 262 u16 val[5]; 263 u16 mask; 264 u8 gmap; 265 bool type; 266 bool valid; 267 bool key_mode; 268 }; 269 270 struct gswip_rmon_cnt_desc { 271 unsigned int size; 272 unsigned int offset; 273 const char *name; 274 }; 275 276 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 277 278 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 279 /** Receive Packet Count (only packets that are accepted and not discarded). */ 280 MIB_DESC(1, 0x1F, "RxGoodPkts"), 281 MIB_DESC(1, 0x23, "RxUnicastPkts"), 282 MIB_DESC(1, 0x22, "RxMulticastPkts"), 283 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 284 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 285 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 286 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 287 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 288 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 289 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 290 MIB_DESC(1, 0x12, "Rx64BytePkts"), 291 MIB_DESC(1, 0x13, "Rx127BytePkts"), 292 MIB_DESC(1, 0x14, "Rx255BytePkts"), 293 MIB_DESC(1, 0x15, "Rx511BytePkts"), 294 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 295 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 296 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 297 MIB_DESC(1, 0x18, "RxDroppedPkts"), 298 MIB_DESC(1, 0x19, "RxFilteredPkts"), 299 MIB_DESC(2, 0x24, "RxGoodBytes"), 300 MIB_DESC(2, 0x26, "RxBadBytes"), 301 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 302 MIB_DESC(1, 0x0C, "TxGoodPkts"), 303 MIB_DESC(1, 0x06, "TxUnicastPkts"), 304 MIB_DESC(1, 0x07, "TxMulticastPkts"), 305 MIB_DESC(1, 0x00, "Tx64BytePkts"), 306 MIB_DESC(1, 0x01, "Tx127BytePkts"), 307 MIB_DESC(1, 0x02, "Tx255BytePkts"), 308 MIB_DESC(1, 0x03, "Tx511BytePkts"), 309 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 310 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 311 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 312 MIB_DESC(1, 0x08, "TxSingleCollCount"), 313 MIB_DESC(1, 0x09, "TxMultCollCount"), 314 MIB_DESC(1, 0x0A, "TxLateCollCount"), 315 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 316 MIB_DESC(1, 0x0D, "TxPauseCount"), 317 MIB_DESC(1, 0x10, "TxDroppedPkts"), 318 MIB_DESC(2, 0x0E, "TxGoodBytes"), 319 }; 320 321 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 322 { 323 return __raw_readl(priv->gswip + (offset * 4)); 324 } 325 326 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 327 { 328 __raw_writel(val, priv->gswip + (offset * 4)); 329 } 330 331 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 332 u32 offset) 333 { 334 u32 val = gswip_switch_r(priv, offset); 335 336 val &= ~(clear); 337 val |= set; 338 gswip_switch_w(priv, val, offset); 339 } 340 341 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 342 u32 cleared) 343 { 344 u32 val; 345 346 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 347 (val & cleared) == 0, 20, 50000); 348 } 349 350 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 351 { 352 return __raw_readl(priv->mdio + (offset * 4)); 353 } 354 355 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 356 { 357 __raw_writel(val, priv->mdio + (offset * 4)); 358 } 359 360 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 361 u32 offset) 362 { 363 u32 val = gswip_mdio_r(priv, offset); 364 365 val &= ~(clear); 366 val |= set; 367 gswip_mdio_w(priv, val, offset); 368 } 369 370 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 371 { 372 return __raw_readl(priv->mii + (offset * 4)); 373 } 374 375 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 376 { 377 __raw_writel(val, priv->mii + (offset * 4)); 378 } 379 380 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 381 u32 offset) 382 { 383 u32 val = gswip_mii_r(priv, offset); 384 385 val &= ~(clear); 386 val |= set; 387 gswip_mii_w(priv, val, offset); 388 } 389 390 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 391 int port) 392 { 393 /* There's no MII_CFG register for the CPU port */ 394 if (!dsa_is_cpu_port(priv->ds, port)) 395 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); 396 } 397 398 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 399 int port) 400 { 401 switch (port) { 402 case 0: 403 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 404 break; 405 case 1: 406 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 407 break; 408 case 5: 409 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 410 break; 411 } 412 } 413 414 static int gswip_mdio_poll(struct gswip_priv *priv) 415 { 416 int cnt = 100; 417 418 while (likely(cnt--)) { 419 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 420 421 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 422 return 0; 423 usleep_range(20, 40); 424 } 425 426 return -ETIMEDOUT; 427 } 428 429 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 430 { 431 struct gswip_priv *priv = bus->priv; 432 int err; 433 434 err = gswip_mdio_poll(priv); 435 if (err) { 436 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 437 return err; 438 } 439 440 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 441 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 442 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 443 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 444 GSWIP_MDIO_CTRL); 445 446 return 0; 447 } 448 449 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 450 { 451 struct gswip_priv *priv = bus->priv; 452 int err; 453 454 err = gswip_mdio_poll(priv); 455 if (err) { 456 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 457 return err; 458 } 459 460 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 461 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 462 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 463 GSWIP_MDIO_CTRL); 464 465 err = gswip_mdio_poll(priv); 466 if (err) { 467 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 468 return err; 469 } 470 471 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 472 } 473 474 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np) 475 { 476 struct dsa_switch *ds = priv->ds; 477 478 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev); 479 if (!ds->slave_mii_bus) 480 return -ENOMEM; 481 482 ds->slave_mii_bus->priv = priv; 483 ds->slave_mii_bus->read = gswip_mdio_rd; 484 ds->slave_mii_bus->write = gswip_mdio_wr; 485 ds->slave_mii_bus->name = "lantiq,xrx200-mdio"; 486 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", 487 dev_name(priv->dev)); 488 ds->slave_mii_bus->parent = priv->dev; 489 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask; 490 491 return of_mdiobus_register(ds->slave_mii_bus, mdio_np); 492 } 493 494 static int gswip_pce_table_entry_read(struct gswip_priv *priv, 495 struct gswip_pce_table_entry *tbl) 496 { 497 int i; 498 int err; 499 u16 crtl; 500 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 501 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 502 503 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 504 GSWIP_PCE_TBL_CTRL_BAS); 505 if (err) 506 return err; 507 508 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 509 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 510 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 511 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 512 GSWIP_PCE_TBL_CTRL); 513 514 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 515 GSWIP_PCE_TBL_CTRL_BAS); 516 if (err) 517 return err; 518 519 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 520 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 521 522 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 523 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 524 525 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 526 527 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 528 529 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 530 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 531 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 532 533 return 0; 534 } 535 536 static int gswip_pce_table_entry_write(struct gswip_priv *priv, 537 struct gswip_pce_table_entry *tbl) 538 { 539 int i; 540 int err; 541 u16 crtl; 542 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 543 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 544 545 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 546 GSWIP_PCE_TBL_CTRL_BAS); 547 if (err) 548 return err; 549 550 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 551 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 552 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 553 tbl->table | addr_mode, 554 GSWIP_PCE_TBL_CTRL); 555 556 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 557 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 558 559 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 560 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 561 562 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 563 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 564 tbl->table | addr_mode, 565 GSWIP_PCE_TBL_CTRL); 566 567 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 568 569 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 570 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 571 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 572 if (tbl->type) 573 crtl |= GSWIP_PCE_TBL_CTRL_TYPE; 574 if (tbl->valid) 575 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 576 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 577 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 578 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 579 580 return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 581 GSWIP_PCE_TBL_CTRL_BAS); 582 } 583 584 /* Add the LAN port into a bridge with the CPU port by 585 * default. This prevents automatic forwarding of 586 * packages between the LAN ports when no explicit 587 * bridge is configured. 588 */ 589 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) 590 { 591 struct gswip_pce_table_entry vlan_active = {0,}; 592 struct gswip_pce_table_entry vlan_mapping = {0,}; 593 unsigned int cpu_port = priv->hw_info->cpu_port; 594 unsigned int max_ports = priv->hw_info->max_ports; 595 int err; 596 597 if (port >= max_ports) { 598 dev_err(priv->dev, "single port for %i supported\n", port); 599 return -EIO; 600 } 601 602 vlan_active.index = port + 1; 603 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 604 vlan_active.key[0] = 0; /* vid */ 605 vlan_active.val[0] = port + 1 /* fid */; 606 vlan_active.valid = add; 607 err = gswip_pce_table_entry_write(priv, &vlan_active); 608 if (err) { 609 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 610 return err; 611 } 612 613 if (!add) 614 return 0; 615 616 vlan_mapping.index = port + 1; 617 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 618 vlan_mapping.val[0] = 0 /* vid */; 619 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); 620 vlan_mapping.val[2] = 0; 621 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 622 if (err) { 623 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 624 return err; 625 } 626 627 return 0; 628 } 629 630 static int gswip_port_enable(struct dsa_switch *ds, int port, 631 struct phy_device *phydev) 632 { 633 struct gswip_priv *priv = ds->priv; 634 int err; 635 636 if (!dsa_is_user_port(ds, port)) 637 return 0; 638 639 if (!dsa_is_cpu_port(ds, port)) { 640 err = gswip_add_single_port_br(priv, port, true); 641 if (err) 642 return err; 643 } 644 645 /* RMON Counter Enable for port */ 646 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 647 648 /* enable port fetch/store dma & VLAN Modification */ 649 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 650 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 651 GSWIP_FDMA_PCTRLp(port)); 652 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 653 GSWIP_SDMA_PCTRLp(port)); 654 655 if (!dsa_is_cpu_port(ds, port)) { 656 u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO | 657 GSWIP_MDIO_PHY_SPEED_AUTO | 658 GSWIP_MDIO_PHY_FDUP_AUTO | 659 GSWIP_MDIO_PHY_FCONTX_AUTO | 660 GSWIP_MDIO_PHY_FCONRX_AUTO | 661 (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK); 662 663 gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port)); 664 /* Activate MDIO auto polling */ 665 gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0); 666 } 667 668 return 0; 669 } 670 671 static void gswip_port_disable(struct dsa_switch *ds, int port) 672 { 673 struct gswip_priv *priv = ds->priv; 674 675 if (!dsa_is_user_port(ds, port)) 676 return; 677 678 if (!dsa_is_cpu_port(ds, port)) { 679 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_DOWN, 680 GSWIP_MDIO_PHY_LINK_MASK, 681 GSWIP_MDIO_PHYp(port)); 682 /* Deactivate MDIO auto polling */ 683 gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0); 684 } 685 686 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 687 GSWIP_FDMA_PCTRLp(port)); 688 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 689 GSWIP_SDMA_PCTRLp(port)); 690 } 691 692 static int gswip_pce_load_microcode(struct gswip_priv *priv) 693 { 694 int i; 695 int err; 696 697 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 698 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 699 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 700 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 701 702 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { 703 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 704 gswip_switch_w(priv, gswip_pce_microcode[i].val_0, 705 GSWIP_PCE_TBL_VAL(0)); 706 gswip_switch_w(priv, gswip_pce_microcode[i].val_1, 707 GSWIP_PCE_TBL_VAL(1)); 708 gswip_switch_w(priv, gswip_pce_microcode[i].val_2, 709 GSWIP_PCE_TBL_VAL(2)); 710 gswip_switch_w(priv, gswip_pce_microcode[i].val_3, 711 GSWIP_PCE_TBL_VAL(3)); 712 713 /* start the table access: */ 714 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 715 GSWIP_PCE_TBL_CTRL); 716 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 717 GSWIP_PCE_TBL_CTRL_BAS); 718 if (err) 719 return err; 720 } 721 722 /* tell the switch that the microcode is loaded */ 723 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 724 GSWIP_PCE_GCTRL_0); 725 726 return 0; 727 } 728 729 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 730 bool vlan_filtering) 731 { 732 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 733 struct gswip_priv *priv = ds->priv; 734 735 /* Do not allow changing the VLAN filtering options while in bridge */ 736 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) 737 return -EIO; 738 739 if (vlan_filtering) { 740 /* Use port based VLAN tag */ 741 gswip_switch_mask(priv, 742 GSWIP_PCE_VCTRL_VSR, 743 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 744 GSWIP_PCE_VCTRL_VEMR, 745 GSWIP_PCE_VCTRL(port)); 746 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 747 GSWIP_PCE_PCTRL_0p(port)); 748 } else { 749 /* Use port based VLAN tag */ 750 gswip_switch_mask(priv, 751 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 752 GSWIP_PCE_VCTRL_VEMR, 753 GSWIP_PCE_VCTRL_VSR, 754 GSWIP_PCE_VCTRL(port)); 755 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 756 GSWIP_PCE_PCTRL_0p(port)); 757 } 758 759 return 0; 760 } 761 762 static int gswip_setup(struct dsa_switch *ds) 763 { 764 struct gswip_priv *priv = ds->priv; 765 unsigned int cpu_port = priv->hw_info->cpu_port; 766 int i; 767 int err; 768 769 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 770 usleep_range(5000, 10000); 771 gswip_switch_w(priv, 0, GSWIP_SWRES); 772 773 /* disable port fetch/store dma on all ports */ 774 for (i = 0; i < priv->hw_info->max_ports; i++) { 775 gswip_port_disable(ds, i); 776 gswip_port_vlan_filtering(ds, i, false); 777 } 778 779 /* enable Switch */ 780 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 781 782 err = gswip_pce_load_microcode(priv); 783 if (err) { 784 dev_err(priv->dev, "writing PCE microcode failed, %i", err); 785 return err; 786 } 787 788 /* Default unknown Broadcast/Multicast/Unicast port maps */ 789 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); 790 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); 791 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); 792 793 /* disable PHY auto polling */ 794 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 795 /* Configure the MDIO Clock 2.5 MHz */ 796 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 797 798 /* Disable the xMII link */ 799 for (i = 0; i < priv->hw_info->max_ports; i++) 800 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i); 801 802 /* enable special tag insertion on cpu port */ 803 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 804 GSWIP_FDMA_PCTRLp(cpu_port)); 805 806 /* accept special tag in ingress direction */ 807 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 808 GSWIP_PCE_PCTRL_0p(cpu_port)); 809 810 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 811 GSWIP_MAC_CTRL_2p(cpu_port)); 812 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8, GSWIP_MAC_FLEN); 813 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 814 GSWIP_BM_QUEUE_GCTRL); 815 816 /* VLAN aware Switching */ 817 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 818 819 /* Flush MAC Table */ 820 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 821 822 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 823 GSWIP_PCE_GCTRL_0_MTFL); 824 if (err) { 825 dev_err(priv->dev, "MAC flushing didn't finish\n"); 826 return err; 827 } 828 829 gswip_port_enable(ds, cpu_port, NULL); 830 831 ds->configure_vlan_while_not_filtering = false; 832 833 return 0; 834 } 835 836 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 837 int port, 838 enum dsa_tag_protocol mp) 839 { 840 return DSA_TAG_PROTO_GSWIP; 841 } 842 843 static int gswip_vlan_active_create(struct gswip_priv *priv, 844 struct net_device *bridge, 845 int fid, u16 vid) 846 { 847 struct gswip_pce_table_entry vlan_active = {0,}; 848 unsigned int max_ports = priv->hw_info->max_ports; 849 int idx = -1; 850 int err; 851 int i; 852 853 /* Look for a free slot */ 854 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 855 if (!priv->vlans[i].bridge) { 856 idx = i; 857 break; 858 } 859 } 860 861 if (idx == -1) 862 return -ENOSPC; 863 864 if (fid == -1) 865 fid = idx; 866 867 vlan_active.index = idx; 868 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 869 vlan_active.key[0] = vid; 870 vlan_active.val[0] = fid; 871 vlan_active.valid = true; 872 873 err = gswip_pce_table_entry_write(priv, &vlan_active); 874 if (err) { 875 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 876 return err; 877 } 878 879 priv->vlans[idx].bridge = bridge; 880 priv->vlans[idx].vid = vid; 881 priv->vlans[idx].fid = fid; 882 883 return idx; 884 } 885 886 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) 887 { 888 struct gswip_pce_table_entry vlan_active = {0,}; 889 int err; 890 891 vlan_active.index = idx; 892 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 893 vlan_active.valid = false; 894 err = gswip_pce_table_entry_write(priv, &vlan_active); 895 if (err) 896 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); 897 priv->vlans[idx].bridge = NULL; 898 899 return err; 900 } 901 902 static int gswip_vlan_add_unaware(struct gswip_priv *priv, 903 struct net_device *bridge, int port) 904 { 905 struct gswip_pce_table_entry vlan_mapping = {0,}; 906 unsigned int max_ports = priv->hw_info->max_ports; 907 unsigned int cpu_port = priv->hw_info->cpu_port; 908 bool active_vlan_created = false; 909 int idx = -1; 910 int i; 911 int err; 912 913 /* Check if there is already a page for this bridge */ 914 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 915 if (priv->vlans[i].bridge == bridge) { 916 idx = i; 917 break; 918 } 919 } 920 921 /* If this bridge is not programmed yet, add a Active VLAN table 922 * entry in a free slot and prepare the VLAN mapping table entry. 923 */ 924 if (idx == -1) { 925 idx = gswip_vlan_active_create(priv, bridge, -1, 0); 926 if (idx < 0) 927 return idx; 928 active_vlan_created = true; 929 930 vlan_mapping.index = idx; 931 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 932 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 933 vlan_mapping.val[0] = 0; 934 } else { 935 /* Read the existing VLAN mapping entry from the switch */ 936 vlan_mapping.index = idx; 937 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 938 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 939 if (err) { 940 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 941 err); 942 return err; 943 } 944 } 945 946 /* Update the VLAN mapping entry and write it to the switch */ 947 vlan_mapping.val[1] |= BIT(cpu_port); 948 vlan_mapping.val[1] |= BIT(port); 949 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 950 if (err) { 951 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 952 /* In case an Active VLAN was creaetd delete it again */ 953 if (active_vlan_created) 954 gswip_vlan_active_remove(priv, idx); 955 return err; 956 } 957 958 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 959 return 0; 960 } 961 962 static int gswip_vlan_add_aware(struct gswip_priv *priv, 963 struct net_device *bridge, int port, 964 u16 vid, bool untagged, 965 bool pvid) 966 { 967 struct gswip_pce_table_entry vlan_mapping = {0,}; 968 unsigned int max_ports = priv->hw_info->max_ports; 969 unsigned int cpu_port = priv->hw_info->cpu_port; 970 bool active_vlan_created = false; 971 int idx = -1; 972 int fid = -1; 973 int i; 974 int err; 975 976 /* Check if there is already a page for this bridge */ 977 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 978 if (priv->vlans[i].bridge == bridge) { 979 if (fid != -1 && fid != priv->vlans[i].fid) 980 dev_err(priv->dev, "one bridge with multiple flow ids\n"); 981 fid = priv->vlans[i].fid; 982 if (priv->vlans[i].vid == vid) { 983 idx = i; 984 break; 985 } 986 } 987 } 988 989 /* If this bridge is not programmed yet, add a Active VLAN table 990 * entry in a free slot and prepare the VLAN mapping table entry. 991 */ 992 if (idx == -1) { 993 idx = gswip_vlan_active_create(priv, bridge, fid, vid); 994 if (idx < 0) 995 return idx; 996 active_vlan_created = true; 997 998 vlan_mapping.index = idx; 999 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1000 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 1001 vlan_mapping.val[0] = vid; 1002 } else { 1003 /* Read the existing VLAN mapping entry from the switch */ 1004 vlan_mapping.index = idx; 1005 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1006 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1007 if (err) { 1008 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 1009 err); 1010 return err; 1011 } 1012 } 1013 1014 vlan_mapping.val[0] = vid; 1015 /* Update the VLAN mapping entry and write it to the switch */ 1016 vlan_mapping.val[1] |= BIT(cpu_port); 1017 vlan_mapping.val[2] |= BIT(cpu_port); 1018 vlan_mapping.val[1] |= BIT(port); 1019 if (untagged) 1020 vlan_mapping.val[2] &= ~BIT(port); 1021 else 1022 vlan_mapping.val[2] |= BIT(port); 1023 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1024 if (err) { 1025 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1026 /* In case an Active VLAN was creaetd delete it again */ 1027 if (active_vlan_created) 1028 gswip_vlan_active_remove(priv, idx); 1029 return err; 1030 } 1031 1032 if (pvid) 1033 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 1034 1035 return 0; 1036 } 1037 1038 static int gswip_vlan_remove(struct gswip_priv *priv, 1039 struct net_device *bridge, int port, 1040 u16 vid, bool pvid, bool vlan_aware) 1041 { 1042 struct gswip_pce_table_entry vlan_mapping = {0,}; 1043 unsigned int max_ports = priv->hw_info->max_ports; 1044 unsigned int cpu_port = priv->hw_info->cpu_port; 1045 int idx = -1; 1046 int i; 1047 int err; 1048 1049 /* Check if there is already a page for this bridge */ 1050 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1051 if (priv->vlans[i].bridge == bridge && 1052 (!vlan_aware || priv->vlans[i].vid == vid)) { 1053 idx = i; 1054 break; 1055 } 1056 } 1057 1058 if (idx == -1) { 1059 dev_err(priv->dev, "bridge to leave does not exists\n"); 1060 return -ENOENT; 1061 } 1062 1063 vlan_mapping.index = idx; 1064 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1065 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1066 if (err) { 1067 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); 1068 return err; 1069 } 1070 1071 vlan_mapping.val[1] &= ~BIT(port); 1072 vlan_mapping.val[2] &= ~BIT(port); 1073 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1074 if (err) { 1075 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1076 return err; 1077 } 1078 1079 /* In case all ports are removed from the bridge, remove the VLAN */ 1080 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { 1081 err = gswip_vlan_active_remove(priv, idx); 1082 if (err) { 1083 dev_err(priv->dev, "failed to write active VLAN: %d\n", 1084 err); 1085 return err; 1086 } 1087 } 1088 1089 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 1090 if (pvid) 1091 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1092 1093 return 0; 1094 } 1095 1096 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, 1097 struct net_device *bridge) 1098 { 1099 struct gswip_priv *priv = ds->priv; 1100 int err; 1101 1102 /* When the bridge uses VLAN filtering we have to configure VLAN 1103 * specific bridges. No bridge is configured here. 1104 */ 1105 if (!br_vlan_enabled(bridge)) { 1106 err = gswip_vlan_add_unaware(priv, bridge, port); 1107 if (err) 1108 return err; 1109 priv->port_vlan_filter &= ~BIT(port); 1110 } else { 1111 priv->port_vlan_filter |= BIT(port); 1112 } 1113 return gswip_add_single_port_br(priv, port, false); 1114 } 1115 1116 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, 1117 struct net_device *bridge) 1118 { 1119 struct gswip_priv *priv = ds->priv; 1120 1121 gswip_add_single_port_br(priv, port, true); 1122 1123 /* When the bridge uses VLAN filtering we have to configure VLAN 1124 * specific bridges. No bridge is configured here. 1125 */ 1126 if (!br_vlan_enabled(bridge)) 1127 gswip_vlan_remove(priv, bridge, port, 0, true, false); 1128 } 1129 1130 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, 1131 const struct switchdev_obj_port_vlan *vlan) 1132 { 1133 struct gswip_priv *priv = ds->priv; 1134 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1135 unsigned int max_ports = priv->hw_info->max_ports; 1136 int pos = max_ports; 1137 int i, idx = -1; 1138 1139 /* We only support VLAN filtering on bridges */ 1140 if (!dsa_is_cpu_port(ds, port) && !bridge) 1141 return -EOPNOTSUPP; 1142 1143 /* Check if there is already a page for this VLAN */ 1144 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1145 if (priv->vlans[i].bridge == bridge && 1146 priv->vlans[i].vid == vlan->vid) { 1147 idx = i; 1148 break; 1149 } 1150 } 1151 1152 /* If this VLAN is not programmed yet, we have to reserve 1153 * one entry in the VLAN table. Make sure we start at the 1154 * next position round. 1155 */ 1156 if (idx == -1) { 1157 /* Look for a free slot */ 1158 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { 1159 if (!priv->vlans[pos].bridge) { 1160 idx = pos; 1161 pos++; 1162 break; 1163 } 1164 } 1165 1166 if (idx == -1) 1167 return -ENOSPC; 1168 } 1169 1170 return 0; 1171 } 1172 1173 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, 1174 const struct switchdev_obj_port_vlan *vlan) 1175 { 1176 struct gswip_priv *priv = ds->priv; 1177 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1178 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1179 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1180 int err; 1181 1182 err = gswip_port_vlan_prepare(ds, port, vlan); 1183 if (err) 1184 return err; 1185 1186 /* We have to receive all packets on the CPU port and should not 1187 * do any VLAN filtering here. This is also called with bridge 1188 * NULL and then we do not know for which bridge to configure 1189 * this. 1190 */ 1191 if (dsa_is_cpu_port(ds, port)) 1192 return 0; 1193 1194 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, 1195 untagged, pvid); 1196 } 1197 1198 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, 1199 const struct switchdev_obj_port_vlan *vlan) 1200 { 1201 struct gswip_priv *priv = ds->priv; 1202 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1203 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1204 1205 /* We have to receive all packets on the CPU port and should not 1206 * do any VLAN filtering here. This is also called with bridge 1207 * NULL and then we do not know for which bridge to configure 1208 * this. 1209 */ 1210 if (dsa_is_cpu_port(ds, port)) 1211 return 0; 1212 1213 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); 1214 } 1215 1216 static void gswip_port_fast_age(struct dsa_switch *ds, int port) 1217 { 1218 struct gswip_priv *priv = ds->priv; 1219 struct gswip_pce_table_entry mac_bridge = {0,}; 1220 int i; 1221 int err; 1222 1223 for (i = 0; i < 2048; i++) { 1224 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1225 mac_bridge.index = i; 1226 1227 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1228 if (err) { 1229 dev_err(priv->dev, "failed to read mac bridge: %d\n", 1230 err); 1231 return; 1232 } 1233 1234 if (!mac_bridge.valid) 1235 continue; 1236 1237 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) 1238 continue; 1239 1240 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) 1241 continue; 1242 1243 mac_bridge.valid = false; 1244 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1245 if (err) { 1246 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1247 err); 1248 return; 1249 } 1250 } 1251 } 1252 1253 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1254 { 1255 struct gswip_priv *priv = ds->priv; 1256 u32 stp_state; 1257 1258 switch (state) { 1259 case BR_STATE_DISABLED: 1260 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1261 GSWIP_SDMA_PCTRLp(port)); 1262 return; 1263 case BR_STATE_BLOCKING: 1264 case BR_STATE_LISTENING: 1265 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; 1266 break; 1267 case BR_STATE_LEARNING: 1268 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; 1269 break; 1270 case BR_STATE_FORWARDING: 1271 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; 1272 break; 1273 default: 1274 dev_err(priv->dev, "invalid STP state: %d\n", state); 1275 return; 1276 } 1277 1278 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1279 GSWIP_SDMA_PCTRLp(port)); 1280 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1281 GSWIP_PCE_PCTRL_0p(port)); 1282 } 1283 1284 static int gswip_port_fdb(struct dsa_switch *ds, int port, 1285 const unsigned char *addr, u16 vid, bool add) 1286 { 1287 struct gswip_priv *priv = ds->priv; 1288 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1289 struct gswip_pce_table_entry mac_bridge = {0,}; 1290 unsigned int cpu_port = priv->hw_info->cpu_port; 1291 int fid = -1; 1292 int i; 1293 int err; 1294 1295 if (!bridge) 1296 return -EINVAL; 1297 1298 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) { 1299 if (priv->vlans[i].bridge == bridge) { 1300 fid = priv->vlans[i].fid; 1301 break; 1302 } 1303 } 1304 1305 if (fid == -1) { 1306 dev_err(priv->dev, "Port not part of a bridge\n"); 1307 return -EINVAL; 1308 } 1309 1310 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1311 mac_bridge.key_mode = true; 1312 mac_bridge.key[0] = addr[5] | (addr[4] << 8); 1313 mac_bridge.key[1] = addr[3] | (addr[2] << 8); 1314 mac_bridge.key[2] = addr[1] | (addr[0] << 8); 1315 mac_bridge.key[3] = fid; 1316 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ 1317 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; 1318 mac_bridge.valid = add; 1319 1320 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1321 if (err) 1322 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); 1323 1324 return err; 1325 } 1326 1327 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, 1328 const unsigned char *addr, u16 vid) 1329 { 1330 return gswip_port_fdb(ds, port, addr, vid, true); 1331 } 1332 1333 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, 1334 const unsigned char *addr, u16 vid) 1335 { 1336 return gswip_port_fdb(ds, port, addr, vid, false); 1337 } 1338 1339 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, 1340 dsa_fdb_dump_cb_t *cb, void *data) 1341 { 1342 struct gswip_priv *priv = ds->priv; 1343 struct gswip_pce_table_entry mac_bridge = {0,}; 1344 unsigned char addr[6]; 1345 int i; 1346 int err; 1347 1348 for (i = 0; i < 2048; i++) { 1349 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1350 mac_bridge.index = i; 1351 1352 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1353 if (err) { 1354 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1355 err); 1356 return err; 1357 } 1358 1359 if (!mac_bridge.valid) 1360 continue; 1361 1362 addr[5] = mac_bridge.key[0] & 0xff; 1363 addr[4] = (mac_bridge.key[0] >> 8) & 0xff; 1364 addr[3] = mac_bridge.key[1] & 0xff; 1365 addr[2] = (mac_bridge.key[1] >> 8) & 0xff; 1366 addr[1] = mac_bridge.key[2] & 0xff; 1367 addr[0] = (mac_bridge.key[2] >> 8) & 0xff; 1368 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { 1369 if (mac_bridge.val[0] & BIT(port)) 1370 cb(addr, 0, true, data); 1371 } else { 1372 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) 1373 cb(addr, 0, false, data); 1374 } 1375 } 1376 return 0; 1377 } 1378 1379 static void gswip_phylink_validate(struct dsa_switch *ds, int port, 1380 unsigned long *supported, 1381 struct phylink_link_state *state) 1382 { 1383 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1384 1385 switch (port) { 1386 case 0: 1387 case 1: 1388 if (!phy_interface_mode_is_rgmii(state->interface) && 1389 state->interface != PHY_INTERFACE_MODE_MII && 1390 state->interface != PHY_INTERFACE_MODE_REVMII && 1391 state->interface != PHY_INTERFACE_MODE_RMII) 1392 goto unsupported; 1393 break; 1394 case 2: 1395 case 3: 1396 case 4: 1397 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 1398 goto unsupported; 1399 break; 1400 case 5: 1401 if (!phy_interface_mode_is_rgmii(state->interface) && 1402 state->interface != PHY_INTERFACE_MODE_INTERNAL) 1403 goto unsupported; 1404 break; 1405 default: 1406 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1407 dev_err(ds->dev, "Unsupported port: %i\n", port); 1408 return; 1409 } 1410 1411 /* Allow all the expected bits */ 1412 phylink_set(mask, Autoneg); 1413 phylink_set_port_modes(mask); 1414 phylink_set(mask, Pause); 1415 phylink_set(mask, Asym_Pause); 1416 1417 /* With the exclusion of MII, Reverse MII and Reduced MII, we 1418 * support Gigabit, including Half duplex 1419 */ 1420 if (state->interface != PHY_INTERFACE_MODE_MII && 1421 state->interface != PHY_INTERFACE_MODE_REVMII && 1422 state->interface != PHY_INTERFACE_MODE_RMII) { 1423 phylink_set(mask, 1000baseT_Full); 1424 phylink_set(mask, 1000baseT_Half); 1425 } 1426 1427 phylink_set(mask, 10baseT_Half); 1428 phylink_set(mask, 10baseT_Full); 1429 phylink_set(mask, 100baseT_Half); 1430 phylink_set(mask, 100baseT_Full); 1431 1432 bitmap_and(supported, supported, mask, 1433 __ETHTOOL_LINK_MODE_MASK_NBITS); 1434 bitmap_and(state->advertising, state->advertising, mask, 1435 __ETHTOOL_LINK_MODE_MASK_NBITS); 1436 return; 1437 1438 unsupported: 1439 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1440 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", 1441 phy_modes(state->interface), port); 1442 return; 1443 } 1444 1445 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, 1446 unsigned int mode, 1447 const struct phylink_link_state *state) 1448 { 1449 struct gswip_priv *priv = ds->priv; 1450 u32 miicfg = 0; 1451 1452 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 1453 1454 switch (state->interface) { 1455 case PHY_INTERFACE_MODE_MII: 1456 case PHY_INTERFACE_MODE_INTERNAL: 1457 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 1458 break; 1459 case PHY_INTERFACE_MODE_REVMII: 1460 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 1461 break; 1462 case PHY_INTERFACE_MODE_RMII: 1463 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 1464 break; 1465 case PHY_INTERFACE_MODE_RGMII: 1466 case PHY_INTERFACE_MODE_RGMII_ID: 1467 case PHY_INTERFACE_MODE_RGMII_RXID: 1468 case PHY_INTERFACE_MODE_RGMII_TXID: 1469 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 1470 break; 1471 default: 1472 dev_err(ds->dev, 1473 "Unsupported interface: %d\n", state->interface); 1474 return; 1475 } 1476 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK, miicfg, port); 1477 1478 switch (state->interface) { 1479 case PHY_INTERFACE_MODE_RGMII_ID: 1480 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 1481 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1482 break; 1483 case PHY_INTERFACE_MODE_RGMII_RXID: 1484 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1485 break; 1486 case PHY_INTERFACE_MODE_RGMII_TXID: 1487 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 1488 break; 1489 default: 1490 break; 1491 } 1492 } 1493 1494 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, 1495 unsigned int mode, 1496 phy_interface_t interface) 1497 { 1498 struct gswip_priv *priv = ds->priv; 1499 1500 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 1501 } 1502 1503 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, 1504 unsigned int mode, 1505 phy_interface_t interface, 1506 struct phy_device *phydev, 1507 int speed, int duplex, 1508 bool tx_pause, bool rx_pause) 1509 { 1510 struct gswip_priv *priv = ds->priv; 1511 1512 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1513 } 1514 1515 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1516 uint8_t *data) 1517 { 1518 int i; 1519 1520 if (stringset != ETH_SS_STATS) 1521 return; 1522 1523 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 1524 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name, 1525 ETH_GSTRING_LEN); 1526 } 1527 1528 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1529 u32 index) 1530 { 1531 u32 result; 1532 int err; 1533 1534 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1535 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1536 GSWIP_BM_RAM_CTRL_OPMOD, 1537 table | GSWIP_BM_RAM_CTRL_BAS, 1538 GSWIP_BM_RAM_CTRL); 1539 1540 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1541 GSWIP_BM_RAM_CTRL_BAS); 1542 if (err) { 1543 dev_err(priv->dev, "timeout while reading table: %u, index: %u", 1544 table, index); 1545 return 0; 1546 } 1547 1548 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1549 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1550 1551 return result; 1552 } 1553 1554 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 1555 uint64_t *data) 1556 { 1557 struct gswip_priv *priv = ds->priv; 1558 const struct gswip_rmon_cnt_desc *rmon_cnt; 1559 int i; 1560 u64 high; 1561 1562 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 1563 rmon_cnt = &gswip_rmon_cnt[i]; 1564 1565 data[i] = gswip_bcm_ram_entry_read(priv, port, 1566 rmon_cnt->offset); 1567 if (rmon_cnt->size == 2) { 1568 high = gswip_bcm_ram_entry_read(priv, port, 1569 rmon_cnt->offset + 1); 1570 data[i] |= high << 32; 1571 } 1572 } 1573 } 1574 1575 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 1576 { 1577 if (sset != ETH_SS_STATS) 1578 return 0; 1579 1580 return ARRAY_SIZE(gswip_rmon_cnt); 1581 } 1582 1583 static const struct dsa_switch_ops gswip_switch_ops = { 1584 .get_tag_protocol = gswip_get_tag_protocol, 1585 .setup = gswip_setup, 1586 .port_enable = gswip_port_enable, 1587 .port_disable = gswip_port_disable, 1588 .port_bridge_join = gswip_port_bridge_join, 1589 .port_bridge_leave = gswip_port_bridge_leave, 1590 .port_fast_age = gswip_port_fast_age, 1591 .port_vlan_filtering = gswip_port_vlan_filtering, 1592 .port_vlan_add = gswip_port_vlan_add, 1593 .port_vlan_del = gswip_port_vlan_del, 1594 .port_stp_state_set = gswip_port_stp_state_set, 1595 .port_fdb_add = gswip_port_fdb_add, 1596 .port_fdb_del = gswip_port_fdb_del, 1597 .port_fdb_dump = gswip_port_fdb_dump, 1598 .phylink_validate = gswip_phylink_validate, 1599 .phylink_mac_config = gswip_phylink_mac_config, 1600 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1601 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1602 .get_strings = gswip_get_strings, 1603 .get_ethtool_stats = gswip_get_ethtool_stats, 1604 .get_sset_count = gswip_get_sset_count, 1605 }; 1606 1607 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 1608 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 1609 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 1610 }; 1611 1612 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 1613 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 1614 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 1615 }; 1616 1617 static const struct xway_gphy_match_data xrx300_gphy_data = { 1618 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 1619 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 1620 }; 1621 1622 static const struct of_device_id xway_gphy_match[] = { 1623 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 1624 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 1625 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 1626 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 1627 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 1628 {}, 1629 }; 1630 1631 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 1632 { 1633 struct device *dev = priv->dev; 1634 const struct firmware *fw; 1635 void *fw_addr; 1636 dma_addr_t dma_addr; 1637 dma_addr_t dev_addr; 1638 size_t size; 1639 int ret; 1640 1641 ret = clk_prepare_enable(gphy_fw->clk_gate); 1642 if (ret) 1643 return ret; 1644 1645 reset_control_assert(gphy_fw->reset); 1646 1647 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 1648 if (ret) { 1649 dev_err(dev, "failed to load firmware: %s, error: %i\n", 1650 gphy_fw->fw_name, ret); 1651 return ret; 1652 } 1653 1654 /* GPHY cores need the firmware code in a persistent and contiguous 1655 * memory area with a 16 kB boundary aligned start address. 1656 */ 1657 size = fw->size + XRX200_GPHY_FW_ALIGN; 1658 1659 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 1660 if (fw_addr) { 1661 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 1662 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 1663 memcpy(fw_addr, fw->data, fw->size); 1664 } else { 1665 dev_err(dev, "failed to alloc firmware memory\n"); 1666 release_firmware(fw); 1667 return -ENOMEM; 1668 } 1669 1670 release_firmware(fw); 1671 1672 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 1673 if (ret) 1674 return ret; 1675 1676 reset_control_deassert(gphy_fw->reset); 1677 1678 return ret; 1679 } 1680 1681 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 1682 struct gswip_gphy_fw *gphy_fw, 1683 struct device_node *gphy_fw_np, int i) 1684 { 1685 struct device *dev = priv->dev; 1686 u32 gphy_mode; 1687 int ret; 1688 char gphyname[10]; 1689 1690 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 1691 1692 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 1693 if (IS_ERR(gphy_fw->clk_gate)) { 1694 dev_err(dev, "Failed to lookup gate clock\n"); 1695 return PTR_ERR(gphy_fw->clk_gate); 1696 } 1697 1698 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 1699 if (ret) 1700 return ret; 1701 1702 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 1703 /* Default to GE mode */ 1704 if (ret) 1705 gphy_mode = GPHY_MODE_GE; 1706 1707 switch (gphy_mode) { 1708 case GPHY_MODE_FE: 1709 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 1710 break; 1711 case GPHY_MODE_GE: 1712 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 1713 break; 1714 default: 1715 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); 1716 return -EINVAL; 1717 } 1718 1719 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 1720 if (IS_ERR(gphy_fw->reset)) { 1721 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER) 1722 dev_err(dev, "Failed to lookup gphy reset\n"); 1723 return PTR_ERR(gphy_fw->reset); 1724 } 1725 1726 return gswip_gphy_fw_load(priv, gphy_fw); 1727 } 1728 1729 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 1730 struct gswip_gphy_fw *gphy_fw) 1731 { 1732 int ret; 1733 1734 /* check if the device was fully probed */ 1735 if (!gphy_fw->fw_name) 1736 return; 1737 1738 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 1739 if (ret) 1740 dev_err(priv->dev, "can not reset GPHY FW pointer"); 1741 1742 clk_disable_unprepare(gphy_fw->clk_gate); 1743 1744 reset_control_put(gphy_fw->reset); 1745 } 1746 1747 static int gswip_gphy_fw_list(struct gswip_priv *priv, 1748 struct device_node *gphy_fw_list_np, u32 version) 1749 { 1750 struct device *dev = priv->dev; 1751 struct device_node *gphy_fw_np; 1752 const struct of_device_id *match; 1753 int err; 1754 int i = 0; 1755 1756 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 1757 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 1758 * needs a different GPHY firmware. 1759 */ 1760 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 1761 switch (version) { 1762 case GSWIP_VERSION_2_0: 1763 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 1764 break; 1765 case GSWIP_VERSION_2_1: 1766 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 1767 break; 1768 default: 1769 dev_err(dev, "unknown GSWIP version: 0x%x", version); 1770 return -ENOENT; 1771 } 1772 } 1773 1774 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 1775 if (match && match->data) 1776 priv->gphy_fw_name_cfg = match->data; 1777 1778 if (!priv->gphy_fw_name_cfg) { 1779 dev_err(dev, "GPHY compatible type not supported"); 1780 return -ENOENT; 1781 } 1782 1783 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 1784 if (!priv->num_gphy_fw) 1785 return -ENOENT; 1786 1787 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 1788 "lantiq,rcu"); 1789 if (IS_ERR(priv->rcu_regmap)) 1790 return PTR_ERR(priv->rcu_regmap); 1791 1792 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 1793 sizeof(*priv->gphy_fw), 1794 GFP_KERNEL | __GFP_ZERO); 1795 if (!priv->gphy_fw) 1796 return -ENOMEM; 1797 1798 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 1799 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 1800 gphy_fw_np, i); 1801 if (err) 1802 goto remove_gphy; 1803 i++; 1804 } 1805 1806 /* The standalone PHY11G requires 300ms to be fully 1807 * initialized and ready for any MDIO communication after being 1808 * taken out of reset. For the SoC-internal GPHY variant there 1809 * is no (known) documentation for the minimum time after a 1810 * reset. Use the same value as for the standalone variant as 1811 * some users have reported internal PHYs not being detected 1812 * without any delay. 1813 */ 1814 msleep(300); 1815 1816 return 0; 1817 1818 remove_gphy: 1819 for (i = 0; i < priv->num_gphy_fw; i++) 1820 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1821 return err; 1822 } 1823 1824 static int gswip_probe(struct platform_device *pdev) 1825 { 1826 struct gswip_priv *priv; 1827 struct device_node *mdio_np, *gphy_fw_np; 1828 struct device *dev = &pdev->dev; 1829 int err; 1830 int i; 1831 u32 version; 1832 1833 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1834 if (!priv) 1835 return -ENOMEM; 1836 1837 priv->gswip = devm_platform_ioremap_resource(pdev, 0); 1838 if (IS_ERR(priv->gswip)) 1839 return PTR_ERR(priv->gswip); 1840 1841 priv->mdio = devm_platform_ioremap_resource(pdev, 1); 1842 if (IS_ERR(priv->mdio)) 1843 return PTR_ERR(priv->mdio); 1844 1845 priv->mii = devm_platform_ioremap_resource(pdev, 2); 1846 if (IS_ERR(priv->mii)) 1847 return PTR_ERR(priv->mii); 1848 1849 priv->hw_info = of_device_get_match_data(dev); 1850 if (!priv->hw_info) 1851 return -EINVAL; 1852 1853 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 1854 if (!priv->ds) 1855 return -ENOMEM; 1856 1857 priv->ds->dev = dev; 1858 priv->ds->num_ports = priv->hw_info->max_ports; 1859 priv->ds->priv = priv; 1860 priv->ds->ops = &gswip_switch_ops; 1861 priv->dev = dev; 1862 version = gswip_switch_r(priv, GSWIP_VERSION); 1863 1864 /* bring up the mdio bus */ 1865 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 1866 if (gphy_fw_np) { 1867 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 1868 of_node_put(gphy_fw_np); 1869 if (err) { 1870 dev_err(dev, "gphy fw probe failed\n"); 1871 return err; 1872 } 1873 } 1874 1875 /* bring up the mdio bus */ 1876 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio"); 1877 if (mdio_np) { 1878 err = gswip_mdio(priv, mdio_np); 1879 if (err) { 1880 dev_err(dev, "mdio probe failed\n"); 1881 goto put_mdio_node; 1882 } 1883 } 1884 1885 err = dsa_register_switch(priv->ds); 1886 if (err) { 1887 dev_err(dev, "dsa switch register failed: %i\n", err); 1888 goto mdio_bus; 1889 } 1890 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { 1891 dev_err(dev, "wrong CPU port defined, HW only supports port: %i", 1892 priv->hw_info->cpu_port); 1893 err = -EINVAL; 1894 goto disable_switch; 1895 } 1896 1897 platform_set_drvdata(pdev, priv); 1898 1899 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 1900 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, 1901 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); 1902 return 0; 1903 1904 disable_switch: 1905 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 1906 dsa_unregister_switch(priv->ds); 1907 mdio_bus: 1908 if (mdio_np) 1909 mdiobus_unregister(priv->ds->slave_mii_bus); 1910 put_mdio_node: 1911 of_node_put(mdio_np); 1912 for (i = 0; i < priv->num_gphy_fw; i++) 1913 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1914 return err; 1915 } 1916 1917 static int gswip_remove(struct platform_device *pdev) 1918 { 1919 struct gswip_priv *priv = platform_get_drvdata(pdev); 1920 int i; 1921 1922 /* disable the switch */ 1923 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 1924 1925 dsa_unregister_switch(priv->ds); 1926 1927 if (priv->ds->slave_mii_bus) { 1928 mdiobus_unregister(priv->ds->slave_mii_bus); 1929 of_node_put(priv->ds->slave_mii_bus->dev.of_node); 1930 } 1931 1932 for (i = 0; i < priv->num_gphy_fw; i++) 1933 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1934 1935 return 0; 1936 } 1937 1938 static const struct gswip_hw_info gswip_xrx200 = { 1939 .max_ports = 7, 1940 .cpu_port = 6, 1941 }; 1942 1943 static const struct of_device_id gswip_of_match[] = { 1944 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 1945 {}, 1946 }; 1947 MODULE_DEVICE_TABLE(of, gswip_of_match); 1948 1949 static struct platform_driver gswip_driver = { 1950 .probe = gswip_probe, 1951 .remove = gswip_remove, 1952 .driver = { 1953 .name = "gswip", 1954 .of_match_table = gswip_of_match, 1955 }, 1956 }; 1957 1958 module_platform_driver(gswip_driver); 1959 1960 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 1961 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 1962 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 1963 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 1964 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 1965 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 1966 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 1967 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 1968 MODULE_LICENSE("GPL v2"); 1969