1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * The VLAN and bridge model the GSWIP hardware uses does not directly 10 * matches the model DSA uses. 11 * 12 * The hardware has 64 possible table entries for bridges with one VLAN 13 * ID, one flow id and a list of ports for each bridge. All entries which 14 * match the same flow ID are combined in the mac learning table, they 15 * act as one global bridge. 16 * The hardware does not support VLAN filter on the port, but on the 17 * bridge, this driver converts the DSA model to the hardware. 18 * 19 * The CPU gets all the exception frames which do not match any forwarding 20 * rule and the CPU port is also added to all bridges. This makes it possible 21 * to handle all the special cases easily in software. 22 * At the initialization the driver allocates one bridge table entry for 23 * each switch port which is used when the port is used without an 24 * explicit bridge. This prevents the frames from being forwarded 25 * between all LAN ports by default. 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 #include <linux/etherdevice.h> 31 #include <linux/firmware.h> 32 #include <linux/if_bridge.h> 33 #include <linux/if_vlan.h> 34 #include <linux/iopoll.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/module.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/of_platform.h> 40 #include <linux/phy.h> 41 #include <linux/phylink.h> 42 #include <linux/platform_device.h> 43 #include <linux/regmap.h> 44 #include <linux/reset.h> 45 #include <net/dsa.h> 46 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 47 48 #include "lantiq_pce.h" 49 50 /* GSWIP MDIO Registers */ 51 #define GSWIP_MDIO_GLOB 0x00 52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 53 #define GSWIP_MDIO_CTRL 0x08 54 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 55 #define GSWIP_MDIO_CTRL_RD BIT(11) 56 #define GSWIP_MDIO_CTRL_WR BIT(10) 57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 60 #define GSWIP_MDIO_READ 0x09 61 #define GSWIP_MDIO_WRITE 0x0A 62 #define GSWIP_MDIO_MDC_CFG0 0x0B 63 #define GSWIP_MDIO_MDC_CFG1 0x0C 64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 88 GSWIP_MDIO_PHY_FCONRX_MASK | \ 89 GSWIP_MDIO_PHY_FCONTX_MASK | \ 90 GSWIP_MDIO_PHY_LINK_MASK | \ 91 GSWIP_MDIO_PHY_SPEED_MASK | \ 92 GSWIP_MDIO_PHY_FDUP_MASK) 93 94 /* GSWIP MII Registers */ 95 #define GSWIP_MII_CFGp(p) (0x2 * (p)) 96 #define GSWIP_MII_CFG_EN BIT(14) 97 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 98 #define GSWIP_MII_CFG_MODE_MIIP 0x0 99 #define GSWIP_MII_CFG_MODE_MIIM 0x1 100 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 101 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 102 #define GSWIP_MII_CFG_MODE_RGMII 0x4 103 #define GSWIP_MII_CFG_MODE_GMII 0x9 104 #define GSWIP_MII_CFG_MODE_MASK 0xf 105 #define GSWIP_MII_CFG_RATE_M2P5 0x00 106 #define GSWIP_MII_CFG_RATE_M25 0x10 107 #define GSWIP_MII_CFG_RATE_M125 0x20 108 #define GSWIP_MII_CFG_RATE_M50 0x30 109 #define GSWIP_MII_CFG_RATE_AUTO 0x40 110 #define GSWIP_MII_CFG_RATE_MASK 0x70 111 #define GSWIP_MII_PCDU0 0x01 112 #define GSWIP_MII_PCDU1 0x03 113 #define GSWIP_MII_PCDU5 0x05 114 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 115 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 116 117 /* GSWIP Core Registers */ 118 #define GSWIP_SWRES 0x000 119 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 120 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 121 #define GSWIP_VERSION 0x013 122 #define GSWIP_VERSION_REV_SHIFT 0 123 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 124 #define GSWIP_VERSION_MOD_SHIFT 8 125 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 126 #define GSWIP_VERSION_2_0 0x100 127 #define GSWIP_VERSION_2_1 0x021 128 #define GSWIP_VERSION_2_2 0x122 129 #define GSWIP_VERSION_2_2_ETC 0x022 130 131 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 132 #define GSWIP_BM_RAM_ADDR 0x044 133 #define GSWIP_BM_RAM_CTRL 0x045 134 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 135 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 136 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 137 #define GSWIP_BM_QUEUE_GCTRL 0x04A 138 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 139 /* buffer management Port Configuration Register */ 140 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 141 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 142 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 143 /* buffer management Port Control Register */ 144 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 145 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 146 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 147 148 /* PCE */ 149 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 150 #define GSWIP_PCE_TBL_MASK 0x448 151 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 152 #define GSWIP_PCE_TBL_ADDR 0x44E 153 #define GSWIP_PCE_TBL_CTRL 0x44F 154 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 155 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 156 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 157 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 158 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 159 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 160 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 161 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 162 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 163 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 164 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 165 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 166 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 167 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 168 #define GSWIP_PCE_GCTRL_0 0x456 169 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ 170 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 171 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 172 #define GSWIP_PCE_GCTRL_1 0x457 173 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 174 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 175 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 176 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ 177 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ 178 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ 179 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 180 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 181 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 182 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 183 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 184 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 185 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) 186 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ 187 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ 188 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ 189 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ 190 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ 191 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) 192 193 #define GSWIP_MAC_FLEN 0x8C5 194 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 195 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 196 197 /* Ethernet Switch Fetch DMA Port Control Register */ 198 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 199 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 200 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 201 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 202 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 203 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 204 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 205 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 206 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 207 208 /* Ethernet Switch Store DMA Port Control Register */ 209 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 210 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 211 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 212 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */ 213 214 #define GSWIP_TABLE_ACTIVE_VLAN 0x01 215 #define GSWIP_TABLE_VLAN_MAPPING 0x02 216 #define GSWIP_TABLE_MAC_BRIDGE 0x0b 217 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ 218 219 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 220 221 struct gswip_hw_info { 222 int max_ports; 223 int cpu_port; 224 const struct dsa_switch_ops *ops; 225 }; 226 227 struct xway_gphy_match_data { 228 char *fe_firmware_name; 229 char *ge_firmware_name; 230 }; 231 232 struct gswip_gphy_fw { 233 struct clk *clk_gate; 234 struct reset_control *reset; 235 u32 fw_addr_offset; 236 char *fw_name; 237 }; 238 239 struct gswip_vlan { 240 struct net_device *bridge; 241 u16 vid; 242 u8 fid; 243 }; 244 245 struct gswip_priv { 246 __iomem void *gswip; 247 __iomem void *mdio; 248 __iomem void *mii; 249 const struct gswip_hw_info *hw_info; 250 const struct xway_gphy_match_data *gphy_fw_name_cfg; 251 struct dsa_switch *ds; 252 struct device *dev; 253 struct regmap *rcu_regmap; 254 struct gswip_vlan vlans[64]; 255 int num_gphy_fw; 256 struct gswip_gphy_fw *gphy_fw; 257 u32 port_vlan_filter; 258 }; 259 260 struct gswip_pce_table_entry { 261 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index 262 u16 table; // PCE_TBL_CTRL.ADDR = pData->table 263 u16 key[8]; 264 u16 val[5]; 265 u16 mask; 266 u8 gmap; 267 bool type; 268 bool valid; 269 bool key_mode; 270 }; 271 272 struct gswip_rmon_cnt_desc { 273 unsigned int size; 274 unsigned int offset; 275 const char *name; 276 }; 277 278 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 279 280 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 281 /** Receive Packet Count (only packets that are accepted and not discarded). */ 282 MIB_DESC(1, 0x1F, "RxGoodPkts"), 283 MIB_DESC(1, 0x23, "RxUnicastPkts"), 284 MIB_DESC(1, 0x22, "RxMulticastPkts"), 285 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 286 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 287 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 288 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 289 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 290 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 291 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 292 MIB_DESC(1, 0x12, "Rx64BytePkts"), 293 MIB_DESC(1, 0x13, "Rx127BytePkts"), 294 MIB_DESC(1, 0x14, "Rx255BytePkts"), 295 MIB_DESC(1, 0x15, "Rx511BytePkts"), 296 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 297 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 298 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 299 MIB_DESC(1, 0x18, "RxDroppedPkts"), 300 MIB_DESC(1, 0x19, "RxFilteredPkts"), 301 MIB_DESC(2, 0x24, "RxGoodBytes"), 302 MIB_DESC(2, 0x26, "RxBadBytes"), 303 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 304 MIB_DESC(1, 0x0C, "TxGoodPkts"), 305 MIB_DESC(1, 0x06, "TxUnicastPkts"), 306 MIB_DESC(1, 0x07, "TxMulticastPkts"), 307 MIB_DESC(1, 0x00, "Tx64BytePkts"), 308 MIB_DESC(1, 0x01, "Tx127BytePkts"), 309 MIB_DESC(1, 0x02, "Tx255BytePkts"), 310 MIB_DESC(1, 0x03, "Tx511BytePkts"), 311 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 312 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 313 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 314 MIB_DESC(1, 0x08, "TxSingleCollCount"), 315 MIB_DESC(1, 0x09, "TxMultCollCount"), 316 MIB_DESC(1, 0x0A, "TxLateCollCount"), 317 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 318 MIB_DESC(1, 0x0D, "TxPauseCount"), 319 MIB_DESC(1, 0x10, "TxDroppedPkts"), 320 MIB_DESC(2, 0x0E, "TxGoodBytes"), 321 }; 322 323 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 324 { 325 return __raw_readl(priv->gswip + (offset * 4)); 326 } 327 328 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 329 { 330 __raw_writel(val, priv->gswip + (offset * 4)); 331 } 332 333 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 334 u32 offset) 335 { 336 u32 val = gswip_switch_r(priv, offset); 337 338 val &= ~(clear); 339 val |= set; 340 gswip_switch_w(priv, val, offset); 341 } 342 343 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 344 u32 cleared) 345 { 346 u32 val; 347 348 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 349 (val & cleared) == 0, 20, 50000); 350 } 351 352 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 353 { 354 return __raw_readl(priv->mdio + (offset * 4)); 355 } 356 357 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 358 { 359 __raw_writel(val, priv->mdio + (offset * 4)); 360 } 361 362 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 363 u32 offset) 364 { 365 u32 val = gswip_mdio_r(priv, offset); 366 367 val &= ~(clear); 368 val |= set; 369 gswip_mdio_w(priv, val, offset); 370 } 371 372 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 373 { 374 return __raw_readl(priv->mii + (offset * 4)); 375 } 376 377 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 378 { 379 __raw_writel(val, priv->mii + (offset * 4)); 380 } 381 382 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 383 u32 offset) 384 { 385 u32 val = gswip_mii_r(priv, offset); 386 387 val &= ~(clear); 388 val |= set; 389 gswip_mii_w(priv, val, offset); 390 } 391 392 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 393 int port) 394 { 395 /* There's no MII_CFG register for the CPU port */ 396 if (!dsa_is_cpu_port(priv->ds, port)) 397 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); 398 } 399 400 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 401 int port) 402 { 403 switch (port) { 404 case 0: 405 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 406 break; 407 case 1: 408 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 409 break; 410 case 5: 411 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 412 break; 413 } 414 } 415 416 static int gswip_mdio_poll(struct gswip_priv *priv) 417 { 418 int cnt = 100; 419 420 while (likely(cnt--)) { 421 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 422 423 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 424 return 0; 425 usleep_range(20, 40); 426 } 427 428 return -ETIMEDOUT; 429 } 430 431 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 432 { 433 struct gswip_priv *priv = bus->priv; 434 int err; 435 436 err = gswip_mdio_poll(priv); 437 if (err) { 438 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 439 return err; 440 } 441 442 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 443 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 444 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 445 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 446 GSWIP_MDIO_CTRL); 447 448 return 0; 449 } 450 451 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 452 { 453 struct gswip_priv *priv = bus->priv; 454 int err; 455 456 err = gswip_mdio_poll(priv); 457 if (err) { 458 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 459 return err; 460 } 461 462 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 463 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 464 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 465 GSWIP_MDIO_CTRL); 466 467 err = gswip_mdio_poll(priv); 468 if (err) { 469 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 470 return err; 471 } 472 473 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 474 } 475 476 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np) 477 { 478 struct dsa_switch *ds = priv->ds; 479 480 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev); 481 if (!ds->slave_mii_bus) 482 return -ENOMEM; 483 484 ds->slave_mii_bus->priv = priv; 485 ds->slave_mii_bus->read = gswip_mdio_rd; 486 ds->slave_mii_bus->write = gswip_mdio_wr; 487 ds->slave_mii_bus->name = "lantiq,xrx200-mdio"; 488 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", 489 dev_name(priv->dev)); 490 ds->slave_mii_bus->parent = priv->dev; 491 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask; 492 493 return of_mdiobus_register(ds->slave_mii_bus, mdio_np); 494 } 495 496 static int gswip_pce_table_entry_read(struct gswip_priv *priv, 497 struct gswip_pce_table_entry *tbl) 498 { 499 int i; 500 int err; 501 u16 crtl; 502 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 503 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 504 505 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 506 GSWIP_PCE_TBL_CTRL_BAS); 507 if (err) 508 return err; 509 510 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 511 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 512 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 513 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 514 GSWIP_PCE_TBL_CTRL); 515 516 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 517 GSWIP_PCE_TBL_CTRL_BAS); 518 if (err) 519 return err; 520 521 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 522 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 523 524 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 525 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 526 527 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 528 529 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 530 531 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 532 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 533 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 534 535 return 0; 536 } 537 538 static int gswip_pce_table_entry_write(struct gswip_priv *priv, 539 struct gswip_pce_table_entry *tbl) 540 { 541 int i; 542 int err; 543 u16 crtl; 544 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 545 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 546 547 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 548 GSWIP_PCE_TBL_CTRL_BAS); 549 if (err) 550 return err; 551 552 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 553 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 554 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 555 tbl->table | addr_mode, 556 GSWIP_PCE_TBL_CTRL); 557 558 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 559 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 560 561 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 562 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 563 564 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 565 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 566 tbl->table | addr_mode, 567 GSWIP_PCE_TBL_CTRL); 568 569 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 570 571 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 572 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 573 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 574 if (tbl->type) 575 crtl |= GSWIP_PCE_TBL_CTRL_TYPE; 576 if (tbl->valid) 577 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 578 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 579 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 580 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 581 582 return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 583 GSWIP_PCE_TBL_CTRL_BAS); 584 } 585 586 /* Add the LAN port into a bridge with the CPU port by 587 * default. This prevents automatic forwarding of 588 * packages between the LAN ports when no explicit 589 * bridge is configured. 590 */ 591 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) 592 { 593 struct gswip_pce_table_entry vlan_active = {0,}; 594 struct gswip_pce_table_entry vlan_mapping = {0,}; 595 unsigned int cpu_port = priv->hw_info->cpu_port; 596 unsigned int max_ports = priv->hw_info->max_ports; 597 int err; 598 599 if (port >= max_ports) { 600 dev_err(priv->dev, "single port for %i supported\n", port); 601 return -EIO; 602 } 603 604 vlan_active.index = port + 1; 605 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 606 vlan_active.key[0] = 0; /* vid */ 607 vlan_active.val[0] = port + 1 /* fid */; 608 vlan_active.valid = add; 609 err = gswip_pce_table_entry_write(priv, &vlan_active); 610 if (err) { 611 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 612 return err; 613 } 614 615 if (!add) 616 return 0; 617 618 vlan_mapping.index = port + 1; 619 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 620 vlan_mapping.val[0] = 0 /* vid */; 621 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); 622 vlan_mapping.val[2] = 0; 623 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 624 if (err) { 625 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 626 return err; 627 } 628 629 return 0; 630 } 631 632 static int gswip_port_enable(struct dsa_switch *ds, int port, 633 struct phy_device *phydev) 634 { 635 struct gswip_priv *priv = ds->priv; 636 int err; 637 638 if (!dsa_is_user_port(ds, port)) 639 return 0; 640 641 if (!dsa_is_cpu_port(ds, port)) { 642 err = gswip_add_single_port_br(priv, port, true); 643 if (err) 644 return err; 645 } 646 647 /* RMON Counter Enable for port */ 648 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 649 650 /* enable port fetch/store dma & VLAN Modification */ 651 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 652 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 653 GSWIP_FDMA_PCTRLp(port)); 654 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 655 GSWIP_SDMA_PCTRLp(port)); 656 657 if (!dsa_is_cpu_port(ds, port)) { 658 u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO | 659 GSWIP_MDIO_PHY_SPEED_AUTO | 660 GSWIP_MDIO_PHY_FDUP_AUTO | 661 GSWIP_MDIO_PHY_FCONTX_AUTO | 662 GSWIP_MDIO_PHY_FCONRX_AUTO | 663 (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK); 664 665 gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port)); 666 /* Activate MDIO auto polling */ 667 gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0); 668 } 669 670 return 0; 671 } 672 673 static void gswip_port_disable(struct dsa_switch *ds, int port) 674 { 675 struct gswip_priv *priv = ds->priv; 676 677 if (!dsa_is_user_port(ds, port)) 678 return; 679 680 if (!dsa_is_cpu_port(ds, port)) { 681 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_DOWN, 682 GSWIP_MDIO_PHY_LINK_MASK, 683 GSWIP_MDIO_PHYp(port)); 684 /* Deactivate MDIO auto polling */ 685 gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0); 686 } 687 688 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 689 GSWIP_FDMA_PCTRLp(port)); 690 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 691 GSWIP_SDMA_PCTRLp(port)); 692 } 693 694 static int gswip_pce_load_microcode(struct gswip_priv *priv) 695 { 696 int i; 697 int err; 698 699 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 700 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 701 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 702 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 703 704 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { 705 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 706 gswip_switch_w(priv, gswip_pce_microcode[i].val_0, 707 GSWIP_PCE_TBL_VAL(0)); 708 gswip_switch_w(priv, gswip_pce_microcode[i].val_1, 709 GSWIP_PCE_TBL_VAL(1)); 710 gswip_switch_w(priv, gswip_pce_microcode[i].val_2, 711 GSWIP_PCE_TBL_VAL(2)); 712 gswip_switch_w(priv, gswip_pce_microcode[i].val_3, 713 GSWIP_PCE_TBL_VAL(3)); 714 715 /* start the table access: */ 716 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 717 GSWIP_PCE_TBL_CTRL); 718 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 719 GSWIP_PCE_TBL_CTRL_BAS); 720 if (err) 721 return err; 722 } 723 724 /* tell the switch that the microcode is loaded */ 725 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 726 GSWIP_PCE_GCTRL_0); 727 728 return 0; 729 } 730 731 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 732 bool vlan_filtering, 733 struct netlink_ext_ack *extack) 734 { 735 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 736 struct gswip_priv *priv = ds->priv; 737 738 /* Do not allow changing the VLAN filtering options while in bridge */ 739 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { 740 NL_SET_ERR_MSG_MOD(extack, 741 "Dynamic toggling of vlan_filtering not supported"); 742 return -EIO; 743 } 744 745 if (vlan_filtering) { 746 /* Use port based VLAN tag */ 747 gswip_switch_mask(priv, 748 GSWIP_PCE_VCTRL_VSR, 749 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 750 GSWIP_PCE_VCTRL_VEMR, 751 GSWIP_PCE_VCTRL(port)); 752 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 753 GSWIP_PCE_PCTRL_0p(port)); 754 } else { 755 /* Use port based VLAN tag */ 756 gswip_switch_mask(priv, 757 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 758 GSWIP_PCE_VCTRL_VEMR, 759 GSWIP_PCE_VCTRL_VSR, 760 GSWIP_PCE_VCTRL(port)); 761 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 762 GSWIP_PCE_PCTRL_0p(port)); 763 } 764 765 return 0; 766 } 767 768 static int gswip_setup(struct dsa_switch *ds) 769 { 770 struct gswip_priv *priv = ds->priv; 771 unsigned int cpu_port = priv->hw_info->cpu_port; 772 int i; 773 int err; 774 775 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 776 usleep_range(5000, 10000); 777 gswip_switch_w(priv, 0, GSWIP_SWRES); 778 779 /* disable port fetch/store dma on all ports */ 780 for (i = 0; i < priv->hw_info->max_ports; i++) { 781 gswip_port_disable(ds, i); 782 gswip_port_vlan_filtering(ds, i, false, NULL); 783 } 784 785 /* enable Switch */ 786 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 787 788 err = gswip_pce_load_microcode(priv); 789 if (err) { 790 dev_err(priv->dev, "writing PCE microcode failed, %i", err); 791 return err; 792 } 793 794 /* Default unknown Broadcast/Multicast/Unicast port maps */ 795 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); 796 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); 797 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); 798 799 /* disable PHY auto polling */ 800 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 801 /* Configure the MDIO Clock 2.5 MHz */ 802 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 803 804 /* Disable the xMII link */ 805 for (i = 0; i < priv->hw_info->max_ports; i++) 806 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i); 807 808 /* enable special tag insertion on cpu port */ 809 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 810 GSWIP_FDMA_PCTRLp(cpu_port)); 811 812 /* accept special tag in ingress direction */ 813 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 814 GSWIP_PCE_PCTRL_0p(cpu_port)); 815 816 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 817 GSWIP_MAC_CTRL_2p(cpu_port)); 818 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8, GSWIP_MAC_FLEN); 819 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 820 GSWIP_BM_QUEUE_GCTRL); 821 822 /* VLAN aware Switching */ 823 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 824 825 /* Flush MAC Table */ 826 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 827 828 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 829 GSWIP_PCE_GCTRL_0_MTFL); 830 if (err) { 831 dev_err(priv->dev, "MAC flushing didn't finish\n"); 832 return err; 833 } 834 835 gswip_port_enable(ds, cpu_port, NULL); 836 837 ds->configure_vlan_while_not_filtering = false; 838 839 return 0; 840 } 841 842 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 843 int port, 844 enum dsa_tag_protocol mp) 845 { 846 return DSA_TAG_PROTO_GSWIP; 847 } 848 849 static int gswip_vlan_active_create(struct gswip_priv *priv, 850 struct net_device *bridge, 851 int fid, u16 vid) 852 { 853 struct gswip_pce_table_entry vlan_active = {0,}; 854 unsigned int max_ports = priv->hw_info->max_ports; 855 int idx = -1; 856 int err; 857 int i; 858 859 /* Look for a free slot */ 860 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 861 if (!priv->vlans[i].bridge) { 862 idx = i; 863 break; 864 } 865 } 866 867 if (idx == -1) 868 return -ENOSPC; 869 870 if (fid == -1) 871 fid = idx; 872 873 vlan_active.index = idx; 874 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 875 vlan_active.key[0] = vid; 876 vlan_active.val[0] = fid; 877 vlan_active.valid = true; 878 879 err = gswip_pce_table_entry_write(priv, &vlan_active); 880 if (err) { 881 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 882 return err; 883 } 884 885 priv->vlans[idx].bridge = bridge; 886 priv->vlans[idx].vid = vid; 887 priv->vlans[idx].fid = fid; 888 889 return idx; 890 } 891 892 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) 893 { 894 struct gswip_pce_table_entry vlan_active = {0,}; 895 int err; 896 897 vlan_active.index = idx; 898 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 899 vlan_active.valid = false; 900 err = gswip_pce_table_entry_write(priv, &vlan_active); 901 if (err) 902 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); 903 priv->vlans[idx].bridge = NULL; 904 905 return err; 906 } 907 908 static int gswip_vlan_add_unaware(struct gswip_priv *priv, 909 struct net_device *bridge, int port) 910 { 911 struct gswip_pce_table_entry vlan_mapping = {0,}; 912 unsigned int max_ports = priv->hw_info->max_ports; 913 unsigned int cpu_port = priv->hw_info->cpu_port; 914 bool active_vlan_created = false; 915 int idx = -1; 916 int i; 917 int err; 918 919 /* Check if there is already a page for this bridge */ 920 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 921 if (priv->vlans[i].bridge == bridge) { 922 idx = i; 923 break; 924 } 925 } 926 927 /* If this bridge is not programmed yet, add a Active VLAN table 928 * entry in a free slot and prepare the VLAN mapping table entry. 929 */ 930 if (idx == -1) { 931 idx = gswip_vlan_active_create(priv, bridge, -1, 0); 932 if (idx < 0) 933 return idx; 934 active_vlan_created = true; 935 936 vlan_mapping.index = idx; 937 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 938 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 939 vlan_mapping.val[0] = 0; 940 } else { 941 /* Read the existing VLAN mapping entry from the switch */ 942 vlan_mapping.index = idx; 943 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 944 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 945 if (err) { 946 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 947 err); 948 return err; 949 } 950 } 951 952 /* Update the VLAN mapping entry and write it to the switch */ 953 vlan_mapping.val[1] |= BIT(cpu_port); 954 vlan_mapping.val[1] |= BIT(port); 955 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 956 if (err) { 957 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 958 /* In case an Active VLAN was creaetd delete it again */ 959 if (active_vlan_created) 960 gswip_vlan_active_remove(priv, idx); 961 return err; 962 } 963 964 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 965 return 0; 966 } 967 968 static int gswip_vlan_add_aware(struct gswip_priv *priv, 969 struct net_device *bridge, int port, 970 u16 vid, bool untagged, 971 bool pvid) 972 { 973 struct gswip_pce_table_entry vlan_mapping = {0,}; 974 unsigned int max_ports = priv->hw_info->max_ports; 975 unsigned int cpu_port = priv->hw_info->cpu_port; 976 bool active_vlan_created = false; 977 int idx = -1; 978 int fid = -1; 979 int i; 980 int err; 981 982 /* Check if there is already a page for this bridge */ 983 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 984 if (priv->vlans[i].bridge == bridge) { 985 if (fid != -1 && fid != priv->vlans[i].fid) 986 dev_err(priv->dev, "one bridge with multiple flow ids\n"); 987 fid = priv->vlans[i].fid; 988 if (priv->vlans[i].vid == vid) { 989 idx = i; 990 break; 991 } 992 } 993 } 994 995 /* If this bridge is not programmed yet, add a Active VLAN table 996 * entry in a free slot and prepare the VLAN mapping table entry. 997 */ 998 if (idx == -1) { 999 idx = gswip_vlan_active_create(priv, bridge, fid, vid); 1000 if (idx < 0) 1001 return idx; 1002 active_vlan_created = true; 1003 1004 vlan_mapping.index = idx; 1005 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1006 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 1007 vlan_mapping.val[0] = vid; 1008 } else { 1009 /* Read the existing VLAN mapping entry from the switch */ 1010 vlan_mapping.index = idx; 1011 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1012 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1013 if (err) { 1014 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 1015 err); 1016 return err; 1017 } 1018 } 1019 1020 vlan_mapping.val[0] = vid; 1021 /* Update the VLAN mapping entry and write it to the switch */ 1022 vlan_mapping.val[1] |= BIT(cpu_port); 1023 vlan_mapping.val[2] |= BIT(cpu_port); 1024 vlan_mapping.val[1] |= BIT(port); 1025 if (untagged) 1026 vlan_mapping.val[2] &= ~BIT(port); 1027 else 1028 vlan_mapping.val[2] |= BIT(port); 1029 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1030 if (err) { 1031 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1032 /* In case an Active VLAN was creaetd delete it again */ 1033 if (active_vlan_created) 1034 gswip_vlan_active_remove(priv, idx); 1035 return err; 1036 } 1037 1038 if (pvid) 1039 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 1040 1041 return 0; 1042 } 1043 1044 static int gswip_vlan_remove(struct gswip_priv *priv, 1045 struct net_device *bridge, int port, 1046 u16 vid, bool pvid, bool vlan_aware) 1047 { 1048 struct gswip_pce_table_entry vlan_mapping = {0,}; 1049 unsigned int max_ports = priv->hw_info->max_ports; 1050 unsigned int cpu_port = priv->hw_info->cpu_port; 1051 int idx = -1; 1052 int i; 1053 int err; 1054 1055 /* Check if there is already a page for this bridge */ 1056 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1057 if (priv->vlans[i].bridge == bridge && 1058 (!vlan_aware || priv->vlans[i].vid == vid)) { 1059 idx = i; 1060 break; 1061 } 1062 } 1063 1064 if (idx == -1) { 1065 dev_err(priv->dev, "bridge to leave does not exists\n"); 1066 return -ENOENT; 1067 } 1068 1069 vlan_mapping.index = idx; 1070 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1071 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1072 if (err) { 1073 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); 1074 return err; 1075 } 1076 1077 vlan_mapping.val[1] &= ~BIT(port); 1078 vlan_mapping.val[2] &= ~BIT(port); 1079 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1080 if (err) { 1081 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1082 return err; 1083 } 1084 1085 /* In case all ports are removed from the bridge, remove the VLAN */ 1086 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { 1087 err = gswip_vlan_active_remove(priv, idx); 1088 if (err) { 1089 dev_err(priv->dev, "failed to write active VLAN: %d\n", 1090 err); 1091 return err; 1092 } 1093 } 1094 1095 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 1096 if (pvid) 1097 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1098 1099 return 0; 1100 } 1101 1102 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, 1103 struct net_device *bridge) 1104 { 1105 struct gswip_priv *priv = ds->priv; 1106 int err; 1107 1108 /* When the bridge uses VLAN filtering we have to configure VLAN 1109 * specific bridges. No bridge is configured here. 1110 */ 1111 if (!br_vlan_enabled(bridge)) { 1112 err = gswip_vlan_add_unaware(priv, bridge, port); 1113 if (err) 1114 return err; 1115 priv->port_vlan_filter &= ~BIT(port); 1116 } else { 1117 priv->port_vlan_filter |= BIT(port); 1118 } 1119 return gswip_add_single_port_br(priv, port, false); 1120 } 1121 1122 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, 1123 struct net_device *bridge) 1124 { 1125 struct gswip_priv *priv = ds->priv; 1126 1127 gswip_add_single_port_br(priv, port, true); 1128 1129 /* When the bridge uses VLAN filtering we have to configure VLAN 1130 * specific bridges. No bridge is configured here. 1131 */ 1132 if (!br_vlan_enabled(bridge)) 1133 gswip_vlan_remove(priv, bridge, port, 0, true, false); 1134 } 1135 1136 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, 1137 const struct switchdev_obj_port_vlan *vlan, 1138 struct netlink_ext_ack *extack) 1139 { 1140 struct gswip_priv *priv = ds->priv; 1141 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1142 unsigned int max_ports = priv->hw_info->max_ports; 1143 int pos = max_ports; 1144 int i, idx = -1; 1145 1146 /* We only support VLAN filtering on bridges */ 1147 if (!dsa_is_cpu_port(ds, port) && !bridge) 1148 return -EOPNOTSUPP; 1149 1150 /* Check if there is already a page for this VLAN */ 1151 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1152 if (priv->vlans[i].bridge == bridge && 1153 priv->vlans[i].vid == vlan->vid) { 1154 idx = i; 1155 break; 1156 } 1157 } 1158 1159 /* If this VLAN is not programmed yet, we have to reserve 1160 * one entry in the VLAN table. Make sure we start at the 1161 * next position round. 1162 */ 1163 if (idx == -1) { 1164 /* Look for a free slot */ 1165 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { 1166 if (!priv->vlans[pos].bridge) { 1167 idx = pos; 1168 pos++; 1169 break; 1170 } 1171 } 1172 1173 if (idx == -1) { 1174 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table"); 1175 return -ENOSPC; 1176 } 1177 } 1178 1179 return 0; 1180 } 1181 1182 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, 1183 const struct switchdev_obj_port_vlan *vlan, 1184 struct netlink_ext_ack *extack) 1185 { 1186 struct gswip_priv *priv = ds->priv; 1187 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1188 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1189 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1190 int err; 1191 1192 err = gswip_port_vlan_prepare(ds, port, vlan, extack); 1193 if (err) 1194 return err; 1195 1196 /* We have to receive all packets on the CPU port and should not 1197 * do any VLAN filtering here. This is also called with bridge 1198 * NULL and then we do not know for which bridge to configure 1199 * this. 1200 */ 1201 if (dsa_is_cpu_port(ds, port)) 1202 return 0; 1203 1204 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, 1205 untagged, pvid); 1206 } 1207 1208 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, 1209 const struct switchdev_obj_port_vlan *vlan) 1210 { 1211 struct gswip_priv *priv = ds->priv; 1212 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1213 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1214 1215 /* We have to receive all packets on the CPU port and should not 1216 * do any VLAN filtering here. This is also called with bridge 1217 * NULL and then we do not know for which bridge to configure 1218 * this. 1219 */ 1220 if (dsa_is_cpu_port(ds, port)) 1221 return 0; 1222 1223 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); 1224 } 1225 1226 static void gswip_port_fast_age(struct dsa_switch *ds, int port) 1227 { 1228 struct gswip_priv *priv = ds->priv; 1229 struct gswip_pce_table_entry mac_bridge = {0,}; 1230 int i; 1231 int err; 1232 1233 for (i = 0; i < 2048; i++) { 1234 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1235 mac_bridge.index = i; 1236 1237 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1238 if (err) { 1239 dev_err(priv->dev, "failed to read mac bridge: %d\n", 1240 err); 1241 return; 1242 } 1243 1244 if (!mac_bridge.valid) 1245 continue; 1246 1247 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) 1248 continue; 1249 1250 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) 1251 continue; 1252 1253 mac_bridge.valid = false; 1254 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1255 if (err) { 1256 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1257 err); 1258 return; 1259 } 1260 } 1261 } 1262 1263 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1264 { 1265 struct gswip_priv *priv = ds->priv; 1266 u32 stp_state; 1267 1268 switch (state) { 1269 case BR_STATE_DISABLED: 1270 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1271 GSWIP_SDMA_PCTRLp(port)); 1272 return; 1273 case BR_STATE_BLOCKING: 1274 case BR_STATE_LISTENING: 1275 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; 1276 break; 1277 case BR_STATE_LEARNING: 1278 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; 1279 break; 1280 case BR_STATE_FORWARDING: 1281 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; 1282 break; 1283 default: 1284 dev_err(priv->dev, "invalid STP state: %d\n", state); 1285 return; 1286 } 1287 1288 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1289 GSWIP_SDMA_PCTRLp(port)); 1290 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1291 GSWIP_PCE_PCTRL_0p(port)); 1292 } 1293 1294 static int gswip_port_fdb(struct dsa_switch *ds, int port, 1295 const unsigned char *addr, u16 vid, bool add) 1296 { 1297 struct gswip_priv *priv = ds->priv; 1298 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1299 struct gswip_pce_table_entry mac_bridge = {0,}; 1300 unsigned int cpu_port = priv->hw_info->cpu_port; 1301 int fid = -1; 1302 int i; 1303 int err; 1304 1305 if (!bridge) 1306 return -EINVAL; 1307 1308 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) { 1309 if (priv->vlans[i].bridge == bridge) { 1310 fid = priv->vlans[i].fid; 1311 break; 1312 } 1313 } 1314 1315 if (fid == -1) { 1316 dev_err(priv->dev, "Port not part of a bridge\n"); 1317 return -EINVAL; 1318 } 1319 1320 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1321 mac_bridge.key_mode = true; 1322 mac_bridge.key[0] = addr[5] | (addr[4] << 8); 1323 mac_bridge.key[1] = addr[3] | (addr[2] << 8); 1324 mac_bridge.key[2] = addr[1] | (addr[0] << 8); 1325 mac_bridge.key[3] = fid; 1326 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ 1327 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; 1328 mac_bridge.valid = add; 1329 1330 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1331 if (err) 1332 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); 1333 1334 return err; 1335 } 1336 1337 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, 1338 const unsigned char *addr, u16 vid) 1339 { 1340 return gswip_port_fdb(ds, port, addr, vid, true); 1341 } 1342 1343 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, 1344 const unsigned char *addr, u16 vid) 1345 { 1346 return gswip_port_fdb(ds, port, addr, vid, false); 1347 } 1348 1349 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, 1350 dsa_fdb_dump_cb_t *cb, void *data) 1351 { 1352 struct gswip_priv *priv = ds->priv; 1353 struct gswip_pce_table_entry mac_bridge = {0,}; 1354 unsigned char addr[6]; 1355 int i; 1356 int err; 1357 1358 for (i = 0; i < 2048; i++) { 1359 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1360 mac_bridge.index = i; 1361 1362 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1363 if (err) { 1364 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1365 err); 1366 return err; 1367 } 1368 1369 if (!mac_bridge.valid) 1370 continue; 1371 1372 addr[5] = mac_bridge.key[0] & 0xff; 1373 addr[4] = (mac_bridge.key[0] >> 8) & 0xff; 1374 addr[3] = mac_bridge.key[1] & 0xff; 1375 addr[2] = (mac_bridge.key[1] >> 8) & 0xff; 1376 addr[1] = mac_bridge.key[2] & 0xff; 1377 addr[0] = (mac_bridge.key[2] >> 8) & 0xff; 1378 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { 1379 if (mac_bridge.val[0] & BIT(port)) 1380 cb(addr, 0, true, data); 1381 } else { 1382 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) 1383 cb(addr, 0, false, data); 1384 } 1385 } 1386 return 0; 1387 } 1388 1389 static void gswip_phylink_set_capab(unsigned long *supported, 1390 struct phylink_link_state *state) 1391 { 1392 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1393 1394 /* Allow all the expected bits */ 1395 phylink_set(mask, Autoneg); 1396 phylink_set_port_modes(mask); 1397 phylink_set(mask, Pause); 1398 phylink_set(mask, Asym_Pause); 1399 1400 /* With the exclusion of MII, Reverse MII and Reduced MII, we 1401 * support Gigabit, including Half duplex 1402 */ 1403 if (state->interface != PHY_INTERFACE_MODE_MII && 1404 state->interface != PHY_INTERFACE_MODE_REVMII && 1405 state->interface != PHY_INTERFACE_MODE_RMII) { 1406 phylink_set(mask, 1000baseT_Full); 1407 phylink_set(mask, 1000baseT_Half); 1408 } 1409 1410 phylink_set(mask, 10baseT_Half); 1411 phylink_set(mask, 10baseT_Full); 1412 phylink_set(mask, 100baseT_Half); 1413 phylink_set(mask, 100baseT_Full); 1414 1415 bitmap_and(supported, supported, mask, 1416 __ETHTOOL_LINK_MODE_MASK_NBITS); 1417 bitmap_and(state->advertising, state->advertising, mask, 1418 __ETHTOOL_LINK_MODE_MASK_NBITS); 1419 } 1420 1421 static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port, 1422 unsigned long *supported, 1423 struct phylink_link_state *state) 1424 { 1425 switch (port) { 1426 case 0: 1427 case 1: 1428 if (!phy_interface_mode_is_rgmii(state->interface) && 1429 state->interface != PHY_INTERFACE_MODE_MII && 1430 state->interface != PHY_INTERFACE_MODE_REVMII && 1431 state->interface != PHY_INTERFACE_MODE_RMII) 1432 goto unsupported; 1433 break; 1434 case 2: 1435 case 3: 1436 case 4: 1437 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 1438 goto unsupported; 1439 break; 1440 case 5: 1441 if (!phy_interface_mode_is_rgmii(state->interface) && 1442 state->interface != PHY_INTERFACE_MODE_INTERNAL) 1443 goto unsupported; 1444 break; 1445 default: 1446 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1447 dev_err(ds->dev, "Unsupported port: %i\n", port); 1448 return; 1449 } 1450 1451 gswip_phylink_set_capab(supported, state); 1452 1453 return; 1454 1455 unsupported: 1456 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1457 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", 1458 phy_modes(state->interface), port); 1459 } 1460 1461 static void gswip_xrx300_phylink_validate(struct dsa_switch *ds, int port, 1462 unsigned long *supported, 1463 struct phylink_link_state *state) 1464 { 1465 switch (port) { 1466 case 0: 1467 if (!phy_interface_mode_is_rgmii(state->interface) && 1468 state->interface != PHY_INTERFACE_MODE_GMII && 1469 state->interface != PHY_INTERFACE_MODE_RMII) 1470 goto unsupported; 1471 break; 1472 case 1: 1473 case 2: 1474 case 3: 1475 case 4: 1476 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 1477 goto unsupported; 1478 break; 1479 case 5: 1480 if (!phy_interface_mode_is_rgmii(state->interface) && 1481 state->interface != PHY_INTERFACE_MODE_INTERNAL && 1482 state->interface != PHY_INTERFACE_MODE_RMII) 1483 goto unsupported; 1484 break; 1485 default: 1486 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1487 dev_err(ds->dev, "Unsupported port: %i\n", port); 1488 return; 1489 } 1490 1491 gswip_phylink_set_capab(supported, state); 1492 1493 return; 1494 1495 unsupported: 1496 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1497 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", 1498 phy_modes(state->interface), port); 1499 } 1500 1501 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, 1502 unsigned int mode, 1503 const struct phylink_link_state *state) 1504 { 1505 struct gswip_priv *priv = ds->priv; 1506 u32 miicfg = 0; 1507 1508 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 1509 1510 switch (state->interface) { 1511 case PHY_INTERFACE_MODE_MII: 1512 case PHY_INTERFACE_MODE_INTERNAL: 1513 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 1514 break; 1515 case PHY_INTERFACE_MODE_REVMII: 1516 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 1517 break; 1518 case PHY_INTERFACE_MODE_RMII: 1519 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 1520 break; 1521 case PHY_INTERFACE_MODE_RGMII: 1522 case PHY_INTERFACE_MODE_RGMII_ID: 1523 case PHY_INTERFACE_MODE_RGMII_RXID: 1524 case PHY_INTERFACE_MODE_RGMII_TXID: 1525 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 1526 break; 1527 case PHY_INTERFACE_MODE_GMII: 1528 miicfg |= GSWIP_MII_CFG_MODE_GMII; 1529 break; 1530 default: 1531 dev_err(ds->dev, 1532 "Unsupported interface: %d\n", state->interface); 1533 return; 1534 } 1535 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK, miicfg, port); 1536 1537 switch (state->interface) { 1538 case PHY_INTERFACE_MODE_RGMII_ID: 1539 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 1540 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1541 break; 1542 case PHY_INTERFACE_MODE_RGMII_RXID: 1543 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1544 break; 1545 case PHY_INTERFACE_MODE_RGMII_TXID: 1546 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 1547 break; 1548 default: 1549 break; 1550 } 1551 } 1552 1553 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, 1554 unsigned int mode, 1555 phy_interface_t interface) 1556 { 1557 struct gswip_priv *priv = ds->priv; 1558 1559 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 1560 } 1561 1562 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, 1563 unsigned int mode, 1564 phy_interface_t interface, 1565 struct phy_device *phydev, 1566 int speed, int duplex, 1567 bool tx_pause, bool rx_pause) 1568 { 1569 struct gswip_priv *priv = ds->priv; 1570 1571 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1572 } 1573 1574 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1575 uint8_t *data) 1576 { 1577 int i; 1578 1579 if (stringset != ETH_SS_STATS) 1580 return; 1581 1582 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 1583 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name, 1584 ETH_GSTRING_LEN); 1585 } 1586 1587 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1588 u32 index) 1589 { 1590 u32 result; 1591 int err; 1592 1593 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1594 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1595 GSWIP_BM_RAM_CTRL_OPMOD, 1596 table | GSWIP_BM_RAM_CTRL_BAS, 1597 GSWIP_BM_RAM_CTRL); 1598 1599 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1600 GSWIP_BM_RAM_CTRL_BAS); 1601 if (err) { 1602 dev_err(priv->dev, "timeout while reading table: %u, index: %u", 1603 table, index); 1604 return 0; 1605 } 1606 1607 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1608 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1609 1610 return result; 1611 } 1612 1613 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 1614 uint64_t *data) 1615 { 1616 struct gswip_priv *priv = ds->priv; 1617 const struct gswip_rmon_cnt_desc *rmon_cnt; 1618 int i; 1619 u64 high; 1620 1621 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 1622 rmon_cnt = &gswip_rmon_cnt[i]; 1623 1624 data[i] = gswip_bcm_ram_entry_read(priv, port, 1625 rmon_cnt->offset); 1626 if (rmon_cnt->size == 2) { 1627 high = gswip_bcm_ram_entry_read(priv, port, 1628 rmon_cnt->offset + 1); 1629 data[i] |= high << 32; 1630 } 1631 } 1632 } 1633 1634 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 1635 { 1636 if (sset != ETH_SS_STATS) 1637 return 0; 1638 1639 return ARRAY_SIZE(gswip_rmon_cnt); 1640 } 1641 1642 static const struct dsa_switch_ops gswip_xrx200_switch_ops = { 1643 .get_tag_protocol = gswip_get_tag_protocol, 1644 .setup = gswip_setup, 1645 .port_enable = gswip_port_enable, 1646 .port_disable = gswip_port_disable, 1647 .port_bridge_join = gswip_port_bridge_join, 1648 .port_bridge_leave = gswip_port_bridge_leave, 1649 .port_fast_age = gswip_port_fast_age, 1650 .port_vlan_filtering = gswip_port_vlan_filtering, 1651 .port_vlan_add = gswip_port_vlan_add, 1652 .port_vlan_del = gswip_port_vlan_del, 1653 .port_stp_state_set = gswip_port_stp_state_set, 1654 .port_fdb_add = gswip_port_fdb_add, 1655 .port_fdb_del = gswip_port_fdb_del, 1656 .port_fdb_dump = gswip_port_fdb_dump, 1657 .phylink_validate = gswip_xrx200_phylink_validate, 1658 .phylink_mac_config = gswip_phylink_mac_config, 1659 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1660 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1661 .get_strings = gswip_get_strings, 1662 .get_ethtool_stats = gswip_get_ethtool_stats, 1663 .get_sset_count = gswip_get_sset_count, 1664 }; 1665 1666 static const struct dsa_switch_ops gswip_xrx300_switch_ops = { 1667 .get_tag_protocol = gswip_get_tag_protocol, 1668 .setup = gswip_setup, 1669 .port_enable = gswip_port_enable, 1670 .port_disable = gswip_port_disable, 1671 .port_bridge_join = gswip_port_bridge_join, 1672 .port_bridge_leave = gswip_port_bridge_leave, 1673 .port_fast_age = gswip_port_fast_age, 1674 .port_vlan_filtering = gswip_port_vlan_filtering, 1675 .port_vlan_add = gswip_port_vlan_add, 1676 .port_vlan_del = gswip_port_vlan_del, 1677 .port_stp_state_set = gswip_port_stp_state_set, 1678 .port_fdb_add = gswip_port_fdb_add, 1679 .port_fdb_del = gswip_port_fdb_del, 1680 .port_fdb_dump = gswip_port_fdb_dump, 1681 .phylink_validate = gswip_xrx300_phylink_validate, 1682 .phylink_mac_config = gswip_phylink_mac_config, 1683 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1684 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1685 .get_strings = gswip_get_strings, 1686 .get_ethtool_stats = gswip_get_ethtool_stats, 1687 .get_sset_count = gswip_get_sset_count, 1688 }; 1689 1690 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 1691 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 1692 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 1693 }; 1694 1695 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 1696 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 1697 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 1698 }; 1699 1700 static const struct xway_gphy_match_data xrx300_gphy_data = { 1701 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 1702 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 1703 }; 1704 1705 static const struct of_device_id xway_gphy_match[] = { 1706 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 1707 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 1708 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 1709 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 1710 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 1711 {}, 1712 }; 1713 1714 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 1715 { 1716 struct device *dev = priv->dev; 1717 const struct firmware *fw; 1718 void *fw_addr; 1719 dma_addr_t dma_addr; 1720 dma_addr_t dev_addr; 1721 size_t size; 1722 int ret; 1723 1724 ret = clk_prepare_enable(gphy_fw->clk_gate); 1725 if (ret) 1726 return ret; 1727 1728 reset_control_assert(gphy_fw->reset); 1729 1730 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 1731 if (ret) { 1732 dev_err(dev, "failed to load firmware: %s, error: %i\n", 1733 gphy_fw->fw_name, ret); 1734 return ret; 1735 } 1736 1737 /* GPHY cores need the firmware code in a persistent and contiguous 1738 * memory area with a 16 kB boundary aligned start address. 1739 */ 1740 size = fw->size + XRX200_GPHY_FW_ALIGN; 1741 1742 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 1743 if (fw_addr) { 1744 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 1745 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 1746 memcpy(fw_addr, fw->data, fw->size); 1747 } else { 1748 dev_err(dev, "failed to alloc firmware memory\n"); 1749 release_firmware(fw); 1750 return -ENOMEM; 1751 } 1752 1753 release_firmware(fw); 1754 1755 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 1756 if (ret) 1757 return ret; 1758 1759 reset_control_deassert(gphy_fw->reset); 1760 1761 return ret; 1762 } 1763 1764 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 1765 struct gswip_gphy_fw *gphy_fw, 1766 struct device_node *gphy_fw_np, int i) 1767 { 1768 struct device *dev = priv->dev; 1769 u32 gphy_mode; 1770 int ret; 1771 char gphyname[10]; 1772 1773 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 1774 1775 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 1776 if (IS_ERR(gphy_fw->clk_gate)) { 1777 dev_err(dev, "Failed to lookup gate clock\n"); 1778 return PTR_ERR(gphy_fw->clk_gate); 1779 } 1780 1781 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 1782 if (ret) 1783 return ret; 1784 1785 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 1786 /* Default to GE mode */ 1787 if (ret) 1788 gphy_mode = GPHY_MODE_GE; 1789 1790 switch (gphy_mode) { 1791 case GPHY_MODE_FE: 1792 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 1793 break; 1794 case GPHY_MODE_GE: 1795 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 1796 break; 1797 default: 1798 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); 1799 return -EINVAL; 1800 } 1801 1802 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 1803 if (IS_ERR(gphy_fw->reset)) { 1804 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER) 1805 dev_err(dev, "Failed to lookup gphy reset\n"); 1806 return PTR_ERR(gphy_fw->reset); 1807 } 1808 1809 return gswip_gphy_fw_load(priv, gphy_fw); 1810 } 1811 1812 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 1813 struct gswip_gphy_fw *gphy_fw) 1814 { 1815 int ret; 1816 1817 /* check if the device was fully probed */ 1818 if (!gphy_fw->fw_name) 1819 return; 1820 1821 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 1822 if (ret) 1823 dev_err(priv->dev, "can not reset GPHY FW pointer"); 1824 1825 clk_disable_unprepare(gphy_fw->clk_gate); 1826 1827 reset_control_put(gphy_fw->reset); 1828 } 1829 1830 static int gswip_gphy_fw_list(struct gswip_priv *priv, 1831 struct device_node *gphy_fw_list_np, u32 version) 1832 { 1833 struct device *dev = priv->dev; 1834 struct device_node *gphy_fw_np; 1835 const struct of_device_id *match; 1836 int err; 1837 int i = 0; 1838 1839 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 1840 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 1841 * needs a different GPHY firmware. 1842 */ 1843 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 1844 switch (version) { 1845 case GSWIP_VERSION_2_0: 1846 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 1847 break; 1848 case GSWIP_VERSION_2_1: 1849 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 1850 break; 1851 default: 1852 dev_err(dev, "unknown GSWIP version: 0x%x", version); 1853 return -ENOENT; 1854 } 1855 } 1856 1857 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 1858 if (match && match->data) 1859 priv->gphy_fw_name_cfg = match->data; 1860 1861 if (!priv->gphy_fw_name_cfg) { 1862 dev_err(dev, "GPHY compatible type not supported"); 1863 return -ENOENT; 1864 } 1865 1866 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 1867 if (!priv->num_gphy_fw) 1868 return -ENOENT; 1869 1870 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 1871 "lantiq,rcu"); 1872 if (IS_ERR(priv->rcu_regmap)) 1873 return PTR_ERR(priv->rcu_regmap); 1874 1875 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 1876 sizeof(*priv->gphy_fw), 1877 GFP_KERNEL | __GFP_ZERO); 1878 if (!priv->gphy_fw) 1879 return -ENOMEM; 1880 1881 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 1882 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 1883 gphy_fw_np, i); 1884 if (err) 1885 goto remove_gphy; 1886 i++; 1887 } 1888 1889 /* The standalone PHY11G requires 300ms to be fully 1890 * initialized and ready for any MDIO communication after being 1891 * taken out of reset. For the SoC-internal GPHY variant there 1892 * is no (known) documentation for the minimum time after a 1893 * reset. Use the same value as for the standalone variant as 1894 * some users have reported internal PHYs not being detected 1895 * without any delay. 1896 */ 1897 msleep(300); 1898 1899 return 0; 1900 1901 remove_gphy: 1902 for (i = 0; i < priv->num_gphy_fw; i++) 1903 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1904 return err; 1905 } 1906 1907 static int gswip_probe(struct platform_device *pdev) 1908 { 1909 struct gswip_priv *priv; 1910 struct device_node *np, *mdio_np, *gphy_fw_np; 1911 struct device *dev = &pdev->dev; 1912 int err; 1913 int i; 1914 u32 version; 1915 1916 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1917 if (!priv) 1918 return -ENOMEM; 1919 1920 priv->gswip = devm_platform_ioremap_resource(pdev, 0); 1921 if (IS_ERR(priv->gswip)) 1922 return PTR_ERR(priv->gswip); 1923 1924 priv->mdio = devm_platform_ioremap_resource(pdev, 1); 1925 if (IS_ERR(priv->mdio)) 1926 return PTR_ERR(priv->mdio); 1927 1928 priv->mii = devm_platform_ioremap_resource(pdev, 2); 1929 if (IS_ERR(priv->mii)) 1930 return PTR_ERR(priv->mii); 1931 1932 priv->hw_info = of_device_get_match_data(dev); 1933 if (!priv->hw_info) 1934 return -EINVAL; 1935 1936 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 1937 if (!priv->ds) 1938 return -ENOMEM; 1939 1940 priv->ds->dev = dev; 1941 priv->ds->num_ports = priv->hw_info->max_ports; 1942 priv->ds->priv = priv; 1943 priv->ds->ops = priv->hw_info->ops; 1944 priv->dev = dev; 1945 version = gswip_switch_r(priv, GSWIP_VERSION); 1946 1947 np = dev->of_node; 1948 switch (version) { 1949 case GSWIP_VERSION_2_0: 1950 case GSWIP_VERSION_2_1: 1951 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip")) 1952 return -EINVAL; 1953 break; 1954 case GSWIP_VERSION_2_2: 1955 case GSWIP_VERSION_2_2_ETC: 1956 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") && 1957 !of_device_is_compatible(np, "lantiq,xrx330-gswip")) 1958 return -EINVAL; 1959 break; 1960 default: 1961 dev_err(dev, "unknown GSWIP version: 0x%x", version); 1962 return -ENOENT; 1963 } 1964 1965 /* bring up the mdio bus */ 1966 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 1967 if (gphy_fw_np) { 1968 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 1969 of_node_put(gphy_fw_np); 1970 if (err) { 1971 dev_err(dev, "gphy fw probe failed\n"); 1972 return err; 1973 } 1974 } 1975 1976 /* bring up the mdio bus */ 1977 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio"); 1978 if (mdio_np) { 1979 err = gswip_mdio(priv, mdio_np); 1980 if (err) { 1981 dev_err(dev, "mdio probe failed\n"); 1982 goto put_mdio_node; 1983 } 1984 } 1985 1986 err = dsa_register_switch(priv->ds); 1987 if (err) { 1988 dev_err(dev, "dsa switch register failed: %i\n", err); 1989 goto mdio_bus; 1990 } 1991 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { 1992 dev_err(dev, "wrong CPU port defined, HW only supports port: %i", 1993 priv->hw_info->cpu_port); 1994 err = -EINVAL; 1995 goto disable_switch; 1996 } 1997 1998 platform_set_drvdata(pdev, priv); 1999 2000 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 2001 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, 2002 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); 2003 return 0; 2004 2005 disable_switch: 2006 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2007 dsa_unregister_switch(priv->ds); 2008 mdio_bus: 2009 if (mdio_np) 2010 mdiobus_unregister(priv->ds->slave_mii_bus); 2011 put_mdio_node: 2012 of_node_put(mdio_np); 2013 for (i = 0; i < priv->num_gphy_fw; i++) 2014 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2015 return err; 2016 } 2017 2018 static int gswip_remove(struct platform_device *pdev) 2019 { 2020 struct gswip_priv *priv = platform_get_drvdata(pdev); 2021 int i; 2022 2023 /* disable the switch */ 2024 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2025 2026 dsa_unregister_switch(priv->ds); 2027 2028 if (priv->ds->slave_mii_bus) { 2029 mdiobus_unregister(priv->ds->slave_mii_bus); 2030 of_node_put(priv->ds->slave_mii_bus->dev.of_node); 2031 } 2032 2033 for (i = 0; i < priv->num_gphy_fw; i++) 2034 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2035 2036 return 0; 2037 } 2038 2039 static const struct gswip_hw_info gswip_xrx200 = { 2040 .max_ports = 7, 2041 .cpu_port = 6, 2042 .ops = &gswip_xrx200_switch_ops, 2043 }; 2044 2045 static const struct gswip_hw_info gswip_xrx300 = { 2046 .max_ports = 7, 2047 .cpu_port = 6, 2048 .ops = &gswip_xrx300_switch_ops, 2049 }; 2050 2051 static const struct of_device_id gswip_of_match[] = { 2052 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 2053 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 }, 2054 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 }, 2055 {}, 2056 }; 2057 MODULE_DEVICE_TABLE(of, gswip_of_match); 2058 2059 static struct platform_driver gswip_driver = { 2060 .probe = gswip_probe, 2061 .remove = gswip_remove, 2062 .driver = { 2063 .name = "gswip", 2064 .of_match_table = gswip_of_match, 2065 }, 2066 }; 2067 2068 module_platform_driver(gswip_driver); 2069 2070 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 2071 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 2072 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 2073 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 2074 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 2075 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 2076 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 2077 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 2078 MODULE_LICENSE("GPL v2"); 2079