1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * The VLAN and bridge model the GSWIP hardware uses does not directly 10 * matches the model DSA uses. 11 * 12 * The hardware has 64 possible table entries for bridges with one VLAN 13 * ID, one flow id and a list of ports for each bridge. All entries which 14 * match the same flow ID are combined in the mac learning table, they 15 * act as one global bridge. 16 * The hardware does not support VLAN filter on the port, but on the 17 * bridge, this driver converts the DSA model to the hardware. 18 * 19 * The CPU gets all the exception frames which do not match any forwarding 20 * rule and the CPU port is also added to all bridges. This makes it possible 21 * to handle all the special cases easily in software. 22 * At the initialization the driver allocates one bridge table entry for 23 * each switch port which is used when the port is used without an 24 * explicit bridge. This prevents the frames from being forwarded 25 * between all LAN ports by default. 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/etherdevice.h> 30 #include <linux/firmware.h> 31 #include <linux/if_bridge.h> 32 #include <linux/if_vlan.h> 33 #include <linux/iopoll.h> 34 #include <linux/mfd/syscon.h> 35 #include <linux/module.h> 36 #include <linux/of_mdio.h> 37 #include <linux/of_net.h> 38 #include <linux/of_platform.h> 39 #include <linux/phy.h> 40 #include <linux/phylink.h> 41 #include <linux/platform_device.h> 42 #include <linux/regmap.h> 43 #include <linux/reset.h> 44 #include <net/dsa.h> 45 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 46 47 #include "lantiq_pce.h" 48 49 /* GSWIP MDIO Registers */ 50 #define GSWIP_MDIO_GLOB 0x00 51 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 52 #define GSWIP_MDIO_CTRL 0x08 53 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 54 #define GSWIP_MDIO_CTRL_RD BIT(11) 55 #define GSWIP_MDIO_CTRL_WR BIT(10) 56 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 57 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 58 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 59 #define GSWIP_MDIO_READ 0x09 60 #define GSWIP_MDIO_WRITE 0x0A 61 #define GSWIP_MDIO_MDC_CFG0 0x0B 62 #define GSWIP_MDIO_MDC_CFG1 0x0C 63 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 64 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 65 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 66 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 67 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 68 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 69 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 70 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 71 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 72 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 73 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 74 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 75 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 76 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 77 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 78 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 79 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 80 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 81 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 82 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 83 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 84 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 85 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 86 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 87 GSWIP_MDIO_PHY_FCONRX_MASK | \ 88 GSWIP_MDIO_PHY_FCONTX_MASK | \ 89 GSWIP_MDIO_PHY_LINK_MASK | \ 90 GSWIP_MDIO_PHY_SPEED_MASK | \ 91 GSWIP_MDIO_PHY_FDUP_MASK) 92 93 /* GSWIP MII Registers */ 94 #define GSWIP_MII_CFG0 0x00 95 #define GSWIP_MII_CFG1 0x02 96 #define GSWIP_MII_CFG5 0x04 97 #define GSWIP_MII_CFG_EN BIT(14) 98 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 99 #define GSWIP_MII_CFG_MODE_MIIP 0x0 100 #define GSWIP_MII_CFG_MODE_MIIM 0x1 101 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 102 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 103 #define GSWIP_MII_CFG_MODE_RGMII 0x4 104 #define GSWIP_MII_CFG_MODE_MASK 0xf 105 #define GSWIP_MII_CFG_RATE_M2P5 0x00 106 #define GSWIP_MII_CFG_RATE_M25 0x10 107 #define GSWIP_MII_CFG_RATE_M125 0x20 108 #define GSWIP_MII_CFG_RATE_M50 0x30 109 #define GSWIP_MII_CFG_RATE_AUTO 0x40 110 #define GSWIP_MII_CFG_RATE_MASK 0x70 111 #define GSWIP_MII_PCDU0 0x01 112 #define GSWIP_MII_PCDU1 0x03 113 #define GSWIP_MII_PCDU5 0x05 114 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 115 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 116 117 /* GSWIP Core Registers */ 118 #define GSWIP_SWRES 0x000 119 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 120 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 121 #define GSWIP_VERSION 0x013 122 #define GSWIP_VERSION_REV_SHIFT 0 123 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 124 #define GSWIP_VERSION_MOD_SHIFT 8 125 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 126 #define GSWIP_VERSION_2_0 0x100 127 #define GSWIP_VERSION_2_1 0x021 128 #define GSWIP_VERSION_2_2 0x122 129 #define GSWIP_VERSION_2_2_ETC 0x022 130 131 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 132 #define GSWIP_BM_RAM_ADDR 0x044 133 #define GSWIP_BM_RAM_CTRL 0x045 134 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 135 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 136 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 137 #define GSWIP_BM_QUEUE_GCTRL 0x04A 138 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 139 /* buffer management Port Configuration Register */ 140 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 141 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 142 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 143 /* buffer management Port Control Register */ 144 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 145 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 146 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 147 148 /* PCE */ 149 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 150 #define GSWIP_PCE_TBL_MASK 0x448 151 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 152 #define GSWIP_PCE_TBL_ADDR 0x44E 153 #define GSWIP_PCE_TBL_CTRL 0x44F 154 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 155 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 156 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 157 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 158 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 159 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 160 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 161 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 162 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 163 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 164 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 165 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 166 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 167 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 168 #define GSWIP_PCE_GCTRL_0 0x456 169 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ 170 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 171 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 172 #define GSWIP_PCE_GCTRL_1 0x457 173 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 174 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 175 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 176 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ 177 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ 178 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ 179 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 180 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 181 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 182 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 183 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 184 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 185 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) 186 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ 187 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ 188 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ 189 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ 190 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ 191 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) 192 193 #define GSWIP_MAC_FLEN 0x8C5 194 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 195 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 196 197 /* Ethernet Switch Fetch DMA Port Control Register */ 198 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 199 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 200 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 201 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 202 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 203 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 204 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 205 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 206 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 207 208 /* Ethernet Switch Store DMA Port Control Register */ 209 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 210 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 211 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 212 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */ 213 214 #define GSWIP_TABLE_ACTIVE_VLAN 0x01 215 #define GSWIP_TABLE_VLAN_MAPPING 0x02 216 #define GSWIP_TABLE_MAC_BRIDGE 0x0b 217 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ 218 219 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 220 221 struct gswip_hw_info { 222 int max_ports; 223 int cpu_port; 224 }; 225 226 struct xway_gphy_match_data { 227 char *fe_firmware_name; 228 char *ge_firmware_name; 229 }; 230 231 struct gswip_gphy_fw { 232 struct clk *clk_gate; 233 struct reset_control *reset; 234 u32 fw_addr_offset; 235 char *fw_name; 236 }; 237 238 struct gswip_vlan { 239 struct net_device *bridge; 240 u16 vid; 241 u8 fid; 242 }; 243 244 struct gswip_priv { 245 __iomem void *gswip; 246 __iomem void *mdio; 247 __iomem void *mii; 248 const struct gswip_hw_info *hw_info; 249 const struct xway_gphy_match_data *gphy_fw_name_cfg; 250 struct dsa_switch *ds; 251 struct device *dev; 252 struct regmap *rcu_regmap; 253 struct gswip_vlan vlans[64]; 254 int num_gphy_fw; 255 struct gswip_gphy_fw *gphy_fw; 256 u32 port_vlan_filter; 257 }; 258 259 struct gswip_pce_table_entry { 260 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index 261 u16 table; // PCE_TBL_CTRL.ADDR = pData->table 262 u16 key[8]; 263 u16 val[5]; 264 u16 mask; 265 u8 gmap; 266 bool type; 267 bool valid; 268 bool key_mode; 269 }; 270 271 struct gswip_rmon_cnt_desc { 272 unsigned int size; 273 unsigned int offset; 274 const char *name; 275 }; 276 277 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 278 279 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 280 /** Receive Packet Count (only packets that are accepted and not discarded). */ 281 MIB_DESC(1, 0x1F, "RxGoodPkts"), 282 MIB_DESC(1, 0x23, "RxUnicastPkts"), 283 MIB_DESC(1, 0x22, "RxMulticastPkts"), 284 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 285 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 286 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 287 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 288 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 289 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 290 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 291 MIB_DESC(1, 0x12, "Rx64BytePkts"), 292 MIB_DESC(1, 0x13, "Rx127BytePkts"), 293 MIB_DESC(1, 0x14, "Rx255BytePkts"), 294 MIB_DESC(1, 0x15, "Rx511BytePkts"), 295 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 296 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 297 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 298 MIB_DESC(1, 0x18, "RxDroppedPkts"), 299 MIB_DESC(1, 0x19, "RxFilteredPkts"), 300 MIB_DESC(2, 0x24, "RxGoodBytes"), 301 MIB_DESC(2, 0x26, "RxBadBytes"), 302 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 303 MIB_DESC(1, 0x0C, "TxGoodPkts"), 304 MIB_DESC(1, 0x06, "TxUnicastPkts"), 305 MIB_DESC(1, 0x07, "TxMulticastPkts"), 306 MIB_DESC(1, 0x00, "Tx64BytePkts"), 307 MIB_DESC(1, 0x01, "Tx127BytePkts"), 308 MIB_DESC(1, 0x02, "Tx255BytePkts"), 309 MIB_DESC(1, 0x03, "Tx511BytePkts"), 310 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 311 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 312 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 313 MIB_DESC(1, 0x08, "TxSingleCollCount"), 314 MIB_DESC(1, 0x09, "TxMultCollCount"), 315 MIB_DESC(1, 0x0A, "TxLateCollCount"), 316 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 317 MIB_DESC(1, 0x0D, "TxPauseCount"), 318 MIB_DESC(1, 0x10, "TxDroppedPkts"), 319 MIB_DESC(2, 0x0E, "TxGoodBytes"), 320 }; 321 322 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 323 { 324 return __raw_readl(priv->gswip + (offset * 4)); 325 } 326 327 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 328 { 329 __raw_writel(val, priv->gswip + (offset * 4)); 330 } 331 332 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 333 u32 offset) 334 { 335 u32 val = gswip_switch_r(priv, offset); 336 337 val &= ~(clear); 338 val |= set; 339 gswip_switch_w(priv, val, offset); 340 } 341 342 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 343 u32 cleared) 344 { 345 u32 val; 346 347 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 348 (val & cleared) == 0, 20, 50000); 349 } 350 351 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 352 { 353 return __raw_readl(priv->mdio + (offset * 4)); 354 } 355 356 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 357 { 358 __raw_writel(val, priv->mdio + (offset * 4)); 359 } 360 361 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 362 u32 offset) 363 { 364 u32 val = gswip_mdio_r(priv, offset); 365 366 val &= ~(clear); 367 val |= set; 368 gswip_mdio_w(priv, val, offset); 369 } 370 371 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 372 { 373 return __raw_readl(priv->mii + (offset * 4)); 374 } 375 376 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 377 { 378 __raw_writel(val, priv->mii + (offset * 4)); 379 } 380 381 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 382 u32 offset) 383 { 384 u32 val = gswip_mii_r(priv, offset); 385 386 val &= ~(clear); 387 val |= set; 388 gswip_mii_w(priv, val, offset); 389 } 390 391 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 392 int port) 393 { 394 switch (port) { 395 case 0: 396 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG0); 397 break; 398 case 1: 399 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG1); 400 break; 401 case 5: 402 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG5); 403 break; 404 } 405 } 406 407 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 408 int port) 409 { 410 switch (port) { 411 case 0: 412 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 413 break; 414 case 1: 415 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 416 break; 417 case 5: 418 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 419 break; 420 } 421 } 422 423 static int gswip_mdio_poll(struct gswip_priv *priv) 424 { 425 int cnt = 100; 426 427 while (likely(cnt--)) { 428 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 429 430 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 431 return 0; 432 usleep_range(20, 40); 433 } 434 435 return -ETIMEDOUT; 436 } 437 438 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 439 { 440 struct gswip_priv *priv = bus->priv; 441 int err; 442 443 err = gswip_mdio_poll(priv); 444 if (err) { 445 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 446 return err; 447 } 448 449 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 450 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 451 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 452 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 453 GSWIP_MDIO_CTRL); 454 455 return 0; 456 } 457 458 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 459 { 460 struct gswip_priv *priv = bus->priv; 461 int err; 462 463 err = gswip_mdio_poll(priv); 464 if (err) { 465 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 466 return err; 467 } 468 469 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 470 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 471 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 472 GSWIP_MDIO_CTRL); 473 474 err = gswip_mdio_poll(priv); 475 if (err) { 476 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 477 return err; 478 } 479 480 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 481 } 482 483 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np) 484 { 485 struct dsa_switch *ds = priv->ds; 486 487 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev); 488 if (!ds->slave_mii_bus) 489 return -ENOMEM; 490 491 ds->slave_mii_bus->priv = priv; 492 ds->slave_mii_bus->read = gswip_mdio_rd; 493 ds->slave_mii_bus->write = gswip_mdio_wr; 494 ds->slave_mii_bus->name = "lantiq,xrx200-mdio"; 495 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", 496 dev_name(priv->dev)); 497 ds->slave_mii_bus->parent = priv->dev; 498 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask; 499 500 return of_mdiobus_register(ds->slave_mii_bus, mdio_np); 501 } 502 503 static int gswip_pce_table_entry_read(struct gswip_priv *priv, 504 struct gswip_pce_table_entry *tbl) 505 { 506 int i; 507 int err; 508 u16 crtl; 509 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 510 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 511 512 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 513 GSWIP_PCE_TBL_CTRL_BAS); 514 if (err) 515 return err; 516 517 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 518 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 519 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 520 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 521 GSWIP_PCE_TBL_CTRL); 522 523 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 524 GSWIP_PCE_TBL_CTRL_BAS); 525 if (err) 526 return err; 527 528 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 529 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 530 531 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 532 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 533 534 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 535 536 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 537 538 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 539 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 540 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 541 542 return 0; 543 } 544 545 static int gswip_pce_table_entry_write(struct gswip_priv *priv, 546 struct gswip_pce_table_entry *tbl) 547 { 548 int i; 549 int err; 550 u16 crtl; 551 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 552 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 553 554 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 555 GSWIP_PCE_TBL_CTRL_BAS); 556 if (err) 557 return err; 558 559 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 560 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 561 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 562 tbl->table | addr_mode, 563 GSWIP_PCE_TBL_CTRL); 564 565 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 566 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 567 568 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 569 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 570 571 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 572 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 573 tbl->table | addr_mode, 574 GSWIP_PCE_TBL_CTRL); 575 576 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 577 578 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 579 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 580 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 581 if (tbl->type) 582 crtl |= GSWIP_PCE_TBL_CTRL_TYPE; 583 if (tbl->valid) 584 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 585 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 586 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 587 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 588 589 return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 590 GSWIP_PCE_TBL_CTRL_BAS); 591 } 592 593 /* Add the LAN port into a bridge with the CPU port by 594 * default. This prevents automatic forwarding of 595 * packages between the LAN ports when no explicit 596 * bridge is configured. 597 */ 598 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) 599 { 600 struct gswip_pce_table_entry vlan_active = {0,}; 601 struct gswip_pce_table_entry vlan_mapping = {0,}; 602 unsigned int cpu_port = priv->hw_info->cpu_port; 603 unsigned int max_ports = priv->hw_info->max_ports; 604 int err; 605 606 if (port >= max_ports) { 607 dev_err(priv->dev, "single port for %i supported\n", port); 608 return -EIO; 609 } 610 611 vlan_active.index = port + 1; 612 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 613 vlan_active.key[0] = 0; /* vid */ 614 vlan_active.val[0] = port + 1 /* fid */; 615 vlan_active.valid = add; 616 err = gswip_pce_table_entry_write(priv, &vlan_active); 617 if (err) { 618 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 619 return err; 620 } 621 622 if (!add) 623 return 0; 624 625 vlan_mapping.index = port + 1; 626 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 627 vlan_mapping.val[0] = 0 /* vid */; 628 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); 629 vlan_mapping.val[2] = 0; 630 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 631 if (err) { 632 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 633 return err; 634 } 635 636 return 0; 637 } 638 639 static int gswip_port_enable(struct dsa_switch *ds, int port, 640 struct phy_device *phydev) 641 { 642 struct gswip_priv *priv = ds->priv; 643 int err; 644 645 if (!dsa_is_user_port(ds, port)) 646 return 0; 647 648 if (!dsa_is_cpu_port(ds, port)) { 649 err = gswip_add_single_port_br(priv, port, true); 650 if (err) 651 return err; 652 } 653 654 /* RMON Counter Enable for port */ 655 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 656 657 /* enable port fetch/store dma & VLAN Modification */ 658 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 659 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 660 GSWIP_FDMA_PCTRLp(port)); 661 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 662 GSWIP_SDMA_PCTRLp(port)); 663 664 if (!dsa_is_cpu_port(ds, port)) { 665 u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO | 666 GSWIP_MDIO_PHY_SPEED_AUTO | 667 GSWIP_MDIO_PHY_FDUP_AUTO | 668 GSWIP_MDIO_PHY_FCONTX_AUTO | 669 GSWIP_MDIO_PHY_FCONRX_AUTO | 670 (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK); 671 672 gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port)); 673 /* Activate MDIO auto polling */ 674 gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0); 675 } 676 677 return 0; 678 } 679 680 static void gswip_port_disable(struct dsa_switch *ds, int port) 681 { 682 struct gswip_priv *priv = ds->priv; 683 684 if (!dsa_is_user_port(ds, port)) 685 return; 686 687 if (!dsa_is_cpu_port(ds, port)) { 688 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_DOWN, 689 GSWIP_MDIO_PHY_LINK_MASK, 690 GSWIP_MDIO_PHYp(port)); 691 /* Deactivate MDIO auto polling */ 692 gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0); 693 } 694 695 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 696 GSWIP_FDMA_PCTRLp(port)); 697 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 698 GSWIP_SDMA_PCTRLp(port)); 699 } 700 701 static int gswip_pce_load_microcode(struct gswip_priv *priv) 702 { 703 int i; 704 int err; 705 706 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 707 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 708 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 709 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 710 711 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { 712 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 713 gswip_switch_w(priv, gswip_pce_microcode[i].val_0, 714 GSWIP_PCE_TBL_VAL(0)); 715 gswip_switch_w(priv, gswip_pce_microcode[i].val_1, 716 GSWIP_PCE_TBL_VAL(1)); 717 gswip_switch_w(priv, gswip_pce_microcode[i].val_2, 718 GSWIP_PCE_TBL_VAL(2)); 719 gswip_switch_w(priv, gswip_pce_microcode[i].val_3, 720 GSWIP_PCE_TBL_VAL(3)); 721 722 /* start the table access: */ 723 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 724 GSWIP_PCE_TBL_CTRL); 725 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 726 GSWIP_PCE_TBL_CTRL_BAS); 727 if (err) 728 return err; 729 } 730 731 /* tell the switch that the microcode is loaded */ 732 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 733 GSWIP_PCE_GCTRL_0); 734 735 return 0; 736 } 737 738 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 739 bool vlan_filtering) 740 { 741 struct gswip_priv *priv = ds->priv; 742 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 743 744 /* Do not allow changing the VLAN filtering options while in bridge */ 745 if (!!(priv->port_vlan_filter & BIT(port)) != vlan_filtering && bridge) 746 return -EIO; 747 748 if (vlan_filtering) { 749 /* Use port based VLAN tag */ 750 gswip_switch_mask(priv, 751 GSWIP_PCE_VCTRL_VSR, 752 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 753 GSWIP_PCE_VCTRL_VEMR, 754 GSWIP_PCE_VCTRL(port)); 755 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 756 GSWIP_PCE_PCTRL_0p(port)); 757 } else { 758 /* Use port based VLAN tag */ 759 gswip_switch_mask(priv, 760 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 761 GSWIP_PCE_VCTRL_VEMR, 762 GSWIP_PCE_VCTRL_VSR, 763 GSWIP_PCE_VCTRL(port)); 764 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 765 GSWIP_PCE_PCTRL_0p(port)); 766 } 767 768 return 0; 769 } 770 771 static int gswip_setup(struct dsa_switch *ds) 772 { 773 struct gswip_priv *priv = ds->priv; 774 unsigned int cpu_port = priv->hw_info->cpu_port; 775 int i; 776 int err; 777 778 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 779 usleep_range(5000, 10000); 780 gswip_switch_w(priv, 0, GSWIP_SWRES); 781 782 /* disable port fetch/store dma on all ports */ 783 for (i = 0; i < priv->hw_info->max_ports; i++) { 784 gswip_port_disable(ds, i); 785 gswip_port_vlan_filtering(ds, i, false); 786 } 787 788 /* enable Switch */ 789 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 790 791 err = gswip_pce_load_microcode(priv); 792 if (err) { 793 dev_err(priv->dev, "writing PCE microcode failed, %i", err); 794 return err; 795 } 796 797 /* Default unknown Broadcast/Multicast/Unicast port maps */ 798 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); 799 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); 800 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); 801 802 /* disable PHY auto polling */ 803 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 804 /* Configure the MDIO Clock 2.5 MHz */ 805 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 806 807 /* Disable the xMII link */ 808 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 0); 809 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 1); 810 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 5); 811 812 /* enable special tag insertion on cpu port */ 813 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 814 GSWIP_FDMA_PCTRLp(cpu_port)); 815 816 /* accept special tag in ingress direction */ 817 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 818 GSWIP_PCE_PCTRL_0p(cpu_port)); 819 820 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 821 GSWIP_MAC_CTRL_2p(cpu_port)); 822 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8, GSWIP_MAC_FLEN); 823 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 824 GSWIP_BM_QUEUE_GCTRL); 825 826 /* VLAN aware Switching */ 827 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 828 829 /* Flush MAC Table */ 830 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 831 832 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 833 GSWIP_PCE_GCTRL_0_MTFL); 834 if (err) { 835 dev_err(priv->dev, "MAC flushing didn't finish\n"); 836 return err; 837 } 838 839 gswip_port_enable(ds, cpu_port, NULL); 840 return 0; 841 } 842 843 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 844 int port) 845 { 846 return DSA_TAG_PROTO_GSWIP; 847 } 848 849 static int gswip_vlan_active_create(struct gswip_priv *priv, 850 struct net_device *bridge, 851 int fid, u16 vid) 852 { 853 struct gswip_pce_table_entry vlan_active = {0,}; 854 unsigned int max_ports = priv->hw_info->max_ports; 855 int idx = -1; 856 int err; 857 int i; 858 859 /* Look for a free slot */ 860 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 861 if (!priv->vlans[i].bridge) { 862 idx = i; 863 break; 864 } 865 } 866 867 if (idx == -1) 868 return -ENOSPC; 869 870 if (fid == -1) 871 fid = idx; 872 873 vlan_active.index = idx; 874 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 875 vlan_active.key[0] = vid; 876 vlan_active.val[0] = fid; 877 vlan_active.valid = true; 878 879 err = gswip_pce_table_entry_write(priv, &vlan_active); 880 if (err) { 881 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 882 return err; 883 } 884 885 priv->vlans[idx].bridge = bridge; 886 priv->vlans[idx].vid = vid; 887 priv->vlans[idx].fid = fid; 888 889 return idx; 890 } 891 892 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) 893 { 894 struct gswip_pce_table_entry vlan_active = {0,}; 895 int err; 896 897 vlan_active.index = idx; 898 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 899 vlan_active.valid = false; 900 err = gswip_pce_table_entry_write(priv, &vlan_active); 901 if (err) 902 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); 903 priv->vlans[idx].bridge = NULL; 904 905 return err; 906 } 907 908 static int gswip_vlan_add_unaware(struct gswip_priv *priv, 909 struct net_device *bridge, int port) 910 { 911 struct gswip_pce_table_entry vlan_mapping = {0,}; 912 unsigned int max_ports = priv->hw_info->max_ports; 913 unsigned int cpu_port = priv->hw_info->cpu_port; 914 bool active_vlan_created = false; 915 int idx = -1; 916 int i; 917 int err; 918 919 /* Check if there is already a page for this bridge */ 920 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 921 if (priv->vlans[i].bridge == bridge) { 922 idx = i; 923 break; 924 } 925 } 926 927 /* If this bridge is not programmed yet, add a Active VLAN table 928 * entry in a free slot and prepare the VLAN mapping table entry. 929 */ 930 if (idx == -1) { 931 idx = gswip_vlan_active_create(priv, bridge, -1, 0); 932 if (idx < 0) 933 return idx; 934 active_vlan_created = true; 935 936 vlan_mapping.index = idx; 937 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 938 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 939 vlan_mapping.val[0] = 0; 940 } else { 941 /* Read the existing VLAN mapping entry from the switch */ 942 vlan_mapping.index = idx; 943 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 944 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 945 if (err) { 946 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 947 err); 948 return err; 949 } 950 } 951 952 /* Update the VLAN mapping entry and write it to the switch */ 953 vlan_mapping.val[1] |= BIT(cpu_port); 954 vlan_mapping.val[1] |= BIT(port); 955 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 956 if (err) { 957 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 958 /* In case an Active VLAN was creaetd delete it again */ 959 if (active_vlan_created) 960 gswip_vlan_active_remove(priv, idx); 961 return err; 962 } 963 964 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 965 return 0; 966 } 967 968 static int gswip_vlan_add_aware(struct gswip_priv *priv, 969 struct net_device *bridge, int port, 970 u16 vid, bool untagged, 971 bool pvid) 972 { 973 struct gswip_pce_table_entry vlan_mapping = {0,}; 974 unsigned int max_ports = priv->hw_info->max_ports; 975 unsigned int cpu_port = priv->hw_info->cpu_port; 976 bool active_vlan_created = false; 977 int idx = -1; 978 int fid = -1; 979 int i; 980 int err; 981 982 /* Check if there is already a page for this bridge */ 983 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 984 if (priv->vlans[i].bridge == bridge) { 985 if (fid != -1 && fid != priv->vlans[i].fid) 986 dev_err(priv->dev, "one bridge with multiple flow ids\n"); 987 fid = priv->vlans[i].fid; 988 if (priv->vlans[i].vid == vid) { 989 idx = i; 990 break; 991 } 992 } 993 } 994 995 /* If this bridge is not programmed yet, add a Active VLAN table 996 * entry in a free slot and prepare the VLAN mapping table entry. 997 */ 998 if (idx == -1) { 999 idx = gswip_vlan_active_create(priv, bridge, fid, vid); 1000 if (idx < 0) 1001 return idx; 1002 active_vlan_created = true; 1003 1004 vlan_mapping.index = idx; 1005 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1006 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 1007 vlan_mapping.val[0] = vid; 1008 } else { 1009 /* Read the existing VLAN mapping entry from the switch */ 1010 vlan_mapping.index = idx; 1011 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1012 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1013 if (err) { 1014 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 1015 err); 1016 return err; 1017 } 1018 } 1019 1020 vlan_mapping.val[0] = vid; 1021 /* Update the VLAN mapping entry and write it to the switch */ 1022 vlan_mapping.val[1] |= BIT(cpu_port); 1023 vlan_mapping.val[2] |= BIT(cpu_port); 1024 vlan_mapping.val[1] |= BIT(port); 1025 if (untagged) 1026 vlan_mapping.val[2] &= ~BIT(port); 1027 else 1028 vlan_mapping.val[2] |= BIT(port); 1029 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1030 if (err) { 1031 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1032 /* In case an Active VLAN was creaetd delete it again */ 1033 if (active_vlan_created) 1034 gswip_vlan_active_remove(priv, idx); 1035 return err; 1036 } 1037 1038 if (pvid) 1039 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 1040 1041 return 0; 1042 } 1043 1044 static int gswip_vlan_remove(struct gswip_priv *priv, 1045 struct net_device *bridge, int port, 1046 u16 vid, bool pvid, bool vlan_aware) 1047 { 1048 struct gswip_pce_table_entry vlan_mapping = {0,}; 1049 unsigned int max_ports = priv->hw_info->max_ports; 1050 unsigned int cpu_port = priv->hw_info->cpu_port; 1051 int idx = -1; 1052 int i; 1053 int err; 1054 1055 /* Check if there is already a page for this bridge */ 1056 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1057 if (priv->vlans[i].bridge == bridge && 1058 (!vlan_aware || priv->vlans[i].vid == vid)) { 1059 idx = i; 1060 break; 1061 } 1062 } 1063 1064 if (idx == -1) { 1065 dev_err(priv->dev, "bridge to leave does not exists\n"); 1066 return -ENOENT; 1067 } 1068 1069 vlan_mapping.index = idx; 1070 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1071 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1072 if (err) { 1073 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); 1074 return err; 1075 } 1076 1077 vlan_mapping.val[1] &= ~BIT(port); 1078 vlan_mapping.val[2] &= ~BIT(port); 1079 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1080 if (err) { 1081 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1082 return err; 1083 } 1084 1085 /* In case all ports are removed from the bridge, remove the VLAN */ 1086 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { 1087 err = gswip_vlan_active_remove(priv, idx); 1088 if (err) { 1089 dev_err(priv->dev, "failed to write active VLAN: %d\n", 1090 err); 1091 return err; 1092 } 1093 } 1094 1095 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 1096 if (pvid) 1097 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1098 1099 return 0; 1100 } 1101 1102 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, 1103 struct net_device *bridge) 1104 { 1105 struct gswip_priv *priv = ds->priv; 1106 int err; 1107 1108 /* When the bridge uses VLAN filtering we have to configure VLAN 1109 * specific bridges. No bridge is configured here. 1110 */ 1111 if (!br_vlan_enabled(bridge)) { 1112 err = gswip_vlan_add_unaware(priv, bridge, port); 1113 if (err) 1114 return err; 1115 priv->port_vlan_filter &= ~BIT(port); 1116 } else { 1117 priv->port_vlan_filter |= BIT(port); 1118 } 1119 return gswip_add_single_port_br(priv, port, false); 1120 } 1121 1122 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, 1123 struct net_device *bridge) 1124 { 1125 struct gswip_priv *priv = ds->priv; 1126 1127 gswip_add_single_port_br(priv, port, true); 1128 1129 /* When the bridge uses VLAN filtering we have to configure VLAN 1130 * specific bridges. No bridge is configured here. 1131 */ 1132 if (!br_vlan_enabled(bridge)) 1133 gswip_vlan_remove(priv, bridge, port, 0, true, false); 1134 } 1135 1136 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, 1137 const struct switchdev_obj_port_vlan *vlan) 1138 { 1139 struct gswip_priv *priv = ds->priv; 1140 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1141 unsigned int max_ports = priv->hw_info->max_ports; 1142 u16 vid; 1143 int i; 1144 int pos = max_ports; 1145 1146 /* We only support VLAN filtering on bridges */ 1147 if (!dsa_is_cpu_port(ds, port) && !bridge) 1148 return -EOPNOTSUPP; 1149 1150 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1151 int idx = -1; 1152 1153 /* Check if there is already a page for this VLAN */ 1154 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1155 if (priv->vlans[i].bridge == bridge && 1156 priv->vlans[i].vid == vid) { 1157 idx = i; 1158 break; 1159 } 1160 } 1161 1162 /* If this VLAN is not programmed yet, we have to reserve 1163 * one entry in the VLAN table. Make sure we start at the 1164 * next position round. 1165 */ 1166 if (idx == -1) { 1167 /* Look for a free slot */ 1168 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { 1169 if (!priv->vlans[pos].bridge) { 1170 idx = pos; 1171 pos++; 1172 break; 1173 } 1174 } 1175 1176 if (idx == -1) 1177 return -ENOSPC; 1178 } 1179 } 1180 1181 return 0; 1182 } 1183 1184 static void gswip_port_vlan_add(struct dsa_switch *ds, int port, 1185 const struct switchdev_obj_port_vlan *vlan) 1186 { 1187 struct gswip_priv *priv = ds->priv; 1188 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1189 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1190 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1191 u16 vid; 1192 1193 /* We have to receive all packets on the CPU port and should not 1194 * do any VLAN filtering here. This is also called with bridge 1195 * NULL and then we do not know for which bridge to configure 1196 * this. 1197 */ 1198 if (dsa_is_cpu_port(ds, port)) 1199 return; 1200 1201 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1202 gswip_vlan_add_aware(priv, bridge, port, vid, untagged, pvid); 1203 } 1204 1205 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, 1206 const struct switchdev_obj_port_vlan *vlan) 1207 { 1208 struct gswip_priv *priv = ds->priv; 1209 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1210 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1211 u16 vid; 1212 int err; 1213 1214 /* We have to receive all packets on the CPU port and should not 1215 * do any VLAN filtering here. This is also called with bridge 1216 * NULL and then we do not know for which bridge to configure 1217 * this. 1218 */ 1219 if (dsa_is_cpu_port(ds, port)) 1220 return 0; 1221 1222 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1223 err = gswip_vlan_remove(priv, bridge, port, vid, pvid, true); 1224 if (err) 1225 return err; 1226 } 1227 1228 return 0; 1229 } 1230 1231 static void gswip_port_fast_age(struct dsa_switch *ds, int port) 1232 { 1233 struct gswip_priv *priv = ds->priv; 1234 struct gswip_pce_table_entry mac_bridge = {0,}; 1235 int i; 1236 int err; 1237 1238 for (i = 0; i < 2048; i++) { 1239 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1240 mac_bridge.index = i; 1241 1242 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1243 if (err) { 1244 dev_err(priv->dev, "failed to read mac bridge: %d\n", 1245 err); 1246 return; 1247 } 1248 1249 if (!mac_bridge.valid) 1250 continue; 1251 1252 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) 1253 continue; 1254 1255 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) 1256 continue; 1257 1258 mac_bridge.valid = false; 1259 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1260 if (err) { 1261 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1262 err); 1263 return; 1264 } 1265 } 1266 } 1267 1268 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1269 { 1270 struct gswip_priv *priv = ds->priv; 1271 u32 stp_state; 1272 1273 switch (state) { 1274 case BR_STATE_DISABLED: 1275 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1276 GSWIP_SDMA_PCTRLp(port)); 1277 return; 1278 case BR_STATE_BLOCKING: 1279 case BR_STATE_LISTENING: 1280 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; 1281 break; 1282 case BR_STATE_LEARNING: 1283 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; 1284 break; 1285 case BR_STATE_FORWARDING: 1286 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; 1287 break; 1288 default: 1289 dev_err(priv->dev, "invalid STP state: %d\n", state); 1290 return; 1291 } 1292 1293 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1294 GSWIP_SDMA_PCTRLp(port)); 1295 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1296 GSWIP_PCE_PCTRL_0p(port)); 1297 } 1298 1299 static int gswip_port_fdb(struct dsa_switch *ds, int port, 1300 const unsigned char *addr, u16 vid, bool add) 1301 { 1302 struct gswip_priv *priv = ds->priv; 1303 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1304 struct gswip_pce_table_entry mac_bridge = {0,}; 1305 unsigned int cpu_port = priv->hw_info->cpu_port; 1306 int fid = -1; 1307 int i; 1308 int err; 1309 1310 if (!bridge) 1311 return -EINVAL; 1312 1313 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) { 1314 if (priv->vlans[i].bridge == bridge) { 1315 fid = priv->vlans[i].fid; 1316 break; 1317 } 1318 } 1319 1320 if (fid == -1) { 1321 dev_err(priv->dev, "Port not part of a bridge\n"); 1322 return -EINVAL; 1323 } 1324 1325 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1326 mac_bridge.key_mode = true; 1327 mac_bridge.key[0] = addr[5] | (addr[4] << 8); 1328 mac_bridge.key[1] = addr[3] | (addr[2] << 8); 1329 mac_bridge.key[2] = addr[1] | (addr[0] << 8); 1330 mac_bridge.key[3] = fid; 1331 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ 1332 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; 1333 mac_bridge.valid = add; 1334 1335 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1336 if (err) 1337 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); 1338 1339 return err; 1340 } 1341 1342 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, 1343 const unsigned char *addr, u16 vid) 1344 { 1345 return gswip_port_fdb(ds, port, addr, vid, true); 1346 } 1347 1348 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, 1349 const unsigned char *addr, u16 vid) 1350 { 1351 return gswip_port_fdb(ds, port, addr, vid, false); 1352 } 1353 1354 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, 1355 dsa_fdb_dump_cb_t *cb, void *data) 1356 { 1357 struct gswip_priv *priv = ds->priv; 1358 struct gswip_pce_table_entry mac_bridge = {0,}; 1359 unsigned char addr[6]; 1360 int i; 1361 int err; 1362 1363 for (i = 0; i < 2048; i++) { 1364 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1365 mac_bridge.index = i; 1366 1367 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1368 if (err) { 1369 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1370 err); 1371 return err; 1372 } 1373 1374 if (!mac_bridge.valid) 1375 continue; 1376 1377 addr[5] = mac_bridge.key[0] & 0xff; 1378 addr[4] = (mac_bridge.key[0] >> 8) & 0xff; 1379 addr[3] = mac_bridge.key[1] & 0xff; 1380 addr[2] = (mac_bridge.key[1] >> 8) & 0xff; 1381 addr[1] = mac_bridge.key[2] & 0xff; 1382 addr[0] = (mac_bridge.key[2] >> 8) & 0xff; 1383 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { 1384 if (mac_bridge.val[0] & BIT(port)) 1385 cb(addr, 0, true, data); 1386 } else { 1387 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) 1388 cb(addr, 0, false, data); 1389 } 1390 } 1391 return 0; 1392 } 1393 1394 static void gswip_phylink_validate(struct dsa_switch *ds, int port, 1395 unsigned long *supported, 1396 struct phylink_link_state *state) 1397 { 1398 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1399 1400 switch (port) { 1401 case 0: 1402 case 1: 1403 if (!phy_interface_mode_is_rgmii(state->interface) && 1404 state->interface != PHY_INTERFACE_MODE_MII && 1405 state->interface != PHY_INTERFACE_MODE_REVMII && 1406 state->interface != PHY_INTERFACE_MODE_RMII) 1407 goto unsupported; 1408 break; 1409 case 2: 1410 case 3: 1411 case 4: 1412 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 1413 goto unsupported; 1414 break; 1415 case 5: 1416 if (!phy_interface_mode_is_rgmii(state->interface) && 1417 state->interface != PHY_INTERFACE_MODE_INTERNAL) 1418 goto unsupported; 1419 break; 1420 default: 1421 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1422 dev_err(ds->dev, "Unsupported port: %i\n", port); 1423 return; 1424 } 1425 1426 /* Allow all the expected bits */ 1427 phylink_set(mask, Autoneg); 1428 phylink_set_port_modes(mask); 1429 phylink_set(mask, Pause); 1430 phylink_set(mask, Asym_Pause); 1431 1432 /* With the exclusion of MII and Reverse MII, we support Gigabit, 1433 * including Half duplex 1434 */ 1435 if (state->interface != PHY_INTERFACE_MODE_MII && 1436 state->interface != PHY_INTERFACE_MODE_REVMII) { 1437 phylink_set(mask, 1000baseT_Full); 1438 phylink_set(mask, 1000baseT_Half); 1439 } 1440 1441 phylink_set(mask, 10baseT_Half); 1442 phylink_set(mask, 10baseT_Full); 1443 phylink_set(mask, 100baseT_Half); 1444 phylink_set(mask, 100baseT_Full); 1445 1446 bitmap_and(supported, supported, mask, 1447 __ETHTOOL_LINK_MODE_MASK_NBITS); 1448 bitmap_and(state->advertising, state->advertising, mask, 1449 __ETHTOOL_LINK_MODE_MASK_NBITS); 1450 return; 1451 1452 unsupported: 1453 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1454 dev_err(ds->dev, "Unsupported interface: %d\n", state->interface); 1455 return; 1456 } 1457 1458 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, 1459 unsigned int mode, 1460 const struct phylink_link_state *state) 1461 { 1462 struct gswip_priv *priv = ds->priv; 1463 u32 miicfg = 0; 1464 1465 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 1466 1467 switch (state->interface) { 1468 case PHY_INTERFACE_MODE_MII: 1469 case PHY_INTERFACE_MODE_INTERNAL: 1470 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 1471 break; 1472 case PHY_INTERFACE_MODE_REVMII: 1473 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 1474 break; 1475 case PHY_INTERFACE_MODE_RMII: 1476 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 1477 break; 1478 case PHY_INTERFACE_MODE_RGMII: 1479 case PHY_INTERFACE_MODE_RGMII_ID: 1480 case PHY_INTERFACE_MODE_RGMII_RXID: 1481 case PHY_INTERFACE_MODE_RGMII_TXID: 1482 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 1483 break; 1484 default: 1485 dev_err(ds->dev, 1486 "Unsupported interface: %d\n", state->interface); 1487 return; 1488 } 1489 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK, miicfg, port); 1490 1491 switch (state->interface) { 1492 case PHY_INTERFACE_MODE_RGMII_ID: 1493 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 1494 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1495 break; 1496 case PHY_INTERFACE_MODE_RGMII_RXID: 1497 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1498 break; 1499 case PHY_INTERFACE_MODE_RGMII_TXID: 1500 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 1501 break; 1502 default: 1503 break; 1504 } 1505 } 1506 1507 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, 1508 unsigned int mode, 1509 phy_interface_t interface) 1510 { 1511 struct gswip_priv *priv = ds->priv; 1512 1513 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 1514 } 1515 1516 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, 1517 unsigned int mode, 1518 phy_interface_t interface, 1519 struct phy_device *phydev) 1520 { 1521 struct gswip_priv *priv = ds->priv; 1522 1523 /* Enable the xMII interface only for the external PHY */ 1524 if (interface != PHY_INTERFACE_MODE_INTERNAL) 1525 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1526 } 1527 1528 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1529 uint8_t *data) 1530 { 1531 int i; 1532 1533 if (stringset != ETH_SS_STATS) 1534 return; 1535 1536 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 1537 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name, 1538 ETH_GSTRING_LEN); 1539 } 1540 1541 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1542 u32 index) 1543 { 1544 u32 result; 1545 int err; 1546 1547 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1548 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1549 GSWIP_BM_RAM_CTRL_OPMOD, 1550 table | GSWIP_BM_RAM_CTRL_BAS, 1551 GSWIP_BM_RAM_CTRL); 1552 1553 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1554 GSWIP_BM_RAM_CTRL_BAS); 1555 if (err) { 1556 dev_err(priv->dev, "timeout while reading table: %u, index: %u", 1557 table, index); 1558 return 0; 1559 } 1560 1561 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1562 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1563 1564 return result; 1565 } 1566 1567 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 1568 uint64_t *data) 1569 { 1570 struct gswip_priv *priv = ds->priv; 1571 const struct gswip_rmon_cnt_desc *rmon_cnt; 1572 int i; 1573 u64 high; 1574 1575 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 1576 rmon_cnt = &gswip_rmon_cnt[i]; 1577 1578 data[i] = gswip_bcm_ram_entry_read(priv, port, 1579 rmon_cnt->offset); 1580 if (rmon_cnt->size == 2) { 1581 high = gswip_bcm_ram_entry_read(priv, port, 1582 rmon_cnt->offset + 1); 1583 data[i] |= high << 32; 1584 } 1585 } 1586 } 1587 1588 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 1589 { 1590 if (sset != ETH_SS_STATS) 1591 return 0; 1592 1593 return ARRAY_SIZE(gswip_rmon_cnt); 1594 } 1595 1596 static const struct dsa_switch_ops gswip_switch_ops = { 1597 .get_tag_protocol = gswip_get_tag_protocol, 1598 .setup = gswip_setup, 1599 .port_enable = gswip_port_enable, 1600 .port_disable = gswip_port_disable, 1601 .port_bridge_join = gswip_port_bridge_join, 1602 .port_bridge_leave = gswip_port_bridge_leave, 1603 .port_fast_age = gswip_port_fast_age, 1604 .port_vlan_filtering = gswip_port_vlan_filtering, 1605 .port_vlan_prepare = gswip_port_vlan_prepare, 1606 .port_vlan_add = gswip_port_vlan_add, 1607 .port_vlan_del = gswip_port_vlan_del, 1608 .port_stp_state_set = gswip_port_stp_state_set, 1609 .port_fdb_add = gswip_port_fdb_add, 1610 .port_fdb_del = gswip_port_fdb_del, 1611 .port_fdb_dump = gswip_port_fdb_dump, 1612 .phylink_validate = gswip_phylink_validate, 1613 .phylink_mac_config = gswip_phylink_mac_config, 1614 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1615 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1616 .get_strings = gswip_get_strings, 1617 .get_ethtool_stats = gswip_get_ethtool_stats, 1618 .get_sset_count = gswip_get_sset_count, 1619 }; 1620 1621 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 1622 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 1623 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 1624 }; 1625 1626 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 1627 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 1628 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 1629 }; 1630 1631 static const struct xway_gphy_match_data xrx300_gphy_data = { 1632 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 1633 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 1634 }; 1635 1636 static const struct of_device_id xway_gphy_match[] = { 1637 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 1638 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 1639 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 1640 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 1641 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 1642 {}, 1643 }; 1644 1645 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 1646 { 1647 struct device *dev = priv->dev; 1648 const struct firmware *fw; 1649 void *fw_addr; 1650 dma_addr_t dma_addr; 1651 dma_addr_t dev_addr; 1652 size_t size; 1653 int ret; 1654 1655 ret = clk_prepare_enable(gphy_fw->clk_gate); 1656 if (ret) 1657 return ret; 1658 1659 reset_control_assert(gphy_fw->reset); 1660 1661 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 1662 if (ret) { 1663 dev_err(dev, "failed to load firmware: %s, error: %i\n", 1664 gphy_fw->fw_name, ret); 1665 return ret; 1666 } 1667 1668 /* GPHY cores need the firmware code in a persistent and contiguous 1669 * memory area with a 16 kB boundary aligned start address. 1670 */ 1671 size = fw->size + XRX200_GPHY_FW_ALIGN; 1672 1673 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 1674 if (fw_addr) { 1675 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 1676 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 1677 memcpy(fw_addr, fw->data, fw->size); 1678 } else { 1679 dev_err(dev, "failed to alloc firmware memory\n"); 1680 release_firmware(fw); 1681 return -ENOMEM; 1682 } 1683 1684 release_firmware(fw); 1685 1686 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 1687 if (ret) 1688 return ret; 1689 1690 reset_control_deassert(gphy_fw->reset); 1691 1692 return ret; 1693 } 1694 1695 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 1696 struct gswip_gphy_fw *gphy_fw, 1697 struct device_node *gphy_fw_np, int i) 1698 { 1699 struct device *dev = priv->dev; 1700 u32 gphy_mode; 1701 int ret; 1702 char gphyname[10]; 1703 1704 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 1705 1706 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 1707 if (IS_ERR(gphy_fw->clk_gate)) { 1708 dev_err(dev, "Failed to lookup gate clock\n"); 1709 return PTR_ERR(gphy_fw->clk_gate); 1710 } 1711 1712 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 1713 if (ret) 1714 return ret; 1715 1716 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 1717 /* Default to GE mode */ 1718 if (ret) 1719 gphy_mode = GPHY_MODE_GE; 1720 1721 switch (gphy_mode) { 1722 case GPHY_MODE_FE: 1723 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 1724 break; 1725 case GPHY_MODE_GE: 1726 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 1727 break; 1728 default: 1729 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); 1730 return -EINVAL; 1731 } 1732 1733 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 1734 if (IS_ERR(gphy_fw->reset)) { 1735 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER) 1736 dev_err(dev, "Failed to lookup gphy reset\n"); 1737 return PTR_ERR(gphy_fw->reset); 1738 } 1739 1740 return gswip_gphy_fw_load(priv, gphy_fw); 1741 } 1742 1743 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 1744 struct gswip_gphy_fw *gphy_fw) 1745 { 1746 int ret; 1747 1748 /* check if the device was fully probed */ 1749 if (!gphy_fw->fw_name) 1750 return; 1751 1752 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 1753 if (ret) 1754 dev_err(priv->dev, "can not reset GPHY FW pointer"); 1755 1756 clk_disable_unprepare(gphy_fw->clk_gate); 1757 1758 reset_control_put(gphy_fw->reset); 1759 } 1760 1761 static int gswip_gphy_fw_list(struct gswip_priv *priv, 1762 struct device_node *gphy_fw_list_np, u32 version) 1763 { 1764 struct device *dev = priv->dev; 1765 struct device_node *gphy_fw_np; 1766 const struct of_device_id *match; 1767 int err; 1768 int i = 0; 1769 1770 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 1771 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 1772 * needs a different GPHY firmware. 1773 */ 1774 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 1775 switch (version) { 1776 case GSWIP_VERSION_2_0: 1777 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 1778 break; 1779 case GSWIP_VERSION_2_1: 1780 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 1781 break; 1782 default: 1783 dev_err(dev, "unknown GSWIP version: 0x%x", version); 1784 return -ENOENT; 1785 } 1786 } 1787 1788 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 1789 if (match && match->data) 1790 priv->gphy_fw_name_cfg = match->data; 1791 1792 if (!priv->gphy_fw_name_cfg) { 1793 dev_err(dev, "GPHY compatible type not supported"); 1794 return -ENOENT; 1795 } 1796 1797 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 1798 if (!priv->num_gphy_fw) 1799 return -ENOENT; 1800 1801 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 1802 "lantiq,rcu"); 1803 if (IS_ERR(priv->rcu_regmap)) 1804 return PTR_ERR(priv->rcu_regmap); 1805 1806 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 1807 sizeof(*priv->gphy_fw), 1808 GFP_KERNEL | __GFP_ZERO); 1809 if (!priv->gphy_fw) 1810 return -ENOMEM; 1811 1812 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 1813 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 1814 gphy_fw_np, i); 1815 if (err) 1816 goto remove_gphy; 1817 i++; 1818 } 1819 1820 return 0; 1821 1822 remove_gphy: 1823 for (i = 0; i < priv->num_gphy_fw; i++) 1824 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1825 return err; 1826 } 1827 1828 static int gswip_probe(struct platform_device *pdev) 1829 { 1830 struct gswip_priv *priv; 1831 struct device_node *mdio_np, *gphy_fw_np; 1832 struct device *dev = &pdev->dev; 1833 int err; 1834 int i; 1835 u32 version; 1836 1837 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1838 if (!priv) 1839 return -ENOMEM; 1840 1841 priv->gswip = devm_platform_ioremap_resource(pdev, 0); 1842 if (IS_ERR(priv->gswip)) 1843 return PTR_ERR(priv->gswip); 1844 1845 priv->mdio = devm_platform_ioremap_resource(pdev, 1); 1846 if (IS_ERR(priv->mdio)) 1847 return PTR_ERR(priv->mdio); 1848 1849 priv->mii = devm_platform_ioremap_resource(pdev, 2); 1850 if (IS_ERR(priv->mii)) 1851 return PTR_ERR(priv->mii); 1852 1853 priv->hw_info = of_device_get_match_data(dev); 1854 if (!priv->hw_info) 1855 return -EINVAL; 1856 1857 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 1858 if (!priv->ds) 1859 return -ENOMEM; 1860 1861 priv->ds->dev = dev; 1862 priv->ds->num_ports = priv->hw_info->max_ports; 1863 priv->ds->priv = priv; 1864 priv->ds->ops = &gswip_switch_ops; 1865 priv->dev = dev; 1866 version = gswip_switch_r(priv, GSWIP_VERSION); 1867 1868 /* bring up the mdio bus */ 1869 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 1870 if (gphy_fw_np) { 1871 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 1872 of_node_put(gphy_fw_np); 1873 if (err) { 1874 dev_err(dev, "gphy fw probe failed\n"); 1875 return err; 1876 } 1877 } 1878 1879 /* bring up the mdio bus */ 1880 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio"); 1881 if (mdio_np) { 1882 err = gswip_mdio(priv, mdio_np); 1883 if (err) { 1884 dev_err(dev, "mdio probe failed\n"); 1885 goto put_mdio_node; 1886 } 1887 } 1888 1889 err = dsa_register_switch(priv->ds); 1890 if (err) { 1891 dev_err(dev, "dsa switch register failed: %i\n", err); 1892 goto mdio_bus; 1893 } 1894 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { 1895 dev_err(dev, "wrong CPU port defined, HW only supports port: %i", 1896 priv->hw_info->cpu_port); 1897 err = -EINVAL; 1898 goto disable_switch; 1899 } 1900 1901 platform_set_drvdata(pdev, priv); 1902 1903 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 1904 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, 1905 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); 1906 return 0; 1907 1908 disable_switch: 1909 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 1910 dsa_unregister_switch(priv->ds); 1911 mdio_bus: 1912 if (mdio_np) 1913 mdiobus_unregister(priv->ds->slave_mii_bus); 1914 put_mdio_node: 1915 of_node_put(mdio_np); 1916 for (i = 0; i < priv->num_gphy_fw; i++) 1917 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1918 return err; 1919 } 1920 1921 static int gswip_remove(struct platform_device *pdev) 1922 { 1923 struct gswip_priv *priv = platform_get_drvdata(pdev); 1924 int i; 1925 1926 /* disable the switch */ 1927 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 1928 1929 dsa_unregister_switch(priv->ds); 1930 1931 if (priv->ds->slave_mii_bus) { 1932 mdiobus_unregister(priv->ds->slave_mii_bus); 1933 of_node_put(priv->ds->slave_mii_bus->dev.of_node); 1934 } 1935 1936 for (i = 0; i < priv->num_gphy_fw; i++) 1937 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1938 1939 return 0; 1940 } 1941 1942 static const struct gswip_hw_info gswip_xrx200 = { 1943 .max_ports = 7, 1944 .cpu_port = 6, 1945 }; 1946 1947 static const struct of_device_id gswip_of_match[] = { 1948 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 1949 {}, 1950 }; 1951 MODULE_DEVICE_TABLE(of, gswip_of_match); 1952 1953 static struct platform_driver gswip_driver = { 1954 .probe = gswip_probe, 1955 .remove = gswip_remove, 1956 .driver = { 1957 .name = "gswip", 1958 .of_match_table = gswip_of_match, 1959 }, 1960 }; 1961 1962 module_platform_driver(gswip_driver); 1963 1964 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 1965 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 1966 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 1967 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 1968 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 1969 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 1970 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 1971 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 1972 MODULE_LICENSE("GPL v2"); 1973