1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * The VLAN and bridge model the GSWIP hardware uses does not directly 10 * matches the model DSA uses. 11 * 12 * The hardware has 64 possible table entries for bridges with one VLAN 13 * ID, one flow id and a list of ports for each bridge. All entries which 14 * match the same flow ID are combined in the mac learning table, they 15 * act as one global bridge. 16 * The hardware does not support VLAN filter on the port, but on the 17 * bridge, this driver converts the DSA model to the hardware. 18 * 19 * The CPU gets all the exception frames which do not match any forwarding 20 * rule and the CPU port is also added to all bridges. This makes it possible 21 * to handle all the special cases easily in software. 22 * At the initialization the driver allocates one bridge table entry for 23 * each switch port which is used when the port is used without an 24 * explicit bridge. This prevents the frames from being forwarded 25 * between all LAN ports by default. 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 #include <linux/etherdevice.h> 31 #include <linux/firmware.h> 32 #include <linux/if_bridge.h> 33 #include <linux/if_vlan.h> 34 #include <linux/iopoll.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/module.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/of_platform.h> 40 #include <linux/phy.h> 41 #include <linux/phylink.h> 42 #include <linux/platform_device.h> 43 #include <linux/regmap.h> 44 #include <linux/reset.h> 45 #include <net/dsa.h> 46 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 47 48 #include "lantiq_pce.h" 49 50 /* GSWIP MDIO Registers */ 51 #define GSWIP_MDIO_GLOB 0x00 52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 53 #define GSWIP_MDIO_CTRL 0x08 54 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 55 #define GSWIP_MDIO_CTRL_RD BIT(11) 56 #define GSWIP_MDIO_CTRL_WR BIT(10) 57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 60 #define GSWIP_MDIO_READ 0x09 61 #define GSWIP_MDIO_WRITE 0x0A 62 #define GSWIP_MDIO_MDC_CFG0 0x0B 63 #define GSWIP_MDIO_MDC_CFG1 0x0C 64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 88 GSWIP_MDIO_PHY_FCONRX_MASK | \ 89 GSWIP_MDIO_PHY_FCONTX_MASK | \ 90 GSWIP_MDIO_PHY_LINK_MASK | \ 91 GSWIP_MDIO_PHY_SPEED_MASK | \ 92 GSWIP_MDIO_PHY_FDUP_MASK) 93 94 /* GSWIP MII Registers */ 95 #define GSWIP_MII_CFGp(p) (0x2 * (p)) 96 #define GSWIP_MII_CFG_RESET BIT(15) 97 #define GSWIP_MII_CFG_EN BIT(14) 98 #define GSWIP_MII_CFG_ISOLATE BIT(13) 99 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 100 #define GSWIP_MII_CFG_RGMII_IBS BIT(8) 101 #define GSWIP_MII_CFG_RMII_CLK BIT(7) 102 #define GSWIP_MII_CFG_MODE_MIIP 0x0 103 #define GSWIP_MII_CFG_MODE_MIIM 0x1 104 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 105 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 106 #define GSWIP_MII_CFG_MODE_RGMII 0x4 107 #define GSWIP_MII_CFG_MODE_GMII 0x9 108 #define GSWIP_MII_CFG_MODE_MASK 0xf 109 #define GSWIP_MII_CFG_RATE_M2P5 0x00 110 #define GSWIP_MII_CFG_RATE_M25 0x10 111 #define GSWIP_MII_CFG_RATE_M125 0x20 112 #define GSWIP_MII_CFG_RATE_M50 0x30 113 #define GSWIP_MII_CFG_RATE_AUTO 0x40 114 #define GSWIP_MII_CFG_RATE_MASK 0x70 115 #define GSWIP_MII_PCDU0 0x01 116 #define GSWIP_MII_PCDU1 0x03 117 #define GSWIP_MII_PCDU5 0x05 118 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 119 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 120 121 /* GSWIP Core Registers */ 122 #define GSWIP_SWRES 0x000 123 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 124 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 125 #define GSWIP_VERSION 0x013 126 #define GSWIP_VERSION_REV_SHIFT 0 127 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 128 #define GSWIP_VERSION_MOD_SHIFT 8 129 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 130 #define GSWIP_VERSION_2_0 0x100 131 #define GSWIP_VERSION_2_1 0x021 132 #define GSWIP_VERSION_2_2 0x122 133 #define GSWIP_VERSION_2_2_ETC 0x022 134 135 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 136 #define GSWIP_BM_RAM_ADDR 0x044 137 #define GSWIP_BM_RAM_CTRL 0x045 138 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 139 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 140 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 141 #define GSWIP_BM_QUEUE_GCTRL 0x04A 142 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 143 /* buffer management Port Configuration Register */ 144 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 145 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 146 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 147 /* buffer management Port Control Register */ 148 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 149 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 150 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 151 152 /* PCE */ 153 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 154 #define GSWIP_PCE_TBL_MASK 0x448 155 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 156 #define GSWIP_PCE_TBL_ADDR 0x44E 157 #define GSWIP_PCE_TBL_CTRL 0x44F 158 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 159 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 160 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 161 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 162 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 163 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 164 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 165 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 166 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 167 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 168 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 169 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 170 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 171 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 172 #define GSWIP_PCE_GCTRL_0 0x456 173 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ 174 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 175 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 176 #define GSWIP_PCE_GCTRL_1 0x457 177 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 178 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 179 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 180 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ 181 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ 182 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ 183 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 184 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 185 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 186 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 187 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 188 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 189 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) 190 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ 191 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ 192 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ 193 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ 194 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ 195 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) 196 197 #define GSWIP_MAC_FLEN 0x8C5 198 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC)) 199 #define GSWIP_MAC_CTRL_0_PADEN BIT(8) 200 #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7) 201 #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070 202 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000 203 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010 204 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020 205 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030 206 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040 207 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C 208 #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000 209 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004 210 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C 211 #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003 212 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000 213 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 214 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 215 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 216 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 217 218 /* Ethernet Switch Fetch DMA Port Control Register */ 219 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 220 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 221 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 222 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 223 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 224 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 225 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 226 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 227 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 228 229 /* Ethernet Switch Store DMA Port Control Register */ 230 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 231 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 232 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 233 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */ 234 235 #define GSWIP_TABLE_ACTIVE_VLAN 0x01 236 #define GSWIP_TABLE_VLAN_MAPPING 0x02 237 #define GSWIP_TABLE_MAC_BRIDGE 0x0b 238 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ 239 240 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 241 242 struct gswip_hw_info { 243 int max_ports; 244 int cpu_port; 245 const struct dsa_switch_ops *ops; 246 }; 247 248 struct xway_gphy_match_data { 249 char *fe_firmware_name; 250 char *ge_firmware_name; 251 }; 252 253 struct gswip_gphy_fw { 254 struct clk *clk_gate; 255 struct reset_control *reset; 256 u32 fw_addr_offset; 257 char *fw_name; 258 }; 259 260 struct gswip_vlan { 261 struct net_device *bridge; 262 u16 vid; 263 u8 fid; 264 }; 265 266 struct gswip_priv { 267 __iomem void *gswip; 268 __iomem void *mdio; 269 __iomem void *mii; 270 const struct gswip_hw_info *hw_info; 271 const struct xway_gphy_match_data *gphy_fw_name_cfg; 272 struct dsa_switch *ds; 273 struct device *dev; 274 struct regmap *rcu_regmap; 275 struct gswip_vlan vlans[64]; 276 int num_gphy_fw; 277 struct gswip_gphy_fw *gphy_fw; 278 u32 port_vlan_filter; 279 struct mutex pce_table_lock; 280 }; 281 282 struct gswip_pce_table_entry { 283 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index 284 u16 table; // PCE_TBL_CTRL.ADDR = pData->table 285 u16 key[8]; 286 u16 val[5]; 287 u16 mask; 288 u8 gmap; 289 bool type; 290 bool valid; 291 bool key_mode; 292 }; 293 294 struct gswip_rmon_cnt_desc { 295 unsigned int size; 296 unsigned int offset; 297 const char *name; 298 }; 299 300 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 301 302 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 303 /** Receive Packet Count (only packets that are accepted and not discarded). */ 304 MIB_DESC(1, 0x1F, "RxGoodPkts"), 305 MIB_DESC(1, 0x23, "RxUnicastPkts"), 306 MIB_DESC(1, 0x22, "RxMulticastPkts"), 307 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 308 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 309 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 310 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 311 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 312 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 313 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 314 MIB_DESC(1, 0x12, "Rx64BytePkts"), 315 MIB_DESC(1, 0x13, "Rx127BytePkts"), 316 MIB_DESC(1, 0x14, "Rx255BytePkts"), 317 MIB_DESC(1, 0x15, "Rx511BytePkts"), 318 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 319 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 320 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 321 MIB_DESC(1, 0x18, "RxDroppedPkts"), 322 MIB_DESC(1, 0x19, "RxFilteredPkts"), 323 MIB_DESC(2, 0x24, "RxGoodBytes"), 324 MIB_DESC(2, 0x26, "RxBadBytes"), 325 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 326 MIB_DESC(1, 0x0C, "TxGoodPkts"), 327 MIB_DESC(1, 0x06, "TxUnicastPkts"), 328 MIB_DESC(1, 0x07, "TxMulticastPkts"), 329 MIB_DESC(1, 0x00, "Tx64BytePkts"), 330 MIB_DESC(1, 0x01, "Tx127BytePkts"), 331 MIB_DESC(1, 0x02, "Tx255BytePkts"), 332 MIB_DESC(1, 0x03, "Tx511BytePkts"), 333 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 334 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 335 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 336 MIB_DESC(1, 0x08, "TxSingleCollCount"), 337 MIB_DESC(1, 0x09, "TxMultCollCount"), 338 MIB_DESC(1, 0x0A, "TxLateCollCount"), 339 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 340 MIB_DESC(1, 0x0D, "TxPauseCount"), 341 MIB_DESC(1, 0x10, "TxDroppedPkts"), 342 MIB_DESC(2, 0x0E, "TxGoodBytes"), 343 }; 344 345 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 346 { 347 return __raw_readl(priv->gswip + (offset * 4)); 348 } 349 350 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 351 { 352 __raw_writel(val, priv->gswip + (offset * 4)); 353 } 354 355 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 356 u32 offset) 357 { 358 u32 val = gswip_switch_r(priv, offset); 359 360 val &= ~(clear); 361 val |= set; 362 gswip_switch_w(priv, val, offset); 363 } 364 365 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 366 u32 cleared) 367 { 368 u32 val; 369 370 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 371 (val & cleared) == 0, 20, 50000); 372 } 373 374 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 375 { 376 return __raw_readl(priv->mdio + (offset * 4)); 377 } 378 379 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 380 { 381 __raw_writel(val, priv->mdio + (offset * 4)); 382 } 383 384 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 385 u32 offset) 386 { 387 u32 val = gswip_mdio_r(priv, offset); 388 389 val &= ~(clear); 390 val |= set; 391 gswip_mdio_w(priv, val, offset); 392 } 393 394 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 395 { 396 return __raw_readl(priv->mii + (offset * 4)); 397 } 398 399 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 400 { 401 __raw_writel(val, priv->mii + (offset * 4)); 402 } 403 404 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 405 u32 offset) 406 { 407 u32 val = gswip_mii_r(priv, offset); 408 409 val &= ~(clear); 410 val |= set; 411 gswip_mii_w(priv, val, offset); 412 } 413 414 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 415 int port) 416 { 417 /* There's no MII_CFG register for the CPU port */ 418 if (!dsa_is_cpu_port(priv->ds, port)) 419 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); 420 } 421 422 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 423 int port) 424 { 425 switch (port) { 426 case 0: 427 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 428 break; 429 case 1: 430 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 431 break; 432 case 5: 433 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 434 break; 435 } 436 } 437 438 static int gswip_mdio_poll(struct gswip_priv *priv) 439 { 440 int cnt = 100; 441 442 while (likely(cnt--)) { 443 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 444 445 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 446 return 0; 447 usleep_range(20, 40); 448 } 449 450 return -ETIMEDOUT; 451 } 452 453 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 454 { 455 struct gswip_priv *priv = bus->priv; 456 int err; 457 458 err = gswip_mdio_poll(priv); 459 if (err) { 460 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 461 return err; 462 } 463 464 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 465 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 466 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 467 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 468 GSWIP_MDIO_CTRL); 469 470 return 0; 471 } 472 473 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 474 { 475 struct gswip_priv *priv = bus->priv; 476 int err; 477 478 err = gswip_mdio_poll(priv); 479 if (err) { 480 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 481 return err; 482 } 483 484 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 485 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 486 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 487 GSWIP_MDIO_CTRL); 488 489 err = gswip_mdio_poll(priv); 490 if (err) { 491 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 492 return err; 493 } 494 495 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 496 } 497 498 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np) 499 { 500 struct dsa_switch *ds = priv->ds; 501 int err; 502 503 ds->slave_mii_bus = mdiobus_alloc(); 504 if (!ds->slave_mii_bus) 505 return -ENOMEM; 506 507 ds->slave_mii_bus->priv = priv; 508 ds->slave_mii_bus->read = gswip_mdio_rd; 509 ds->slave_mii_bus->write = gswip_mdio_wr; 510 ds->slave_mii_bus->name = "lantiq,xrx200-mdio"; 511 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", 512 dev_name(priv->dev)); 513 ds->slave_mii_bus->parent = priv->dev; 514 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask; 515 516 err = of_mdiobus_register(ds->slave_mii_bus, mdio_np); 517 if (err) 518 mdiobus_free(ds->slave_mii_bus); 519 520 return err; 521 } 522 523 static int gswip_pce_table_entry_read(struct gswip_priv *priv, 524 struct gswip_pce_table_entry *tbl) 525 { 526 int i; 527 int err; 528 u16 crtl; 529 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 530 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 531 532 mutex_lock(&priv->pce_table_lock); 533 534 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 535 GSWIP_PCE_TBL_CTRL_BAS); 536 if (err) { 537 mutex_unlock(&priv->pce_table_lock); 538 return err; 539 } 540 541 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 542 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 543 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 544 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 545 GSWIP_PCE_TBL_CTRL); 546 547 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 548 GSWIP_PCE_TBL_CTRL_BAS); 549 if (err) { 550 mutex_unlock(&priv->pce_table_lock); 551 return err; 552 } 553 554 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 555 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 556 557 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 558 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 559 560 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 561 562 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 563 564 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 565 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 566 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 567 568 mutex_unlock(&priv->pce_table_lock); 569 570 return 0; 571 } 572 573 static int gswip_pce_table_entry_write(struct gswip_priv *priv, 574 struct gswip_pce_table_entry *tbl) 575 { 576 int i; 577 int err; 578 u16 crtl; 579 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 580 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 581 582 mutex_lock(&priv->pce_table_lock); 583 584 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 585 GSWIP_PCE_TBL_CTRL_BAS); 586 if (err) { 587 mutex_unlock(&priv->pce_table_lock); 588 return err; 589 } 590 591 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 592 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 593 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 594 tbl->table | addr_mode, 595 GSWIP_PCE_TBL_CTRL); 596 597 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 598 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 599 600 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 601 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 602 603 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 604 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 605 tbl->table | addr_mode, 606 GSWIP_PCE_TBL_CTRL); 607 608 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 609 610 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 611 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 612 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 613 if (tbl->type) 614 crtl |= GSWIP_PCE_TBL_CTRL_TYPE; 615 if (tbl->valid) 616 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 617 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 618 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 619 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 620 621 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 622 GSWIP_PCE_TBL_CTRL_BAS); 623 624 mutex_unlock(&priv->pce_table_lock); 625 626 return err; 627 } 628 629 /* Add the LAN port into a bridge with the CPU port by 630 * default. This prevents automatic forwarding of 631 * packages between the LAN ports when no explicit 632 * bridge is configured. 633 */ 634 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) 635 { 636 struct gswip_pce_table_entry vlan_active = {0,}; 637 struct gswip_pce_table_entry vlan_mapping = {0,}; 638 unsigned int cpu_port = priv->hw_info->cpu_port; 639 unsigned int max_ports = priv->hw_info->max_ports; 640 int err; 641 642 if (port >= max_ports) { 643 dev_err(priv->dev, "single port for %i supported\n", port); 644 return -EIO; 645 } 646 647 vlan_active.index = port + 1; 648 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 649 vlan_active.key[0] = 0; /* vid */ 650 vlan_active.val[0] = port + 1 /* fid */; 651 vlan_active.valid = add; 652 err = gswip_pce_table_entry_write(priv, &vlan_active); 653 if (err) { 654 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 655 return err; 656 } 657 658 if (!add) 659 return 0; 660 661 vlan_mapping.index = port + 1; 662 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 663 vlan_mapping.val[0] = 0 /* vid */; 664 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); 665 vlan_mapping.val[2] = 0; 666 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 667 if (err) { 668 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 669 return err; 670 } 671 672 return 0; 673 } 674 675 static int gswip_port_enable(struct dsa_switch *ds, int port, 676 struct phy_device *phydev) 677 { 678 struct gswip_priv *priv = ds->priv; 679 int err; 680 681 if (!dsa_is_user_port(ds, port)) 682 return 0; 683 684 if (!dsa_is_cpu_port(ds, port)) { 685 err = gswip_add_single_port_br(priv, port, true); 686 if (err) 687 return err; 688 } 689 690 /* RMON Counter Enable for port */ 691 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 692 693 /* enable port fetch/store dma & VLAN Modification */ 694 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 695 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 696 GSWIP_FDMA_PCTRLp(port)); 697 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 698 GSWIP_SDMA_PCTRLp(port)); 699 700 if (!dsa_is_cpu_port(ds, port)) { 701 u32 mdio_phy = 0; 702 703 if (phydev) 704 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; 705 706 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, 707 GSWIP_MDIO_PHYp(port)); 708 } 709 710 return 0; 711 } 712 713 static void gswip_port_disable(struct dsa_switch *ds, int port) 714 { 715 struct gswip_priv *priv = ds->priv; 716 717 if (!dsa_is_user_port(ds, port)) 718 return; 719 720 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 721 GSWIP_FDMA_PCTRLp(port)); 722 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 723 GSWIP_SDMA_PCTRLp(port)); 724 } 725 726 static int gswip_pce_load_microcode(struct gswip_priv *priv) 727 { 728 int i; 729 int err; 730 731 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 732 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 733 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 734 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 735 736 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { 737 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 738 gswip_switch_w(priv, gswip_pce_microcode[i].val_0, 739 GSWIP_PCE_TBL_VAL(0)); 740 gswip_switch_w(priv, gswip_pce_microcode[i].val_1, 741 GSWIP_PCE_TBL_VAL(1)); 742 gswip_switch_w(priv, gswip_pce_microcode[i].val_2, 743 GSWIP_PCE_TBL_VAL(2)); 744 gswip_switch_w(priv, gswip_pce_microcode[i].val_3, 745 GSWIP_PCE_TBL_VAL(3)); 746 747 /* start the table access: */ 748 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 749 GSWIP_PCE_TBL_CTRL); 750 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 751 GSWIP_PCE_TBL_CTRL_BAS); 752 if (err) 753 return err; 754 } 755 756 /* tell the switch that the microcode is loaded */ 757 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 758 GSWIP_PCE_GCTRL_0); 759 760 return 0; 761 } 762 763 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 764 bool vlan_filtering, 765 struct netlink_ext_ack *extack) 766 { 767 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 768 struct gswip_priv *priv = ds->priv; 769 770 /* Do not allow changing the VLAN filtering options while in bridge */ 771 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { 772 NL_SET_ERR_MSG_MOD(extack, 773 "Dynamic toggling of vlan_filtering not supported"); 774 return -EIO; 775 } 776 777 if (vlan_filtering) { 778 /* Use port based VLAN tag */ 779 gswip_switch_mask(priv, 780 GSWIP_PCE_VCTRL_VSR, 781 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 782 GSWIP_PCE_VCTRL_VEMR, 783 GSWIP_PCE_VCTRL(port)); 784 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 785 GSWIP_PCE_PCTRL_0p(port)); 786 } else { 787 /* Use port based VLAN tag */ 788 gswip_switch_mask(priv, 789 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 790 GSWIP_PCE_VCTRL_VEMR, 791 GSWIP_PCE_VCTRL_VSR, 792 GSWIP_PCE_VCTRL(port)); 793 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 794 GSWIP_PCE_PCTRL_0p(port)); 795 } 796 797 return 0; 798 } 799 800 static int gswip_setup(struct dsa_switch *ds) 801 { 802 struct gswip_priv *priv = ds->priv; 803 unsigned int cpu_port = priv->hw_info->cpu_port; 804 int i; 805 int err; 806 807 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 808 usleep_range(5000, 10000); 809 gswip_switch_w(priv, 0, GSWIP_SWRES); 810 811 /* disable port fetch/store dma on all ports */ 812 for (i = 0; i < priv->hw_info->max_ports; i++) { 813 gswip_port_disable(ds, i); 814 gswip_port_vlan_filtering(ds, i, false, NULL); 815 } 816 817 /* enable Switch */ 818 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 819 820 err = gswip_pce_load_microcode(priv); 821 if (err) { 822 dev_err(priv->dev, "writing PCE microcode failed, %i", err); 823 return err; 824 } 825 826 /* Default unknown Broadcast/Multicast/Unicast port maps */ 827 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); 828 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); 829 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); 830 831 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an 832 * interoperability problem with this auto polling mechanism because 833 * their status registers think that the link is in a different state 834 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set 835 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the 836 * auto polling state machine consider the link being negotiated with 837 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads 838 * to the switch port being completely dead (RX and TX are both not 839 * working). 840 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F 841 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes 842 * it would work fine for a few minutes to hours and then stop, on 843 * other device it would no traffic could be sent or received at all. 844 * Testing shows that when PHY auto polling is disabled these problems 845 * go away. 846 */ 847 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 848 849 /* Configure the MDIO Clock 2.5 MHz */ 850 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 851 852 /* Disable the xMII interface and clear it's isolation bit */ 853 for (i = 0; i < priv->hw_info->max_ports; i++) 854 gswip_mii_mask_cfg(priv, 855 GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE, 856 0, i); 857 858 /* enable special tag insertion on cpu port */ 859 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 860 GSWIP_FDMA_PCTRLp(cpu_port)); 861 862 /* accept special tag in ingress direction */ 863 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 864 GSWIP_PCE_PCTRL_0p(cpu_port)); 865 866 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 867 GSWIP_MAC_CTRL_2p(cpu_port)); 868 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8 + ETH_FCS_LEN, 869 GSWIP_MAC_FLEN); 870 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 871 GSWIP_BM_QUEUE_GCTRL); 872 873 /* VLAN aware Switching */ 874 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 875 876 /* Flush MAC Table */ 877 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 878 879 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 880 GSWIP_PCE_GCTRL_0_MTFL); 881 if (err) { 882 dev_err(priv->dev, "MAC flushing didn't finish\n"); 883 return err; 884 } 885 886 gswip_port_enable(ds, cpu_port, NULL); 887 888 ds->configure_vlan_while_not_filtering = false; 889 890 return 0; 891 } 892 893 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 894 int port, 895 enum dsa_tag_protocol mp) 896 { 897 return DSA_TAG_PROTO_GSWIP; 898 } 899 900 static int gswip_vlan_active_create(struct gswip_priv *priv, 901 struct net_device *bridge, 902 int fid, u16 vid) 903 { 904 struct gswip_pce_table_entry vlan_active = {0,}; 905 unsigned int max_ports = priv->hw_info->max_ports; 906 int idx = -1; 907 int err; 908 int i; 909 910 /* Look for a free slot */ 911 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 912 if (!priv->vlans[i].bridge) { 913 idx = i; 914 break; 915 } 916 } 917 918 if (idx == -1) 919 return -ENOSPC; 920 921 if (fid == -1) 922 fid = idx; 923 924 vlan_active.index = idx; 925 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 926 vlan_active.key[0] = vid; 927 vlan_active.val[0] = fid; 928 vlan_active.valid = true; 929 930 err = gswip_pce_table_entry_write(priv, &vlan_active); 931 if (err) { 932 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 933 return err; 934 } 935 936 priv->vlans[idx].bridge = bridge; 937 priv->vlans[idx].vid = vid; 938 priv->vlans[idx].fid = fid; 939 940 return idx; 941 } 942 943 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) 944 { 945 struct gswip_pce_table_entry vlan_active = {0,}; 946 int err; 947 948 vlan_active.index = idx; 949 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 950 vlan_active.valid = false; 951 err = gswip_pce_table_entry_write(priv, &vlan_active); 952 if (err) 953 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); 954 priv->vlans[idx].bridge = NULL; 955 956 return err; 957 } 958 959 static int gswip_vlan_add_unaware(struct gswip_priv *priv, 960 struct net_device *bridge, int port) 961 { 962 struct gswip_pce_table_entry vlan_mapping = {0,}; 963 unsigned int max_ports = priv->hw_info->max_ports; 964 unsigned int cpu_port = priv->hw_info->cpu_port; 965 bool active_vlan_created = false; 966 int idx = -1; 967 int i; 968 int err; 969 970 /* Check if there is already a page for this bridge */ 971 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 972 if (priv->vlans[i].bridge == bridge) { 973 idx = i; 974 break; 975 } 976 } 977 978 /* If this bridge is not programmed yet, add a Active VLAN table 979 * entry in a free slot and prepare the VLAN mapping table entry. 980 */ 981 if (idx == -1) { 982 idx = gswip_vlan_active_create(priv, bridge, -1, 0); 983 if (idx < 0) 984 return idx; 985 active_vlan_created = true; 986 987 vlan_mapping.index = idx; 988 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 989 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 990 vlan_mapping.val[0] = 0; 991 } else { 992 /* Read the existing VLAN mapping entry from the switch */ 993 vlan_mapping.index = idx; 994 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 995 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 996 if (err) { 997 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 998 err); 999 return err; 1000 } 1001 } 1002 1003 /* Update the VLAN mapping entry and write it to the switch */ 1004 vlan_mapping.val[1] |= BIT(cpu_port); 1005 vlan_mapping.val[1] |= BIT(port); 1006 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1007 if (err) { 1008 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1009 /* In case an Active VLAN was creaetd delete it again */ 1010 if (active_vlan_created) 1011 gswip_vlan_active_remove(priv, idx); 1012 return err; 1013 } 1014 1015 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1016 return 0; 1017 } 1018 1019 static int gswip_vlan_add_aware(struct gswip_priv *priv, 1020 struct net_device *bridge, int port, 1021 u16 vid, bool untagged, 1022 bool pvid) 1023 { 1024 struct gswip_pce_table_entry vlan_mapping = {0,}; 1025 unsigned int max_ports = priv->hw_info->max_ports; 1026 unsigned int cpu_port = priv->hw_info->cpu_port; 1027 bool active_vlan_created = false; 1028 int idx = -1; 1029 int fid = -1; 1030 int i; 1031 int err; 1032 1033 /* Check if there is already a page for this bridge */ 1034 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1035 if (priv->vlans[i].bridge == bridge) { 1036 if (fid != -1 && fid != priv->vlans[i].fid) 1037 dev_err(priv->dev, "one bridge with multiple flow ids\n"); 1038 fid = priv->vlans[i].fid; 1039 if (priv->vlans[i].vid == vid) { 1040 idx = i; 1041 break; 1042 } 1043 } 1044 } 1045 1046 /* If this bridge is not programmed yet, add a Active VLAN table 1047 * entry in a free slot and prepare the VLAN mapping table entry. 1048 */ 1049 if (idx == -1) { 1050 idx = gswip_vlan_active_create(priv, bridge, fid, vid); 1051 if (idx < 0) 1052 return idx; 1053 active_vlan_created = true; 1054 1055 vlan_mapping.index = idx; 1056 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1057 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 1058 vlan_mapping.val[0] = vid; 1059 } else { 1060 /* Read the existing VLAN mapping entry from the switch */ 1061 vlan_mapping.index = idx; 1062 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1063 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1064 if (err) { 1065 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 1066 err); 1067 return err; 1068 } 1069 } 1070 1071 vlan_mapping.val[0] = vid; 1072 /* Update the VLAN mapping entry and write it to the switch */ 1073 vlan_mapping.val[1] |= BIT(cpu_port); 1074 vlan_mapping.val[2] |= BIT(cpu_port); 1075 vlan_mapping.val[1] |= BIT(port); 1076 if (untagged) 1077 vlan_mapping.val[2] &= ~BIT(port); 1078 else 1079 vlan_mapping.val[2] |= BIT(port); 1080 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1081 if (err) { 1082 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1083 /* In case an Active VLAN was creaetd delete it again */ 1084 if (active_vlan_created) 1085 gswip_vlan_active_remove(priv, idx); 1086 return err; 1087 } 1088 1089 if (pvid) 1090 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 1091 1092 return 0; 1093 } 1094 1095 static int gswip_vlan_remove(struct gswip_priv *priv, 1096 struct net_device *bridge, int port, 1097 u16 vid, bool pvid, bool vlan_aware) 1098 { 1099 struct gswip_pce_table_entry vlan_mapping = {0,}; 1100 unsigned int max_ports = priv->hw_info->max_ports; 1101 unsigned int cpu_port = priv->hw_info->cpu_port; 1102 int idx = -1; 1103 int i; 1104 int err; 1105 1106 /* Check if there is already a page for this bridge */ 1107 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1108 if (priv->vlans[i].bridge == bridge && 1109 (!vlan_aware || priv->vlans[i].vid == vid)) { 1110 idx = i; 1111 break; 1112 } 1113 } 1114 1115 if (idx == -1) { 1116 dev_err(priv->dev, "bridge to leave does not exists\n"); 1117 return -ENOENT; 1118 } 1119 1120 vlan_mapping.index = idx; 1121 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1122 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1123 if (err) { 1124 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); 1125 return err; 1126 } 1127 1128 vlan_mapping.val[1] &= ~BIT(port); 1129 vlan_mapping.val[2] &= ~BIT(port); 1130 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1131 if (err) { 1132 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1133 return err; 1134 } 1135 1136 /* In case all ports are removed from the bridge, remove the VLAN */ 1137 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { 1138 err = gswip_vlan_active_remove(priv, idx); 1139 if (err) { 1140 dev_err(priv->dev, "failed to write active VLAN: %d\n", 1141 err); 1142 return err; 1143 } 1144 } 1145 1146 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 1147 if (pvid) 1148 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1149 1150 return 0; 1151 } 1152 1153 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, 1154 struct dsa_bridge bridge, 1155 bool *tx_fwd_offload) 1156 { 1157 struct net_device *br = bridge.dev; 1158 struct gswip_priv *priv = ds->priv; 1159 int err; 1160 1161 /* When the bridge uses VLAN filtering we have to configure VLAN 1162 * specific bridges. No bridge is configured here. 1163 */ 1164 if (!br_vlan_enabled(br)) { 1165 err = gswip_vlan_add_unaware(priv, br, port); 1166 if (err) 1167 return err; 1168 priv->port_vlan_filter &= ~BIT(port); 1169 } else { 1170 priv->port_vlan_filter |= BIT(port); 1171 } 1172 return gswip_add_single_port_br(priv, port, false); 1173 } 1174 1175 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, 1176 struct dsa_bridge bridge) 1177 { 1178 struct net_device *br = bridge.dev; 1179 struct gswip_priv *priv = ds->priv; 1180 1181 gswip_add_single_port_br(priv, port, true); 1182 1183 /* When the bridge uses VLAN filtering we have to configure VLAN 1184 * specific bridges. No bridge is configured here. 1185 */ 1186 if (!br_vlan_enabled(br)) 1187 gswip_vlan_remove(priv, br, port, 0, true, false); 1188 } 1189 1190 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, 1191 const struct switchdev_obj_port_vlan *vlan, 1192 struct netlink_ext_ack *extack) 1193 { 1194 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1195 struct gswip_priv *priv = ds->priv; 1196 unsigned int max_ports = priv->hw_info->max_ports; 1197 int pos = max_ports; 1198 int i, idx = -1; 1199 1200 /* We only support VLAN filtering on bridges */ 1201 if (!dsa_is_cpu_port(ds, port) && !bridge) 1202 return -EOPNOTSUPP; 1203 1204 /* Check if there is already a page for this VLAN */ 1205 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1206 if (priv->vlans[i].bridge == bridge && 1207 priv->vlans[i].vid == vlan->vid) { 1208 idx = i; 1209 break; 1210 } 1211 } 1212 1213 /* If this VLAN is not programmed yet, we have to reserve 1214 * one entry in the VLAN table. Make sure we start at the 1215 * next position round. 1216 */ 1217 if (idx == -1) { 1218 /* Look for a free slot */ 1219 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { 1220 if (!priv->vlans[pos].bridge) { 1221 idx = pos; 1222 pos++; 1223 break; 1224 } 1225 } 1226 1227 if (idx == -1) { 1228 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table"); 1229 return -ENOSPC; 1230 } 1231 } 1232 1233 return 0; 1234 } 1235 1236 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, 1237 const struct switchdev_obj_port_vlan *vlan, 1238 struct netlink_ext_ack *extack) 1239 { 1240 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1241 struct gswip_priv *priv = ds->priv; 1242 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1243 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1244 int err; 1245 1246 err = gswip_port_vlan_prepare(ds, port, vlan, extack); 1247 if (err) 1248 return err; 1249 1250 /* We have to receive all packets on the CPU port and should not 1251 * do any VLAN filtering here. This is also called with bridge 1252 * NULL and then we do not know for which bridge to configure 1253 * this. 1254 */ 1255 if (dsa_is_cpu_port(ds, port)) 1256 return 0; 1257 1258 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, 1259 untagged, pvid); 1260 } 1261 1262 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, 1263 const struct switchdev_obj_port_vlan *vlan) 1264 { 1265 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1266 struct gswip_priv *priv = ds->priv; 1267 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1268 1269 /* We have to receive all packets on the CPU port and should not 1270 * do any VLAN filtering here. This is also called with bridge 1271 * NULL and then we do not know for which bridge to configure 1272 * this. 1273 */ 1274 if (dsa_is_cpu_port(ds, port)) 1275 return 0; 1276 1277 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); 1278 } 1279 1280 static void gswip_port_fast_age(struct dsa_switch *ds, int port) 1281 { 1282 struct gswip_priv *priv = ds->priv; 1283 struct gswip_pce_table_entry mac_bridge = {0,}; 1284 int i; 1285 int err; 1286 1287 for (i = 0; i < 2048; i++) { 1288 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1289 mac_bridge.index = i; 1290 1291 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1292 if (err) { 1293 dev_err(priv->dev, "failed to read mac bridge: %d\n", 1294 err); 1295 return; 1296 } 1297 1298 if (!mac_bridge.valid) 1299 continue; 1300 1301 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) 1302 continue; 1303 1304 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) 1305 continue; 1306 1307 mac_bridge.valid = false; 1308 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1309 if (err) { 1310 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1311 err); 1312 return; 1313 } 1314 } 1315 } 1316 1317 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1318 { 1319 struct gswip_priv *priv = ds->priv; 1320 u32 stp_state; 1321 1322 switch (state) { 1323 case BR_STATE_DISABLED: 1324 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1325 GSWIP_SDMA_PCTRLp(port)); 1326 return; 1327 case BR_STATE_BLOCKING: 1328 case BR_STATE_LISTENING: 1329 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; 1330 break; 1331 case BR_STATE_LEARNING: 1332 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; 1333 break; 1334 case BR_STATE_FORWARDING: 1335 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; 1336 break; 1337 default: 1338 dev_err(priv->dev, "invalid STP state: %d\n", state); 1339 return; 1340 } 1341 1342 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1343 GSWIP_SDMA_PCTRLp(port)); 1344 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1345 GSWIP_PCE_PCTRL_0p(port)); 1346 } 1347 1348 static int gswip_port_fdb(struct dsa_switch *ds, int port, 1349 const unsigned char *addr, u16 vid, bool add) 1350 { 1351 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1352 struct gswip_priv *priv = ds->priv; 1353 struct gswip_pce_table_entry mac_bridge = {0,}; 1354 unsigned int cpu_port = priv->hw_info->cpu_port; 1355 int fid = -1; 1356 int i; 1357 int err; 1358 1359 if (!bridge) 1360 return -EINVAL; 1361 1362 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) { 1363 if (priv->vlans[i].bridge == bridge) { 1364 fid = priv->vlans[i].fid; 1365 break; 1366 } 1367 } 1368 1369 if (fid == -1) { 1370 dev_err(priv->dev, "Port not part of a bridge\n"); 1371 return -EINVAL; 1372 } 1373 1374 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1375 mac_bridge.key_mode = true; 1376 mac_bridge.key[0] = addr[5] | (addr[4] << 8); 1377 mac_bridge.key[1] = addr[3] | (addr[2] << 8); 1378 mac_bridge.key[2] = addr[1] | (addr[0] << 8); 1379 mac_bridge.key[3] = fid; 1380 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ 1381 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; 1382 mac_bridge.valid = add; 1383 1384 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1385 if (err) 1386 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); 1387 1388 return err; 1389 } 1390 1391 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, 1392 const unsigned char *addr, u16 vid) 1393 { 1394 return gswip_port_fdb(ds, port, addr, vid, true); 1395 } 1396 1397 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, 1398 const unsigned char *addr, u16 vid) 1399 { 1400 return gswip_port_fdb(ds, port, addr, vid, false); 1401 } 1402 1403 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, 1404 dsa_fdb_dump_cb_t *cb, void *data) 1405 { 1406 struct gswip_priv *priv = ds->priv; 1407 struct gswip_pce_table_entry mac_bridge = {0,}; 1408 unsigned char addr[6]; 1409 int i; 1410 int err; 1411 1412 for (i = 0; i < 2048; i++) { 1413 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1414 mac_bridge.index = i; 1415 1416 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1417 if (err) { 1418 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1419 err); 1420 return err; 1421 } 1422 1423 if (!mac_bridge.valid) 1424 continue; 1425 1426 addr[5] = mac_bridge.key[0] & 0xff; 1427 addr[4] = (mac_bridge.key[0] >> 8) & 0xff; 1428 addr[3] = mac_bridge.key[1] & 0xff; 1429 addr[2] = (mac_bridge.key[1] >> 8) & 0xff; 1430 addr[1] = mac_bridge.key[2] & 0xff; 1431 addr[0] = (mac_bridge.key[2] >> 8) & 0xff; 1432 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { 1433 if (mac_bridge.val[0] & BIT(port)) { 1434 err = cb(addr, 0, true, data); 1435 if (err) 1436 return err; 1437 } 1438 } else { 1439 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) { 1440 err = cb(addr, 0, false, data); 1441 if (err) 1442 return err; 1443 } 1444 } 1445 } 1446 return 0; 1447 } 1448 1449 static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port, 1450 struct phylink_config *config) 1451 { 1452 switch (port) { 1453 case 0: 1454 case 1: 1455 phy_interface_set_rgmii(config->supported_interfaces); 1456 __set_bit(PHY_INTERFACE_MODE_MII, 1457 config->supported_interfaces); 1458 __set_bit(PHY_INTERFACE_MODE_REVMII, 1459 config->supported_interfaces); 1460 __set_bit(PHY_INTERFACE_MODE_RMII, 1461 config->supported_interfaces); 1462 break; 1463 1464 case 2: 1465 case 3: 1466 case 4: 1467 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1468 config->supported_interfaces); 1469 break; 1470 1471 case 5: 1472 phy_interface_set_rgmii(config->supported_interfaces); 1473 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1474 config->supported_interfaces); 1475 break; 1476 } 1477 1478 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1479 MAC_10 | MAC_100 | MAC_1000; 1480 } 1481 1482 static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port, 1483 struct phylink_config *config) 1484 { 1485 switch (port) { 1486 case 0: 1487 phy_interface_set_rgmii(config->supported_interfaces); 1488 __set_bit(PHY_INTERFACE_MODE_GMII, 1489 config->supported_interfaces); 1490 __set_bit(PHY_INTERFACE_MODE_RMII, 1491 config->supported_interfaces); 1492 break; 1493 1494 case 1: 1495 case 2: 1496 case 3: 1497 case 4: 1498 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1499 config->supported_interfaces); 1500 break; 1501 1502 case 5: 1503 phy_interface_set_rgmii(config->supported_interfaces); 1504 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1505 config->supported_interfaces); 1506 __set_bit(PHY_INTERFACE_MODE_RMII, 1507 config->supported_interfaces); 1508 break; 1509 } 1510 1511 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1512 MAC_10 | MAC_100 | MAC_1000; 1513 } 1514 1515 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) 1516 { 1517 u32 mdio_phy; 1518 1519 if (link) 1520 mdio_phy = GSWIP_MDIO_PHY_LINK_UP; 1521 else 1522 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN; 1523 1524 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy, 1525 GSWIP_MDIO_PHYp(port)); 1526 } 1527 1528 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, 1529 phy_interface_t interface) 1530 { 1531 u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0; 1532 1533 switch (speed) { 1534 case SPEED_10: 1535 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10; 1536 1537 if (interface == PHY_INTERFACE_MODE_RMII) 1538 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1539 else 1540 mii_cfg = GSWIP_MII_CFG_RATE_M2P5; 1541 1542 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1543 break; 1544 1545 case SPEED_100: 1546 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100; 1547 1548 if (interface == PHY_INTERFACE_MODE_RMII) 1549 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1550 else 1551 mii_cfg = GSWIP_MII_CFG_RATE_M25; 1552 1553 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1554 break; 1555 1556 case SPEED_1000: 1557 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1; 1558 1559 mii_cfg = GSWIP_MII_CFG_RATE_M125; 1560 1561 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII; 1562 break; 1563 } 1564 1565 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy, 1566 GSWIP_MDIO_PHYp(port)); 1567 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); 1568 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0, 1569 GSWIP_MAC_CTRL_0p(port)); 1570 } 1571 1572 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) 1573 { 1574 u32 mac_ctrl_0, mdio_phy; 1575 1576 if (duplex == DUPLEX_FULL) { 1577 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN; 1578 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN; 1579 } else { 1580 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS; 1581 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS; 1582 } 1583 1584 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0, 1585 GSWIP_MAC_CTRL_0p(port)); 1586 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy, 1587 GSWIP_MDIO_PHYp(port)); 1588 } 1589 1590 static void gswip_port_set_pause(struct gswip_priv *priv, int port, 1591 bool tx_pause, bool rx_pause) 1592 { 1593 u32 mac_ctrl_0, mdio_phy; 1594 1595 if (tx_pause && rx_pause) { 1596 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX; 1597 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1598 GSWIP_MDIO_PHY_FCONRX_EN; 1599 } else if (tx_pause) { 1600 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX; 1601 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1602 GSWIP_MDIO_PHY_FCONRX_DIS; 1603 } else if (rx_pause) { 1604 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX; 1605 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1606 GSWIP_MDIO_PHY_FCONRX_EN; 1607 } else { 1608 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE; 1609 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1610 GSWIP_MDIO_PHY_FCONRX_DIS; 1611 } 1612 1613 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK, 1614 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); 1615 gswip_mdio_mask(priv, 1616 GSWIP_MDIO_PHY_FCONTX_MASK | 1617 GSWIP_MDIO_PHY_FCONRX_MASK, 1618 mdio_phy, GSWIP_MDIO_PHYp(port)); 1619 } 1620 1621 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, 1622 unsigned int mode, 1623 const struct phylink_link_state *state) 1624 { 1625 struct gswip_priv *priv = ds->priv; 1626 u32 miicfg = 0; 1627 1628 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 1629 1630 switch (state->interface) { 1631 case PHY_INTERFACE_MODE_MII: 1632 case PHY_INTERFACE_MODE_INTERNAL: 1633 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 1634 break; 1635 case PHY_INTERFACE_MODE_REVMII: 1636 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 1637 break; 1638 case PHY_INTERFACE_MODE_RMII: 1639 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 1640 1641 /* Configure the RMII clock as output: */ 1642 miicfg |= GSWIP_MII_CFG_RMII_CLK; 1643 break; 1644 case PHY_INTERFACE_MODE_RGMII: 1645 case PHY_INTERFACE_MODE_RGMII_ID: 1646 case PHY_INTERFACE_MODE_RGMII_RXID: 1647 case PHY_INTERFACE_MODE_RGMII_TXID: 1648 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 1649 break; 1650 case PHY_INTERFACE_MODE_GMII: 1651 miicfg |= GSWIP_MII_CFG_MODE_GMII; 1652 break; 1653 default: 1654 dev_err(ds->dev, 1655 "Unsupported interface: %d\n", state->interface); 1656 return; 1657 } 1658 1659 gswip_mii_mask_cfg(priv, 1660 GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK | 1661 GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS, 1662 miicfg, port); 1663 1664 switch (state->interface) { 1665 case PHY_INTERFACE_MODE_RGMII_ID: 1666 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 1667 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1668 break; 1669 case PHY_INTERFACE_MODE_RGMII_RXID: 1670 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1671 break; 1672 case PHY_INTERFACE_MODE_RGMII_TXID: 1673 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 1674 break; 1675 default: 1676 break; 1677 } 1678 } 1679 1680 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, 1681 unsigned int mode, 1682 phy_interface_t interface) 1683 { 1684 struct gswip_priv *priv = ds->priv; 1685 1686 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 1687 1688 if (!dsa_is_cpu_port(ds, port)) 1689 gswip_port_set_link(priv, port, false); 1690 } 1691 1692 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, 1693 unsigned int mode, 1694 phy_interface_t interface, 1695 struct phy_device *phydev, 1696 int speed, int duplex, 1697 bool tx_pause, bool rx_pause) 1698 { 1699 struct gswip_priv *priv = ds->priv; 1700 1701 if (!dsa_is_cpu_port(ds, port)) { 1702 gswip_port_set_link(priv, port, true); 1703 gswip_port_set_speed(priv, port, speed, interface); 1704 gswip_port_set_duplex(priv, port, duplex); 1705 gswip_port_set_pause(priv, port, tx_pause, rx_pause); 1706 } 1707 1708 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1709 } 1710 1711 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1712 uint8_t *data) 1713 { 1714 int i; 1715 1716 if (stringset != ETH_SS_STATS) 1717 return; 1718 1719 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 1720 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name, 1721 ETH_GSTRING_LEN); 1722 } 1723 1724 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1725 u32 index) 1726 { 1727 u32 result; 1728 int err; 1729 1730 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1731 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1732 GSWIP_BM_RAM_CTRL_OPMOD, 1733 table | GSWIP_BM_RAM_CTRL_BAS, 1734 GSWIP_BM_RAM_CTRL); 1735 1736 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1737 GSWIP_BM_RAM_CTRL_BAS); 1738 if (err) { 1739 dev_err(priv->dev, "timeout while reading table: %u, index: %u", 1740 table, index); 1741 return 0; 1742 } 1743 1744 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1745 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1746 1747 return result; 1748 } 1749 1750 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 1751 uint64_t *data) 1752 { 1753 struct gswip_priv *priv = ds->priv; 1754 const struct gswip_rmon_cnt_desc *rmon_cnt; 1755 int i; 1756 u64 high; 1757 1758 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 1759 rmon_cnt = &gswip_rmon_cnt[i]; 1760 1761 data[i] = gswip_bcm_ram_entry_read(priv, port, 1762 rmon_cnt->offset); 1763 if (rmon_cnt->size == 2) { 1764 high = gswip_bcm_ram_entry_read(priv, port, 1765 rmon_cnt->offset + 1); 1766 data[i] |= high << 32; 1767 } 1768 } 1769 } 1770 1771 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 1772 { 1773 if (sset != ETH_SS_STATS) 1774 return 0; 1775 1776 return ARRAY_SIZE(gswip_rmon_cnt); 1777 } 1778 1779 static const struct dsa_switch_ops gswip_xrx200_switch_ops = { 1780 .get_tag_protocol = gswip_get_tag_protocol, 1781 .setup = gswip_setup, 1782 .port_enable = gswip_port_enable, 1783 .port_disable = gswip_port_disable, 1784 .port_bridge_join = gswip_port_bridge_join, 1785 .port_bridge_leave = gswip_port_bridge_leave, 1786 .port_fast_age = gswip_port_fast_age, 1787 .port_vlan_filtering = gswip_port_vlan_filtering, 1788 .port_vlan_add = gswip_port_vlan_add, 1789 .port_vlan_del = gswip_port_vlan_del, 1790 .port_stp_state_set = gswip_port_stp_state_set, 1791 .port_fdb_add = gswip_port_fdb_add, 1792 .port_fdb_del = gswip_port_fdb_del, 1793 .port_fdb_dump = gswip_port_fdb_dump, 1794 .phylink_get_caps = gswip_xrx200_phylink_get_caps, 1795 .phylink_mac_config = gswip_phylink_mac_config, 1796 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1797 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1798 .get_strings = gswip_get_strings, 1799 .get_ethtool_stats = gswip_get_ethtool_stats, 1800 .get_sset_count = gswip_get_sset_count, 1801 }; 1802 1803 static const struct dsa_switch_ops gswip_xrx300_switch_ops = { 1804 .get_tag_protocol = gswip_get_tag_protocol, 1805 .setup = gswip_setup, 1806 .port_enable = gswip_port_enable, 1807 .port_disable = gswip_port_disable, 1808 .port_bridge_join = gswip_port_bridge_join, 1809 .port_bridge_leave = gswip_port_bridge_leave, 1810 .port_fast_age = gswip_port_fast_age, 1811 .port_vlan_filtering = gswip_port_vlan_filtering, 1812 .port_vlan_add = gswip_port_vlan_add, 1813 .port_vlan_del = gswip_port_vlan_del, 1814 .port_stp_state_set = gswip_port_stp_state_set, 1815 .port_fdb_add = gswip_port_fdb_add, 1816 .port_fdb_del = gswip_port_fdb_del, 1817 .port_fdb_dump = gswip_port_fdb_dump, 1818 .phylink_get_caps = gswip_xrx300_phylink_get_caps, 1819 .phylink_mac_config = gswip_phylink_mac_config, 1820 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1821 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1822 .get_strings = gswip_get_strings, 1823 .get_ethtool_stats = gswip_get_ethtool_stats, 1824 .get_sset_count = gswip_get_sset_count, 1825 }; 1826 1827 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 1828 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 1829 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 1830 }; 1831 1832 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 1833 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 1834 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 1835 }; 1836 1837 static const struct xway_gphy_match_data xrx300_gphy_data = { 1838 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 1839 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 1840 }; 1841 1842 static const struct of_device_id xway_gphy_match[] = { 1843 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 1844 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 1845 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 1846 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 1847 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 1848 {}, 1849 }; 1850 1851 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 1852 { 1853 struct device *dev = priv->dev; 1854 const struct firmware *fw; 1855 void *fw_addr; 1856 dma_addr_t dma_addr; 1857 dma_addr_t dev_addr; 1858 size_t size; 1859 int ret; 1860 1861 ret = clk_prepare_enable(gphy_fw->clk_gate); 1862 if (ret) 1863 return ret; 1864 1865 reset_control_assert(gphy_fw->reset); 1866 1867 /* The vendor BSP uses a 200ms delay after asserting the reset line. 1868 * Without this some users are observing that the PHY is not coming up 1869 * on the MDIO bus. 1870 */ 1871 msleep(200); 1872 1873 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 1874 if (ret) { 1875 dev_err(dev, "failed to load firmware: %s, error: %i\n", 1876 gphy_fw->fw_name, ret); 1877 return ret; 1878 } 1879 1880 /* GPHY cores need the firmware code in a persistent and contiguous 1881 * memory area with a 16 kB boundary aligned start address. 1882 */ 1883 size = fw->size + XRX200_GPHY_FW_ALIGN; 1884 1885 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 1886 if (fw_addr) { 1887 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 1888 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 1889 memcpy(fw_addr, fw->data, fw->size); 1890 } else { 1891 dev_err(dev, "failed to alloc firmware memory\n"); 1892 release_firmware(fw); 1893 return -ENOMEM; 1894 } 1895 1896 release_firmware(fw); 1897 1898 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 1899 if (ret) 1900 return ret; 1901 1902 reset_control_deassert(gphy_fw->reset); 1903 1904 return ret; 1905 } 1906 1907 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 1908 struct gswip_gphy_fw *gphy_fw, 1909 struct device_node *gphy_fw_np, int i) 1910 { 1911 struct device *dev = priv->dev; 1912 u32 gphy_mode; 1913 int ret; 1914 char gphyname[10]; 1915 1916 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 1917 1918 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 1919 if (IS_ERR(gphy_fw->clk_gate)) { 1920 dev_err(dev, "Failed to lookup gate clock\n"); 1921 return PTR_ERR(gphy_fw->clk_gate); 1922 } 1923 1924 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 1925 if (ret) 1926 return ret; 1927 1928 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 1929 /* Default to GE mode */ 1930 if (ret) 1931 gphy_mode = GPHY_MODE_GE; 1932 1933 switch (gphy_mode) { 1934 case GPHY_MODE_FE: 1935 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 1936 break; 1937 case GPHY_MODE_GE: 1938 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 1939 break; 1940 default: 1941 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); 1942 return -EINVAL; 1943 } 1944 1945 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 1946 if (IS_ERR(gphy_fw->reset)) { 1947 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER) 1948 dev_err(dev, "Failed to lookup gphy reset\n"); 1949 return PTR_ERR(gphy_fw->reset); 1950 } 1951 1952 return gswip_gphy_fw_load(priv, gphy_fw); 1953 } 1954 1955 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 1956 struct gswip_gphy_fw *gphy_fw) 1957 { 1958 int ret; 1959 1960 /* check if the device was fully probed */ 1961 if (!gphy_fw->fw_name) 1962 return; 1963 1964 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 1965 if (ret) 1966 dev_err(priv->dev, "can not reset GPHY FW pointer"); 1967 1968 clk_disable_unprepare(gphy_fw->clk_gate); 1969 1970 reset_control_put(gphy_fw->reset); 1971 } 1972 1973 static int gswip_gphy_fw_list(struct gswip_priv *priv, 1974 struct device_node *gphy_fw_list_np, u32 version) 1975 { 1976 struct device *dev = priv->dev; 1977 struct device_node *gphy_fw_np; 1978 const struct of_device_id *match; 1979 int err; 1980 int i = 0; 1981 1982 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 1983 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 1984 * needs a different GPHY firmware. 1985 */ 1986 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 1987 switch (version) { 1988 case GSWIP_VERSION_2_0: 1989 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 1990 break; 1991 case GSWIP_VERSION_2_1: 1992 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 1993 break; 1994 default: 1995 dev_err(dev, "unknown GSWIP version: 0x%x", version); 1996 return -ENOENT; 1997 } 1998 } 1999 2000 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 2001 if (match && match->data) 2002 priv->gphy_fw_name_cfg = match->data; 2003 2004 if (!priv->gphy_fw_name_cfg) { 2005 dev_err(dev, "GPHY compatible type not supported"); 2006 return -ENOENT; 2007 } 2008 2009 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 2010 if (!priv->num_gphy_fw) 2011 return -ENOENT; 2012 2013 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 2014 "lantiq,rcu"); 2015 if (IS_ERR(priv->rcu_regmap)) 2016 return PTR_ERR(priv->rcu_regmap); 2017 2018 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 2019 sizeof(*priv->gphy_fw), 2020 GFP_KERNEL | __GFP_ZERO); 2021 if (!priv->gphy_fw) 2022 return -ENOMEM; 2023 2024 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 2025 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 2026 gphy_fw_np, i); 2027 if (err) 2028 goto remove_gphy; 2029 i++; 2030 } 2031 2032 /* The standalone PHY11G requires 300ms to be fully 2033 * initialized and ready for any MDIO communication after being 2034 * taken out of reset. For the SoC-internal GPHY variant there 2035 * is no (known) documentation for the minimum time after a 2036 * reset. Use the same value as for the standalone variant as 2037 * some users have reported internal PHYs not being detected 2038 * without any delay. 2039 */ 2040 msleep(300); 2041 2042 return 0; 2043 2044 remove_gphy: 2045 for (i = 0; i < priv->num_gphy_fw; i++) 2046 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2047 return err; 2048 } 2049 2050 static int gswip_probe(struct platform_device *pdev) 2051 { 2052 struct gswip_priv *priv; 2053 struct device_node *np, *mdio_np, *gphy_fw_np; 2054 struct device *dev = &pdev->dev; 2055 int err; 2056 int i; 2057 u32 version; 2058 2059 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2060 if (!priv) 2061 return -ENOMEM; 2062 2063 priv->gswip = devm_platform_ioremap_resource(pdev, 0); 2064 if (IS_ERR(priv->gswip)) 2065 return PTR_ERR(priv->gswip); 2066 2067 priv->mdio = devm_platform_ioremap_resource(pdev, 1); 2068 if (IS_ERR(priv->mdio)) 2069 return PTR_ERR(priv->mdio); 2070 2071 priv->mii = devm_platform_ioremap_resource(pdev, 2); 2072 if (IS_ERR(priv->mii)) 2073 return PTR_ERR(priv->mii); 2074 2075 priv->hw_info = of_device_get_match_data(dev); 2076 if (!priv->hw_info) 2077 return -EINVAL; 2078 2079 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 2080 if (!priv->ds) 2081 return -ENOMEM; 2082 2083 priv->ds->dev = dev; 2084 priv->ds->num_ports = priv->hw_info->max_ports; 2085 priv->ds->priv = priv; 2086 priv->ds->ops = priv->hw_info->ops; 2087 priv->dev = dev; 2088 mutex_init(&priv->pce_table_lock); 2089 version = gswip_switch_r(priv, GSWIP_VERSION); 2090 2091 np = dev->of_node; 2092 switch (version) { 2093 case GSWIP_VERSION_2_0: 2094 case GSWIP_VERSION_2_1: 2095 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip")) 2096 return -EINVAL; 2097 break; 2098 case GSWIP_VERSION_2_2: 2099 case GSWIP_VERSION_2_2_ETC: 2100 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") && 2101 !of_device_is_compatible(np, "lantiq,xrx330-gswip")) 2102 return -EINVAL; 2103 break; 2104 default: 2105 dev_err(dev, "unknown GSWIP version: 0x%x", version); 2106 return -ENOENT; 2107 } 2108 2109 /* bring up the mdio bus */ 2110 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 2111 if (gphy_fw_np) { 2112 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 2113 of_node_put(gphy_fw_np); 2114 if (err) { 2115 dev_err(dev, "gphy fw probe failed\n"); 2116 return err; 2117 } 2118 } 2119 2120 /* bring up the mdio bus */ 2121 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio"); 2122 if (mdio_np) { 2123 err = gswip_mdio(priv, mdio_np); 2124 if (err) { 2125 dev_err(dev, "mdio probe failed\n"); 2126 goto put_mdio_node; 2127 } 2128 } 2129 2130 err = dsa_register_switch(priv->ds); 2131 if (err) { 2132 dev_err(dev, "dsa switch register failed: %i\n", err); 2133 goto mdio_bus; 2134 } 2135 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { 2136 dev_err(dev, "wrong CPU port defined, HW only supports port: %i", 2137 priv->hw_info->cpu_port); 2138 err = -EINVAL; 2139 goto disable_switch; 2140 } 2141 2142 platform_set_drvdata(pdev, priv); 2143 2144 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 2145 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, 2146 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); 2147 return 0; 2148 2149 disable_switch: 2150 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2151 dsa_unregister_switch(priv->ds); 2152 mdio_bus: 2153 if (mdio_np) { 2154 mdiobus_unregister(priv->ds->slave_mii_bus); 2155 mdiobus_free(priv->ds->slave_mii_bus); 2156 } 2157 put_mdio_node: 2158 of_node_put(mdio_np); 2159 for (i = 0; i < priv->num_gphy_fw; i++) 2160 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2161 return err; 2162 } 2163 2164 static int gswip_remove(struct platform_device *pdev) 2165 { 2166 struct gswip_priv *priv = platform_get_drvdata(pdev); 2167 int i; 2168 2169 if (!priv) 2170 return 0; 2171 2172 /* disable the switch */ 2173 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2174 2175 dsa_unregister_switch(priv->ds); 2176 2177 if (priv->ds->slave_mii_bus) { 2178 mdiobus_unregister(priv->ds->slave_mii_bus); 2179 of_node_put(priv->ds->slave_mii_bus->dev.of_node); 2180 mdiobus_free(priv->ds->slave_mii_bus); 2181 } 2182 2183 for (i = 0; i < priv->num_gphy_fw; i++) 2184 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2185 2186 platform_set_drvdata(pdev, NULL); 2187 2188 return 0; 2189 } 2190 2191 static void gswip_shutdown(struct platform_device *pdev) 2192 { 2193 struct gswip_priv *priv = platform_get_drvdata(pdev); 2194 2195 if (!priv) 2196 return; 2197 2198 dsa_switch_shutdown(priv->ds); 2199 2200 platform_set_drvdata(pdev, NULL); 2201 } 2202 2203 static const struct gswip_hw_info gswip_xrx200 = { 2204 .max_ports = 7, 2205 .cpu_port = 6, 2206 .ops = &gswip_xrx200_switch_ops, 2207 }; 2208 2209 static const struct gswip_hw_info gswip_xrx300 = { 2210 .max_ports = 7, 2211 .cpu_port = 6, 2212 .ops = &gswip_xrx300_switch_ops, 2213 }; 2214 2215 static const struct of_device_id gswip_of_match[] = { 2216 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 2217 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 }, 2218 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 }, 2219 {}, 2220 }; 2221 MODULE_DEVICE_TABLE(of, gswip_of_match); 2222 2223 static struct platform_driver gswip_driver = { 2224 .probe = gswip_probe, 2225 .remove = gswip_remove, 2226 .shutdown = gswip_shutdown, 2227 .driver = { 2228 .name = "gswip", 2229 .of_match_table = gswip_of_match, 2230 }, 2231 }; 2232 2233 module_platform_driver(gswip_driver); 2234 2235 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 2236 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 2237 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 2238 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 2239 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 2240 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 2241 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 2242 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 2243 MODULE_LICENSE("GPL v2"); 2244