1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * The VLAN and bridge model the GSWIP hardware uses does not directly 10 * matches the model DSA uses. 11 * 12 * The hardware has 64 possible table entries for bridges with one VLAN 13 * ID, one flow id and a list of ports for each bridge. All entries which 14 * match the same flow ID are combined in the mac learning table, they 15 * act as one global bridge. 16 * The hardware does not support VLAN filter on the port, but on the 17 * bridge, this driver converts the DSA model to the hardware. 18 * 19 * The CPU gets all the exception frames which do not match any forwarding 20 * rule and the CPU port is also added to all bridges. This makes it possible 21 * to handle all the special cases easily in software. 22 * At the initialization the driver allocates one bridge table entry for 23 * each switch port which is used when the port is used without an 24 * explicit bridge. This prevents the frames from being forwarded 25 * between all LAN ports by default. 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 #include <linux/etherdevice.h> 31 #include <linux/firmware.h> 32 #include <linux/if_bridge.h> 33 #include <linux/if_vlan.h> 34 #include <linux/iopoll.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/module.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/of_platform.h> 40 #include <linux/phy.h> 41 #include <linux/phylink.h> 42 #include <linux/platform_device.h> 43 #include <linux/regmap.h> 44 #include <linux/reset.h> 45 #include <net/dsa.h> 46 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 47 48 #include "lantiq_pce.h" 49 50 /* GSWIP MDIO Registers */ 51 #define GSWIP_MDIO_GLOB 0x00 52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 53 #define GSWIP_MDIO_CTRL 0x08 54 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 55 #define GSWIP_MDIO_CTRL_RD BIT(11) 56 #define GSWIP_MDIO_CTRL_WR BIT(10) 57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 60 #define GSWIP_MDIO_READ 0x09 61 #define GSWIP_MDIO_WRITE 0x0A 62 #define GSWIP_MDIO_MDC_CFG0 0x0B 63 #define GSWIP_MDIO_MDC_CFG1 0x0C 64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 88 GSWIP_MDIO_PHY_FCONRX_MASK | \ 89 GSWIP_MDIO_PHY_FCONTX_MASK | \ 90 GSWIP_MDIO_PHY_LINK_MASK | \ 91 GSWIP_MDIO_PHY_SPEED_MASK | \ 92 GSWIP_MDIO_PHY_FDUP_MASK) 93 94 /* GSWIP MII Registers */ 95 #define GSWIP_MII_CFGp(p) (0x2 * (p)) 96 #define GSWIP_MII_CFG_RESET BIT(15) 97 #define GSWIP_MII_CFG_EN BIT(14) 98 #define GSWIP_MII_CFG_ISOLATE BIT(13) 99 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 100 #define GSWIP_MII_CFG_RGMII_IBS BIT(8) 101 #define GSWIP_MII_CFG_RMII_CLK BIT(7) 102 #define GSWIP_MII_CFG_MODE_MIIP 0x0 103 #define GSWIP_MII_CFG_MODE_MIIM 0x1 104 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 105 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 106 #define GSWIP_MII_CFG_MODE_RGMII 0x4 107 #define GSWIP_MII_CFG_MODE_GMII 0x9 108 #define GSWIP_MII_CFG_MODE_MASK 0xf 109 #define GSWIP_MII_CFG_RATE_M2P5 0x00 110 #define GSWIP_MII_CFG_RATE_M25 0x10 111 #define GSWIP_MII_CFG_RATE_M125 0x20 112 #define GSWIP_MII_CFG_RATE_M50 0x30 113 #define GSWIP_MII_CFG_RATE_AUTO 0x40 114 #define GSWIP_MII_CFG_RATE_MASK 0x70 115 #define GSWIP_MII_PCDU0 0x01 116 #define GSWIP_MII_PCDU1 0x03 117 #define GSWIP_MII_PCDU5 0x05 118 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 119 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 120 121 /* GSWIP Core Registers */ 122 #define GSWIP_SWRES 0x000 123 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 124 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 125 #define GSWIP_VERSION 0x013 126 #define GSWIP_VERSION_REV_SHIFT 0 127 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 128 #define GSWIP_VERSION_MOD_SHIFT 8 129 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 130 #define GSWIP_VERSION_2_0 0x100 131 #define GSWIP_VERSION_2_1 0x021 132 #define GSWIP_VERSION_2_2 0x122 133 #define GSWIP_VERSION_2_2_ETC 0x022 134 135 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 136 #define GSWIP_BM_RAM_ADDR 0x044 137 #define GSWIP_BM_RAM_CTRL 0x045 138 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 139 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 140 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 141 #define GSWIP_BM_QUEUE_GCTRL 0x04A 142 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 143 /* buffer management Port Configuration Register */ 144 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 145 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 146 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 147 /* buffer management Port Control Register */ 148 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 149 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 150 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 151 152 /* PCE */ 153 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 154 #define GSWIP_PCE_TBL_MASK 0x448 155 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 156 #define GSWIP_PCE_TBL_ADDR 0x44E 157 #define GSWIP_PCE_TBL_CTRL 0x44F 158 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 159 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 160 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 161 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 162 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 163 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 164 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 165 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 166 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 167 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 168 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 169 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 170 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 171 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 172 #define GSWIP_PCE_GCTRL_0 0x456 173 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ 174 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 175 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 176 #define GSWIP_PCE_GCTRL_1 0x457 177 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 178 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 179 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 180 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ 181 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ 182 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ 183 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 184 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 185 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 186 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 187 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 188 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 189 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) 190 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ 191 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ 192 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ 193 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ 194 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ 195 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) 196 197 #define GSWIP_MAC_FLEN 0x8C5 198 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC)) 199 #define GSWIP_MAC_CTRL_0_PADEN BIT(8) 200 #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7) 201 #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070 202 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000 203 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010 204 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020 205 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030 206 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040 207 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C 208 #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000 209 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004 210 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C 211 #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003 212 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000 213 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 214 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 215 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 216 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 217 218 /* Ethernet Switch Fetch DMA Port Control Register */ 219 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 220 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 221 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 222 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 223 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 224 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 225 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 226 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 227 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 228 229 /* Ethernet Switch Store DMA Port Control Register */ 230 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 231 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 232 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 233 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */ 234 235 #define GSWIP_TABLE_ACTIVE_VLAN 0x01 236 #define GSWIP_TABLE_VLAN_MAPPING 0x02 237 #define GSWIP_TABLE_MAC_BRIDGE 0x0b 238 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ 239 240 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 241 242 struct gswip_hw_info { 243 int max_ports; 244 int cpu_port; 245 const struct dsa_switch_ops *ops; 246 }; 247 248 struct xway_gphy_match_data { 249 char *fe_firmware_name; 250 char *ge_firmware_name; 251 }; 252 253 struct gswip_gphy_fw { 254 struct clk *clk_gate; 255 struct reset_control *reset; 256 u32 fw_addr_offset; 257 char *fw_name; 258 }; 259 260 struct gswip_vlan { 261 struct net_device *bridge; 262 u16 vid; 263 u8 fid; 264 }; 265 266 struct gswip_priv { 267 __iomem void *gswip; 268 __iomem void *mdio; 269 __iomem void *mii; 270 const struct gswip_hw_info *hw_info; 271 const struct xway_gphy_match_data *gphy_fw_name_cfg; 272 struct dsa_switch *ds; 273 struct device *dev; 274 struct regmap *rcu_regmap; 275 struct gswip_vlan vlans[64]; 276 int num_gphy_fw; 277 struct gswip_gphy_fw *gphy_fw; 278 u32 port_vlan_filter; 279 }; 280 281 struct gswip_pce_table_entry { 282 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index 283 u16 table; // PCE_TBL_CTRL.ADDR = pData->table 284 u16 key[8]; 285 u16 val[5]; 286 u16 mask; 287 u8 gmap; 288 bool type; 289 bool valid; 290 bool key_mode; 291 }; 292 293 struct gswip_rmon_cnt_desc { 294 unsigned int size; 295 unsigned int offset; 296 const char *name; 297 }; 298 299 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 300 301 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 302 /** Receive Packet Count (only packets that are accepted and not discarded). */ 303 MIB_DESC(1, 0x1F, "RxGoodPkts"), 304 MIB_DESC(1, 0x23, "RxUnicastPkts"), 305 MIB_DESC(1, 0x22, "RxMulticastPkts"), 306 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 307 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 308 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 309 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 310 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 311 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 312 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 313 MIB_DESC(1, 0x12, "Rx64BytePkts"), 314 MIB_DESC(1, 0x13, "Rx127BytePkts"), 315 MIB_DESC(1, 0x14, "Rx255BytePkts"), 316 MIB_DESC(1, 0x15, "Rx511BytePkts"), 317 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 318 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 319 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 320 MIB_DESC(1, 0x18, "RxDroppedPkts"), 321 MIB_DESC(1, 0x19, "RxFilteredPkts"), 322 MIB_DESC(2, 0x24, "RxGoodBytes"), 323 MIB_DESC(2, 0x26, "RxBadBytes"), 324 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 325 MIB_DESC(1, 0x0C, "TxGoodPkts"), 326 MIB_DESC(1, 0x06, "TxUnicastPkts"), 327 MIB_DESC(1, 0x07, "TxMulticastPkts"), 328 MIB_DESC(1, 0x00, "Tx64BytePkts"), 329 MIB_DESC(1, 0x01, "Tx127BytePkts"), 330 MIB_DESC(1, 0x02, "Tx255BytePkts"), 331 MIB_DESC(1, 0x03, "Tx511BytePkts"), 332 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 333 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 334 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 335 MIB_DESC(1, 0x08, "TxSingleCollCount"), 336 MIB_DESC(1, 0x09, "TxMultCollCount"), 337 MIB_DESC(1, 0x0A, "TxLateCollCount"), 338 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 339 MIB_DESC(1, 0x0D, "TxPauseCount"), 340 MIB_DESC(1, 0x10, "TxDroppedPkts"), 341 MIB_DESC(2, 0x0E, "TxGoodBytes"), 342 }; 343 344 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 345 { 346 return __raw_readl(priv->gswip + (offset * 4)); 347 } 348 349 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 350 { 351 __raw_writel(val, priv->gswip + (offset * 4)); 352 } 353 354 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 355 u32 offset) 356 { 357 u32 val = gswip_switch_r(priv, offset); 358 359 val &= ~(clear); 360 val |= set; 361 gswip_switch_w(priv, val, offset); 362 } 363 364 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 365 u32 cleared) 366 { 367 u32 val; 368 369 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 370 (val & cleared) == 0, 20, 50000); 371 } 372 373 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 374 { 375 return __raw_readl(priv->mdio + (offset * 4)); 376 } 377 378 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 379 { 380 __raw_writel(val, priv->mdio + (offset * 4)); 381 } 382 383 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 384 u32 offset) 385 { 386 u32 val = gswip_mdio_r(priv, offset); 387 388 val &= ~(clear); 389 val |= set; 390 gswip_mdio_w(priv, val, offset); 391 } 392 393 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 394 { 395 return __raw_readl(priv->mii + (offset * 4)); 396 } 397 398 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 399 { 400 __raw_writel(val, priv->mii + (offset * 4)); 401 } 402 403 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 404 u32 offset) 405 { 406 u32 val = gswip_mii_r(priv, offset); 407 408 val &= ~(clear); 409 val |= set; 410 gswip_mii_w(priv, val, offset); 411 } 412 413 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 414 int port) 415 { 416 /* There's no MII_CFG register for the CPU port */ 417 if (!dsa_is_cpu_port(priv->ds, port)) 418 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); 419 } 420 421 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 422 int port) 423 { 424 switch (port) { 425 case 0: 426 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 427 break; 428 case 1: 429 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 430 break; 431 case 5: 432 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 433 break; 434 } 435 } 436 437 static int gswip_mdio_poll(struct gswip_priv *priv) 438 { 439 int cnt = 100; 440 441 while (likely(cnt--)) { 442 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 443 444 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 445 return 0; 446 usleep_range(20, 40); 447 } 448 449 return -ETIMEDOUT; 450 } 451 452 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 453 { 454 struct gswip_priv *priv = bus->priv; 455 int err; 456 457 err = gswip_mdio_poll(priv); 458 if (err) { 459 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 460 return err; 461 } 462 463 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 464 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 465 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 466 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 467 GSWIP_MDIO_CTRL); 468 469 return 0; 470 } 471 472 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 473 { 474 struct gswip_priv *priv = bus->priv; 475 int err; 476 477 err = gswip_mdio_poll(priv); 478 if (err) { 479 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 480 return err; 481 } 482 483 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 484 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 485 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 486 GSWIP_MDIO_CTRL); 487 488 err = gswip_mdio_poll(priv); 489 if (err) { 490 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 491 return err; 492 } 493 494 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 495 } 496 497 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np) 498 { 499 struct dsa_switch *ds = priv->ds; 500 501 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev); 502 if (!ds->slave_mii_bus) 503 return -ENOMEM; 504 505 ds->slave_mii_bus->priv = priv; 506 ds->slave_mii_bus->read = gswip_mdio_rd; 507 ds->slave_mii_bus->write = gswip_mdio_wr; 508 ds->slave_mii_bus->name = "lantiq,xrx200-mdio"; 509 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", 510 dev_name(priv->dev)); 511 ds->slave_mii_bus->parent = priv->dev; 512 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask; 513 514 return of_mdiobus_register(ds->slave_mii_bus, mdio_np); 515 } 516 517 static int gswip_pce_table_entry_read(struct gswip_priv *priv, 518 struct gswip_pce_table_entry *tbl) 519 { 520 int i; 521 int err; 522 u16 crtl; 523 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 524 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 525 526 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 527 GSWIP_PCE_TBL_CTRL_BAS); 528 if (err) 529 return err; 530 531 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 532 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 533 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 534 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 535 GSWIP_PCE_TBL_CTRL); 536 537 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 538 GSWIP_PCE_TBL_CTRL_BAS); 539 if (err) 540 return err; 541 542 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 543 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 544 545 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 546 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 547 548 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 549 550 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 551 552 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 553 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 554 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 555 556 return 0; 557 } 558 559 static int gswip_pce_table_entry_write(struct gswip_priv *priv, 560 struct gswip_pce_table_entry *tbl) 561 { 562 int i; 563 int err; 564 u16 crtl; 565 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 566 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 567 568 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 569 GSWIP_PCE_TBL_CTRL_BAS); 570 if (err) 571 return err; 572 573 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 574 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 575 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 576 tbl->table | addr_mode, 577 GSWIP_PCE_TBL_CTRL); 578 579 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 580 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 581 582 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 583 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 584 585 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 586 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 587 tbl->table | addr_mode, 588 GSWIP_PCE_TBL_CTRL); 589 590 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 591 592 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 593 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 594 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 595 if (tbl->type) 596 crtl |= GSWIP_PCE_TBL_CTRL_TYPE; 597 if (tbl->valid) 598 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 599 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 600 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 601 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 602 603 return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 604 GSWIP_PCE_TBL_CTRL_BAS); 605 } 606 607 /* Add the LAN port into a bridge with the CPU port by 608 * default. This prevents automatic forwarding of 609 * packages between the LAN ports when no explicit 610 * bridge is configured. 611 */ 612 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) 613 { 614 struct gswip_pce_table_entry vlan_active = {0,}; 615 struct gswip_pce_table_entry vlan_mapping = {0,}; 616 unsigned int cpu_port = priv->hw_info->cpu_port; 617 unsigned int max_ports = priv->hw_info->max_ports; 618 int err; 619 620 if (port >= max_ports) { 621 dev_err(priv->dev, "single port for %i supported\n", port); 622 return -EIO; 623 } 624 625 vlan_active.index = port + 1; 626 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 627 vlan_active.key[0] = 0; /* vid */ 628 vlan_active.val[0] = port + 1 /* fid */; 629 vlan_active.valid = add; 630 err = gswip_pce_table_entry_write(priv, &vlan_active); 631 if (err) { 632 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 633 return err; 634 } 635 636 if (!add) 637 return 0; 638 639 vlan_mapping.index = port + 1; 640 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 641 vlan_mapping.val[0] = 0 /* vid */; 642 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); 643 vlan_mapping.val[2] = 0; 644 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 645 if (err) { 646 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 647 return err; 648 } 649 650 return 0; 651 } 652 653 static int gswip_port_enable(struct dsa_switch *ds, int port, 654 struct phy_device *phydev) 655 { 656 struct gswip_priv *priv = ds->priv; 657 int err; 658 659 if (!dsa_is_user_port(ds, port)) 660 return 0; 661 662 if (!dsa_is_cpu_port(ds, port)) { 663 err = gswip_add_single_port_br(priv, port, true); 664 if (err) 665 return err; 666 } 667 668 /* RMON Counter Enable for port */ 669 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 670 671 /* enable port fetch/store dma & VLAN Modification */ 672 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 673 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 674 GSWIP_FDMA_PCTRLp(port)); 675 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 676 GSWIP_SDMA_PCTRLp(port)); 677 678 if (!dsa_is_cpu_port(ds, port)) { 679 u32 mdio_phy = 0; 680 681 if (phydev) 682 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; 683 684 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, 685 GSWIP_MDIO_PHYp(port)); 686 } 687 688 return 0; 689 } 690 691 static void gswip_port_disable(struct dsa_switch *ds, int port) 692 { 693 struct gswip_priv *priv = ds->priv; 694 695 if (!dsa_is_user_port(ds, port)) 696 return; 697 698 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 699 GSWIP_FDMA_PCTRLp(port)); 700 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 701 GSWIP_SDMA_PCTRLp(port)); 702 } 703 704 static int gswip_pce_load_microcode(struct gswip_priv *priv) 705 { 706 int i; 707 int err; 708 709 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 710 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 711 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 712 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 713 714 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { 715 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 716 gswip_switch_w(priv, gswip_pce_microcode[i].val_0, 717 GSWIP_PCE_TBL_VAL(0)); 718 gswip_switch_w(priv, gswip_pce_microcode[i].val_1, 719 GSWIP_PCE_TBL_VAL(1)); 720 gswip_switch_w(priv, gswip_pce_microcode[i].val_2, 721 GSWIP_PCE_TBL_VAL(2)); 722 gswip_switch_w(priv, gswip_pce_microcode[i].val_3, 723 GSWIP_PCE_TBL_VAL(3)); 724 725 /* start the table access: */ 726 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 727 GSWIP_PCE_TBL_CTRL); 728 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 729 GSWIP_PCE_TBL_CTRL_BAS); 730 if (err) 731 return err; 732 } 733 734 /* tell the switch that the microcode is loaded */ 735 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 736 GSWIP_PCE_GCTRL_0); 737 738 return 0; 739 } 740 741 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 742 bool vlan_filtering, 743 struct netlink_ext_ack *extack) 744 { 745 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 746 struct gswip_priv *priv = ds->priv; 747 748 /* Do not allow changing the VLAN filtering options while in bridge */ 749 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { 750 NL_SET_ERR_MSG_MOD(extack, 751 "Dynamic toggling of vlan_filtering not supported"); 752 return -EIO; 753 } 754 755 if (vlan_filtering) { 756 /* Use port based VLAN tag */ 757 gswip_switch_mask(priv, 758 GSWIP_PCE_VCTRL_VSR, 759 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 760 GSWIP_PCE_VCTRL_VEMR, 761 GSWIP_PCE_VCTRL(port)); 762 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 763 GSWIP_PCE_PCTRL_0p(port)); 764 } else { 765 /* Use port based VLAN tag */ 766 gswip_switch_mask(priv, 767 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 768 GSWIP_PCE_VCTRL_VEMR, 769 GSWIP_PCE_VCTRL_VSR, 770 GSWIP_PCE_VCTRL(port)); 771 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 772 GSWIP_PCE_PCTRL_0p(port)); 773 } 774 775 return 0; 776 } 777 778 static int gswip_setup(struct dsa_switch *ds) 779 { 780 struct gswip_priv *priv = ds->priv; 781 unsigned int cpu_port = priv->hw_info->cpu_port; 782 int i; 783 int err; 784 785 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 786 usleep_range(5000, 10000); 787 gswip_switch_w(priv, 0, GSWIP_SWRES); 788 789 /* disable port fetch/store dma on all ports */ 790 for (i = 0; i < priv->hw_info->max_ports; i++) { 791 gswip_port_disable(ds, i); 792 gswip_port_vlan_filtering(ds, i, false, NULL); 793 } 794 795 /* enable Switch */ 796 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 797 798 err = gswip_pce_load_microcode(priv); 799 if (err) { 800 dev_err(priv->dev, "writing PCE microcode failed, %i", err); 801 return err; 802 } 803 804 /* Default unknown Broadcast/Multicast/Unicast port maps */ 805 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); 806 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); 807 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); 808 809 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an 810 * interoperability problem with this auto polling mechanism because 811 * their status registers think that the link is in a different state 812 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set 813 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the 814 * auto polling state machine consider the link being negotiated with 815 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads 816 * to the switch port being completely dead (RX and TX are both not 817 * working). 818 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F 819 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes 820 * it would work fine for a few minutes to hours and then stop, on 821 * other device it would no traffic could be sent or received at all. 822 * Testing shows that when PHY auto polling is disabled these problems 823 * go away. 824 */ 825 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 826 827 /* Configure the MDIO Clock 2.5 MHz */ 828 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 829 830 /* Disable the xMII interface and clear it's isolation bit */ 831 for (i = 0; i < priv->hw_info->max_ports; i++) 832 gswip_mii_mask_cfg(priv, 833 GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE, 834 0, i); 835 836 /* enable special tag insertion on cpu port */ 837 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 838 GSWIP_FDMA_PCTRLp(cpu_port)); 839 840 /* accept special tag in ingress direction */ 841 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 842 GSWIP_PCE_PCTRL_0p(cpu_port)); 843 844 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 845 GSWIP_MAC_CTRL_2p(cpu_port)); 846 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8, GSWIP_MAC_FLEN); 847 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 848 GSWIP_BM_QUEUE_GCTRL); 849 850 /* VLAN aware Switching */ 851 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 852 853 /* Flush MAC Table */ 854 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 855 856 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 857 GSWIP_PCE_GCTRL_0_MTFL); 858 if (err) { 859 dev_err(priv->dev, "MAC flushing didn't finish\n"); 860 return err; 861 } 862 863 gswip_port_enable(ds, cpu_port, NULL); 864 865 ds->configure_vlan_while_not_filtering = false; 866 867 return 0; 868 } 869 870 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 871 int port, 872 enum dsa_tag_protocol mp) 873 { 874 return DSA_TAG_PROTO_GSWIP; 875 } 876 877 static int gswip_vlan_active_create(struct gswip_priv *priv, 878 struct net_device *bridge, 879 int fid, u16 vid) 880 { 881 struct gswip_pce_table_entry vlan_active = {0,}; 882 unsigned int max_ports = priv->hw_info->max_ports; 883 int idx = -1; 884 int err; 885 int i; 886 887 /* Look for a free slot */ 888 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 889 if (!priv->vlans[i].bridge) { 890 idx = i; 891 break; 892 } 893 } 894 895 if (idx == -1) 896 return -ENOSPC; 897 898 if (fid == -1) 899 fid = idx; 900 901 vlan_active.index = idx; 902 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 903 vlan_active.key[0] = vid; 904 vlan_active.val[0] = fid; 905 vlan_active.valid = true; 906 907 err = gswip_pce_table_entry_write(priv, &vlan_active); 908 if (err) { 909 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 910 return err; 911 } 912 913 priv->vlans[idx].bridge = bridge; 914 priv->vlans[idx].vid = vid; 915 priv->vlans[idx].fid = fid; 916 917 return idx; 918 } 919 920 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) 921 { 922 struct gswip_pce_table_entry vlan_active = {0,}; 923 int err; 924 925 vlan_active.index = idx; 926 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 927 vlan_active.valid = false; 928 err = gswip_pce_table_entry_write(priv, &vlan_active); 929 if (err) 930 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); 931 priv->vlans[idx].bridge = NULL; 932 933 return err; 934 } 935 936 static int gswip_vlan_add_unaware(struct gswip_priv *priv, 937 struct net_device *bridge, int port) 938 { 939 struct gswip_pce_table_entry vlan_mapping = {0,}; 940 unsigned int max_ports = priv->hw_info->max_ports; 941 unsigned int cpu_port = priv->hw_info->cpu_port; 942 bool active_vlan_created = false; 943 int idx = -1; 944 int i; 945 int err; 946 947 /* Check if there is already a page for this bridge */ 948 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 949 if (priv->vlans[i].bridge == bridge) { 950 idx = i; 951 break; 952 } 953 } 954 955 /* If this bridge is not programmed yet, add a Active VLAN table 956 * entry in a free slot and prepare the VLAN mapping table entry. 957 */ 958 if (idx == -1) { 959 idx = gswip_vlan_active_create(priv, bridge, -1, 0); 960 if (idx < 0) 961 return idx; 962 active_vlan_created = true; 963 964 vlan_mapping.index = idx; 965 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 966 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 967 vlan_mapping.val[0] = 0; 968 } else { 969 /* Read the existing VLAN mapping entry from the switch */ 970 vlan_mapping.index = idx; 971 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 972 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 973 if (err) { 974 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 975 err); 976 return err; 977 } 978 } 979 980 /* Update the VLAN mapping entry and write it to the switch */ 981 vlan_mapping.val[1] |= BIT(cpu_port); 982 vlan_mapping.val[1] |= BIT(port); 983 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 984 if (err) { 985 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 986 /* In case an Active VLAN was creaetd delete it again */ 987 if (active_vlan_created) 988 gswip_vlan_active_remove(priv, idx); 989 return err; 990 } 991 992 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 993 return 0; 994 } 995 996 static int gswip_vlan_add_aware(struct gswip_priv *priv, 997 struct net_device *bridge, int port, 998 u16 vid, bool untagged, 999 bool pvid) 1000 { 1001 struct gswip_pce_table_entry vlan_mapping = {0,}; 1002 unsigned int max_ports = priv->hw_info->max_ports; 1003 unsigned int cpu_port = priv->hw_info->cpu_port; 1004 bool active_vlan_created = false; 1005 int idx = -1; 1006 int fid = -1; 1007 int i; 1008 int err; 1009 1010 /* Check if there is already a page for this bridge */ 1011 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1012 if (priv->vlans[i].bridge == bridge) { 1013 if (fid != -1 && fid != priv->vlans[i].fid) 1014 dev_err(priv->dev, "one bridge with multiple flow ids\n"); 1015 fid = priv->vlans[i].fid; 1016 if (priv->vlans[i].vid == vid) { 1017 idx = i; 1018 break; 1019 } 1020 } 1021 } 1022 1023 /* If this bridge is not programmed yet, add a Active VLAN table 1024 * entry in a free slot and prepare the VLAN mapping table entry. 1025 */ 1026 if (idx == -1) { 1027 idx = gswip_vlan_active_create(priv, bridge, fid, vid); 1028 if (idx < 0) 1029 return idx; 1030 active_vlan_created = true; 1031 1032 vlan_mapping.index = idx; 1033 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1034 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 1035 vlan_mapping.val[0] = vid; 1036 } else { 1037 /* Read the existing VLAN mapping entry from the switch */ 1038 vlan_mapping.index = idx; 1039 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1040 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1041 if (err) { 1042 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 1043 err); 1044 return err; 1045 } 1046 } 1047 1048 vlan_mapping.val[0] = vid; 1049 /* Update the VLAN mapping entry and write it to the switch */ 1050 vlan_mapping.val[1] |= BIT(cpu_port); 1051 vlan_mapping.val[2] |= BIT(cpu_port); 1052 vlan_mapping.val[1] |= BIT(port); 1053 if (untagged) 1054 vlan_mapping.val[2] &= ~BIT(port); 1055 else 1056 vlan_mapping.val[2] |= BIT(port); 1057 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1058 if (err) { 1059 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1060 /* In case an Active VLAN was creaetd delete it again */ 1061 if (active_vlan_created) 1062 gswip_vlan_active_remove(priv, idx); 1063 return err; 1064 } 1065 1066 if (pvid) 1067 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 1068 1069 return 0; 1070 } 1071 1072 static int gswip_vlan_remove(struct gswip_priv *priv, 1073 struct net_device *bridge, int port, 1074 u16 vid, bool pvid, bool vlan_aware) 1075 { 1076 struct gswip_pce_table_entry vlan_mapping = {0,}; 1077 unsigned int max_ports = priv->hw_info->max_ports; 1078 unsigned int cpu_port = priv->hw_info->cpu_port; 1079 int idx = -1; 1080 int i; 1081 int err; 1082 1083 /* Check if there is already a page for this bridge */ 1084 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1085 if (priv->vlans[i].bridge == bridge && 1086 (!vlan_aware || priv->vlans[i].vid == vid)) { 1087 idx = i; 1088 break; 1089 } 1090 } 1091 1092 if (idx == -1) { 1093 dev_err(priv->dev, "bridge to leave does not exists\n"); 1094 return -ENOENT; 1095 } 1096 1097 vlan_mapping.index = idx; 1098 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1099 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1100 if (err) { 1101 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); 1102 return err; 1103 } 1104 1105 vlan_mapping.val[1] &= ~BIT(port); 1106 vlan_mapping.val[2] &= ~BIT(port); 1107 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1108 if (err) { 1109 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1110 return err; 1111 } 1112 1113 /* In case all ports are removed from the bridge, remove the VLAN */ 1114 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { 1115 err = gswip_vlan_active_remove(priv, idx); 1116 if (err) { 1117 dev_err(priv->dev, "failed to write active VLAN: %d\n", 1118 err); 1119 return err; 1120 } 1121 } 1122 1123 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 1124 if (pvid) 1125 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1126 1127 return 0; 1128 } 1129 1130 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, 1131 struct net_device *bridge) 1132 { 1133 struct gswip_priv *priv = ds->priv; 1134 int err; 1135 1136 /* When the bridge uses VLAN filtering we have to configure VLAN 1137 * specific bridges. No bridge is configured here. 1138 */ 1139 if (!br_vlan_enabled(bridge)) { 1140 err = gswip_vlan_add_unaware(priv, bridge, port); 1141 if (err) 1142 return err; 1143 priv->port_vlan_filter &= ~BIT(port); 1144 } else { 1145 priv->port_vlan_filter |= BIT(port); 1146 } 1147 return gswip_add_single_port_br(priv, port, false); 1148 } 1149 1150 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, 1151 struct net_device *bridge) 1152 { 1153 struct gswip_priv *priv = ds->priv; 1154 1155 gswip_add_single_port_br(priv, port, true); 1156 1157 /* When the bridge uses VLAN filtering we have to configure VLAN 1158 * specific bridges. No bridge is configured here. 1159 */ 1160 if (!br_vlan_enabled(bridge)) 1161 gswip_vlan_remove(priv, bridge, port, 0, true, false); 1162 } 1163 1164 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, 1165 const struct switchdev_obj_port_vlan *vlan, 1166 struct netlink_ext_ack *extack) 1167 { 1168 struct gswip_priv *priv = ds->priv; 1169 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1170 unsigned int max_ports = priv->hw_info->max_ports; 1171 int pos = max_ports; 1172 int i, idx = -1; 1173 1174 /* We only support VLAN filtering on bridges */ 1175 if (!dsa_is_cpu_port(ds, port) && !bridge) 1176 return -EOPNOTSUPP; 1177 1178 /* Check if there is already a page for this VLAN */ 1179 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1180 if (priv->vlans[i].bridge == bridge && 1181 priv->vlans[i].vid == vlan->vid) { 1182 idx = i; 1183 break; 1184 } 1185 } 1186 1187 /* If this VLAN is not programmed yet, we have to reserve 1188 * one entry in the VLAN table. Make sure we start at the 1189 * next position round. 1190 */ 1191 if (idx == -1) { 1192 /* Look for a free slot */ 1193 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { 1194 if (!priv->vlans[pos].bridge) { 1195 idx = pos; 1196 pos++; 1197 break; 1198 } 1199 } 1200 1201 if (idx == -1) { 1202 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table"); 1203 return -ENOSPC; 1204 } 1205 } 1206 1207 return 0; 1208 } 1209 1210 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, 1211 const struct switchdev_obj_port_vlan *vlan, 1212 struct netlink_ext_ack *extack) 1213 { 1214 struct gswip_priv *priv = ds->priv; 1215 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1216 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1217 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1218 int err; 1219 1220 err = gswip_port_vlan_prepare(ds, port, vlan, extack); 1221 if (err) 1222 return err; 1223 1224 /* We have to receive all packets on the CPU port and should not 1225 * do any VLAN filtering here. This is also called with bridge 1226 * NULL and then we do not know for which bridge to configure 1227 * this. 1228 */ 1229 if (dsa_is_cpu_port(ds, port)) 1230 return 0; 1231 1232 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, 1233 untagged, pvid); 1234 } 1235 1236 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, 1237 const struct switchdev_obj_port_vlan *vlan) 1238 { 1239 struct gswip_priv *priv = ds->priv; 1240 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1241 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1242 1243 /* We have to receive all packets on the CPU port and should not 1244 * do any VLAN filtering here. This is also called with bridge 1245 * NULL and then we do not know for which bridge to configure 1246 * this. 1247 */ 1248 if (dsa_is_cpu_port(ds, port)) 1249 return 0; 1250 1251 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); 1252 } 1253 1254 static void gswip_port_fast_age(struct dsa_switch *ds, int port) 1255 { 1256 struct gswip_priv *priv = ds->priv; 1257 struct gswip_pce_table_entry mac_bridge = {0,}; 1258 int i; 1259 int err; 1260 1261 for (i = 0; i < 2048; i++) { 1262 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1263 mac_bridge.index = i; 1264 1265 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1266 if (err) { 1267 dev_err(priv->dev, "failed to read mac bridge: %d\n", 1268 err); 1269 return; 1270 } 1271 1272 if (!mac_bridge.valid) 1273 continue; 1274 1275 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) 1276 continue; 1277 1278 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) 1279 continue; 1280 1281 mac_bridge.valid = false; 1282 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1283 if (err) { 1284 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1285 err); 1286 return; 1287 } 1288 } 1289 } 1290 1291 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1292 { 1293 struct gswip_priv *priv = ds->priv; 1294 u32 stp_state; 1295 1296 switch (state) { 1297 case BR_STATE_DISABLED: 1298 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1299 GSWIP_SDMA_PCTRLp(port)); 1300 return; 1301 case BR_STATE_BLOCKING: 1302 case BR_STATE_LISTENING: 1303 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; 1304 break; 1305 case BR_STATE_LEARNING: 1306 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; 1307 break; 1308 case BR_STATE_FORWARDING: 1309 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; 1310 break; 1311 default: 1312 dev_err(priv->dev, "invalid STP state: %d\n", state); 1313 return; 1314 } 1315 1316 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1317 GSWIP_SDMA_PCTRLp(port)); 1318 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1319 GSWIP_PCE_PCTRL_0p(port)); 1320 } 1321 1322 static int gswip_port_fdb(struct dsa_switch *ds, int port, 1323 const unsigned char *addr, u16 vid, bool add) 1324 { 1325 struct gswip_priv *priv = ds->priv; 1326 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1327 struct gswip_pce_table_entry mac_bridge = {0,}; 1328 unsigned int cpu_port = priv->hw_info->cpu_port; 1329 int fid = -1; 1330 int i; 1331 int err; 1332 1333 if (!bridge) 1334 return -EINVAL; 1335 1336 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) { 1337 if (priv->vlans[i].bridge == bridge) { 1338 fid = priv->vlans[i].fid; 1339 break; 1340 } 1341 } 1342 1343 if (fid == -1) { 1344 dev_err(priv->dev, "Port not part of a bridge\n"); 1345 return -EINVAL; 1346 } 1347 1348 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1349 mac_bridge.key_mode = true; 1350 mac_bridge.key[0] = addr[5] | (addr[4] << 8); 1351 mac_bridge.key[1] = addr[3] | (addr[2] << 8); 1352 mac_bridge.key[2] = addr[1] | (addr[0] << 8); 1353 mac_bridge.key[3] = fid; 1354 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ 1355 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; 1356 mac_bridge.valid = add; 1357 1358 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1359 if (err) 1360 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); 1361 1362 return err; 1363 } 1364 1365 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, 1366 const unsigned char *addr, u16 vid) 1367 { 1368 return gswip_port_fdb(ds, port, addr, vid, true); 1369 } 1370 1371 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, 1372 const unsigned char *addr, u16 vid) 1373 { 1374 return gswip_port_fdb(ds, port, addr, vid, false); 1375 } 1376 1377 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, 1378 dsa_fdb_dump_cb_t *cb, void *data) 1379 { 1380 struct gswip_priv *priv = ds->priv; 1381 struct gswip_pce_table_entry mac_bridge = {0,}; 1382 unsigned char addr[6]; 1383 int i; 1384 int err; 1385 1386 for (i = 0; i < 2048; i++) { 1387 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1388 mac_bridge.index = i; 1389 1390 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1391 if (err) { 1392 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1393 err); 1394 return err; 1395 } 1396 1397 if (!mac_bridge.valid) 1398 continue; 1399 1400 addr[5] = mac_bridge.key[0] & 0xff; 1401 addr[4] = (mac_bridge.key[0] >> 8) & 0xff; 1402 addr[3] = mac_bridge.key[1] & 0xff; 1403 addr[2] = (mac_bridge.key[1] >> 8) & 0xff; 1404 addr[1] = mac_bridge.key[2] & 0xff; 1405 addr[0] = (mac_bridge.key[2] >> 8) & 0xff; 1406 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { 1407 if (mac_bridge.val[0] & BIT(port)) 1408 cb(addr, 0, true, data); 1409 } else { 1410 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) 1411 cb(addr, 0, false, data); 1412 } 1413 } 1414 return 0; 1415 } 1416 1417 static void gswip_phylink_set_capab(unsigned long *supported, 1418 struct phylink_link_state *state) 1419 { 1420 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1421 1422 /* Allow all the expected bits */ 1423 phylink_set(mask, Autoneg); 1424 phylink_set_port_modes(mask); 1425 phylink_set(mask, Pause); 1426 phylink_set(mask, Asym_Pause); 1427 1428 /* With the exclusion of MII, Reverse MII and Reduced MII, we 1429 * support Gigabit, including Half duplex 1430 */ 1431 if (state->interface != PHY_INTERFACE_MODE_MII && 1432 state->interface != PHY_INTERFACE_MODE_REVMII && 1433 state->interface != PHY_INTERFACE_MODE_RMII) { 1434 phylink_set(mask, 1000baseT_Full); 1435 phylink_set(mask, 1000baseT_Half); 1436 } 1437 1438 phylink_set(mask, 10baseT_Half); 1439 phylink_set(mask, 10baseT_Full); 1440 phylink_set(mask, 100baseT_Half); 1441 phylink_set(mask, 100baseT_Full); 1442 1443 bitmap_and(supported, supported, mask, 1444 __ETHTOOL_LINK_MODE_MASK_NBITS); 1445 bitmap_and(state->advertising, state->advertising, mask, 1446 __ETHTOOL_LINK_MODE_MASK_NBITS); 1447 } 1448 1449 static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port, 1450 unsigned long *supported, 1451 struct phylink_link_state *state) 1452 { 1453 switch (port) { 1454 case 0: 1455 case 1: 1456 if (!phy_interface_mode_is_rgmii(state->interface) && 1457 state->interface != PHY_INTERFACE_MODE_MII && 1458 state->interface != PHY_INTERFACE_MODE_REVMII && 1459 state->interface != PHY_INTERFACE_MODE_RMII) 1460 goto unsupported; 1461 break; 1462 case 2: 1463 case 3: 1464 case 4: 1465 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 1466 goto unsupported; 1467 break; 1468 case 5: 1469 if (!phy_interface_mode_is_rgmii(state->interface) && 1470 state->interface != PHY_INTERFACE_MODE_INTERNAL) 1471 goto unsupported; 1472 break; 1473 default: 1474 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1475 dev_err(ds->dev, "Unsupported port: %i\n", port); 1476 return; 1477 } 1478 1479 gswip_phylink_set_capab(supported, state); 1480 1481 return; 1482 1483 unsupported: 1484 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1485 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", 1486 phy_modes(state->interface), port); 1487 } 1488 1489 static void gswip_xrx300_phylink_validate(struct dsa_switch *ds, int port, 1490 unsigned long *supported, 1491 struct phylink_link_state *state) 1492 { 1493 switch (port) { 1494 case 0: 1495 if (!phy_interface_mode_is_rgmii(state->interface) && 1496 state->interface != PHY_INTERFACE_MODE_GMII && 1497 state->interface != PHY_INTERFACE_MODE_RMII) 1498 goto unsupported; 1499 break; 1500 case 1: 1501 case 2: 1502 case 3: 1503 case 4: 1504 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 1505 goto unsupported; 1506 break; 1507 case 5: 1508 if (!phy_interface_mode_is_rgmii(state->interface) && 1509 state->interface != PHY_INTERFACE_MODE_INTERNAL && 1510 state->interface != PHY_INTERFACE_MODE_RMII) 1511 goto unsupported; 1512 break; 1513 default: 1514 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1515 dev_err(ds->dev, "Unsupported port: %i\n", port); 1516 return; 1517 } 1518 1519 gswip_phylink_set_capab(supported, state); 1520 1521 return; 1522 1523 unsupported: 1524 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1525 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", 1526 phy_modes(state->interface), port); 1527 } 1528 1529 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) 1530 { 1531 u32 mdio_phy; 1532 1533 if (link) 1534 mdio_phy = GSWIP_MDIO_PHY_LINK_UP; 1535 else 1536 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN; 1537 1538 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy, 1539 GSWIP_MDIO_PHYp(port)); 1540 } 1541 1542 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, 1543 phy_interface_t interface) 1544 { 1545 u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0; 1546 1547 switch (speed) { 1548 case SPEED_10: 1549 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10; 1550 1551 if (interface == PHY_INTERFACE_MODE_RMII) 1552 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1553 else 1554 mii_cfg = GSWIP_MII_CFG_RATE_M2P5; 1555 1556 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1557 break; 1558 1559 case SPEED_100: 1560 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100; 1561 1562 if (interface == PHY_INTERFACE_MODE_RMII) 1563 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1564 else 1565 mii_cfg = GSWIP_MII_CFG_RATE_M25; 1566 1567 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1568 break; 1569 1570 case SPEED_1000: 1571 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1; 1572 1573 mii_cfg = GSWIP_MII_CFG_RATE_M125; 1574 1575 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII; 1576 break; 1577 } 1578 1579 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy, 1580 GSWIP_MDIO_PHYp(port)); 1581 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); 1582 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0, 1583 GSWIP_MAC_CTRL_0p(port)); 1584 } 1585 1586 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) 1587 { 1588 u32 mac_ctrl_0, mdio_phy; 1589 1590 if (duplex == DUPLEX_FULL) { 1591 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN; 1592 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN; 1593 } else { 1594 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS; 1595 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS; 1596 } 1597 1598 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0, 1599 GSWIP_MAC_CTRL_0p(port)); 1600 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy, 1601 GSWIP_MDIO_PHYp(port)); 1602 } 1603 1604 static void gswip_port_set_pause(struct gswip_priv *priv, int port, 1605 bool tx_pause, bool rx_pause) 1606 { 1607 u32 mac_ctrl_0, mdio_phy; 1608 1609 if (tx_pause && rx_pause) { 1610 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX; 1611 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1612 GSWIP_MDIO_PHY_FCONRX_EN; 1613 } else if (tx_pause) { 1614 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX; 1615 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1616 GSWIP_MDIO_PHY_FCONRX_DIS; 1617 } else if (rx_pause) { 1618 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX; 1619 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1620 GSWIP_MDIO_PHY_FCONRX_EN; 1621 } else { 1622 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE; 1623 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1624 GSWIP_MDIO_PHY_FCONRX_DIS; 1625 } 1626 1627 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK, 1628 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); 1629 gswip_mdio_mask(priv, 1630 GSWIP_MDIO_PHY_FCONTX_MASK | 1631 GSWIP_MDIO_PHY_FCONRX_MASK, 1632 mdio_phy, GSWIP_MDIO_PHYp(port)); 1633 } 1634 1635 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, 1636 unsigned int mode, 1637 const struct phylink_link_state *state) 1638 { 1639 struct gswip_priv *priv = ds->priv; 1640 u32 miicfg = 0; 1641 1642 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 1643 1644 switch (state->interface) { 1645 case PHY_INTERFACE_MODE_MII: 1646 case PHY_INTERFACE_MODE_INTERNAL: 1647 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 1648 break; 1649 case PHY_INTERFACE_MODE_REVMII: 1650 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 1651 break; 1652 case PHY_INTERFACE_MODE_RMII: 1653 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 1654 1655 /* Configure the RMII clock as output: */ 1656 miicfg |= GSWIP_MII_CFG_RMII_CLK; 1657 break; 1658 case PHY_INTERFACE_MODE_RGMII: 1659 case PHY_INTERFACE_MODE_RGMII_ID: 1660 case PHY_INTERFACE_MODE_RGMII_RXID: 1661 case PHY_INTERFACE_MODE_RGMII_TXID: 1662 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 1663 break; 1664 case PHY_INTERFACE_MODE_GMII: 1665 miicfg |= GSWIP_MII_CFG_MODE_GMII; 1666 break; 1667 default: 1668 dev_err(ds->dev, 1669 "Unsupported interface: %d\n", state->interface); 1670 return; 1671 } 1672 1673 gswip_mii_mask_cfg(priv, 1674 GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK | 1675 GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS, 1676 miicfg, port); 1677 1678 switch (state->interface) { 1679 case PHY_INTERFACE_MODE_RGMII_ID: 1680 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 1681 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1682 break; 1683 case PHY_INTERFACE_MODE_RGMII_RXID: 1684 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1685 break; 1686 case PHY_INTERFACE_MODE_RGMII_TXID: 1687 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 1688 break; 1689 default: 1690 break; 1691 } 1692 } 1693 1694 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, 1695 unsigned int mode, 1696 phy_interface_t interface) 1697 { 1698 struct gswip_priv *priv = ds->priv; 1699 1700 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 1701 1702 if (!dsa_is_cpu_port(ds, port)) 1703 gswip_port_set_link(priv, port, false); 1704 } 1705 1706 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, 1707 unsigned int mode, 1708 phy_interface_t interface, 1709 struct phy_device *phydev, 1710 int speed, int duplex, 1711 bool tx_pause, bool rx_pause) 1712 { 1713 struct gswip_priv *priv = ds->priv; 1714 1715 if (!dsa_is_cpu_port(ds, port)) { 1716 gswip_port_set_link(priv, port, true); 1717 gswip_port_set_speed(priv, port, speed, interface); 1718 gswip_port_set_duplex(priv, port, duplex); 1719 gswip_port_set_pause(priv, port, tx_pause, rx_pause); 1720 } 1721 1722 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1723 } 1724 1725 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1726 uint8_t *data) 1727 { 1728 int i; 1729 1730 if (stringset != ETH_SS_STATS) 1731 return; 1732 1733 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 1734 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name, 1735 ETH_GSTRING_LEN); 1736 } 1737 1738 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1739 u32 index) 1740 { 1741 u32 result; 1742 int err; 1743 1744 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1745 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1746 GSWIP_BM_RAM_CTRL_OPMOD, 1747 table | GSWIP_BM_RAM_CTRL_BAS, 1748 GSWIP_BM_RAM_CTRL); 1749 1750 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1751 GSWIP_BM_RAM_CTRL_BAS); 1752 if (err) { 1753 dev_err(priv->dev, "timeout while reading table: %u, index: %u", 1754 table, index); 1755 return 0; 1756 } 1757 1758 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1759 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1760 1761 return result; 1762 } 1763 1764 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 1765 uint64_t *data) 1766 { 1767 struct gswip_priv *priv = ds->priv; 1768 const struct gswip_rmon_cnt_desc *rmon_cnt; 1769 int i; 1770 u64 high; 1771 1772 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 1773 rmon_cnt = &gswip_rmon_cnt[i]; 1774 1775 data[i] = gswip_bcm_ram_entry_read(priv, port, 1776 rmon_cnt->offset); 1777 if (rmon_cnt->size == 2) { 1778 high = gswip_bcm_ram_entry_read(priv, port, 1779 rmon_cnt->offset + 1); 1780 data[i] |= high << 32; 1781 } 1782 } 1783 } 1784 1785 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 1786 { 1787 if (sset != ETH_SS_STATS) 1788 return 0; 1789 1790 return ARRAY_SIZE(gswip_rmon_cnt); 1791 } 1792 1793 static const struct dsa_switch_ops gswip_xrx200_switch_ops = { 1794 .get_tag_protocol = gswip_get_tag_protocol, 1795 .setup = gswip_setup, 1796 .port_enable = gswip_port_enable, 1797 .port_disable = gswip_port_disable, 1798 .port_bridge_join = gswip_port_bridge_join, 1799 .port_bridge_leave = gswip_port_bridge_leave, 1800 .port_fast_age = gswip_port_fast_age, 1801 .port_vlan_filtering = gswip_port_vlan_filtering, 1802 .port_vlan_add = gswip_port_vlan_add, 1803 .port_vlan_del = gswip_port_vlan_del, 1804 .port_stp_state_set = gswip_port_stp_state_set, 1805 .port_fdb_add = gswip_port_fdb_add, 1806 .port_fdb_del = gswip_port_fdb_del, 1807 .port_fdb_dump = gswip_port_fdb_dump, 1808 .phylink_validate = gswip_xrx200_phylink_validate, 1809 .phylink_mac_config = gswip_phylink_mac_config, 1810 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1811 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1812 .get_strings = gswip_get_strings, 1813 .get_ethtool_stats = gswip_get_ethtool_stats, 1814 .get_sset_count = gswip_get_sset_count, 1815 }; 1816 1817 static const struct dsa_switch_ops gswip_xrx300_switch_ops = { 1818 .get_tag_protocol = gswip_get_tag_protocol, 1819 .setup = gswip_setup, 1820 .port_enable = gswip_port_enable, 1821 .port_disable = gswip_port_disable, 1822 .port_bridge_join = gswip_port_bridge_join, 1823 .port_bridge_leave = gswip_port_bridge_leave, 1824 .port_fast_age = gswip_port_fast_age, 1825 .port_vlan_filtering = gswip_port_vlan_filtering, 1826 .port_vlan_add = gswip_port_vlan_add, 1827 .port_vlan_del = gswip_port_vlan_del, 1828 .port_stp_state_set = gswip_port_stp_state_set, 1829 .port_fdb_add = gswip_port_fdb_add, 1830 .port_fdb_del = gswip_port_fdb_del, 1831 .port_fdb_dump = gswip_port_fdb_dump, 1832 .phylink_validate = gswip_xrx300_phylink_validate, 1833 .phylink_mac_config = gswip_phylink_mac_config, 1834 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1835 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1836 .get_strings = gswip_get_strings, 1837 .get_ethtool_stats = gswip_get_ethtool_stats, 1838 .get_sset_count = gswip_get_sset_count, 1839 }; 1840 1841 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 1842 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 1843 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 1844 }; 1845 1846 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 1847 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 1848 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 1849 }; 1850 1851 static const struct xway_gphy_match_data xrx300_gphy_data = { 1852 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 1853 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 1854 }; 1855 1856 static const struct of_device_id xway_gphy_match[] = { 1857 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 1858 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 1859 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 1860 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 1861 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 1862 {}, 1863 }; 1864 1865 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 1866 { 1867 struct device *dev = priv->dev; 1868 const struct firmware *fw; 1869 void *fw_addr; 1870 dma_addr_t dma_addr; 1871 dma_addr_t dev_addr; 1872 size_t size; 1873 int ret; 1874 1875 ret = clk_prepare_enable(gphy_fw->clk_gate); 1876 if (ret) 1877 return ret; 1878 1879 reset_control_assert(gphy_fw->reset); 1880 1881 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 1882 if (ret) { 1883 dev_err(dev, "failed to load firmware: %s, error: %i\n", 1884 gphy_fw->fw_name, ret); 1885 return ret; 1886 } 1887 1888 /* GPHY cores need the firmware code in a persistent and contiguous 1889 * memory area with a 16 kB boundary aligned start address. 1890 */ 1891 size = fw->size + XRX200_GPHY_FW_ALIGN; 1892 1893 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 1894 if (fw_addr) { 1895 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 1896 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 1897 memcpy(fw_addr, fw->data, fw->size); 1898 } else { 1899 dev_err(dev, "failed to alloc firmware memory\n"); 1900 release_firmware(fw); 1901 return -ENOMEM; 1902 } 1903 1904 release_firmware(fw); 1905 1906 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 1907 if (ret) 1908 return ret; 1909 1910 reset_control_deassert(gphy_fw->reset); 1911 1912 return ret; 1913 } 1914 1915 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 1916 struct gswip_gphy_fw *gphy_fw, 1917 struct device_node *gphy_fw_np, int i) 1918 { 1919 struct device *dev = priv->dev; 1920 u32 gphy_mode; 1921 int ret; 1922 char gphyname[10]; 1923 1924 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 1925 1926 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 1927 if (IS_ERR(gphy_fw->clk_gate)) { 1928 dev_err(dev, "Failed to lookup gate clock\n"); 1929 return PTR_ERR(gphy_fw->clk_gate); 1930 } 1931 1932 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 1933 if (ret) 1934 return ret; 1935 1936 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 1937 /* Default to GE mode */ 1938 if (ret) 1939 gphy_mode = GPHY_MODE_GE; 1940 1941 switch (gphy_mode) { 1942 case GPHY_MODE_FE: 1943 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 1944 break; 1945 case GPHY_MODE_GE: 1946 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 1947 break; 1948 default: 1949 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); 1950 return -EINVAL; 1951 } 1952 1953 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 1954 if (IS_ERR(gphy_fw->reset)) { 1955 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER) 1956 dev_err(dev, "Failed to lookup gphy reset\n"); 1957 return PTR_ERR(gphy_fw->reset); 1958 } 1959 1960 return gswip_gphy_fw_load(priv, gphy_fw); 1961 } 1962 1963 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 1964 struct gswip_gphy_fw *gphy_fw) 1965 { 1966 int ret; 1967 1968 /* check if the device was fully probed */ 1969 if (!gphy_fw->fw_name) 1970 return; 1971 1972 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 1973 if (ret) 1974 dev_err(priv->dev, "can not reset GPHY FW pointer"); 1975 1976 clk_disable_unprepare(gphy_fw->clk_gate); 1977 1978 reset_control_put(gphy_fw->reset); 1979 } 1980 1981 static int gswip_gphy_fw_list(struct gswip_priv *priv, 1982 struct device_node *gphy_fw_list_np, u32 version) 1983 { 1984 struct device *dev = priv->dev; 1985 struct device_node *gphy_fw_np; 1986 const struct of_device_id *match; 1987 int err; 1988 int i = 0; 1989 1990 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 1991 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 1992 * needs a different GPHY firmware. 1993 */ 1994 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 1995 switch (version) { 1996 case GSWIP_VERSION_2_0: 1997 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 1998 break; 1999 case GSWIP_VERSION_2_1: 2000 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 2001 break; 2002 default: 2003 dev_err(dev, "unknown GSWIP version: 0x%x", version); 2004 return -ENOENT; 2005 } 2006 } 2007 2008 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 2009 if (match && match->data) 2010 priv->gphy_fw_name_cfg = match->data; 2011 2012 if (!priv->gphy_fw_name_cfg) { 2013 dev_err(dev, "GPHY compatible type not supported"); 2014 return -ENOENT; 2015 } 2016 2017 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 2018 if (!priv->num_gphy_fw) 2019 return -ENOENT; 2020 2021 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 2022 "lantiq,rcu"); 2023 if (IS_ERR(priv->rcu_regmap)) 2024 return PTR_ERR(priv->rcu_regmap); 2025 2026 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 2027 sizeof(*priv->gphy_fw), 2028 GFP_KERNEL | __GFP_ZERO); 2029 if (!priv->gphy_fw) 2030 return -ENOMEM; 2031 2032 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 2033 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 2034 gphy_fw_np, i); 2035 if (err) 2036 goto remove_gphy; 2037 i++; 2038 } 2039 2040 /* The standalone PHY11G requires 300ms to be fully 2041 * initialized and ready for any MDIO communication after being 2042 * taken out of reset. For the SoC-internal GPHY variant there 2043 * is no (known) documentation for the minimum time after a 2044 * reset. Use the same value as for the standalone variant as 2045 * some users have reported internal PHYs not being detected 2046 * without any delay. 2047 */ 2048 msleep(300); 2049 2050 return 0; 2051 2052 remove_gphy: 2053 for (i = 0; i < priv->num_gphy_fw; i++) 2054 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2055 return err; 2056 } 2057 2058 static int gswip_probe(struct platform_device *pdev) 2059 { 2060 struct gswip_priv *priv; 2061 struct device_node *np, *mdio_np, *gphy_fw_np; 2062 struct device *dev = &pdev->dev; 2063 int err; 2064 int i; 2065 u32 version; 2066 2067 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2068 if (!priv) 2069 return -ENOMEM; 2070 2071 priv->gswip = devm_platform_ioremap_resource(pdev, 0); 2072 if (IS_ERR(priv->gswip)) 2073 return PTR_ERR(priv->gswip); 2074 2075 priv->mdio = devm_platform_ioremap_resource(pdev, 1); 2076 if (IS_ERR(priv->mdio)) 2077 return PTR_ERR(priv->mdio); 2078 2079 priv->mii = devm_platform_ioremap_resource(pdev, 2); 2080 if (IS_ERR(priv->mii)) 2081 return PTR_ERR(priv->mii); 2082 2083 priv->hw_info = of_device_get_match_data(dev); 2084 if (!priv->hw_info) 2085 return -EINVAL; 2086 2087 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 2088 if (!priv->ds) 2089 return -ENOMEM; 2090 2091 priv->ds->dev = dev; 2092 priv->ds->num_ports = priv->hw_info->max_ports; 2093 priv->ds->priv = priv; 2094 priv->ds->ops = priv->hw_info->ops; 2095 priv->dev = dev; 2096 version = gswip_switch_r(priv, GSWIP_VERSION); 2097 2098 np = dev->of_node; 2099 switch (version) { 2100 case GSWIP_VERSION_2_0: 2101 case GSWIP_VERSION_2_1: 2102 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip")) 2103 return -EINVAL; 2104 break; 2105 case GSWIP_VERSION_2_2: 2106 case GSWIP_VERSION_2_2_ETC: 2107 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") && 2108 !of_device_is_compatible(np, "lantiq,xrx330-gswip")) 2109 return -EINVAL; 2110 break; 2111 default: 2112 dev_err(dev, "unknown GSWIP version: 0x%x", version); 2113 return -ENOENT; 2114 } 2115 2116 /* bring up the mdio bus */ 2117 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 2118 if (gphy_fw_np) { 2119 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 2120 of_node_put(gphy_fw_np); 2121 if (err) { 2122 dev_err(dev, "gphy fw probe failed\n"); 2123 return err; 2124 } 2125 } 2126 2127 /* bring up the mdio bus */ 2128 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio"); 2129 if (mdio_np) { 2130 err = gswip_mdio(priv, mdio_np); 2131 if (err) { 2132 dev_err(dev, "mdio probe failed\n"); 2133 goto put_mdio_node; 2134 } 2135 } 2136 2137 err = dsa_register_switch(priv->ds); 2138 if (err) { 2139 dev_err(dev, "dsa switch register failed: %i\n", err); 2140 goto mdio_bus; 2141 } 2142 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { 2143 dev_err(dev, "wrong CPU port defined, HW only supports port: %i", 2144 priv->hw_info->cpu_port); 2145 err = -EINVAL; 2146 goto disable_switch; 2147 } 2148 2149 platform_set_drvdata(pdev, priv); 2150 2151 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 2152 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, 2153 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); 2154 return 0; 2155 2156 disable_switch: 2157 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2158 dsa_unregister_switch(priv->ds); 2159 mdio_bus: 2160 if (mdio_np) 2161 mdiobus_unregister(priv->ds->slave_mii_bus); 2162 put_mdio_node: 2163 of_node_put(mdio_np); 2164 for (i = 0; i < priv->num_gphy_fw; i++) 2165 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2166 return err; 2167 } 2168 2169 static int gswip_remove(struct platform_device *pdev) 2170 { 2171 struct gswip_priv *priv = platform_get_drvdata(pdev); 2172 int i; 2173 2174 /* disable the switch */ 2175 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2176 2177 dsa_unregister_switch(priv->ds); 2178 2179 if (priv->ds->slave_mii_bus) { 2180 mdiobus_unregister(priv->ds->slave_mii_bus); 2181 of_node_put(priv->ds->slave_mii_bus->dev.of_node); 2182 } 2183 2184 for (i = 0; i < priv->num_gphy_fw; i++) 2185 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2186 2187 return 0; 2188 } 2189 2190 static const struct gswip_hw_info gswip_xrx200 = { 2191 .max_ports = 7, 2192 .cpu_port = 6, 2193 .ops = &gswip_xrx200_switch_ops, 2194 }; 2195 2196 static const struct gswip_hw_info gswip_xrx300 = { 2197 .max_ports = 7, 2198 .cpu_port = 6, 2199 .ops = &gswip_xrx300_switch_ops, 2200 }; 2201 2202 static const struct of_device_id gswip_of_match[] = { 2203 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 2204 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 }, 2205 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 }, 2206 {}, 2207 }; 2208 MODULE_DEVICE_TABLE(of, gswip_of_match); 2209 2210 static struct platform_driver gswip_driver = { 2211 .probe = gswip_probe, 2212 .remove = gswip_remove, 2213 .driver = { 2214 .name = "gswip", 2215 .of_match_table = gswip_of_match, 2216 }, 2217 }; 2218 2219 module_platform_driver(gswip_driver); 2220 2221 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 2222 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 2223 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 2224 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 2225 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 2226 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 2227 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 2228 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 2229 MODULE_LICENSE("GPL v2"); 2230