1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * The VLAN and bridge model the GSWIP hardware uses does not directly 10 * matches the model DSA uses. 11 * 12 * The hardware has 64 possible table entries for bridges with one VLAN 13 * ID, one flow id and a list of ports for each bridge. All entries which 14 * match the same flow ID are combined in the mac learning table, they 15 * act as one global bridge. 16 * The hardware does not support VLAN filter on the port, but on the 17 * bridge, this driver converts the DSA model to the hardware. 18 * 19 * The CPU gets all the exception frames which do not match any forwarding 20 * rule and the CPU port is also added to all bridges. This makes it possible 21 * to handle all the special cases easily in software. 22 * At the initialization the driver allocates one bridge table entry for 23 * each switch port which is used when the port is used without an 24 * explicit bridge. This prevents the frames from being forwarded 25 * between all LAN ports by default. 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 #include <linux/etherdevice.h> 31 #include <linux/firmware.h> 32 #include <linux/if_bridge.h> 33 #include <linux/if_vlan.h> 34 #include <linux/iopoll.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/module.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/of_platform.h> 40 #include <linux/phy.h> 41 #include <linux/phylink.h> 42 #include <linux/platform_device.h> 43 #include <linux/regmap.h> 44 #include <linux/reset.h> 45 #include <net/dsa.h> 46 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 47 48 #include "lantiq_pce.h" 49 50 /* GSWIP MDIO Registers */ 51 #define GSWIP_MDIO_GLOB 0x00 52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 53 #define GSWIP_MDIO_CTRL 0x08 54 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 55 #define GSWIP_MDIO_CTRL_RD BIT(11) 56 #define GSWIP_MDIO_CTRL_WR BIT(10) 57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 60 #define GSWIP_MDIO_READ 0x09 61 #define GSWIP_MDIO_WRITE 0x0A 62 #define GSWIP_MDIO_MDC_CFG0 0x0B 63 #define GSWIP_MDIO_MDC_CFG1 0x0C 64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 88 GSWIP_MDIO_PHY_FCONRX_MASK | \ 89 GSWIP_MDIO_PHY_FCONTX_MASK | \ 90 GSWIP_MDIO_PHY_LINK_MASK | \ 91 GSWIP_MDIO_PHY_SPEED_MASK | \ 92 GSWIP_MDIO_PHY_FDUP_MASK) 93 94 /* GSWIP MII Registers */ 95 #define GSWIP_MII_CFGp(p) (0x2 * (p)) 96 #define GSWIP_MII_CFG_RESET BIT(15) 97 #define GSWIP_MII_CFG_EN BIT(14) 98 #define GSWIP_MII_CFG_ISOLATE BIT(13) 99 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 100 #define GSWIP_MII_CFG_RGMII_IBS BIT(8) 101 #define GSWIP_MII_CFG_RMII_CLK BIT(7) 102 #define GSWIP_MII_CFG_MODE_MIIP 0x0 103 #define GSWIP_MII_CFG_MODE_MIIM 0x1 104 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 105 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 106 #define GSWIP_MII_CFG_MODE_RGMII 0x4 107 #define GSWIP_MII_CFG_MODE_GMII 0x9 108 #define GSWIP_MII_CFG_MODE_MASK 0xf 109 #define GSWIP_MII_CFG_RATE_M2P5 0x00 110 #define GSWIP_MII_CFG_RATE_M25 0x10 111 #define GSWIP_MII_CFG_RATE_M125 0x20 112 #define GSWIP_MII_CFG_RATE_M50 0x30 113 #define GSWIP_MII_CFG_RATE_AUTO 0x40 114 #define GSWIP_MII_CFG_RATE_MASK 0x70 115 #define GSWIP_MII_PCDU0 0x01 116 #define GSWIP_MII_PCDU1 0x03 117 #define GSWIP_MII_PCDU5 0x05 118 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 119 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 120 121 /* GSWIP Core Registers */ 122 #define GSWIP_SWRES 0x000 123 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 124 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 125 #define GSWIP_VERSION 0x013 126 #define GSWIP_VERSION_REV_SHIFT 0 127 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 128 #define GSWIP_VERSION_MOD_SHIFT 8 129 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 130 #define GSWIP_VERSION_2_0 0x100 131 #define GSWIP_VERSION_2_1 0x021 132 #define GSWIP_VERSION_2_2 0x122 133 #define GSWIP_VERSION_2_2_ETC 0x022 134 135 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 136 #define GSWIP_BM_RAM_ADDR 0x044 137 #define GSWIP_BM_RAM_CTRL 0x045 138 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 139 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 140 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 141 #define GSWIP_BM_QUEUE_GCTRL 0x04A 142 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 143 /* buffer management Port Configuration Register */ 144 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 145 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 146 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 147 /* buffer management Port Control Register */ 148 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 149 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 150 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 151 152 /* PCE */ 153 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 154 #define GSWIP_PCE_TBL_MASK 0x448 155 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 156 #define GSWIP_PCE_TBL_ADDR 0x44E 157 #define GSWIP_PCE_TBL_CTRL 0x44F 158 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 159 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 160 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 161 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 162 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 163 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 164 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 165 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 166 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 167 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 168 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 169 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 170 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 171 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 172 #define GSWIP_PCE_GCTRL_0 0x456 173 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ 174 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 175 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 176 #define GSWIP_PCE_GCTRL_1 0x457 177 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 178 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 179 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 180 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ 181 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ 182 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ 183 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 184 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 185 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 186 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 187 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 188 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 189 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) 190 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ 191 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ 192 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ 193 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ 194 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ 195 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) 196 197 #define GSWIP_MAC_FLEN 0x8C5 198 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC)) 199 #define GSWIP_MAC_CTRL_0_PADEN BIT(8) 200 #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7) 201 #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070 202 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000 203 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010 204 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020 205 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030 206 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040 207 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C 208 #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000 209 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004 210 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C 211 #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003 212 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000 213 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 214 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 215 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 216 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 217 218 /* Ethernet Switch Fetch DMA Port Control Register */ 219 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 220 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 221 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 222 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 223 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 224 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 225 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 226 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 227 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 228 229 /* Ethernet Switch Store DMA Port Control Register */ 230 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 231 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 232 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 233 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */ 234 235 #define GSWIP_TABLE_ACTIVE_VLAN 0x01 236 #define GSWIP_TABLE_VLAN_MAPPING 0x02 237 #define GSWIP_TABLE_MAC_BRIDGE 0x0b 238 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ 239 240 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 241 242 struct gswip_hw_info { 243 int max_ports; 244 int cpu_port; 245 const struct dsa_switch_ops *ops; 246 }; 247 248 struct xway_gphy_match_data { 249 char *fe_firmware_name; 250 char *ge_firmware_name; 251 }; 252 253 struct gswip_gphy_fw { 254 struct clk *clk_gate; 255 struct reset_control *reset; 256 u32 fw_addr_offset; 257 char *fw_name; 258 }; 259 260 struct gswip_vlan { 261 struct net_device *bridge; 262 u16 vid; 263 u8 fid; 264 }; 265 266 struct gswip_priv { 267 __iomem void *gswip; 268 __iomem void *mdio; 269 __iomem void *mii; 270 const struct gswip_hw_info *hw_info; 271 const struct xway_gphy_match_data *gphy_fw_name_cfg; 272 struct dsa_switch *ds; 273 struct device *dev; 274 struct regmap *rcu_regmap; 275 struct gswip_vlan vlans[64]; 276 int num_gphy_fw; 277 struct gswip_gphy_fw *gphy_fw; 278 u32 port_vlan_filter; 279 struct mutex pce_table_lock; 280 }; 281 282 struct gswip_pce_table_entry { 283 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index 284 u16 table; // PCE_TBL_CTRL.ADDR = pData->table 285 u16 key[8]; 286 u16 val[5]; 287 u16 mask; 288 u8 gmap; 289 bool type; 290 bool valid; 291 bool key_mode; 292 }; 293 294 struct gswip_rmon_cnt_desc { 295 unsigned int size; 296 unsigned int offset; 297 const char *name; 298 }; 299 300 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 301 302 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 303 /** Receive Packet Count (only packets that are accepted and not discarded). */ 304 MIB_DESC(1, 0x1F, "RxGoodPkts"), 305 MIB_DESC(1, 0x23, "RxUnicastPkts"), 306 MIB_DESC(1, 0x22, "RxMulticastPkts"), 307 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 308 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 309 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 310 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 311 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 312 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 313 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 314 MIB_DESC(1, 0x12, "Rx64BytePkts"), 315 MIB_DESC(1, 0x13, "Rx127BytePkts"), 316 MIB_DESC(1, 0x14, "Rx255BytePkts"), 317 MIB_DESC(1, 0x15, "Rx511BytePkts"), 318 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 319 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 320 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 321 MIB_DESC(1, 0x18, "RxDroppedPkts"), 322 MIB_DESC(1, 0x19, "RxFilteredPkts"), 323 MIB_DESC(2, 0x24, "RxGoodBytes"), 324 MIB_DESC(2, 0x26, "RxBadBytes"), 325 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 326 MIB_DESC(1, 0x0C, "TxGoodPkts"), 327 MIB_DESC(1, 0x06, "TxUnicastPkts"), 328 MIB_DESC(1, 0x07, "TxMulticastPkts"), 329 MIB_DESC(1, 0x00, "Tx64BytePkts"), 330 MIB_DESC(1, 0x01, "Tx127BytePkts"), 331 MIB_DESC(1, 0x02, "Tx255BytePkts"), 332 MIB_DESC(1, 0x03, "Tx511BytePkts"), 333 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 334 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 335 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 336 MIB_DESC(1, 0x08, "TxSingleCollCount"), 337 MIB_DESC(1, 0x09, "TxMultCollCount"), 338 MIB_DESC(1, 0x0A, "TxLateCollCount"), 339 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 340 MIB_DESC(1, 0x0D, "TxPauseCount"), 341 MIB_DESC(1, 0x10, "TxDroppedPkts"), 342 MIB_DESC(2, 0x0E, "TxGoodBytes"), 343 }; 344 345 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 346 { 347 return __raw_readl(priv->gswip + (offset * 4)); 348 } 349 350 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 351 { 352 __raw_writel(val, priv->gswip + (offset * 4)); 353 } 354 355 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 356 u32 offset) 357 { 358 u32 val = gswip_switch_r(priv, offset); 359 360 val &= ~(clear); 361 val |= set; 362 gswip_switch_w(priv, val, offset); 363 } 364 365 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 366 u32 cleared) 367 { 368 u32 val; 369 370 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 371 (val & cleared) == 0, 20, 50000); 372 } 373 374 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 375 { 376 return __raw_readl(priv->mdio + (offset * 4)); 377 } 378 379 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 380 { 381 __raw_writel(val, priv->mdio + (offset * 4)); 382 } 383 384 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 385 u32 offset) 386 { 387 u32 val = gswip_mdio_r(priv, offset); 388 389 val &= ~(clear); 390 val |= set; 391 gswip_mdio_w(priv, val, offset); 392 } 393 394 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 395 { 396 return __raw_readl(priv->mii + (offset * 4)); 397 } 398 399 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 400 { 401 __raw_writel(val, priv->mii + (offset * 4)); 402 } 403 404 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 405 u32 offset) 406 { 407 u32 val = gswip_mii_r(priv, offset); 408 409 val &= ~(clear); 410 val |= set; 411 gswip_mii_w(priv, val, offset); 412 } 413 414 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 415 int port) 416 { 417 /* There's no MII_CFG register for the CPU port */ 418 if (!dsa_is_cpu_port(priv->ds, port)) 419 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); 420 } 421 422 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 423 int port) 424 { 425 switch (port) { 426 case 0: 427 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 428 break; 429 case 1: 430 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 431 break; 432 case 5: 433 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 434 break; 435 } 436 } 437 438 static int gswip_mdio_poll(struct gswip_priv *priv) 439 { 440 int cnt = 100; 441 442 while (likely(cnt--)) { 443 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 444 445 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 446 return 0; 447 usleep_range(20, 40); 448 } 449 450 return -ETIMEDOUT; 451 } 452 453 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 454 { 455 struct gswip_priv *priv = bus->priv; 456 int err; 457 458 err = gswip_mdio_poll(priv); 459 if (err) { 460 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 461 return err; 462 } 463 464 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 465 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 466 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 467 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 468 GSWIP_MDIO_CTRL); 469 470 return 0; 471 } 472 473 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 474 { 475 struct gswip_priv *priv = bus->priv; 476 int err; 477 478 err = gswip_mdio_poll(priv); 479 if (err) { 480 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 481 return err; 482 } 483 484 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 485 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 486 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 487 GSWIP_MDIO_CTRL); 488 489 err = gswip_mdio_poll(priv); 490 if (err) { 491 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 492 return err; 493 } 494 495 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 496 } 497 498 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np) 499 { 500 struct dsa_switch *ds = priv->ds; 501 502 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev); 503 if (!ds->slave_mii_bus) 504 return -ENOMEM; 505 506 ds->slave_mii_bus->priv = priv; 507 ds->slave_mii_bus->read = gswip_mdio_rd; 508 ds->slave_mii_bus->write = gswip_mdio_wr; 509 ds->slave_mii_bus->name = "lantiq,xrx200-mdio"; 510 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", 511 dev_name(priv->dev)); 512 ds->slave_mii_bus->parent = priv->dev; 513 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask; 514 515 return of_mdiobus_register(ds->slave_mii_bus, mdio_np); 516 } 517 518 static int gswip_pce_table_entry_read(struct gswip_priv *priv, 519 struct gswip_pce_table_entry *tbl) 520 { 521 int i; 522 int err; 523 u16 crtl; 524 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 525 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 526 527 mutex_lock(&priv->pce_table_lock); 528 529 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 530 GSWIP_PCE_TBL_CTRL_BAS); 531 if (err) { 532 mutex_unlock(&priv->pce_table_lock); 533 return err; 534 } 535 536 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 537 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 538 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 539 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 540 GSWIP_PCE_TBL_CTRL); 541 542 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 543 GSWIP_PCE_TBL_CTRL_BAS); 544 if (err) { 545 mutex_unlock(&priv->pce_table_lock); 546 return err; 547 } 548 549 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 550 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 551 552 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 553 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 554 555 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 556 557 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 558 559 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 560 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 561 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 562 563 mutex_unlock(&priv->pce_table_lock); 564 565 return 0; 566 } 567 568 static int gswip_pce_table_entry_write(struct gswip_priv *priv, 569 struct gswip_pce_table_entry *tbl) 570 { 571 int i; 572 int err; 573 u16 crtl; 574 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 575 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 576 577 mutex_lock(&priv->pce_table_lock); 578 579 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 580 GSWIP_PCE_TBL_CTRL_BAS); 581 if (err) { 582 mutex_unlock(&priv->pce_table_lock); 583 return err; 584 } 585 586 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 587 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 588 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 589 tbl->table | addr_mode, 590 GSWIP_PCE_TBL_CTRL); 591 592 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 593 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 594 595 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 596 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 597 598 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 599 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 600 tbl->table | addr_mode, 601 GSWIP_PCE_TBL_CTRL); 602 603 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 604 605 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 606 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 607 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 608 if (tbl->type) 609 crtl |= GSWIP_PCE_TBL_CTRL_TYPE; 610 if (tbl->valid) 611 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 612 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 613 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 614 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 615 616 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 617 GSWIP_PCE_TBL_CTRL_BAS); 618 619 mutex_unlock(&priv->pce_table_lock); 620 621 return err; 622 } 623 624 /* Add the LAN port into a bridge with the CPU port by 625 * default. This prevents automatic forwarding of 626 * packages between the LAN ports when no explicit 627 * bridge is configured. 628 */ 629 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) 630 { 631 struct gswip_pce_table_entry vlan_active = {0,}; 632 struct gswip_pce_table_entry vlan_mapping = {0,}; 633 unsigned int cpu_port = priv->hw_info->cpu_port; 634 unsigned int max_ports = priv->hw_info->max_ports; 635 int err; 636 637 if (port >= max_ports) { 638 dev_err(priv->dev, "single port for %i supported\n", port); 639 return -EIO; 640 } 641 642 vlan_active.index = port + 1; 643 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 644 vlan_active.key[0] = 0; /* vid */ 645 vlan_active.val[0] = port + 1 /* fid */; 646 vlan_active.valid = add; 647 err = gswip_pce_table_entry_write(priv, &vlan_active); 648 if (err) { 649 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 650 return err; 651 } 652 653 if (!add) 654 return 0; 655 656 vlan_mapping.index = port + 1; 657 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 658 vlan_mapping.val[0] = 0 /* vid */; 659 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); 660 vlan_mapping.val[2] = 0; 661 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 662 if (err) { 663 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 664 return err; 665 } 666 667 return 0; 668 } 669 670 static int gswip_port_enable(struct dsa_switch *ds, int port, 671 struct phy_device *phydev) 672 { 673 struct gswip_priv *priv = ds->priv; 674 int err; 675 676 if (!dsa_is_user_port(ds, port)) 677 return 0; 678 679 if (!dsa_is_cpu_port(ds, port)) { 680 err = gswip_add_single_port_br(priv, port, true); 681 if (err) 682 return err; 683 } 684 685 /* RMON Counter Enable for port */ 686 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 687 688 /* enable port fetch/store dma & VLAN Modification */ 689 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 690 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 691 GSWIP_FDMA_PCTRLp(port)); 692 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 693 GSWIP_SDMA_PCTRLp(port)); 694 695 if (!dsa_is_cpu_port(ds, port)) { 696 u32 mdio_phy = 0; 697 698 if (phydev) 699 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; 700 701 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, 702 GSWIP_MDIO_PHYp(port)); 703 } 704 705 return 0; 706 } 707 708 static void gswip_port_disable(struct dsa_switch *ds, int port) 709 { 710 struct gswip_priv *priv = ds->priv; 711 712 if (!dsa_is_user_port(ds, port)) 713 return; 714 715 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 716 GSWIP_FDMA_PCTRLp(port)); 717 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 718 GSWIP_SDMA_PCTRLp(port)); 719 } 720 721 static int gswip_pce_load_microcode(struct gswip_priv *priv) 722 { 723 int i; 724 int err; 725 726 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 727 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 728 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 729 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 730 731 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { 732 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 733 gswip_switch_w(priv, gswip_pce_microcode[i].val_0, 734 GSWIP_PCE_TBL_VAL(0)); 735 gswip_switch_w(priv, gswip_pce_microcode[i].val_1, 736 GSWIP_PCE_TBL_VAL(1)); 737 gswip_switch_w(priv, gswip_pce_microcode[i].val_2, 738 GSWIP_PCE_TBL_VAL(2)); 739 gswip_switch_w(priv, gswip_pce_microcode[i].val_3, 740 GSWIP_PCE_TBL_VAL(3)); 741 742 /* start the table access: */ 743 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 744 GSWIP_PCE_TBL_CTRL); 745 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 746 GSWIP_PCE_TBL_CTRL_BAS); 747 if (err) 748 return err; 749 } 750 751 /* tell the switch that the microcode is loaded */ 752 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 753 GSWIP_PCE_GCTRL_0); 754 755 return 0; 756 } 757 758 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 759 bool vlan_filtering, 760 struct netlink_ext_ack *extack) 761 { 762 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 763 struct gswip_priv *priv = ds->priv; 764 765 /* Do not allow changing the VLAN filtering options while in bridge */ 766 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { 767 NL_SET_ERR_MSG_MOD(extack, 768 "Dynamic toggling of vlan_filtering not supported"); 769 return -EIO; 770 } 771 772 if (vlan_filtering) { 773 /* Use port based VLAN tag */ 774 gswip_switch_mask(priv, 775 GSWIP_PCE_VCTRL_VSR, 776 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 777 GSWIP_PCE_VCTRL_VEMR, 778 GSWIP_PCE_VCTRL(port)); 779 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 780 GSWIP_PCE_PCTRL_0p(port)); 781 } else { 782 /* Use port based VLAN tag */ 783 gswip_switch_mask(priv, 784 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 785 GSWIP_PCE_VCTRL_VEMR, 786 GSWIP_PCE_VCTRL_VSR, 787 GSWIP_PCE_VCTRL(port)); 788 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 789 GSWIP_PCE_PCTRL_0p(port)); 790 } 791 792 return 0; 793 } 794 795 static int gswip_setup(struct dsa_switch *ds) 796 { 797 struct gswip_priv *priv = ds->priv; 798 unsigned int cpu_port = priv->hw_info->cpu_port; 799 int i; 800 int err; 801 802 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 803 usleep_range(5000, 10000); 804 gswip_switch_w(priv, 0, GSWIP_SWRES); 805 806 /* disable port fetch/store dma on all ports */ 807 for (i = 0; i < priv->hw_info->max_ports; i++) { 808 gswip_port_disable(ds, i); 809 gswip_port_vlan_filtering(ds, i, false, NULL); 810 } 811 812 /* enable Switch */ 813 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 814 815 err = gswip_pce_load_microcode(priv); 816 if (err) { 817 dev_err(priv->dev, "writing PCE microcode failed, %i", err); 818 return err; 819 } 820 821 /* Default unknown Broadcast/Multicast/Unicast port maps */ 822 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); 823 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); 824 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); 825 826 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an 827 * interoperability problem with this auto polling mechanism because 828 * their status registers think that the link is in a different state 829 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set 830 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the 831 * auto polling state machine consider the link being negotiated with 832 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads 833 * to the switch port being completely dead (RX and TX are both not 834 * working). 835 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F 836 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes 837 * it would work fine for a few minutes to hours and then stop, on 838 * other device it would no traffic could be sent or received at all. 839 * Testing shows that when PHY auto polling is disabled these problems 840 * go away. 841 */ 842 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 843 844 /* Configure the MDIO Clock 2.5 MHz */ 845 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 846 847 /* Disable the xMII interface and clear it's isolation bit */ 848 for (i = 0; i < priv->hw_info->max_ports; i++) 849 gswip_mii_mask_cfg(priv, 850 GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE, 851 0, i); 852 853 /* enable special tag insertion on cpu port */ 854 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 855 GSWIP_FDMA_PCTRLp(cpu_port)); 856 857 /* accept special tag in ingress direction */ 858 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 859 GSWIP_PCE_PCTRL_0p(cpu_port)); 860 861 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 862 GSWIP_MAC_CTRL_2p(cpu_port)); 863 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8 + ETH_FCS_LEN, 864 GSWIP_MAC_FLEN); 865 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 866 GSWIP_BM_QUEUE_GCTRL); 867 868 /* VLAN aware Switching */ 869 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 870 871 /* Flush MAC Table */ 872 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 873 874 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 875 GSWIP_PCE_GCTRL_0_MTFL); 876 if (err) { 877 dev_err(priv->dev, "MAC flushing didn't finish\n"); 878 return err; 879 } 880 881 gswip_port_enable(ds, cpu_port, NULL); 882 883 ds->configure_vlan_while_not_filtering = false; 884 885 return 0; 886 } 887 888 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 889 int port, 890 enum dsa_tag_protocol mp) 891 { 892 return DSA_TAG_PROTO_GSWIP; 893 } 894 895 static int gswip_vlan_active_create(struct gswip_priv *priv, 896 struct net_device *bridge, 897 int fid, u16 vid) 898 { 899 struct gswip_pce_table_entry vlan_active = {0,}; 900 unsigned int max_ports = priv->hw_info->max_ports; 901 int idx = -1; 902 int err; 903 int i; 904 905 /* Look for a free slot */ 906 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 907 if (!priv->vlans[i].bridge) { 908 idx = i; 909 break; 910 } 911 } 912 913 if (idx == -1) 914 return -ENOSPC; 915 916 if (fid == -1) 917 fid = idx; 918 919 vlan_active.index = idx; 920 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 921 vlan_active.key[0] = vid; 922 vlan_active.val[0] = fid; 923 vlan_active.valid = true; 924 925 err = gswip_pce_table_entry_write(priv, &vlan_active); 926 if (err) { 927 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 928 return err; 929 } 930 931 priv->vlans[idx].bridge = bridge; 932 priv->vlans[idx].vid = vid; 933 priv->vlans[idx].fid = fid; 934 935 return idx; 936 } 937 938 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) 939 { 940 struct gswip_pce_table_entry vlan_active = {0,}; 941 int err; 942 943 vlan_active.index = idx; 944 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 945 vlan_active.valid = false; 946 err = gswip_pce_table_entry_write(priv, &vlan_active); 947 if (err) 948 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); 949 priv->vlans[idx].bridge = NULL; 950 951 return err; 952 } 953 954 static int gswip_vlan_add_unaware(struct gswip_priv *priv, 955 struct net_device *bridge, int port) 956 { 957 struct gswip_pce_table_entry vlan_mapping = {0,}; 958 unsigned int max_ports = priv->hw_info->max_ports; 959 unsigned int cpu_port = priv->hw_info->cpu_port; 960 bool active_vlan_created = false; 961 int idx = -1; 962 int i; 963 int err; 964 965 /* Check if there is already a page for this bridge */ 966 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 967 if (priv->vlans[i].bridge == bridge) { 968 idx = i; 969 break; 970 } 971 } 972 973 /* If this bridge is not programmed yet, add a Active VLAN table 974 * entry in a free slot and prepare the VLAN mapping table entry. 975 */ 976 if (idx == -1) { 977 idx = gswip_vlan_active_create(priv, bridge, -1, 0); 978 if (idx < 0) 979 return idx; 980 active_vlan_created = true; 981 982 vlan_mapping.index = idx; 983 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 984 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 985 vlan_mapping.val[0] = 0; 986 } else { 987 /* Read the existing VLAN mapping entry from the switch */ 988 vlan_mapping.index = idx; 989 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 990 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 991 if (err) { 992 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 993 err); 994 return err; 995 } 996 } 997 998 /* Update the VLAN mapping entry and write it to the switch */ 999 vlan_mapping.val[1] |= BIT(cpu_port); 1000 vlan_mapping.val[1] |= BIT(port); 1001 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1002 if (err) { 1003 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1004 /* In case an Active VLAN was creaetd delete it again */ 1005 if (active_vlan_created) 1006 gswip_vlan_active_remove(priv, idx); 1007 return err; 1008 } 1009 1010 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1011 return 0; 1012 } 1013 1014 static int gswip_vlan_add_aware(struct gswip_priv *priv, 1015 struct net_device *bridge, int port, 1016 u16 vid, bool untagged, 1017 bool pvid) 1018 { 1019 struct gswip_pce_table_entry vlan_mapping = {0,}; 1020 unsigned int max_ports = priv->hw_info->max_ports; 1021 unsigned int cpu_port = priv->hw_info->cpu_port; 1022 bool active_vlan_created = false; 1023 int idx = -1; 1024 int fid = -1; 1025 int i; 1026 int err; 1027 1028 /* Check if there is already a page for this bridge */ 1029 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1030 if (priv->vlans[i].bridge == bridge) { 1031 if (fid != -1 && fid != priv->vlans[i].fid) 1032 dev_err(priv->dev, "one bridge with multiple flow ids\n"); 1033 fid = priv->vlans[i].fid; 1034 if (priv->vlans[i].vid == vid) { 1035 idx = i; 1036 break; 1037 } 1038 } 1039 } 1040 1041 /* If this bridge is not programmed yet, add a Active VLAN table 1042 * entry in a free slot and prepare the VLAN mapping table entry. 1043 */ 1044 if (idx == -1) { 1045 idx = gswip_vlan_active_create(priv, bridge, fid, vid); 1046 if (idx < 0) 1047 return idx; 1048 active_vlan_created = true; 1049 1050 vlan_mapping.index = idx; 1051 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1052 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 1053 vlan_mapping.val[0] = vid; 1054 } else { 1055 /* Read the existing VLAN mapping entry from the switch */ 1056 vlan_mapping.index = idx; 1057 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1058 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1059 if (err) { 1060 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 1061 err); 1062 return err; 1063 } 1064 } 1065 1066 vlan_mapping.val[0] = vid; 1067 /* Update the VLAN mapping entry and write it to the switch */ 1068 vlan_mapping.val[1] |= BIT(cpu_port); 1069 vlan_mapping.val[2] |= BIT(cpu_port); 1070 vlan_mapping.val[1] |= BIT(port); 1071 if (untagged) 1072 vlan_mapping.val[2] &= ~BIT(port); 1073 else 1074 vlan_mapping.val[2] |= BIT(port); 1075 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1076 if (err) { 1077 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1078 /* In case an Active VLAN was creaetd delete it again */ 1079 if (active_vlan_created) 1080 gswip_vlan_active_remove(priv, idx); 1081 return err; 1082 } 1083 1084 if (pvid) 1085 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 1086 1087 return 0; 1088 } 1089 1090 static int gswip_vlan_remove(struct gswip_priv *priv, 1091 struct net_device *bridge, int port, 1092 u16 vid, bool pvid, bool vlan_aware) 1093 { 1094 struct gswip_pce_table_entry vlan_mapping = {0,}; 1095 unsigned int max_ports = priv->hw_info->max_ports; 1096 unsigned int cpu_port = priv->hw_info->cpu_port; 1097 int idx = -1; 1098 int i; 1099 int err; 1100 1101 /* Check if there is already a page for this bridge */ 1102 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1103 if (priv->vlans[i].bridge == bridge && 1104 (!vlan_aware || priv->vlans[i].vid == vid)) { 1105 idx = i; 1106 break; 1107 } 1108 } 1109 1110 if (idx == -1) { 1111 dev_err(priv->dev, "bridge to leave does not exists\n"); 1112 return -ENOENT; 1113 } 1114 1115 vlan_mapping.index = idx; 1116 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1117 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1118 if (err) { 1119 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); 1120 return err; 1121 } 1122 1123 vlan_mapping.val[1] &= ~BIT(port); 1124 vlan_mapping.val[2] &= ~BIT(port); 1125 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1126 if (err) { 1127 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1128 return err; 1129 } 1130 1131 /* In case all ports are removed from the bridge, remove the VLAN */ 1132 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { 1133 err = gswip_vlan_active_remove(priv, idx); 1134 if (err) { 1135 dev_err(priv->dev, "failed to write active VLAN: %d\n", 1136 err); 1137 return err; 1138 } 1139 } 1140 1141 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 1142 if (pvid) 1143 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1144 1145 return 0; 1146 } 1147 1148 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, 1149 struct dsa_bridge bridge, 1150 bool *tx_fwd_offload) 1151 { 1152 struct net_device *br = bridge.dev; 1153 struct gswip_priv *priv = ds->priv; 1154 int err; 1155 1156 /* When the bridge uses VLAN filtering we have to configure VLAN 1157 * specific bridges. No bridge is configured here. 1158 */ 1159 if (!br_vlan_enabled(br)) { 1160 err = gswip_vlan_add_unaware(priv, br, port); 1161 if (err) 1162 return err; 1163 priv->port_vlan_filter &= ~BIT(port); 1164 } else { 1165 priv->port_vlan_filter |= BIT(port); 1166 } 1167 return gswip_add_single_port_br(priv, port, false); 1168 } 1169 1170 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, 1171 struct dsa_bridge bridge) 1172 { 1173 struct net_device *br = bridge.dev; 1174 struct gswip_priv *priv = ds->priv; 1175 1176 gswip_add_single_port_br(priv, port, true); 1177 1178 /* When the bridge uses VLAN filtering we have to configure VLAN 1179 * specific bridges. No bridge is configured here. 1180 */ 1181 if (!br_vlan_enabled(br)) 1182 gswip_vlan_remove(priv, br, port, 0, true, false); 1183 } 1184 1185 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, 1186 const struct switchdev_obj_port_vlan *vlan, 1187 struct netlink_ext_ack *extack) 1188 { 1189 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1190 struct gswip_priv *priv = ds->priv; 1191 unsigned int max_ports = priv->hw_info->max_ports; 1192 int pos = max_ports; 1193 int i, idx = -1; 1194 1195 /* We only support VLAN filtering on bridges */ 1196 if (!dsa_is_cpu_port(ds, port) && !bridge) 1197 return -EOPNOTSUPP; 1198 1199 /* Check if there is already a page for this VLAN */ 1200 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1201 if (priv->vlans[i].bridge == bridge && 1202 priv->vlans[i].vid == vlan->vid) { 1203 idx = i; 1204 break; 1205 } 1206 } 1207 1208 /* If this VLAN is not programmed yet, we have to reserve 1209 * one entry in the VLAN table. Make sure we start at the 1210 * next position round. 1211 */ 1212 if (idx == -1) { 1213 /* Look for a free slot */ 1214 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { 1215 if (!priv->vlans[pos].bridge) { 1216 idx = pos; 1217 pos++; 1218 break; 1219 } 1220 } 1221 1222 if (idx == -1) { 1223 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table"); 1224 return -ENOSPC; 1225 } 1226 } 1227 1228 return 0; 1229 } 1230 1231 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, 1232 const struct switchdev_obj_port_vlan *vlan, 1233 struct netlink_ext_ack *extack) 1234 { 1235 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1236 struct gswip_priv *priv = ds->priv; 1237 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1238 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1239 int err; 1240 1241 err = gswip_port_vlan_prepare(ds, port, vlan, extack); 1242 if (err) 1243 return err; 1244 1245 /* We have to receive all packets on the CPU port and should not 1246 * do any VLAN filtering here. This is also called with bridge 1247 * NULL and then we do not know for which bridge to configure 1248 * this. 1249 */ 1250 if (dsa_is_cpu_port(ds, port)) 1251 return 0; 1252 1253 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, 1254 untagged, pvid); 1255 } 1256 1257 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, 1258 const struct switchdev_obj_port_vlan *vlan) 1259 { 1260 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1261 struct gswip_priv *priv = ds->priv; 1262 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1263 1264 /* We have to receive all packets on the CPU port and should not 1265 * do any VLAN filtering here. This is also called with bridge 1266 * NULL and then we do not know for which bridge to configure 1267 * this. 1268 */ 1269 if (dsa_is_cpu_port(ds, port)) 1270 return 0; 1271 1272 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); 1273 } 1274 1275 static void gswip_port_fast_age(struct dsa_switch *ds, int port) 1276 { 1277 struct gswip_priv *priv = ds->priv; 1278 struct gswip_pce_table_entry mac_bridge = {0,}; 1279 int i; 1280 int err; 1281 1282 for (i = 0; i < 2048; i++) { 1283 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1284 mac_bridge.index = i; 1285 1286 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1287 if (err) { 1288 dev_err(priv->dev, "failed to read mac bridge: %d\n", 1289 err); 1290 return; 1291 } 1292 1293 if (!mac_bridge.valid) 1294 continue; 1295 1296 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) 1297 continue; 1298 1299 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) 1300 continue; 1301 1302 mac_bridge.valid = false; 1303 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1304 if (err) { 1305 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1306 err); 1307 return; 1308 } 1309 } 1310 } 1311 1312 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1313 { 1314 struct gswip_priv *priv = ds->priv; 1315 u32 stp_state; 1316 1317 switch (state) { 1318 case BR_STATE_DISABLED: 1319 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1320 GSWIP_SDMA_PCTRLp(port)); 1321 return; 1322 case BR_STATE_BLOCKING: 1323 case BR_STATE_LISTENING: 1324 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; 1325 break; 1326 case BR_STATE_LEARNING: 1327 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; 1328 break; 1329 case BR_STATE_FORWARDING: 1330 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; 1331 break; 1332 default: 1333 dev_err(priv->dev, "invalid STP state: %d\n", state); 1334 return; 1335 } 1336 1337 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1338 GSWIP_SDMA_PCTRLp(port)); 1339 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1340 GSWIP_PCE_PCTRL_0p(port)); 1341 } 1342 1343 static int gswip_port_fdb(struct dsa_switch *ds, int port, 1344 const unsigned char *addr, u16 vid, bool add) 1345 { 1346 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1347 struct gswip_priv *priv = ds->priv; 1348 struct gswip_pce_table_entry mac_bridge = {0,}; 1349 unsigned int cpu_port = priv->hw_info->cpu_port; 1350 int fid = -1; 1351 int i; 1352 int err; 1353 1354 if (!bridge) 1355 return -EINVAL; 1356 1357 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) { 1358 if (priv->vlans[i].bridge == bridge) { 1359 fid = priv->vlans[i].fid; 1360 break; 1361 } 1362 } 1363 1364 if (fid == -1) { 1365 dev_err(priv->dev, "Port not part of a bridge\n"); 1366 return -EINVAL; 1367 } 1368 1369 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1370 mac_bridge.key_mode = true; 1371 mac_bridge.key[0] = addr[5] | (addr[4] << 8); 1372 mac_bridge.key[1] = addr[3] | (addr[2] << 8); 1373 mac_bridge.key[2] = addr[1] | (addr[0] << 8); 1374 mac_bridge.key[3] = fid; 1375 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ 1376 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; 1377 mac_bridge.valid = add; 1378 1379 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1380 if (err) 1381 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); 1382 1383 return err; 1384 } 1385 1386 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, 1387 const unsigned char *addr, u16 vid) 1388 { 1389 return gswip_port_fdb(ds, port, addr, vid, true); 1390 } 1391 1392 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, 1393 const unsigned char *addr, u16 vid) 1394 { 1395 return gswip_port_fdb(ds, port, addr, vid, false); 1396 } 1397 1398 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, 1399 dsa_fdb_dump_cb_t *cb, void *data) 1400 { 1401 struct gswip_priv *priv = ds->priv; 1402 struct gswip_pce_table_entry mac_bridge = {0,}; 1403 unsigned char addr[6]; 1404 int i; 1405 int err; 1406 1407 for (i = 0; i < 2048; i++) { 1408 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1409 mac_bridge.index = i; 1410 1411 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1412 if (err) { 1413 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1414 err); 1415 return err; 1416 } 1417 1418 if (!mac_bridge.valid) 1419 continue; 1420 1421 addr[5] = mac_bridge.key[0] & 0xff; 1422 addr[4] = (mac_bridge.key[0] >> 8) & 0xff; 1423 addr[3] = mac_bridge.key[1] & 0xff; 1424 addr[2] = (mac_bridge.key[1] >> 8) & 0xff; 1425 addr[1] = mac_bridge.key[2] & 0xff; 1426 addr[0] = (mac_bridge.key[2] >> 8) & 0xff; 1427 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { 1428 if (mac_bridge.val[0] & BIT(port)) { 1429 err = cb(addr, 0, true, data); 1430 if (err) 1431 return err; 1432 } 1433 } else { 1434 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) { 1435 err = cb(addr, 0, false, data); 1436 if (err) 1437 return err; 1438 } 1439 } 1440 } 1441 return 0; 1442 } 1443 1444 static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port, 1445 struct phylink_config *config) 1446 { 1447 switch (port) { 1448 case 0: 1449 case 1: 1450 phy_interface_set_rgmii(config->supported_interfaces); 1451 __set_bit(PHY_INTERFACE_MODE_MII, 1452 config->supported_interfaces); 1453 __set_bit(PHY_INTERFACE_MODE_REVMII, 1454 config->supported_interfaces); 1455 __set_bit(PHY_INTERFACE_MODE_RMII, 1456 config->supported_interfaces); 1457 break; 1458 1459 case 2: 1460 case 3: 1461 case 4: 1462 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1463 config->supported_interfaces); 1464 break; 1465 1466 case 5: 1467 phy_interface_set_rgmii(config->supported_interfaces); 1468 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1469 config->supported_interfaces); 1470 break; 1471 } 1472 1473 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1474 MAC_10 | MAC_100 | MAC_1000; 1475 } 1476 1477 static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port, 1478 struct phylink_config *config) 1479 { 1480 switch (port) { 1481 case 0: 1482 phy_interface_set_rgmii(config->supported_interfaces); 1483 __set_bit(PHY_INTERFACE_MODE_GMII, 1484 config->supported_interfaces); 1485 __set_bit(PHY_INTERFACE_MODE_RMII, 1486 config->supported_interfaces); 1487 break; 1488 1489 case 1: 1490 case 2: 1491 case 3: 1492 case 4: 1493 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1494 config->supported_interfaces); 1495 break; 1496 1497 case 5: 1498 phy_interface_set_rgmii(config->supported_interfaces); 1499 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1500 config->supported_interfaces); 1501 __set_bit(PHY_INTERFACE_MODE_RMII, 1502 config->supported_interfaces); 1503 break; 1504 } 1505 1506 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1507 MAC_10 | MAC_100 | MAC_1000; 1508 } 1509 1510 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) 1511 { 1512 u32 mdio_phy; 1513 1514 if (link) 1515 mdio_phy = GSWIP_MDIO_PHY_LINK_UP; 1516 else 1517 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN; 1518 1519 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy, 1520 GSWIP_MDIO_PHYp(port)); 1521 } 1522 1523 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, 1524 phy_interface_t interface) 1525 { 1526 u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0; 1527 1528 switch (speed) { 1529 case SPEED_10: 1530 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10; 1531 1532 if (interface == PHY_INTERFACE_MODE_RMII) 1533 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1534 else 1535 mii_cfg = GSWIP_MII_CFG_RATE_M2P5; 1536 1537 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1538 break; 1539 1540 case SPEED_100: 1541 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100; 1542 1543 if (interface == PHY_INTERFACE_MODE_RMII) 1544 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1545 else 1546 mii_cfg = GSWIP_MII_CFG_RATE_M25; 1547 1548 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1549 break; 1550 1551 case SPEED_1000: 1552 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1; 1553 1554 mii_cfg = GSWIP_MII_CFG_RATE_M125; 1555 1556 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII; 1557 break; 1558 } 1559 1560 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy, 1561 GSWIP_MDIO_PHYp(port)); 1562 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); 1563 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0, 1564 GSWIP_MAC_CTRL_0p(port)); 1565 } 1566 1567 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) 1568 { 1569 u32 mac_ctrl_0, mdio_phy; 1570 1571 if (duplex == DUPLEX_FULL) { 1572 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN; 1573 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN; 1574 } else { 1575 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS; 1576 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS; 1577 } 1578 1579 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0, 1580 GSWIP_MAC_CTRL_0p(port)); 1581 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy, 1582 GSWIP_MDIO_PHYp(port)); 1583 } 1584 1585 static void gswip_port_set_pause(struct gswip_priv *priv, int port, 1586 bool tx_pause, bool rx_pause) 1587 { 1588 u32 mac_ctrl_0, mdio_phy; 1589 1590 if (tx_pause && rx_pause) { 1591 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX; 1592 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1593 GSWIP_MDIO_PHY_FCONRX_EN; 1594 } else if (tx_pause) { 1595 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX; 1596 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1597 GSWIP_MDIO_PHY_FCONRX_DIS; 1598 } else if (rx_pause) { 1599 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX; 1600 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1601 GSWIP_MDIO_PHY_FCONRX_EN; 1602 } else { 1603 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE; 1604 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1605 GSWIP_MDIO_PHY_FCONRX_DIS; 1606 } 1607 1608 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK, 1609 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); 1610 gswip_mdio_mask(priv, 1611 GSWIP_MDIO_PHY_FCONTX_MASK | 1612 GSWIP_MDIO_PHY_FCONRX_MASK, 1613 mdio_phy, GSWIP_MDIO_PHYp(port)); 1614 } 1615 1616 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, 1617 unsigned int mode, 1618 const struct phylink_link_state *state) 1619 { 1620 struct gswip_priv *priv = ds->priv; 1621 u32 miicfg = 0; 1622 1623 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 1624 1625 switch (state->interface) { 1626 case PHY_INTERFACE_MODE_MII: 1627 case PHY_INTERFACE_MODE_INTERNAL: 1628 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 1629 break; 1630 case PHY_INTERFACE_MODE_REVMII: 1631 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 1632 break; 1633 case PHY_INTERFACE_MODE_RMII: 1634 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 1635 1636 /* Configure the RMII clock as output: */ 1637 miicfg |= GSWIP_MII_CFG_RMII_CLK; 1638 break; 1639 case PHY_INTERFACE_MODE_RGMII: 1640 case PHY_INTERFACE_MODE_RGMII_ID: 1641 case PHY_INTERFACE_MODE_RGMII_RXID: 1642 case PHY_INTERFACE_MODE_RGMII_TXID: 1643 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 1644 break; 1645 case PHY_INTERFACE_MODE_GMII: 1646 miicfg |= GSWIP_MII_CFG_MODE_GMII; 1647 break; 1648 default: 1649 dev_err(ds->dev, 1650 "Unsupported interface: %d\n", state->interface); 1651 return; 1652 } 1653 1654 gswip_mii_mask_cfg(priv, 1655 GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK | 1656 GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS, 1657 miicfg, port); 1658 1659 switch (state->interface) { 1660 case PHY_INTERFACE_MODE_RGMII_ID: 1661 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 1662 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1663 break; 1664 case PHY_INTERFACE_MODE_RGMII_RXID: 1665 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1666 break; 1667 case PHY_INTERFACE_MODE_RGMII_TXID: 1668 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 1669 break; 1670 default: 1671 break; 1672 } 1673 } 1674 1675 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, 1676 unsigned int mode, 1677 phy_interface_t interface) 1678 { 1679 struct gswip_priv *priv = ds->priv; 1680 1681 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 1682 1683 if (!dsa_is_cpu_port(ds, port)) 1684 gswip_port_set_link(priv, port, false); 1685 } 1686 1687 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, 1688 unsigned int mode, 1689 phy_interface_t interface, 1690 struct phy_device *phydev, 1691 int speed, int duplex, 1692 bool tx_pause, bool rx_pause) 1693 { 1694 struct gswip_priv *priv = ds->priv; 1695 1696 if (!dsa_is_cpu_port(ds, port)) { 1697 gswip_port_set_link(priv, port, true); 1698 gswip_port_set_speed(priv, port, speed, interface); 1699 gswip_port_set_duplex(priv, port, duplex); 1700 gswip_port_set_pause(priv, port, tx_pause, rx_pause); 1701 } 1702 1703 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1704 } 1705 1706 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1707 uint8_t *data) 1708 { 1709 int i; 1710 1711 if (stringset != ETH_SS_STATS) 1712 return; 1713 1714 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 1715 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name, 1716 ETH_GSTRING_LEN); 1717 } 1718 1719 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1720 u32 index) 1721 { 1722 u32 result; 1723 int err; 1724 1725 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1726 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1727 GSWIP_BM_RAM_CTRL_OPMOD, 1728 table | GSWIP_BM_RAM_CTRL_BAS, 1729 GSWIP_BM_RAM_CTRL); 1730 1731 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1732 GSWIP_BM_RAM_CTRL_BAS); 1733 if (err) { 1734 dev_err(priv->dev, "timeout while reading table: %u, index: %u", 1735 table, index); 1736 return 0; 1737 } 1738 1739 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1740 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1741 1742 return result; 1743 } 1744 1745 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 1746 uint64_t *data) 1747 { 1748 struct gswip_priv *priv = ds->priv; 1749 const struct gswip_rmon_cnt_desc *rmon_cnt; 1750 int i; 1751 u64 high; 1752 1753 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 1754 rmon_cnt = &gswip_rmon_cnt[i]; 1755 1756 data[i] = gswip_bcm_ram_entry_read(priv, port, 1757 rmon_cnt->offset); 1758 if (rmon_cnt->size == 2) { 1759 high = gswip_bcm_ram_entry_read(priv, port, 1760 rmon_cnt->offset + 1); 1761 data[i] |= high << 32; 1762 } 1763 } 1764 } 1765 1766 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 1767 { 1768 if (sset != ETH_SS_STATS) 1769 return 0; 1770 1771 return ARRAY_SIZE(gswip_rmon_cnt); 1772 } 1773 1774 static const struct dsa_switch_ops gswip_xrx200_switch_ops = { 1775 .get_tag_protocol = gswip_get_tag_protocol, 1776 .setup = gswip_setup, 1777 .port_enable = gswip_port_enable, 1778 .port_disable = gswip_port_disable, 1779 .port_bridge_join = gswip_port_bridge_join, 1780 .port_bridge_leave = gswip_port_bridge_leave, 1781 .port_fast_age = gswip_port_fast_age, 1782 .port_vlan_filtering = gswip_port_vlan_filtering, 1783 .port_vlan_add = gswip_port_vlan_add, 1784 .port_vlan_del = gswip_port_vlan_del, 1785 .port_stp_state_set = gswip_port_stp_state_set, 1786 .port_fdb_add = gswip_port_fdb_add, 1787 .port_fdb_del = gswip_port_fdb_del, 1788 .port_fdb_dump = gswip_port_fdb_dump, 1789 .phylink_get_caps = gswip_xrx200_phylink_get_caps, 1790 .phylink_mac_config = gswip_phylink_mac_config, 1791 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1792 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1793 .get_strings = gswip_get_strings, 1794 .get_ethtool_stats = gswip_get_ethtool_stats, 1795 .get_sset_count = gswip_get_sset_count, 1796 }; 1797 1798 static const struct dsa_switch_ops gswip_xrx300_switch_ops = { 1799 .get_tag_protocol = gswip_get_tag_protocol, 1800 .setup = gswip_setup, 1801 .port_enable = gswip_port_enable, 1802 .port_disable = gswip_port_disable, 1803 .port_bridge_join = gswip_port_bridge_join, 1804 .port_bridge_leave = gswip_port_bridge_leave, 1805 .port_fast_age = gswip_port_fast_age, 1806 .port_vlan_filtering = gswip_port_vlan_filtering, 1807 .port_vlan_add = gswip_port_vlan_add, 1808 .port_vlan_del = gswip_port_vlan_del, 1809 .port_stp_state_set = gswip_port_stp_state_set, 1810 .port_fdb_add = gswip_port_fdb_add, 1811 .port_fdb_del = gswip_port_fdb_del, 1812 .port_fdb_dump = gswip_port_fdb_dump, 1813 .phylink_get_caps = gswip_xrx300_phylink_get_caps, 1814 .phylink_mac_config = gswip_phylink_mac_config, 1815 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1816 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1817 .get_strings = gswip_get_strings, 1818 .get_ethtool_stats = gswip_get_ethtool_stats, 1819 .get_sset_count = gswip_get_sset_count, 1820 }; 1821 1822 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 1823 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 1824 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 1825 }; 1826 1827 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 1828 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 1829 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 1830 }; 1831 1832 static const struct xway_gphy_match_data xrx300_gphy_data = { 1833 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 1834 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 1835 }; 1836 1837 static const struct of_device_id xway_gphy_match[] = { 1838 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 1839 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 1840 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 1841 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 1842 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 1843 {}, 1844 }; 1845 1846 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 1847 { 1848 struct device *dev = priv->dev; 1849 const struct firmware *fw; 1850 void *fw_addr; 1851 dma_addr_t dma_addr; 1852 dma_addr_t dev_addr; 1853 size_t size; 1854 int ret; 1855 1856 ret = clk_prepare_enable(gphy_fw->clk_gate); 1857 if (ret) 1858 return ret; 1859 1860 reset_control_assert(gphy_fw->reset); 1861 1862 /* The vendor BSP uses a 200ms delay after asserting the reset line. 1863 * Without this some users are observing that the PHY is not coming up 1864 * on the MDIO bus. 1865 */ 1866 msleep(200); 1867 1868 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 1869 if (ret) { 1870 dev_err(dev, "failed to load firmware: %s, error: %i\n", 1871 gphy_fw->fw_name, ret); 1872 return ret; 1873 } 1874 1875 /* GPHY cores need the firmware code in a persistent and contiguous 1876 * memory area with a 16 kB boundary aligned start address. 1877 */ 1878 size = fw->size + XRX200_GPHY_FW_ALIGN; 1879 1880 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 1881 if (fw_addr) { 1882 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 1883 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 1884 memcpy(fw_addr, fw->data, fw->size); 1885 } else { 1886 dev_err(dev, "failed to alloc firmware memory\n"); 1887 release_firmware(fw); 1888 return -ENOMEM; 1889 } 1890 1891 release_firmware(fw); 1892 1893 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 1894 if (ret) 1895 return ret; 1896 1897 reset_control_deassert(gphy_fw->reset); 1898 1899 return ret; 1900 } 1901 1902 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 1903 struct gswip_gphy_fw *gphy_fw, 1904 struct device_node *gphy_fw_np, int i) 1905 { 1906 struct device *dev = priv->dev; 1907 u32 gphy_mode; 1908 int ret; 1909 char gphyname[10]; 1910 1911 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 1912 1913 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 1914 if (IS_ERR(gphy_fw->clk_gate)) { 1915 dev_err(dev, "Failed to lookup gate clock\n"); 1916 return PTR_ERR(gphy_fw->clk_gate); 1917 } 1918 1919 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 1920 if (ret) 1921 return ret; 1922 1923 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 1924 /* Default to GE mode */ 1925 if (ret) 1926 gphy_mode = GPHY_MODE_GE; 1927 1928 switch (gphy_mode) { 1929 case GPHY_MODE_FE: 1930 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 1931 break; 1932 case GPHY_MODE_GE: 1933 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 1934 break; 1935 default: 1936 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); 1937 return -EINVAL; 1938 } 1939 1940 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 1941 if (IS_ERR(gphy_fw->reset)) { 1942 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER) 1943 dev_err(dev, "Failed to lookup gphy reset\n"); 1944 return PTR_ERR(gphy_fw->reset); 1945 } 1946 1947 return gswip_gphy_fw_load(priv, gphy_fw); 1948 } 1949 1950 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 1951 struct gswip_gphy_fw *gphy_fw) 1952 { 1953 int ret; 1954 1955 /* check if the device was fully probed */ 1956 if (!gphy_fw->fw_name) 1957 return; 1958 1959 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 1960 if (ret) 1961 dev_err(priv->dev, "can not reset GPHY FW pointer"); 1962 1963 clk_disable_unprepare(gphy_fw->clk_gate); 1964 1965 reset_control_put(gphy_fw->reset); 1966 } 1967 1968 static int gswip_gphy_fw_list(struct gswip_priv *priv, 1969 struct device_node *gphy_fw_list_np, u32 version) 1970 { 1971 struct device *dev = priv->dev; 1972 struct device_node *gphy_fw_np; 1973 const struct of_device_id *match; 1974 int err; 1975 int i = 0; 1976 1977 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 1978 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 1979 * needs a different GPHY firmware. 1980 */ 1981 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 1982 switch (version) { 1983 case GSWIP_VERSION_2_0: 1984 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 1985 break; 1986 case GSWIP_VERSION_2_1: 1987 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 1988 break; 1989 default: 1990 dev_err(dev, "unknown GSWIP version: 0x%x", version); 1991 return -ENOENT; 1992 } 1993 } 1994 1995 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 1996 if (match && match->data) 1997 priv->gphy_fw_name_cfg = match->data; 1998 1999 if (!priv->gphy_fw_name_cfg) { 2000 dev_err(dev, "GPHY compatible type not supported"); 2001 return -ENOENT; 2002 } 2003 2004 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 2005 if (!priv->num_gphy_fw) 2006 return -ENOENT; 2007 2008 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 2009 "lantiq,rcu"); 2010 if (IS_ERR(priv->rcu_regmap)) 2011 return PTR_ERR(priv->rcu_regmap); 2012 2013 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 2014 sizeof(*priv->gphy_fw), 2015 GFP_KERNEL | __GFP_ZERO); 2016 if (!priv->gphy_fw) 2017 return -ENOMEM; 2018 2019 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 2020 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 2021 gphy_fw_np, i); 2022 if (err) 2023 goto remove_gphy; 2024 i++; 2025 } 2026 2027 /* The standalone PHY11G requires 300ms to be fully 2028 * initialized and ready for any MDIO communication after being 2029 * taken out of reset. For the SoC-internal GPHY variant there 2030 * is no (known) documentation for the minimum time after a 2031 * reset. Use the same value as for the standalone variant as 2032 * some users have reported internal PHYs not being detected 2033 * without any delay. 2034 */ 2035 msleep(300); 2036 2037 return 0; 2038 2039 remove_gphy: 2040 for (i = 0; i < priv->num_gphy_fw; i++) 2041 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2042 return err; 2043 } 2044 2045 static int gswip_probe(struct platform_device *pdev) 2046 { 2047 struct gswip_priv *priv; 2048 struct device_node *np, *mdio_np, *gphy_fw_np; 2049 struct device *dev = &pdev->dev; 2050 int err; 2051 int i; 2052 u32 version; 2053 2054 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2055 if (!priv) 2056 return -ENOMEM; 2057 2058 priv->gswip = devm_platform_ioremap_resource(pdev, 0); 2059 if (IS_ERR(priv->gswip)) 2060 return PTR_ERR(priv->gswip); 2061 2062 priv->mdio = devm_platform_ioremap_resource(pdev, 1); 2063 if (IS_ERR(priv->mdio)) 2064 return PTR_ERR(priv->mdio); 2065 2066 priv->mii = devm_platform_ioremap_resource(pdev, 2); 2067 if (IS_ERR(priv->mii)) 2068 return PTR_ERR(priv->mii); 2069 2070 priv->hw_info = of_device_get_match_data(dev); 2071 if (!priv->hw_info) 2072 return -EINVAL; 2073 2074 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 2075 if (!priv->ds) 2076 return -ENOMEM; 2077 2078 priv->ds->dev = dev; 2079 priv->ds->num_ports = priv->hw_info->max_ports; 2080 priv->ds->priv = priv; 2081 priv->ds->ops = priv->hw_info->ops; 2082 priv->dev = dev; 2083 mutex_init(&priv->pce_table_lock); 2084 version = gswip_switch_r(priv, GSWIP_VERSION); 2085 2086 np = dev->of_node; 2087 switch (version) { 2088 case GSWIP_VERSION_2_0: 2089 case GSWIP_VERSION_2_1: 2090 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip")) 2091 return -EINVAL; 2092 break; 2093 case GSWIP_VERSION_2_2: 2094 case GSWIP_VERSION_2_2_ETC: 2095 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") && 2096 !of_device_is_compatible(np, "lantiq,xrx330-gswip")) 2097 return -EINVAL; 2098 break; 2099 default: 2100 dev_err(dev, "unknown GSWIP version: 0x%x", version); 2101 return -ENOENT; 2102 } 2103 2104 /* bring up the mdio bus */ 2105 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 2106 if (gphy_fw_np) { 2107 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 2108 of_node_put(gphy_fw_np); 2109 if (err) { 2110 dev_err(dev, "gphy fw probe failed\n"); 2111 return err; 2112 } 2113 } 2114 2115 /* bring up the mdio bus */ 2116 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio"); 2117 if (mdio_np) { 2118 err = gswip_mdio(priv, mdio_np); 2119 if (err) { 2120 dev_err(dev, "mdio probe failed\n"); 2121 goto put_mdio_node; 2122 } 2123 } 2124 2125 err = dsa_register_switch(priv->ds); 2126 if (err) { 2127 dev_err(dev, "dsa switch register failed: %i\n", err); 2128 goto mdio_bus; 2129 } 2130 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { 2131 dev_err(dev, "wrong CPU port defined, HW only supports port: %i", 2132 priv->hw_info->cpu_port); 2133 err = -EINVAL; 2134 goto disable_switch; 2135 } 2136 2137 platform_set_drvdata(pdev, priv); 2138 2139 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 2140 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, 2141 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); 2142 return 0; 2143 2144 disable_switch: 2145 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2146 dsa_unregister_switch(priv->ds); 2147 mdio_bus: 2148 if (mdio_np) 2149 mdiobus_unregister(priv->ds->slave_mii_bus); 2150 put_mdio_node: 2151 of_node_put(mdio_np); 2152 for (i = 0; i < priv->num_gphy_fw; i++) 2153 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2154 return err; 2155 } 2156 2157 static int gswip_remove(struct platform_device *pdev) 2158 { 2159 struct gswip_priv *priv = platform_get_drvdata(pdev); 2160 int i; 2161 2162 if (!priv) 2163 return 0; 2164 2165 /* disable the switch */ 2166 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2167 2168 dsa_unregister_switch(priv->ds); 2169 2170 if (priv->ds->slave_mii_bus) { 2171 mdiobus_unregister(priv->ds->slave_mii_bus); 2172 of_node_put(priv->ds->slave_mii_bus->dev.of_node); 2173 } 2174 2175 for (i = 0; i < priv->num_gphy_fw; i++) 2176 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2177 2178 platform_set_drvdata(pdev, NULL); 2179 2180 return 0; 2181 } 2182 2183 static void gswip_shutdown(struct platform_device *pdev) 2184 { 2185 struct gswip_priv *priv = platform_get_drvdata(pdev); 2186 2187 if (!priv) 2188 return; 2189 2190 dsa_switch_shutdown(priv->ds); 2191 2192 platform_set_drvdata(pdev, NULL); 2193 } 2194 2195 static const struct gswip_hw_info gswip_xrx200 = { 2196 .max_ports = 7, 2197 .cpu_port = 6, 2198 .ops = &gswip_xrx200_switch_ops, 2199 }; 2200 2201 static const struct gswip_hw_info gswip_xrx300 = { 2202 .max_ports = 7, 2203 .cpu_port = 6, 2204 .ops = &gswip_xrx300_switch_ops, 2205 }; 2206 2207 static const struct of_device_id gswip_of_match[] = { 2208 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 2209 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 }, 2210 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 }, 2211 {}, 2212 }; 2213 MODULE_DEVICE_TABLE(of, gswip_of_match); 2214 2215 static struct platform_driver gswip_driver = { 2216 .probe = gswip_probe, 2217 .remove = gswip_remove, 2218 .shutdown = gswip_shutdown, 2219 .driver = { 2220 .name = "gswip", 2221 .of_match_table = gswip_of_match, 2222 }, 2223 }; 2224 2225 module_platform_driver(gswip_driver); 2226 2227 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 2228 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 2229 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 2230 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 2231 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 2232 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 2233 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 2234 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 2235 MODULE_LICENSE("GPL v2"); 2236