1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * The VLAN and bridge model the GSWIP hardware uses does not directly 10 * matches the model DSA uses. 11 * 12 * The hardware has 64 possible table entries for bridges with one VLAN 13 * ID, one flow id and a list of ports for each bridge. All entries which 14 * match the same flow ID are combined in the mac learning table, they 15 * act as one global bridge. 16 * The hardware does not support VLAN filter on the port, but on the 17 * bridge, this driver converts the DSA model to the hardware. 18 * 19 * The CPU gets all the exception frames which do not match any forwarding 20 * rule and the CPU port is also added to all bridges. This makes it possible 21 * to handle all the special cases easily in software. 22 * At the initialization the driver allocates one bridge table entry for 23 * each switch port which is used when the port is used without an 24 * explicit bridge. This prevents the frames from being forwarded 25 * between all LAN ports by default. 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 #include <linux/etherdevice.h> 31 #include <linux/firmware.h> 32 #include <linux/if_bridge.h> 33 #include <linux/if_vlan.h> 34 #include <linux/iopoll.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/module.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/of_platform.h> 40 #include <linux/phy.h> 41 #include <linux/phylink.h> 42 #include <linux/platform_device.h> 43 #include <linux/regmap.h> 44 #include <linux/reset.h> 45 #include <net/dsa.h> 46 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 47 48 #include "lantiq_pce.h" 49 50 /* GSWIP MDIO Registers */ 51 #define GSWIP_MDIO_GLOB 0x00 52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 53 #define GSWIP_MDIO_CTRL 0x08 54 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 55 #define GSWIP_MDIO_CTRL_RD BIT(11) 56 #define GSWIP_MDIO_CTRL_WR BIT(10) 57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 60 #define GSWIP_MDIO_READ 0x09 61 #define GSWIP_MDIO_WRITE 0x0A 62 #define GSWIP_MDIO_MDC_CFG0 0x0B 63 #define GSWIP_MDIO_MDC_CFG1 0x0C 64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 88 GSWIP_MDIO_PHY_FCONRX_MASK | \ 89 GSWIP_MDIO_PHY_FCONTX_MASK | \ 90 GSWIP_MDIO_PHY_LINK_MASK | \ 91 GSWIP_MDIO_PHY_SPEED_MASK | \ 92 GSWIP_MDIO_PHY_FDUP_MASK) 93 94 /* GSWIP MII Registers */ 95 #define GSWIP_MII_CFGp(p) (0x2 * (p)) 96 #define GSWIP_MII_CFG_RESET BIT(15) 97 #define GSWIP_MII_CFG_EN BIT(14) 98 #define GSWIP_MII_CFG_ISOLATE BIT(13) 99 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 100 #define GSWIP_MII_CFG_RGMII_IBS BIT(8) 101 #define GSWIP_MII_CFG_RMII_CLK BIT(7) 102 #define GSWIP_MII_CFG_MODE_MIIP 0x0 103 #define GSWIP_MII_CFG_MODE_MIIM 0x1 104 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 105 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 106 #define GSWIP_MII_CFG_MODE_RGMII 0x4 107 #define GSWIP_MII_CFG_MODE_MASK 0xf 108 #define GSWIP_MII_CFG_RATE_M2P5 0x00 109 #define GSWIP_MII_CFG_RATE_M25 0x10 110 #define GSWIP_MII_CFG_RATE_M125 0x20 111 #define GSWIP_MII_CFG_RATE_M50 0x30 112 #define GSWIP_MII_CFG_RATE_AUTO 0x40 113 #define GSWIP_MII_CFG_RATE_MASK 0x70 114 #define GSWIP_MII_PCDU0 0x01 115 #define GSWIP_MII_PCDU1 0x03 116 #define GSWIP_MII_PCDU5 0x05 117 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 118 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 119 120 /* GSWIP Core Registers */ 121 #define GSWIP_SWRES 0x000 122 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 123 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 124 #define GSWIP_VERSION 0x013 125 #define GSWIP_VERSION_REV_SHIFT 0 126 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 127 #define GSWIP_VERSION_MOD_SHIFT 8 128 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 129 #define GSWIP_VERSION_2_0 0x100 130 #define GSWIP_VERSION_2_1 0x021 131 #define GSWIP_VERSION_2_2 0x122 132 #define GSWIP_VERSION_2_2_ETC 0x022 133 134 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 135 #define GSWIP_BM_RAM_ADDR 0x044 136 #define GSWIP_BM_RAM_CTRL 0x045 137 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 138 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 139 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 140 #define GSWIP_BM_QUEUE_GCTRL 0x04A 141 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 142 /* buffer management Port Configuration Register */ 143 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 144 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 145 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 146 /* buffer management Port Control Register */ 147 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 148 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 149 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 150 151 /* PCE */ 152 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 153 #define GSWIP_PCE_TBL_MASK 0x448 154 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 155 #define GSWIP_PCE_TBL_ADDR 0x44E 156 #define GSWIP_PCE_TBL_CTRL 0x44F 157 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 158 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 159 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 160 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 161 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 162 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 163 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 164 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 165 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 166 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 167 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 168 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 169 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 170 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 171 #define GSWIP_PCE_GCTRL_0 0x456 172 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ 173 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 174 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 175 #define GSWIP_PCE_GCTRL_1 0x457 176 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 177 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 178 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 179 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ 180 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ 181 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ 182 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 183 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 184 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 185 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 186 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 187 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 188 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) 189 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ 190 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ 191 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ 192 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ 193 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ 194 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) 195 196 #define GSWIP_MAC_FLEN 0x8C5 197 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC)) 198 #define GSWIP_MAC_CTRL_0_PADEN BIT(8) 199 #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7) 200 #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070 201 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000 202 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010 203 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020 204 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030 205 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040 206 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C 207 #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000 208 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004 209 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C 210 #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003 211 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000 212 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 213 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 214 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 215 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 216 217 /* Ethernet Switch Fetch DMA Port Control Register */ 218 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 219 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 220 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 221 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 222 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 223 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 224 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 225 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 226 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 227 228 /* Ethernet Switch Store DMA Port Control Register */ 229 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 230 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 231 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 232 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */ 233 234 #define GSWIP_TABLE_ACTIVE_VLAN 0x01 235 #define GSWIP_TABLE_VLAN_MAPPING 0x02 236 #define GSWIP_TABLE_MAC_BRIDGE 0x0b 237 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ 238 239 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 240 241 struct gswip_hw_info { 242 int max_ports; 243 int cpu_port; 244 }; 245 246 struct xway_gphy_match_data { 247 char *fe_firmware_name; 248 char *ge_firmware_name; 249 }; 250 251 struct gswip_gphy_fw { 252 struct clk *clk_gate; 253 struct reset_control *reset; 254 u32 fw_addr_offset; 255 char *fw_name; 256 }; 257 258 struct gswip_vlan { 259 struct net_device *bridge; 260 u16 vid; 261 u8 fid; 262 }; 263 264 struct gswip_priv { 265 __iomem void *gswip; 266 __iomem void *mdio; 267 __iomem void *mii; 268 const struct gswip_hw_info *hw_info; 269 const struct xway_gphy_match_data *gphy_fw_name_cfg; 270 struct dsa_switch *ds; 271 struct device *dev; 272 struct regmap *rcu_regmap; 273 struct gswip_vlan vlans[64]; 274 int num_gphy_fw; 275 struct gswip_gphy_fw *gphy_fw; 276 u32 port_vlan_filter; 277 }; 278 279 struct gswip_pce_table_entry { 280 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index 281 u16 table; // PCE_TBL_CTRL.ADDR = pData->table 282 u16 key[8]; 283 u16 val[5]; 284 u16 mask; 285 u8 gmap; 286 bool type; 287 bool valid; 288 bool key_mode; 289 }; 290 291 struct gswip_rmon_cnt_desc { 292 unsigned int size; 293 unsigned int offset; 294 const char *name; 295 }; 296 297 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 298 299 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 300 /** Receive Packet Count (only packets that are accepted and not discarded). */ 301 MIB_DESC(1, 0x1F, "RxGoodPkts"), 302 MIB_DESC(1, 0x23, "RxUnicastPkts"), 303 MIB_DESC(1, 0x22, "RxMulticastPkts"), 304 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 305 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 306 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 307 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 308 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 309 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 310 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 311 MIB_DESC(1, 0x12, "Rx64BytePkts"), 312 MIB_DESC(1, 0x13, "Rx127BytePkts"), 313 MIB_DESC(1, 0x14, "Rx255BytePkts"), 314 MIB_DESC(1, 0x15, "Rx511BytePkts"), 315 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 316 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 317 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 318 MIB_DESC(1, 0x18, "RxDroppedPkts"), 319 MIB_DESC(1, 0x19, "RxFilteredPkts"), 320 MIB_DESC(2, 0x24, "RxGoodBytes"), 321 MIB_DESC(2, 0x26, "RxBadBytes"), 322 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 323 MIB_DESC(1, 0x0C, "TxGoodPkts"), 324 MIB_DESC(1, 0x06, "TxUnicastPkts"), 325 MIB_DESC(1, 0x07, "TxMulticastPkts"), 326 MIB_DESC(1, 0x00, "Tx64BytePkts"), 327 MIB_DESC(1, 0x01, "Tx127BytePkts"), 328 MIB_DESC(1, 0x02, "Tx255BytePkts"), 329 MIB_DESC(1, 0x03, "Tx511BytePkts"), 330 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 331 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 332 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 333 MIB_DESC(1, 0x08, "TxSingleCollCount"), 334 MIB_DESC(1, 0x09, "TxMultCollCount"), 335 MIB_DESC(1, 0x0A, "TxLateCollCount"), 336 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 337 MIB_DESC(1, 0x0D, "TxPauseCount"), 338 MIB_DESC(1, 0x10, "TxDroppedPkts"), 339 MIB_DESC(2, 0x0E, "TxGoodBytes"), 340 }; 341 342 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 343 { 344 return __raw_readl(priv->gswip + (offset * 4)); 345 } 346 347 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 348 { 349 __raw_writel(val, priv->gswip + (offset * 4)); 350 } 351 352 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 353 u32 offset) 354 { 355 u32 val = gswip_switch_r(priv, offset); 356 357 val &= ~(clear); 358 val |= set; 359 gswip_switch_w(priv, val, offset); 360 } 361 362 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 363 u32 cleared) 364 { 365 u32 val; 366 367 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 368 (val & cleared) == 0, 20, 50000); 369 } 370 371 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 372 { 373 return __raw_readl(priv->mdio + (offset * 4)); 374 } 375 376 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 377 { 378 __raw_writel(val, priv->mdio + (offset * 4)); 379 } 380 381 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 382 u32 offset) 383 { 384 u32 val = gswip_mdio_r(priv, offset); 385 386 val &= ~(clear); 387 val |= set; 388 gswip_mdio_w(priv, val, offset); 389 } 390 391 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 392 { 393 return __raw_readl(priv->mii + (offset * 4)); 394 } 395 396 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 397 { 398 __raw_writel(val, priv->mii + (offset * 4)); 399 } 400 401 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 402 u32 offset) 403 { 404 u32 val = gswip_mii_r(priv, offset); 405 406 val &= ~(clear); 407 val |= set; 408 gswip_mii_w(priv, val, offset); 409 } 410 411 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 412 int port) 413 { 414 /* There's no MII_CFG register for the CPU port */ 415 if (!dsa_is_cpu_port(priv->ds, port)) 416 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); 417 } 418 419 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 420 int port) 421 { 422 switch (port) { 423 case 0: 424 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 425 break; 426 case 1: 427 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 428 break; 429 case 5: 430 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 431 break; 432 } 433 } 434 435 static int gswip_mdio_poll(struct gswip_priv *priv) 436 { 437 int cnt = 100; 438 439 while (likely(cnt--)) { 440 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 441 442 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 443 return 0; 444 usleep_range(20, 40); 445 } 446 447 return -ETIMEDOUT; 448 } 449 450 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 451 { 452 struct gswip_priv *priv = bus->priv; 453 int err; 454 455 err = gswip_mdio_poll(priv); 456 if (err) { 457 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 458 return err; 459 } 460 461 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 462 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 463 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 464 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 465 GSWIP_MDIO_CTRL); 466 467 return 0; 468 } 469 470 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 471 { 472 struct gswip_priv *priv = bus->priv; 473 int err; 474 475 err = gswip_mdio_poll(priv); 476 if (err) { 477 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 478 return err; 479 } 480 481 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 482 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 483 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 484 GSWIP_MDIO_CTRL); 485 486 err = gswip_mdio_poll(priv); 487 if (err) { 488 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 489 return err; 490 } 491 492 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 493 } 494 495 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np) 496 { 497 struct dsa_switch *ds = priv->ds; 498 499 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev); 500 if (!ds->slave_mii_bus) 501 return -ENOMEM; 502 503 ds->slave_mii_bus->priv = priv; 504 ds->slave_mii_bus->read = gswip_mdio_rd; 505 ds->slave_mii_bus->write = gswip_mdio_wr; 506 ds->slave_mii_bus->name = "lantiq,xrx200-mdio"; 507 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", 508 dev_name(priv->dev)); 509 ds->slave_mii_bus->parent = priv->dev; 510 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask; 511 512 return of_mdiobus_register(ds->slave_mii_bus, mdio_np); 513 } 514 515 static int gswip_pce_table_entry_read(struct gswip_priv *priv, 516 struct gswip_pce_table_entry *tbl) 517 { 518 int i; 519 int err; 520 u16 crtl; 521 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 522 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 523 524 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 525 GSWIP_PCE_TBL_CTRL_BAS); 526 if (err) 527 return err; 528 529 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 530 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 531 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 532 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 533 GSWIP_PCE_TBL_CTRL); 534 535 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 536 GSWIP_PCE_TBL_CTRL_BAS); 537 if (err) 538 return err; 539 540 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 541 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 542 543 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 544 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 545 546 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 547 548 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 549 550 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 551 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 552 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 553 554 return 0; 555 } 556 557 static int gswip_pce_table_entry_write(struct gswip_priv *priv, 558 struct gswip_pce_table_entry *tbl) 559 { 560 int i; 561 int err; 562 u16 crtl; 563 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 564 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 565 566 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 567 GSWIP_PCE_TBL_CTRL_BAS); 568 if (err) 569 return err; 570 571 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 572 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 573 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 574 tbl->table | addr_mode, 575 GSWIP_PCE_TBL_CTRL); 576 577 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 578 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 579 580 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 581 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 582 583 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 584 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 585 tbl->table | addr_mode, 586 GSWIP_PCE_TBL_CTRL); 587 588 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 589 590 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 591 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 592 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 593 if (tbl->type) 594 crtl |= GSWIP_PCE_TBL_CTRL_TYPE; 595 if (tbl->valid) 596 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 597 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 598 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 599 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 600 601 return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 602 GSWIP_PCE_TBL_CTRL_BAS); 603 } 604 605 /* Add the LAN port into a bridge with the CPU port by 606 * default. This prevents automatic forwarding of 607 * packages between the LAN ports when no explicit 608 * bridge is configured. 609 */ 610 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) 611 { 612 struct gswip_pce_table_entry vlan_active = {0,}; 613 struct gswip_pce_table_entry vlan_mapping = {0,}; 614 unsigned int cpu_port = priv->hw_info->cpu_port; 615 unsigned int max_ports = priv->hw_info->max_ports; 616 int err; 617 618 if (port >= max_ports) { 619 dev_err(priv->dev, "single port for %i supported\n", port); 620 return -EIO; 621 } 622 623 vlan_active.index = port + 1; 624 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 625 vlan_active.key[0] = 0; /* vid */ 626 vlan_active.val[0] = port + 1 /* fid */; 627 vlan_active.valid = add; 628 err = gswip_pce_table_entry_write(priv, &vlan_active); 629 if (err) { 630 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 631 return err; 632 } 633 634 if (!add) 635 return 0; 636 637 vlan_mapping.index = port + 1; 638 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 639 vlan_mapping.val[0] = 0 /* vid */; 640 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); 641 vlan_mapping.val[2] = 0; 642 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 643 if (err) { 644 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 645 return err; 646 } 647 648 return 0; 649 } 650 651 static int gswip_port_enable(struct dsa_switch *ds, int port, 652 struct phy_device *phydev) 653 { 654 struct gswip_priv *priv = ds->priv; 655 int err; 656 657 if (!dsa_is_user_port(ds, port)) 658 return 0; 659 660 if (!dsa_is_cpu_port(ds, port)) { 661 err = gswip_add_single_port_br(priv, port, true); 662 if (err) 663 return err; 664 } 665 666 /* RMON Counter Enable for port */ 667 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 668 669 /* enable port fetch/store dma & VLAN Modification */ 670 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 671 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 672 GSWIP_FDMA_PCTRLp(port)); 673 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 674 GSWIP_SDMA_PCTRLp(port)); 675 676 if (!dsa_is_cpu_port(ds, port)) { 677 u32 mdio_phy = 0; 678 679 if (phydev) 680 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; 681 682 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, 683 GSWIP_MDIO_PHYp(port)); 684 } 685 686 return 0; 687 } 688 689 static void gswip_port_disable(struct dsa_switch *ds, int port) 690 { 691 struct gswip_priv *priv = ds->priv; 692 693 if (!dsa_is_user_port(ds, port)) 694 return; 695 696 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 697 GSWIP_FDMA_PCTRLp(port)); 698 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 699 GSWIP_SDMA_PCTRLp(port)); 700 } 701 702 static int gswip_pce_load_microcode(struct gswip_priv *priv) 703 { 704 int i; 705 int err; 706 707 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 708 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 709 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 710 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 711 712 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { 713 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 714 gswip_switch_w(priv, gswip_pce_microcode[i].val_0, 715 GSWIP_PCE_TBL_VAL(0)); 716 gswip_switch_w(priv, gswip_pce_microcode[i].val_1, 717 GSWIP_PCE_TBL_VAL(1)); 718 gswip_switch_w(priv, gswip_pce_microcode[i].val_2, 719 GSWIP_PCE_TBL_VAL(2)); 720 gswip_switch_w(priv, gswip_pce_microcode[i].val_3, 721 GSWIP_PCE_TBL_VAL(3)); 722 723 /* start the table access: */ 724 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 725 GSWIP_PCE_TBL_CTRL); 726 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 727 GSWIP_PCE_TBL_CTRL_BAS); 728 if (err) 729 return err; 730 } 731 732 /* tell the switch that the microcode is loaded */ 733 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 734 GSWIP_PCE_GCTRL_0); 735 736 return 0; 737 } 738 739 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 740 bool vlan_filtering, 741 struct netlink_ext_ack *extack) 742 { 743 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 744 struct gswip_priv *priv = ds->priv; 745 746 /* Do not allow changing the VLAN filtering options while in bridge */ 747 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { 748 NL_SET_ERR_MSG_MOD(extack, 749 "Dynamic toggling of vlan_filtering not supported"); 750 return -EIO; 751 } 752 753 if (vlan_filtering) { 754 /* Use port based VLAN tag */ 755 gswip_switch_mask(priv, 756 GSWIP_PCE_VCTRL_VSR, 757 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 758 GSWIP_PCE_VCTRL_VEMR, 759 GSWIP_PCE_VCTRL(port)); 760 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 761 GSWIP_PCE_PCTRL_0p(port)); 762 } else { 763 /* Use port based VLAN tag */ 764 gswip_switch_mask(priv, 765 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 766 GSWIP_PCE_VCTRL_VEMR, 767 GSWIP_PCE_VCTRL_VSR, 768 GSWIP_PCE_VCTRL(port)); 769 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 770 GSWIP_PCE_PCTRL_0p(port)); 771 } 772 773 return 0; 774 } 775 776 static int gswip_setup(struct dsa_switch *ds) 777 { 778 struct gswip_priv *priv = ds->priv; 779 unsigned int cpu_port = priv->hw_info->cpu_port; 780 int i; 781 int err; 782 783 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 784 usleep_range(5000, 10000); 785 gswip_switch_w(priv, 0, GSWIP_SWRES); 786 787 /* disable port fetch/store dma on all ports */ 788 for (i = 0; i < priv->hw_info->max_ports; i++) { 789 gswip_port_disable(ds, i); 790 gswip_port_vlan_filtering(ds, i, false, NULL); 791 } 792 793 /* enable Switch */ 794 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 795 796 err = gswip_pce_load_microcode(priv); 797 if (err) { 798 dev_err(priv->dev, "writing PCE microcode failed, %i", err); 799 return err; 800 } 801 802 /* Default unknown Broadcast/Multicast/Unicast port maps */ 803 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); 804 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); 805 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); 806 807 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an 808 * interoperability problem with this auto polling mechanism because 809 * their status registers think that the link is in a different state 810 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set 811 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the 812 * auto polling state machine consider the link being negotiated with 813 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads 814 * to the switch port being completely dead (RX and TX are both not 815 * working). 816 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F 817 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes 818 * it would work fine for a few minutes to hours and then stop, on 819 * other device it would no traffic could be sent or received at all. 820 * Testing shows that when PHY auto polling is disabled these problems 821 * go away. 822 */ 823 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 824 825 /* Configure the MDIO Clock 2.5 MHz */ 826 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 827 828 /* Disable the xMII interface and clear it's isolation bit */ 829 for (i = 0; i < priv->hw_info->max_ports; i++) 830 gswip_mii_mask_cfg(priv, 831 GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE, 832 0, i); 833 834 /* enable special tag insertion on cpu port */ 835 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 836 GSWIP_FDMA_PCTRLp(cpu_port)); 837 838 /* accept special tag in ingress direction */ 839 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 840 GSWIP_PCE_PCTRL_0p(cpu_port)); 841 842 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 843 GSWIP_MAC_CTRL_2p(cpu_port)); 844 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8, GSWIP_MAC_FLEN); 845 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 846 GSWIP_BM_QUEUE_GCTRL); 847 848 /* VLAN aware Switching */ 849 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 850 851 /* Flush MAC Table */ 852 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 853 854 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 855 GSWIP_PCE_GCTRL_0_MTFL); 856 if (err) { 857 dev_err(priv->dev, "MAC flushing didn't finish\n"); 858 return err; 859 } 860 861 gswip_port_enable(ds, cpu_port, NULL); 862 863 ds->configure_vlan_while_not_filtering = false; 864 865 return 0; 866 } 867 868 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 869 int port, 870 enum dsa_tag_protocol mp) 871 { 872 return DSA_TAG_PROTO_GSWIP; 873 } 874 875 static int gswip_vlan_active_create(struct gswip_priv *priv, 876 struct net_device *bridge, 877 int fid, u16 vid) 878 { 879 struct gswip_pce_table_entry vlan_active = {0,}; 880 unsigned int max_ports = priv->hw_info->max_ports; 881 int idx = -1; 882 int err; 883 int i; 884 885 /* Look for a free slot */ 886 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 887 if (!priv->vlans[i].bridge) { 888 idx = i; 889 break; 890 } 891 } 892 893 if (idx == -1) 894 return -ENOSPC; 895 896 if (fid == -1) 897 fid = idx; 898 899 vlan_active.index = idx; 900 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 901 vlan_active.key[0] = vid; 902 vlan_active.val[0] = fid; 903 vlan_active.valid = true; 904 905 err = gswip_pce_table_entry_write(priv, &vlan_active); 906 if (err) { 907 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 908 return err; 909 } 910 911 priv->vlans[idx].bridge = bridge; 912 priv->vlans[idx].vid = vid; 913 priv->vlans[idx].fid = fid; 914 915 return idx; 916 } 917 918 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) 919 { 920 struct gswip_pce_table_entry vlan_active = {0,}; 921 int err; 922 923 vlan_active.index = idx; 924 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 925 vlan_active.valid = false; 926 err = gswip_pce_table_entry_write(priv, &vlan_active); 927 if (err) 928 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); 929 priv->vlans[idx].bridge = NULL; 930 931 return err; 932 } 933 934 static int gswip_vlan_add_unaware(struct gswip_priv *priv, 935 struct net_device *bridge, int port) 936 { 937 struct gswip_pce_table_entry vlan_mapping = {0,}; 938 unsigned int max_ports = priv->hw_info->max_ports; 939 unsigned int cpu_port = priv->hw_info->cpu_port; 940 bool active_vlan_created = false; 941 int idx = -1; 942 int i; 943 int err; 944 945 /* Check if there is already a page for this bridge */ 946 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 947 if (priv->vlans[i].bridge == bridge) { 948 idx = i; 949 break; 950 } 951 } 952 953 /* If this bridge is not programmed yet, add a Active VLAN table 954 * entry in a free slot and prepare the VLAN mapping table entry. 955 */ 956 if (idx == -1) { 957 idx = gswip_vlan_active_create(priv, bridge, -1, 0); 958 if (idx < 0) 959 return idx; 960 active_vlan_created = true; 961 962 vlan_mapping.index = idx; 963 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 964 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 965 vlan_mapping.val[0] = 0; 966 } else { 967 /* Read the existing VLAN mapping entry from the switch */ 968 vlan_mapping.index = idx; 969 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 970 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 971 if (err) { 972 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 973 err); 974 return err; 975 } 976 } 977 978 /* Update the VLAN mapping entry and write it to the switch */ 979 vlan_mapping.val[1] |= BIT(cpu_port); 980 vlan_mapping.val[1] |= BIT(port); 981 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 982 if (err) { 983 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 984 /* In case an Active VLAN was creaetd delete it again */ 985 if (active_vlan_created) 986 gswip_vlan_active_remove(priv, idx); 987 return err; 988 } 989 990 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 991 return 0; 992 } 993 994 static int gswip_vlan_add_aware(struct gswip_priv *priv, 995 struct net_device *bridge, int port, 996 u16 vid, bool untagged, 997 bool pvid) 998 { 999 struct gswip_pce_table_entry vlan_mapping = {0,}; 1000 unsigned int max_ports = priv->hw_info->max_ports; 1001 unsigned int cpu_port = priv->hw_info->cpu_port; 1002 bool active_vlan_created = false; 1003 int idx = -1; 1004 int fid = -1; 1005 int i; 1006 int err; 1007 1008 /* Check if there is already a page for this bridge */ 1009 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1010 if (priv->vlans[i].bridge == bridge) { 1011 if (fid != -1 && fid != priv->vlans[i].fid) 1012 dev_err(priv->dev, "one bridge with multiple flow ids\n"); 1013 fid = priv->vlans[i].fid; 1014 if (priv->vlans[i].vid == vid) { 1015 idx = i; 1016 break; 1017 } 1018 } 1019 } 1020 1021 /* If this bridge is not programmed yet, add a Active VLAN table 1022 * entry in a free slot and prepare the VLAN mapping table entry. 1023 */ 1024 if (idx == -1) { 1025 idx = gswip_vlan_active_create(priv, bridge, fid, vid); 1026 if (idx < 0) 1027 return idx; 1028 active_vlan_created = true; 1029 1030 vlan_mapping.index = idx; 1031 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1032 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 1033 vlan_mapping.val[0] = vid; 1034 } else { 1035 /* Read the existing VLAN mapping entry from the switch */ 1036 vlan_mapping.index = idx; 1037 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1038 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1039 if (err) { 1040 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 1041 err); 1042 return err; 1043 } 1044 } 1045 1046 vlan_mapping.val[0] = vid; 1047 /* Update the VLAN mapping entry and write it to the switch */ 1048 vlan_mapping.val[1] |= BIT(cpu_port); 1049 vlan_mapping.val[2] |= BIT(cpu_port); 1050 vlan_mapping.val[1] |= BIT(port); 1051 if (untagged) 1052 vlan_mapping.val[2] &= ~BIT(port); 1053 else 1054 vlan_mapping.val[2] |= BIT(port); 1055 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1056 if (err) { 1057 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1058 /* In case an Active VLAN was creaetd delete it again */ 1059 if (active_vlan_created) 1060 gswip_vlan_active_remove(priv, idx); 1061 return err; 1062 } 1063 1064 if (pvid) 1065 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 1066 1067 return 0; 1068 } 1069 1070 static int gswip_vlan_remove(struct gswip_priv *priv, 1071 struct net_device *bridge, int port, 1072 u16 vid, bool pvid, bool vlan_aware) 1073 { 1074 struct gswip_pce_table_entry vlan_mapping = {0,}; 1075 unsigned int max_ports = priv->hw_info->max_ports; 1076 unsigned int cpu_port = priv->hw_info->cpu_port; 1077 int idx = -1; 1078 int i; 1079 int err; 1080 1081 /* Check if there is already a page for this bridge */ 1082 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1083 if (priv->vlans[i].bridge == bridge && 1084 (!vlan_aware || priv->vlans[i].vid == vid)) { 1085 idx = i; 1086 break; 1087 } 1088 } 1089 1090 if (idx == -1) { 1091 dev_err(priv->dev, "bridge to leave does not exists\n"); 1092 return -ENOENT; 1093 } 1094 1095 vlan_mapping.index = idx; 1096 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1097 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1098 if (err) { 1099 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); 1100 return err; 1101 } 1102 1103 vlan_mapping.val[1] &= ~BIT(port); 1104 vlan_mapping.val[2] &= ~BIT(port); 1105 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1106 if (err) { 1107 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1108 return err; 1109 } 1110 1111 /* In case all ports are removed from the bridge, remove the VLAN */ 1112 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { 1113 err = gswip_vlan_active_remove(priv, idx); 1114 if (err) { 1115 dev_err(priv->dev, "failed to write active VLAN: %d\n", 1116 err); 1117 return err; 1118 } 1119 } 1120 1121 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 1122 if (pvid) 1123 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1124 1125 return 0; 1126 } 1127 1128 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, 1129 struct net_device *bridge) 1130 { 1131 struct gswip_priv *priv = ds->priv; 1132 int err; 1133 1134 /* When the bridge uses VLAN filtering we have to configure VLAN 1135 * specific bridges. No bridge is configured here. 1136 */ 1137 if (!br_vlan_enabled(bridge)) { 1138 err = gswip_vlan_add_unaware(priv, bridge, port); 1139 if (err) 1140 return err; 1141 priv->port_vlan_filter &= ~BIT(port); 1142 } else { 1143 priv->port_vlan_filter |= BIT(port); 1144 } 1145 return gswip_add_single_port_br(priv, port, false); 1146 } 1147 1148 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, 1149 struct net_device *bridge) 1150 { 1151 struct gswip_priv *priv = ds->priv; 1152 1153 gswip_add_single_port_br(priv, port, true); 1154 1155 /* When the bridge uses VLAN filtering we have to configure VLAN 1156 * specific bridges. No bridge is configured here. 1157 */ 1158 if (!br_vlan_enabled(bridge)) 1159 gswip_vlan_remove(priv, bridge, port, 0, true, false); 1160 } 1161 1162 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, 1163 const struct switchdev_obj_port_vlan *vlan, 1164 struct netlink_ext_ack *extack) 1165 { 1166 struct gswip_priv *priv = ds->priv; 1167 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1168 unsigned int max_ports = priv->hw_info->max_ports; 1169 int pos = max_ports; 1170 int i, idx = -1; 1171 1172 /* We only support VLAN filtering on bridges */ 1173 if (!dsa_is_cpu_port(ds, port) && !bridge) 1174 return -EOPNOTSUPP; 1175 1176 /* Check if there is already a page for this VLAN */ 1177 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1178 if (priv->vlans[i].bridge == bridge && 1179 priv->vlans[i].vid == vlan->vid) { 1180 idx = i; 1181 break; 1182 } 1183 } 1184 1185 /* If this VLAN is not programmed yet, we have to reserve 1186 * one entry in the VLAN table. Make sure we start at the 1187 * next position round. 1188 */ 1189 if (idx == -1) { 1190 /* Look for a free slot */ 1191 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { 1192 if (!priv->vlans[pos].bridge) { 1193 idx = pos; 1194 pos++; 1195 break; 1196 } 1197 } 1198 1199 if (idx == -1) { 1200 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table"); 1201 return -ENOSPC; 1202 } 1203 } 1204 1205 return 0; 1206 } 1207 1208 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, 1209 const struct switchdev_obj_port_vlan *vlan, 1210 struct netlink_ext_ack *extack) 1211 { 1212 struct gswip_priv *priv = ds->priv; 1213 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1214 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1215 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1216 int err; 1217 1218 err = gswip_port_vlan_prepare(ds, port, vlan, extack); 1219 if (err) 1220 return err; 1221 1222 /* We have to receive all packets on the CPU port and should not 1223 * do any VLAN filtering here. This is also called with bridge 1224 * NULL and then we do not know for which bridge to configure 1225 * this. 1226 */ 1227 if (dsa_is_cpu_port(ds, port)) 1228 return 0; 1229 1230 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, 1231 untagged, pvid); 1232 } 1233 1234 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, 1235 const struct switchdev_obj_port_vlan *vlan) 1236 { 1237 struct gswip_priv *priv = ds->priv; 1238 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1239 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1240 1241 /* We have to receive all packets on the CPU port and should not 1242 * do any VLAN filtering here. This is also called with bridge 1243 * NULL and then we do not know for which bridge to configure 1244 * this. 1245 */ 1246 if (dsa_is_cpu_port(ds, port)) 1247 return 0; 1248 1249 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); 1250 } 1251 1252 static void gswip_port_fast_age(struct dsa_switch *ds, int port) 1253 { 1254 struct gswip_priv *priv = ds->priv; 1255 struct gswip_pce_table_entry mac_bridge = {0,}; 1256 int i; 1257 int err; 1258 1259 for (i = 0; i < 2048; i++) { 1260 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1261 mac_bridge.index = i; 1262 1263 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1264 if (err) { 1265 dev_err(priv->dev, "failed to read mac bridge: %d\n", 1266 err); 1267 return; 1268 } 1269 1270 if (!mac_bridge.valid) 1271 continue; 1272 1273 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) 1274 continue; 1275 1276 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) 1277 continue; 1278 1279 mac_bridge.valid = false; 1280 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1281 if (err) { 1282 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1283 err); 1284 return; 1285 } 1286 } 1287 } 1288 1289 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1290 { 1291 struct gswip_priv *priv = ds->priv; 1292 u32 stp_state; 1293 1294 switch (state) { 1295 case BR_STATE_DISABLED: 1296 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1297 GSWIP_SDMA_PCTRLp(port)); 1298 return; 1299 case BR_STATE_BLOCKING: 1300 case BR_STATE_LISTENING: 1301 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; 1302 break; 1303 case BR_STATE_LEARNING: 1304 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; 1305 break; 1306 case BR_STATE_FORWARDING: 1307 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; 1308 break; 1309 default: 1310 dev_err(priv->dev, "invalid STP state: %d\n", state); 1311 return; 1312 } 1313 1314 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1315 GSWIP_SDMA_PCTRLp(port)); 1316 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1317 GSWIP_PCE_PCTRL_0p(port)); 1318 } 1319 1320 static int gswip_port_fdb(struct dsa_switch *ds, int port, 1321 const unsigned char *addr, u16 vid, bool add) 1322 { 1323 struct gswip_priv *priv = ds->priv; 1324 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1325 struct gswip_pce_table_entry mac_bridge = {0,}; 1326 unsigned int cpu_port = priv->hw_info->cpu_port; 1327 int fid = -1; 1328 int i; 1329 int err; 1330 1331 if (!bridge) 1332 return -EINVAL; 1333 1334 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) { 1335 if (priv->vlans[i].bridge == bridge) { 1336 fid = priv->vlans[i].fid; 1337 break; 1338 } 1339 } 1340 1341 if (fid == -1) { 1342 dev_err(priv->dev, "Port not part of a bridge\n"); 1343 return -EINVAL; 1344 } 1345 1346 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1347 mac_bridge.key_mode = true; 1348 mac_bridge.key[0] = addr[5] | (addr[4] << 8); 1349 mac_bridge.key[1] = addr[3] | (addr[2] << 8); 1350 mac_bridge.key[2] = addr[1] | (addr[0] << 8); 1351 mac_bridge.key[3] = fid; 1352 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ 1353 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; 1354 mac_bridge.valid = add; 1355 1356 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1357 if (err) 1358 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); 1359 1360 return err; 1361 } 1362 1363 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, 1364 const unsigned char *addr, u16 vid) 1365 { 1366 return gswip_port_fdb(ds, port, addr, vid, true); 1367 } 1368 1369 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, 1370 const unsigned char *addr, u16 vid) 1371 { 1372 return gswip_port_fdb(ds, port, addr, vid, false); 1373 } 1374 1375 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, 1376 dsa_fdb_dump_cb_t *cb, void *data) 1377 { 1378 struct gswip_priv *priv = ds->priv; 1379 struct gswip_pce_table_entry mac_bridge = {0,}; 1380 unsigned char addr[6]; 1381 int i; 1382 int err; 1383 1384 for (i = 0; i < 2048; i++) { 1385 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1386 mac_bridge.index = i; 1387 1388 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1389 if (err) { 1390 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1391 err); 1392 return err; 1393 } 1394 1395 if (!mac_bridge.valid) 1396 continue; 1397 1398 addr[5] = mac_bridge.key[0] & 0xff; 1399 addr[4] = (mac_bridge.key[0] >> 8) & 0xff; 1400 addr[3] = mac_bridge.key[1] & 0xff; 1401 addr[2] = (mac_bridge.key[1] >> 8) & 0xff; 1402 addr[1] = mac_bridge.key[2] & 0xff; 1403 addr[0] = (mac_bridge.key[2] >> 8) & 0xff; 1404 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { 1405 if (mac_bridge.val[0] & BIT(port)) 1406 cb(addr, 0, true, data); 1407 } else { 1408 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) 1409 cb(addr, 0, false, data); 1410 } 1411 } 1412 return 0; 1413 } 1414 1415 static void gswip_phylink_validate(struct dsa_switch *ds, int port, 1416 unsigned long *supported, 1417 struct phylink_link_state *state) 1418 { 1419 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1420 1421 switch (port) { 1422 case 0: 1423 case 1: 1424 if (!phy_interface_mode_is_rgmii(state->interface) && 1425 state->interface != PHY_INTERFACE_MODE_MII && 1426 state->interface != PHY_INTERFACE_MODE_REVMII && 1427 state->interface != PHY_INTERFACE_MODE_RMII) 1428 goto unsupported; 1429 break; 1430 case 2: 1431 case 3: 1432 case 4: 1433 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 1434 goto unsupported; 1435 break; 1436 case 5: 1437 if (!phy_interface_mode_is_rgmii(state->interface) && 1438 state->interface != PHY_INTERFACE_MODE_INTERNAL) 1439 goto unsupported; 1440 break; 1441 default: 1442 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1443 dev_err(ds->dev, "Unsupported port: %i\n", port); 1444 return; 1445 } 1446 1447 /* Allow all the expected bits */ 1448 phylink_set(mask, Autoneg); 1449 phylink_set_port_modes(mask); 1450 phylink_set(mask, Pause); 1451 phylink_set(mask, Asym_Pause); 1452 1453 /* With the exclusion of MII, Reverse MII and Reduced MII, we 1454 * support Gigabit, including Half duplex 1455 */ 1456 if (state->interface != PHY_INTERFACE_MODE_MII && 1457 state->interface != PHY_INTERFACE_MODE_REVMII && 1458 state->interface != PHY_INTERFACE_MODE_RMII) { 1459 phylink_set(mask, 1000baseT_Full); 1460 phylink_set(mask, 1000baseT_Half); 1461 } 1462 1463 phylink_set(mask, 10baseT_Half); 1464 phylink_set(mask, 10baseT_Full); 1465 phylink_set(mask, 100baseT_Half); 1466 phylink_set(mask, 100baseT_Full); 1467 1468 bitmap_and(supported, supported, mask, 1469 __ETHTOOL_LINK_MODE_MASK_NBITS); 1470 bitmap_and(state->advertising, state->advertising, mask, 1471 __ETHTOOL_LINK_MODE_MASK_NBITS); 1472 return; 1473 1474 unsupported: 1475 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1476 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", 1477 phy_modes(state->interface), port); 1478 return; 1479 } 1480 1481 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) 1482 { 1483 u32 mdio_phy; 1484 1485 if (link) 1486 mdio_phy = GSWIP_MDIO_PHY_LINK_UP; 1487 else 1488 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN; 1489 1490 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy, 1491 GSWIP_MDIO_PHYp(port)); 1492 } 1493 1494 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, 1495 phy_interface_t interface) 1496 { 1497 u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0; 1498 1499 switch (speed) { 1500 case SPEED_10: 1501 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10; 1502 1503 if (interface == PHY_INTERFACE_MODE_RMII) 1504 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1505 else 1506 mii_cfg = GSWIP_MII_CFG_RATE_M2P5; 1507 1508 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1509 break; 1510 1511 case SPEED_100: 1512 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100; 1513 1514 if (interface == PHY_INTERFACE_MODE_RMII) 1515 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1516 else 1517 mii_cfg = GSWIP_MII_CFG_RATE_M25; 1518 1519 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1520 break; 1521 1522 case SPEED_1000: 1523 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1; 1524 1525 mii_cfg = GSWIP_MII_CFG_RATE_M125; 1526 1527 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII; 1528 break; 1529 } 1530 1531 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy, 1532 GSWIP_MDIO_PHYp(port)); 1533 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); 1534 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0, 1535 GSWIP_MAC_CTRL_0p(port)); 1536 } 1537 1538 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) 1539 { 1540 u32 mac_ctrl_0, mdio_phy; 1541 1542 if (duplex == DUPLEX_FULL) { 1543 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN; 1544 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN; 1545 } else { 1546 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS; 1547 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS; 1548 } 1549 1550 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0, 1551 GSWIP_MAC_CTRL_0p(port)); 1552 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy, 1553 GSWIP_MDIO_PHYp(port)); 1554 } 1555 1556 static void gswip_port_set_pause(struct gswip_priv *priv, int port, 1557 bool tx_pause, bool rx_pause) 1558 { 1559 u32 mac_ctrl_0, mdio_phy; 1560 1561 if (tx_pause && rx_pause) { 1562 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX; 1563 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1564 GSWIP_MDIO_PHY_FCONRX_EN; 1565 } else if (tx_pause) { 1566 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX; 1567 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1568 GSWIP_MDIO_PHY_FCONRX_DIS; 1569 } else if (rx_pause) { 1570 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX; 1571 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1572 GSWIP_MDIO_PHY_FCONRX_EN; 1573 } else { 1574 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE; 1575 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1576 GSWIP_MDIO_PHY_FCONRX_DIS; 1577 } 1578 1579 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK, 1580 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); 1581 gswip_mdio_mask(priv, 1582 GSWIP_MDIO_PHY_FCONTX_MASK | 1583 GSWIP_MDIO_PHY_FCONRX_MASK, 1584 mdio_phy, GSWIP_MDIO_PHYp(port)); 1585 } 1586 1587 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, 1588 unsigned int mode, 1589 const struct phylink_link_state *state) 1590 { 1591 struct gswip_priv *priv = ds->priv; 1592 u32 miicfg = 0; 1593 1594 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 1595 1596 switch (state->interface) { 1597 case PHY_INTERFACE_MODE_MII: 1598 case PHY_INTERFACE_MODE_INTERNAL: 1599 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 1600 break; 1601 case PHY_INTERFACE_MODE_REVMII: 1602 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 1603 break; 1604 case PHY_INTERFACE_MODE_RMII: 1605 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 1606 1607 /* Configure the RMII clock as output: */ 1608 miicfg |= GSWIP_MII_CFG_RMII_CLK; 1609 break; 1610 case PHY_INTERFACE_MODE_RGMII: 1611 case PHY_INTERFACE_MODE_RGMII_ID: 1612 case PHY_INTERFACE_MODE_RGMII_RXID: 1613 case PHY_INTERFACE_MODE_RGMII_TXID: 1614 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 1615 break; 1616 default: 1617 dev_err(ds->dev, 1618 "Unsupported interface: %d\n", state->interface); 1619 return; 1620 } 1621 1622 gswip_mii_mask_cfg(priv, 1623 GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK | 1624 GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS, 1625 miicfg, port); 1626 1627 switch (state->interface) { 1628 case PHY_INTERFACE_MODE_RGMII_ID: 1629 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 1630 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1631 break; 1632 case PHY_INTERFACE_MODE_RGMII_RXID: 1633 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1634 break; 1635 case PHY_INTERFACE_MODE_RGMII_TXID: 1636 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 1637 break; 1638 default: 1639 break; 1640 } 1641 } 1642 1643 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, 1644 unsigned int mode, 1645 phy_interface_t interface) 1646 { 1647 struct gswip_priv *priv = ds->priv; 1648 1649 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 1650 1651 if (!dsa_is_cpu_port(ds, port)) 1652 gswip_port_set_link(priv, port, false); 1653 } 1654 1655 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, 1656 unsigned int mode, 1657 phy_interface_t interface, 1658 struct phy_device *phydev, 1659 int speed, int duplex, 1660 bool tx_pause, bool rx_pause) 1661 { 1662 struct gswip_priv *priv = ds->priv; 1663 1664 if (!dsa_is_cpu_port(ds, port)) { 1665 gswip_port_set_link(priv, port, true); 1666 gswip_port_set_speed(priv, port, speed, interface); 1667 gswip_port_set_duplex(priv, port, duplex); 1668 gswip_port_set_pause(priv, port, tx_pause, rx_pause); 1669 } 1670 1671 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1672 } 1673 1674 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1675 uint8_t *data) 1676 { 1677 int i; 1678 1679 if (stringset != ETH_SS_STATS) 1680 return; 1681 1682 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 1683 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name, 1684 ETH_GSTRING_LEN); 1685 } 1686 1687 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1688 u32 index) 1689 { 1690 u32 result; 1691 int err; 1692 1693 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1694 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1695 GSWIP_BM_RAM_CTRL_OPMOD, 1696 table | GSWIP_BM_RAM_CTRL_BAS, 1697 GSWIP_BM_RAM_CTRL); 1698 1699 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1700 GSWIP_BM_RAM_CTRL_BAS); 1701 if (err) { 1702 dev_err(priv->dev, "timeout while reading table: %u, index: %u", 1703 table, index); 1704 return 0; 1705 } 1706 1707 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1708 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1709 1710 return result; 1711 } 1712 1713 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 1714 uint64_t *data) 1715 { 1716 struct gswip_priv *priv = ds->priv; 1717 const struct gswip_rmon_cnt_desc *rmon_cnt; 1718 int i; 1719 u64 high; 1720 1721 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 1722 rmon_cnt = &gswip_rmon_cnt[i]; 1723 1724 data[i] = gswip_bcm_ram_entry_read(priv, port, 1725 rmon_cnt->offset); 1726 if (rmon_cnt->size == 2) { 1727 high = gswip_bcm_ram_entry_read(priv, port, 1728 rmon_cnt->offset + 1); 1729 data[i] |= high << 32; 1730 } 1731 } 1732 } 1733 1734 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 1735 { 1736 if (sset != ETH_SS_STATS) 1737 return 0; 1738 1739 return ARRAY_SIZE(gswip_rmon_cnt); 1740 } 1741 1742 static const struct dsa_switch_ops gswip_switch_ops = { 1743 .get_tag_protocol = gswip_get_tag_protocol, 1744 .setup = gswip_setup, 1745 .port_enable = gswip_port_enable, 1746 .port_disable = gswip_port_disable, 1747 .port_bridge_join = gswip_port_bridge_join, 1748 .port_bridge_leave = gswip_port_bridge_leave, 1749 .port_fast_age = gswip_port_fast_age, 1750 .port_vlan_filtering = gswip_port_vlan_filtering, 1751 .port_vlan_add = gswip_port_vlan_add, 1752 .port_vlan_del = gswip_port_vlan_del, 1753 .port_stp_state_set = gswip_port_stp_state_set, 1754 .port_fdb_add = gswip_port_fdb_add, 1755 .port_fdb_del = gswip_port_fdb_del, 1756 .port_fdb_dump = gswip_port_fdb_dump, 1757 .phylink_validate = gswip_phylink_validate, 1758 .phylink_mac_config = gswip_phylink_mac_config, 1759 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1760 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1761 .get_strings = gswip_get_strings, 1762 .get_ethtool_stats = gswip_get_ethtool_stats, 1763 .get_sset_count = gswip_get_sset_count, 1764 }; 1765 1766 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 1767 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 1768 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 1769 }; 1770 1771 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 1772 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 1773 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 1774 }; 1775 1776 static const struct xway_gphy_match_data xrx300_gphy_data = { 1777 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 1778 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 1779 }; 1780 1781 static const struct of_device_id xway_gphy_match[] = { 1782 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 1783 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 1784 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 1785 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 1786 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 1787 {}, 1788 }; 1789 1790 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 1791 { 1792 struct device *dev = priv->dev; 1793 const struct firmware *fw; 1794 void *fw_addr; 1795 dma_addr_t dma_addr; 1796 dma_addr_t dev_addr; 1797 size_t size; 1798 int ret; 1799 1800 ret = clk_prepare_enable(gphy_fw->clk_gate); 1801 if (ret) 1802 return ret; 1803 1804 reset_control_assert(gphy_fw->reset); 1805 1806 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 1807 if (ret) { 1808 dev_err(dev, "failed to load firmware: %s, error: %i\n", 1809 gphy_fw->fw_name, ret); 1810 return ret; 1811 } 1812 1813 /* GPHY cores need the firmware code in a persistent and contiguous 1814 * memory area with a 16 kB boundary aligned start address. 1815 */ 1816 size = fw->size + XRX200_GPHY_FW_ALIGN; 1817 1818 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 1819 if (fw_addr) { 1820 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 1821 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 1822 memcpy(fw_addr, fw->data, fw->size); 1823 } else { 1824 dev_err(dev, "failed to alloc firmware memory\n"); 1825 release_firmware(fw); 1826 return -ENOMEM; 1827 } 1828 1829 release_firmware(fw); 1830 1831 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 1832 if (ret) 1833 return ret; 1834 1835 reset_control_deassert(gphy_fw->reset); 1836 1837 return ret; 1838 } 1839 1840 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 1841 struct gswip_gphy_fw *gphy_fw, 1842 struct device_node *gphy_fw_np, int i) 1843 { 1844 struct device *dev = priv->dev; 1845 u32 gphy_mode; 1846 int ret; 1847 char gphyname[10]; 1848 1849 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 1850 1851 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 1852 if (IS_ERR(gphy_fw->clk_gate)) { 1853 dev_err(dev, "Failed to lookup gate clock\n"); 1854 return PTR_ERR(gphy_fw->clk_gate); 1855 } 1856 1857 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 1858 if (ret) 1859 return ret; 1860 1861 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 1862 /* Default to GE mode */ 1863 if (ret) 1864 gphy_mode = GPHY_MODE_GE; 1865 1866 switch (gphy_mode) { 1867 case GPHY_MODE_FE: 1868 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 1869 break; 1870 case GPHY_MODE_GE: 1871 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 1872 break; 1873 default: 1874 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); 1875 return -EINVAL; 1876 } 1877 1878 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 1879 if (IS_ERR(gphy_fw->reset)) { 1880 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER) 1881 dev_err(dev, "Failed to lookup gphy reset\n"); 1882 return PTR_ERR(gphy_fw->reset); 1883 } 1884 1885 return gswip_gphy_fw_load(priv, gphy_fw); 1886 } 1887 1888 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 1889 struct gswip_gphy_fw *gphy_fw) 1890 { 1891 int ret; 1892 1893 /* check if the device was fully probed */ 1894 if (!gphy_fw->fw_name) 1895 return; 1896 1897 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 1898 if (ret) 1899 dev_err(priv->dev, "can not reset GPHY FW pointer"); 1900 1901 clk_disable_unprepare(gphy_fw->clk_gate); 1902 1903 reset_control_put(gphy_fw->reset); 1904 } 1905 1906 static int gswip_gphy_fw_list(struct gswip_priv *priv, 1907 struct device_node *gphy_fw_list_np, u32 version) 1908 { 1909 struct device *dev = priv->dev; 1910 struct device_node *gphy_fw_np; 1911 const struct of_device_id *match; 1912 int err; 1913 int i = 0; 1914 1915 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 1916 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 1917 * needs a different GPHY firmware. 1918 */ 1919 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 1920 switch (version) { 1921 case GSWIP_VERSION_2_0: 1922 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 1923 break; 1924 case GSWIP_VERSION_2_1: 1925 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 1926 break; 1927 default: 1928 dev_err(dev, "unknown GSWIP version: 0x%x", version); 1929 return -ENOENT; 1930 } 1931 } 1932 1933 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 1934 if (match && match->data) 1935 priv->gphy_fw_name_cfg = match->data; 1936 1937 if (!priv->gphy_fw_name_cfg) { 1938 dev_err(dev, "GPHY compatible type not supported"); 1939 return -ENOENT; 1940 } 1941 1942 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 1943 if (!priv->num_gphy_fw) 1944 return -ENOENT; 1945 1946 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 1947 "lantiq,rcu"); 1948 if (IS_ERR(priv->rcu_regmap)) 1949 return PTR_ERR(priv->rcu_regmap); 1950 1951 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 1952 sizeof(*priv->gphy_fw), 1953 GFP_KERNEL | __GFP_ZERO); 1954 if (!priv->gphy_fw) 1955 return -ENOMEM; 1956 1957 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 1958 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 1959 gphy_fw_np, i); 1960 if (err) 1961 goto remove_gphy; 1962 i++; 1963 } 1964 1965 /* The standalone PHY11G requires 300ms to be fully 1966 * initialized and ready for any MDIO communication after being 1967 * taken out of reset. For the SoC-internal GPHY variant there 1968 * is no (known) documentation for the minimum time after a 1969 * reset. Use the same value as for the standalone variant as 1970 * some users have reported internal PHYs not being detected 1971 * without any delay. 1972 */ 1973 msleep(300); 1974 1975 return 0; 1976 1977 remove_gphy: 1978 for (i = 0; i < priv->num_gphy_fw; i++) 1979 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1980 return err; 1981 } 1982 1983 static int gswip_probe(struct platform_device *pdev) 1984 { 1985 struct gswip_priv *priv; 1986 struct device_node *mdio_np, *gphy_fw_np; 1987 struct device *dev = &pdev->dev; 1988 int err; 1989 int i; 1990 u32 version; 1991 1992 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1993 if (!priv) 1994 return -ENOMEM; 1995 1996 priv->gswip = devm_platform_ioremap_resource(pdev, 0); 1997 if (IS_ERR(priv->gswip)) 1998 return PTR_ERR(priv->gswip); 1999 2000 priv->mdio = devm_platform_ioremap_resource(pdev, 1); 2001 if (IS_ERR(priv->mdio)) 2002 return PTR_ERR(priv->mdio); 2003 2004 priv->mii = devm_platform_ioremap_resource(pdev, 2); 2005 if (IS_ERR(priv->mii)) 2006 return PTR_ERR(priv->mii); 2007 2008 priv->hw_info = of_device_get_match_data(dev); 2009 if (!priv->hw_info) 2010 return -EINVAL; 2011 2012 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 2013 if (!priv->ds) 2014 return -ENOMEM; 2015 2016 priv->ds->dev = dev; 2017 priv->ds->num_ports = priv->hw_info->max_ports; 2018 priv->ds->priv = priv; 2019 priv->ds->ops = &gswip_switch_ops; 2020 priv->dev = dev; 2021 version = gswip_switch_r(priv, GSWIP_VERSION); 2022 2023 /* bring up the mdio bus */ 2024 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 2025 if (gphy_fw_np) { 2026 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 2027 of_node_put(gphy_fw_np); 2028 if (err) { 2029 dev_err(dev, "gphy fw probe failed\n"); 2030 return err; 2031 } 2032 } 2033 2034 /* bring up the mdio bus */ 2035 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio"); 2036 if (mdio_np) { 2037 err = gswip_mdio(priv, mdio_np); 2038 if (err) { 2039 dev_err(dev, "mdio probe failed\n"); 2040 goto put_mdio_node; 2041 } 2042 } 2043 2044 err = dsa_register_switch(priv->ds); 2045 if (err) { 2046 dev_err(dev, "dsa switch register failed: %i\n", err); 2047 goto mdio_bus; 2048 } 2049 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { 2050 dev_err(dev, "wrong CPU port defined, HW only supports port: %i", 2051 priv->hw_info->cpu_port); 2052 err = -EINVAL; 2053 goto disable_switch; 2054 } 2055 2056 platform_set_drvdata(pdev, priv); 2057 2058 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 2059 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, 2060 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); 2061 return 0; 2062 2063 disable_switch: 2064 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2065 dsa_unregister_switch(priv->ds); 2066 mdio_bus: 2067 if (mdio_np) 2068 mdiobus_unregister(priv->ds->slave_mii_bus); 2069 put_mdio_node: 2070 of_node_put(mdio_np); 2071 for (i = 0; i < priv->num_gphy_fw; i++) 2072 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2073 return err; 2074 } 2075 2076 static int gswip_remove(struct platform_device *pdev) 2077 { 2078 struct gswip_priv *priv = platform_get_drvdata(pdev); 2079 int i; 2080 2081 /* disable the switch */ 2082 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2083 2084 dsa_unregister_switch(priv->ds); 2085 2086 if (priv->ds->slave_mii_bus) { 2087 mdiobus_unregister(priv->ds->slave_mii_bus); 2088 of_node_put(priv->ds->slave_mii_bus->dev.of_node); 2089 } 2090 2091 for (i = 0; i < priv->num_gphy_fw; i++) 2092 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2093 2094 return 0; 2095 } 2096 2097 static const struct gswip_hw_info gswip_xrx200 = { 2098 .max_ports = 7, 2099 .cpu_port = 6, 2100 }; 2101 2102 static const struct of_device_id gswip_of_match[] = { 2103 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 2104 {}, 2105 }; 2106 MODULE_DEVICE_TABLE(of, gswip_of_match); 2107 2108 static struct platform_driver gswip_driver = { 2109 .probe = gswip_probe, 2110 .remove = gswip_remove, 2111 .driver = { 2112 .name = "gswip", 2113 .of_match_table = gswip_of_match, 2114 }, 2115 }; 2116 2117 module_platform_driver(gswip_driver); 2118 2119 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 2120 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 2121 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 2122 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 2123 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 2124 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 2125 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 2126 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 2127 MODULE_LICENSE("GPL v2"); 2128