1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/etherdevice.h> 12 #include <linux/firmware.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <linux/iopoll.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/module.h> 18 #include <linux/of_mdio.h> 19 #include <linux/of_net.h> 20 #include <linux/of_platform.h> 21 #include <linux/phy.h> 22 #include <linux/phylink.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 #include <linux/reset.h> 26 #include <net/dsa.h> 27 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 28 29 #include "lantiq_pce.h" 30 31 /* GSWIP MDIO Registers */ 32 #define GSWIP_MDIO_GLOB 0x00 33 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 34 #define GSWIP_MDIO_CTRL 0x08 35 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 36 #define GSWIP_MDIO_CTRL_RD BIT(11) 37 #define GSWIP_MDIO_CTRL_WR BIT(10) 38 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 39 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 40 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 41 #define GSWIP_MDIO_READ 0x09 42 #define GSWIP_MDIO_WRITE 0x0A 43 #define GSWIP_MDIO_MDC_CFG0 0x0B 44 #define GSWIP_MDIO_MDC_CFG1 0x0C 45 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 46 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 47 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 48 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 49 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 50 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 51 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 52 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 53 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 54 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 55 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 56 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 57 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 58 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 59 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 60 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 61 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 62 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 63 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 64 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 65 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 66 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 67 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 68 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 69 GSWIP_MDIO_PHY_FCONRX_MASK | \ 70 GSWIP_MDIO_PHY_FCONTX_MASK | \ 71 GSWIP_MDIO_PHY_LINK_MASK | \ 72 GSWIP_MDIO_PHY_SPEED_MASK | \ 73 GSWIP_MDIO_PHY_FDUP_MASK) 74 75 /* GSWIP MII Registers */ 76 #define GSWIP_MII_CFG0 0x00 77 #define GSWIP_MII_CFG1 0x02 78 #define GSWIP_MII_CFG5 0x04 79 #define GSWIP_MII_CFG_EN BIT(14) 80 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 81 #define GSWIP_MII_CFG_MODE_MIIP 0x0 82 #define GSWIP_MII_CFG_MODE_MIIM 0x1 83 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 84 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 85 #define GSWIP_MII_CFG_MODE_RGMII 0x4 86 #define GSWIP_MII_CFG_MODE_MASK 0xf 87 #define GSWIP_MII_CFG_RATE_M2P5 0x00 88 #define GSWIP_MII_CFG_RATE_M25 0x10 89 #define GSWIP_MII_CFG_RATE_M125 0x20 90 #define GSWIP_MII_CFG_RATE_M50 0x30 91 #define GSWIP_MII_CFG_RATE_AUTO 0x40 92 #define GSWIP_MII_CFG_RATE_MASK 0x70 93 #define GSWIP_MII_PCDU0 0x01 94 #define GSWIP_MII_PCDU1 0x03 95 #define GSWIP_MII_PCDU5 0x05 96 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 97 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 98 99 /* GSWIP Core Registers */ 100 #define GSWIP_SWRES 0x000 101 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 102 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 103 #define GSWIP_VERSION 0x013 104 #define GSWIP_VERSION_REV_SHIFT 0 105 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 106 #define GSWIP_VERSION_MOD_SHIFT 8 107 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 108 #define GSWIP_VERSION_2_0 0x100 109 #define GSWIP_VERSION_2_1 0x021 110 #define GSWIP_VERSION_2_2 0x122 111 #define GSWIP_VERSION_2_2_ETC 0x022 112 113 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 114 #define GSWIP_BM_RAM_ADDR 0x044 115 #define GSWIP_BM_RAM_CTRL 0x045 116 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 117 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 118 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 119 #define GSWIP_BM_QUEUE_GCTRL 0x04A 120 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 121 /* buffer management Port Configuration Register */ 122 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 123 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 124 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 125 /* buffer management Port Control Register */ 126 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 127 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 128 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 129 130 /* PCE */ 131 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 132 #define GSWIP_PCE_TBL_MASK 0x448 133 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 134 #define GSWIP_PCE_TBL_ADDR 0x44E 135 #define GSWIP_PCE_TBL_CTRL 0x44F 136 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 137 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 138 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 139 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 140 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 141 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 142 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 143 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 144 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 145 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 146 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 147 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 148 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 149 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 150 #define GSWIP_PCE_GCTRL_0 0x456 151 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 152 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 153 #define GSWIP_PCE_GCTRL_1 0x457 154 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 155 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 156 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 157 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) 158 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 159 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 160 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 161 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 162 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 163 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 164 165 #define GSWIP_MAC_FLEN 0x8C5 166 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 167 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 168 169 /* Ethernet Switch Fetch DMA Port Control Register */ 170 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 171 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 172 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 173 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 174 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 175 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 176 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 177 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 178 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 179 180 /* Ethernet Switch Store DMA Port Control Register */ 181 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 182 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 183 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 184 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */ 185 186 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 187 188 struct gswip_hw_info { 189 int max_ports; 190 int cpu_port; 191 }; 192 193 struct xway_gphy_match_data { 194 char *fe_firmware_name; 195 char *ge_firmware_name; 196 }; 197 198 struct gswip_gphy_fw { 199 struct clk *clk_gate; 200 struct reset_control *reset; 201 u32 fw_addr_offset; 202 char *fw_name; 203 }; 204 205 struct gswip_priv { 206 __iomem void *gswip; 207 __iomem void *mdio; 208 __iomem void *mii; 209 const struct gswip_hw_info *hw_info; 210 const struct xway_gphy_match_data *gphy_fw_name_cfg; 211 struct dsa_switch *ds; 212 struct device *dev; 213 struct regmap *rcu_regmap; 214 int num_gphy_fw; 215 struct gswip_gphy_fw *gphy_fw; 216 }; 217 218 struct gswip_rmon_cnt_desc { 219 unsigned int size; 220 unsigned int offset; 221 const char *name; 222 }; 223 224 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 225 226 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 227 /** Receive Packet Count (only packets that are accepted and not discarded). */ 228 MIB_DESC(1, 0x1F, "RxGoodPkts"), 229 MIB_DESC(1, 0x23, "RxUnicastPkts"), 230 MIB_DESC(1, 0x22, "RxMulticastPkts"), 231 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 232 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 233 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 234 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 235 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 236 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 237 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 238 MIB_DESC(1, 0x12, "Rx64BytePkts"), 239 MIB_DESC(1, 0x13, "Rx127BytePkts"), 240 MIB_DESC(1, 0x14, "Rx255BytePkts"), 241 MIB_DESC(1, 0x15, "Rx511BytePkts"), 242 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 243 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 244 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 245 MIB_DESC(1, 0x18, "RxDroppedPkts"), 246 MIB_DESC(1, 0x19, "RxFilteredPkts"), 247 MIB_DESC(2, 0x24, "RxGoodBytes"), 248 MIB_DESC(2, 0x26, "RxBadBytes"), 249 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 250 MIB_DESC(1, 0x0C, "TxGoodPkts"), 251 MIB_DESC(1, 0x06, "TxUnicastPkts"), 252 MIB_DESC(1, 0x07, "TxMulticastPkts"), 253 MIB_DESC(1, 0x00, "Tx64BytePkts"), 254 MIB_DESC(1, 0x01, "Tx127BytePkts"), 255 MIB_DESC(1, 0x02, "Tx255BytePkts"), 256 MIB_DESC(1, 0x03, "Tx511BytePkts"), 257 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 258 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 259 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 260 MIB_DESC(1, 0x08, "TxSingleCollCount"), 261 MIB_DESC(1, 0x09, "TxMultCollCount"), 262 MIB_DESC(1, 0x0A, "TxLateCollCount"), 263 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 264 MIB_DESC(1, 0x0D, "TxPauseCount"), 265 MIB_DESC(1, 0x10, "TxDroppedPkts"), 266 MIB_DESC(2, 0x0E, "TxGoodBytes"), 267 }; 268 269 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 270 { 271 return __raw_readl(priv->gswip + (offset * 4)); 272 } 273 274 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 275 { 276 __raw_writel(val, priv->gswip + (offset * 4)); 277 } 278 279 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 280 u32 offset) 281 { 282 u32 val = gswip_switch_r(priv, offset); 283 284 val &= ~(clear); 285 val |= set; 286 gswip_switch_w(priv, val, offset); 287 } 288 289 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 290 u32 cleared) 291 { 292 u32 val; 293 294 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 295 (val & cleared) == 0, 20, 50000); 296 } 297 298 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 299 { 300 return __raw_readl(priv->mdio + (offset * 4)); 301 } 302 303 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 304 { 305 __raw_writel(val, priv->mdio + (offset * 4)); 306 } 307 308 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 309 u32 offset) 310 { 311 u32 val = gswip_mdio_r(priv, offset); 312 313 val &= ~(clear); 314 val |= set; 315 gswip_mdio_w(priv, val, offset); 316 } 317 318 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 319 { 320 return __raw_readl(priv->mii + (offset * 4)); 321 } 322 323 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 324 { 325 __raw_writel(val, priv->mii + (offset * 4)); 326 } 327 328 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 329 u32 offset) 330 { 331 u32 val = gswip_mii_r(priv, offset); 332 333 val &= ~(clear); 334 val |= set; 335 gswip_mii_w(priv, val, offset); 336 } 337 338 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 339 int port) 340 { 341 switch (port) { 342 case 0: 343 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG0); 344 break; 345 case 1: 346 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG1); 347 break; 348 case 5: 349 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG5); 350 break; 351 } 352 } 353 354 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 355 int port) 356 { 357 switch (port) { 358 case 0: 359 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 360 break; 361 case 1: 362 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 363 break; 364 case 5: 365 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 366 break; 367 } 368 } 369 370 static int gswip_mdio_poll(struct gswip_priv *priv) 371 { 372 int cnt = 100; 373 374 while (likely(cnt--)) { 375 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 376 377 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 378 return 0; 379 usleep_range(20, 40); 380 } 381 382 return -ETIMEDOUT; 383 } 384 385 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 386 { 387 struct gswip_priv *priv = bus->priv; 388 int err; 389 390 err = gswip_mdio_poll(priv); 391 if (err) { 392 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 393 return err; 394 } 395 396 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 397 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 398 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 399 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 400 GSWIP_MDIO_CTRL); 401 402 return 0; 403 } 404 405 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 406 { 407 struct gswip_priv *priv = bus->priv; 408 int err; 409 410 err = gswip_mdio_poll(priv); 411 if (err) { 412 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 413 return err; 414 } 415 416 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 417 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 418 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 419 GSWIP_MDIO_CTRL); 420 421 err = gswip_mdio_poll(priv); 422 if (err) { 423 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 424 return err; 425 } 426 427 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 428 } 429 430 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np) 431 { 432 struct dsa_switch *ds = priv->ds; 433 434 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev); 435 if (!ds->slave_mii_bus) 436 return -ENOMEM; 437 438 ds->slave_mii_bus->priv = priv; 439 ds->slave_mii_bus->read = gswip_mdio_rd; 440 ds->slave_mii_bus->write = gswip_mdio_wr; 441 ds->slave_mii_bus->name = "lantiq,xrx200-mdio"; 442 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", 443 dev_name(priv->dev)); 444 ds->slave_mii_bus->parent = priv->dev; 445 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask; 446 447 return of_mdiobus_register(ds->slave_mii_bus, mdio_np); 448 } 449 450 static int gswip_port_enable(struct dsa_switch *ds, int port, 451 struct phy_device *phydev) 452 { 453 struct gswip_priv *priv = ds->priv; 454 455 /* RMON Counter Enable for port */ 456 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 457 458 /* enable port fetch/store dma & VLAN Modification */ 459 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 460 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 461 GSWIP_FDMA_PCTRLp(port)); 462 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 463 GSWIP_SDMA_PCTRLp(port)); 464 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 465 GSWIP_PCE_PCTRL_0p(port)); 466 467 if (!dsa_is_cpu_port(ds, port)) { 468 u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO | 469 GSWIP_MDIO_PHY_SPEED_AUTO | 470 GSWIP_MDIO_PHY_FDUP_AUTO | 471 GSWIP_MDIO_PHY_FCONTX_AUTO | 472 GSWIP_MDIO_PHY_FCONRX_AUTO | 473 (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK); 474 475 gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port)); 476 /* Activate MDIO auto polling */ 477 gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0); 478 } 479 480 return 0; 481 } 482 483 static void gswip_port_disable(struct dsa_switch *ds, int port) 484 { 485 struct gswip_priv *priv = ds->priv; 486 487 if (!dsa_is_cpu_port(ds, port)) { 488 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_DOWN, 489 GSWIP_MDIO_PHY_LINK_MASK, 490 GSWIP_MDIO_PHYp(port)); 491 /* Deactivate MDIO auto polling */ 492 gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0); 493 } 494 495 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 496 GSWIP_FDMA_PCTRLp(port)); 497 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 498 GSWIP_SDMA_PCTRLp(port)); 499 } 500 501 static int gswip_pce_load_microcode(struct gswip_priv *priv) 502 { 503 int i; 504 int err; 505 506 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 507 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 508 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 509 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 510 511 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { 512 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 513 gswip_switch_w(priv, gswip_pce_microcode[i].val_0, 514 GSWIP_PCE_TBL_VAL(0)); 515 gswip_switch_w(priv, gswip_pce_microcode[i].val_1, 516 GSWIP_PCE_TBL_VAL(1)); 517 gswip_switch_w(priv, gswip_pce_microcode[i].val_2, 518 GSWIP_PCE_TBL_VAL(2)); 519 gswip_switch_w(priv, gswip_pce_microcode[i].val_3, 520 GSWIP_PCE_TBL_VAL(3)); 521 522 /* start the table access: */ 523 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 524 GSWIP_PCE_TBL_CTRL); 525 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 526 GSWIP_PCE_TBL_CTRL_BAS); 527 if (err) 528 return err; 529 } 530 531 /* tell the switch that the microcode is loaded */ 532 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 533 GSWIP_PCE_GCTRL_0); 534 535 return 0; 536 } 537 538 static int gswip_setup(struct dsa_switch *ds) 539 { 540 struct gswip_priv *priv = ds->priv; 541 unsigned int cpu_port = priv->hw_info->cpu_port; 542 int i; 543 int err; 544 545 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 546 usleep_range(5000, 10000); 547 gswip_switch_w(priv, 0, GSWIP_SWRES); 548 549 /* disable port fetch/store dma on all ports */ 550 for (i = 0; i < priv->hw_info->max_ports; i++) 551 gswip_port_disable(ds, i); 552 553 /* enable Switch */ 554 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 555 556 err = gswip_pce_load_microcode(priv); 557 if (err) { 558 dev_err(priv->dev, "writing PCE microcode failed, %i", err); 559 return err; 560 } 561 562 /* Default unknown Broadcast/Multicast/Unicast port maps */ 563 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); 564 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); 565 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); 566 567 /* disable PHY auto polling */ 568 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 569 /* Configure the MDIO Clock 2.5 MHz */ 570 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 571 572 /* Disable the xMII link */ 573 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 0); 574 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 1); 575 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 5); 576 577 /* enable special tag insertion on cpu port */ 578 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 579 GSWIP_FDMA_PCTRLp(cpu_port)); 580 581 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 582 GSWIP_MAC_CTRL_2p(cpu_port)); 583 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8, GSWIP_MAC_FLEN); 584 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 585 GSWIP_BM_QUEUE_GCTRL); 586 587 /* VLAN aware Switching */ 588 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 589 590 /* Mac Address Table Lock */ 591 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_1_MAC_GLOCK | 592 GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD, 593 GSWIP_PCE_GCTRL_1); 594 595 gswip_port_enable(ds, cpu_port, NULL); 596 return 0; 597 } 598 599 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 600 int port) 601 { 602 return DSA_TAG_PROTO_GSWIP; 603 } 604 605 static void gswip_phylink_validate(struct dsa_switch *ds, int port, 606 unsigned long *supported, 607 struct phylink_link_state *state) 608 { 609 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 610 611 switch (port) { 612 case 0: 613 case 1: 614 if (!phy_interface_mode_is_rgmii(state->interface) && 615 state->interface != PHY_INTERFACE_MODE_MII && 616 state->interface != PHY_INTERFACE_MODE_REVMII && 617 state->interface != PHY_INTERFACE_MODE_RMII) 618 goto unsupported; 619 break; 620 case 2: 621 case 3: 622 case 4: 623 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 624 goto unsupported; 625 break; 626 case 5: 627 if (!phy_interface_mode_is_rgmii(state->interface) && 628 state->interface != PHY_INTERFACE_MODE_INTERNAL) 629 goto unsupported; 630 break; 631 default: 632 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 633 dev_err(ds->dev, "Unsupported port: %i\n", port); 634 return; 635 } 636 637 /* Allow all the expected bits */ 638 phylink_set(mask, Autoneg); 639 phylink_set_port_modes(mask); 640 phylink_set(mask, Pause); 641 phylink_set(mask, Asym_Pause); 642 643 /* With the exclusion of MII and Reverse MII, we support Gigabit, 644 * including Half duplex 645 */ 646 if (state->interface != PHY_INTERFACE_MODE_MII && 647 state->interface != PHY_INTERFACE_MODE_REVMII) { 648 phylink_set(mask, 1000baseT_Full); 649 phylink_set(mask, 1000baseT_Half); 650 } 651 652 phylink_set(mask, 10baseT_Half); 653 phylink_set(mask, 10baseT_Full); 654 phylink_set(mask, 100baseT_Half); 655 phylink_set(mask, 100baseT_Full); 656 657 bitmap_and(supported, supported, mask, 658 __ETHTOOL_LINK_MODE_MASK_NBITS); 659 bitmap_and(state->advertising, state->advertising, mask, 660 __ETHTOOL_LINK_MODE_MASK_NBITS); 661 return; 662 663 unsupported: 664 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 665 dev_err(ds->dev, "Unsupported interface: %d\n", state->interface); 666 return; 667 } 668 669 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, 670 unsigned int mode, 671 const struct phylink_link_state *state) 672 { 673 struct gswip_priv *priv = ds->priv; 674 u32 miicfg = 0; 675 676 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 677 678 switch (state->interface) { 679 case PHY_INTERFACE_MODE_MII: 680 case PHY_INTERFACE_MODE_INTERNAL: 681 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 682 break; 683 case PHY_INTERFACE_MODE_REVMII: 684 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 685 break; 686 case PHY_INTERFACE_MODE_RMII: 687 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 688 break; 689 case PHY_INTERFACE_MODE_RGMII: 690 case PHY_INTERFACE_MODE_RGMII_ID: 691 case PHY_INTERFACE_MODE_RGMII_RXID: 692 case PHY_INTERFACE_MODE_RGMII_TXID: 693 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 694 break; 695 default: 696 dev_err(ds->dev, 697 "Unsupported interface: %d\n", state->interface); 698 return; 699 } 700 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK, miicfg, port); 701 702 switch (state->interface) { 703 case PHY_INTERFACE_MODE_RGMII_ID: 704 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 705 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 706 break; 707 case PHY_INTERFACE_MODE_RGMII_RXID: 708 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 709 break; 710 case PHY_INTERFACE_MODE_RGMII_TXID: 711 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 712 break; 713 default: 714 break; 715 } 716 } 717 718 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, 719 unsigned int mode, 720 phy_interface_t interface) 721 { 722 struct gswip_priv *priv = ds->priv; 723 724 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 725 } 726 727 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, 728 unsigned int mode, 729 phy_interface_t interface, 730 struct phy_device *phydev) 731 { 732 struct gswip_priv *priv = ds->priv; 733 734 /* Enable the xMII interface only for the external PHY */ 735 if (interface != PHY_INTERFACE_MODE_INTERNAL) 736 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 737 } 738 739 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 740 uint8_t *data) 741 { 742 int i; 743 744 if (stringset != ETH_SS_STATS) 745 return; 746 747 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 748 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name, 749 ETH_GSTRING_LEN); 750 } 751 752 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 753 u32 index) 754 { 755 u32 result; 756 int err; 757 758 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 759 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 760 GSWIP_BM_RAM_CTRL_OPMOD, 761 table | GSWIP_BM_RAM_CTRL_BAS, 762 GSWIP_BM_RAM_CTRL); 763 764 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 765 GSWIP_BM_RAM_CTRL_BAS); 766 if (err) { 767 dev_err(priv->dev, "timeout while reading table: %u, index: %u", 768 table, index); 769 return 0; 770 } 771 772 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 773 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 774 775 return result; 776 } 777 778 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 779 uint64_t *data) 780 { 781 struct gswip_priv *priv = ds->priv; 782 const struct gswip_rmon_cnt_desc *rmon_cnt; 783 int i; 784 u64 high; 785 786 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 787 rmon_cnt = &gswip_rmon_cnt[i]; 788 789 data[i] = gswip_bcm_ram_entry_read(priv, port, 790 rmon_cnt->offset); 791 if (rmon_cnt->size == 2) { 792 high = gswip_bcm_ram_entry_read(priv, port, 793 rmon_cnt->offset + 1); 794 data[i] |= high << 32; 795 } 796 } 797 } 798 799 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 800 { 801 if (sset != ETH_SS_STATS) 802 return 0; 803 804 return ARRAY_SIZE(gswip_rmon_cnt); 805 } 806 807 static const struct dsa_switch_ops gswip_switch_ops = { 808 .get_tag_protocol = gswip_get_tag_protocol, 809 .setup = gswip_setup, 810 .port_enable = gswip_port_enable, 811 .port_disable = gswip_port_disable, 812 .phylink_validate = gswip_phylink_validate, 813 .phylink_mac_config = gswip_phylink_mac_config, 814 .phylink_mac_link_down = gswip_phylink_mac_link_down, 815 .phylink_mac_link_up = gswip_phylink_mac_link_up, 816 .get_strings = gswip_get_strings, 817 .get_ethtool_stats = gswip_get_ethtool_stats, 818 .get_sset_count = gswip_get_sset_count, 819 }; 820 821 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 822 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 823 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 824 }; 825 826 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 827 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 828 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 829 }; 830 831 static const struct xway_gphy_match_data xrx300_gphy_data = { 832 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 833 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 834 }; 835 836 static const struct of_device_id xway_gphy_match[] = { 837 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 838 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 839 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 840 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 841 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 842 {}, 843 }; 844 845 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 846 { 847 struct device *dev = priv->dev; 848 const struct firmware *fw; 849 void *fw_addr; 850 dma_addr_t dma_addr; 851 dma_addr_t dev_addr; 852 size_t size; 853 int ret; 854 855 ret = clk_prepare_enable(gphy_fw->clk_gate); 856 if (ret) 857 return ret; 858 859 reset_control_assert(gphy_fw->reset); 860 861 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 862 if (ret) { 863 dev_err(dev, "failed to load firmware: %s, error: %i\n", 864 gphy_fw->fw_name, ret); 865 return ret; 866 } 867 868 /* GPHY cores need the firmware code in a persistent and contiguous 869 * memory area with a 16 kB boundary aligned start address. 870 */ 871 size = fw->size + XRX200_GPHY_FW_ALIGN; 872 873 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 874 if (fw_addr) { 875 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 876 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 877 memcpy(fw_addr, fw->data, fw->size); 878 } else { 879 dev_err(dev, "failed to alloc firmware memory\n"); 880 release_firmware(fw); 881 return -ENOMEM; 882 } 883 884 release_firmware(fw); 885 886 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 887 if (ret) 888 return ret; 889 890 reset_control_deassert(gphy_fw->reset); 891 892 return ret; 893 } 894 895 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 896 struct gswip_gphy_fw *gphy_fw, 897 struct device_node *gphy_fw_np, int i) 898 { 899 struct device *dev = priv->dev; 900 u32 gphy_mode; 901 int ret; 902 char gphyname[10]; 903 904 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 905 906 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 907 if (IS_ERR(gphy_fw->clk_gate)) { 908 dev_err(dev, "Failed to lookup gate clock\n"); 909 return PTR_ERR(gphy_fw->clk_gate); 910 } 911 912 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 913 if (ret) 914 return ret; 915 916 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 917 /* Default to GE mode */ 918 if (ret) 919 gphy_mode = GPHY_MODE_GE; 920 921 switch (gphy_mode) { 922 case GPHY_MODE_FE: 923 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 924 break; 925 case GPHY_MODE_GE: 926 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 927 break; 928 default: 929 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); 930 return -EINVAL; 931 } 932 933 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 934 if (IS_ERR(gphy_fw->reset)) { 935 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER) 936 dev_err(dev, "Failed to lookup gphy reset\n"); 937 return PTR_ERR(gphy_fw->reset); 938 } 939 940 return gswip_gphy_fw_load(priv, gphy_fw); 941 } 942 943 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 944 struct gswip_gphy_fw *gphy_fw) 945 { 946 int ret; 947 948 /* check if the device was fully probed */ 949 if (!gphy_fw->fw_name) 950 return; 951 952 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 953 if (ret) 954 dev_err(priv->dev, "can not reset GPHY FW pointer"); 955 956 clk_disable_unprepare(gphy_fw->clk_gate); 957 958 reset_control_put(gphy_fw->reset); 959 } 960 961 static int gswip_gphy_fw_list(struct gswip_priv *priv, 962 struct device_node *gphy_fw_list_np, u32 version) 963 { 964 struct device *dev = priv->dev; 965 struct device_node *gphy_fw_np; 966 const struct of_device_id *match; 967 int err; 968 int i = 0; 969 970 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 971 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 972 * needs a different GPHY firmware. 973 */ 974 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 975 switch (version) { 976 case GSWIP_VERSION_2_0: 977 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 978 break; 979 case GSWIP_VERSION_2_1: 980 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 981 break; 982 default: 983 dev_err(dev, "unknown GSWIP version: 0x%x", version); 984 return -ENOENT; 985 } 986 } 987 988 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 989 if (match && match->data) 990 priv->gphy_fw_name_cfg = match->data; 991 992 if (!priv->gphy_fw_name_cfg) { 993 dev_err(dev, "GPHY compatible type not supported"); 994 return -ENOENT; 995 } 996 997 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 998 if (!priv->num_gphy_fw) 999 return -ENOENT; 1000 1001 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 1002 "lantiq,rcu"); 1003 if (IS_ERR(priv->rcu_regmap)) 1004 return PTR_ERR(priv->rcu_regmap); 1005 1006 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 1007 sizeof(*priv->gphy_fw), 1008 GFP_KERNEL | __GFP_ZERO); 1009 if (!priv->gphy_fw) 1010 return -ENOMEM; 1011 1012 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 1013 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 1014 gphy_fw_np, i); 1015 if (err) 1016 goto remove_gphy; 1017 i++; 1018 } 1019 1020 return 0; 1021 1022 remove_gphy: 1023 for (i = 0; i < priv->num_gphy_fw; i++) 1024 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1025 return err; 1026 } 1027 1028 static int gswip_probe(struct platform_device *pdev) 1029 { 1030 struct gswip_priv *priv; 1031 struct resource *gswip_res, *mdio_res, *mii_res; 1032 struct device_node *mdio_np, *gphy_fw_np; 1033 struct device *dev = &pdev->dev; 1034 int err; 1035 int i; 1036 u32 version; 1037 1038 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1039 if (!priv) 1040 return -ENOMEM; 1041 1042 gswip_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1043 priv->gswip = devm_ioremap_resource(dev, gswip_res); 1044 if (IS_ERR(priv->gswip)) 1045 return PTR_ERR(priv->gswip); 1046 1047 mdio_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1048 priv->mdio = devm_ioremap_resource(dev, mdio_res); 1049 if (IS_ERR(priv->mdio)) 1050 return PTR_ERR(priv->mdio); 1051 1052 mii_res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1053 priv->mii = devm_ioremap_resource(dev, mii_res); 1054 if (IS_ERR(priv->mii)) 1055 return PTR_ERR(priv->mii); 1056 1057 priv->hw_info = of_device_get_match_data(dev); 1058 if (!priv->hw_info) 1059 return -EINVAL; 1060 1061 priv->ds = dsa_switch_alloc(dev, priv->hw_info->max_ports); 1062 if (!priv->ds) 1063 return -ENOMEM; 1064 1065 priv->ds->priv = priv; 1066 priv->ds->ops = &gswip_switch_ops; 1067 priv->dev = dev; 1068 version = gswip_switch_r(priv, GSWIP_VERSION); 1069 1070 /* bring up the mdio bus */ 1071 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 1072 if (gphy_fw_np) { 1073 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 1074 of_node_put(gphy_fw_np); 1075 if (err) { 1076 dev_err(dev, "gphy fw probe failed\n"); 1077 return err; 1078 } 1079 } 1080 1081 /* bring up the mdio bus */ 1082 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio"); 1083 if (mdio_np) { 1084 err = gswip_mdio(priv, mdio_np); 1085 if (err) { 1086 dev_err(dev, "mdio probe failed\n"); 1087 goto put_mdio_node; 1088 } 1089 } 1090 1091 err = dsa_register_switch(priv->ds); 1092 if (err) { 1093 dev_err(dev, "dsa switch register failed: %i\n", err); 1094 goto mdio_bus; 1095 } 1096 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { 1097 dev_err(dev, "wrong CPU port defined, HW only supports port: %i", 1098 priv->hw_info->cpu_port); 1099 err = -EINVAL; 1100 goto disable_switch; 1101 } 1102 1103 platform_set_drvdata(pdev, priv); 1104 1105 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 1106 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, 1107 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); 1108 return 0; 1109 1110 disable_switch: 1111 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 1112 dsa_unregister_switch(priv->ds); 1113 mdio_bus: 1114 if (mdio_np) 1115 mdiobus_unregister(priv->ds->slave_mii_bus); 1116 put_mdio_node: 1117 of_node_put(mdio_np); 1118 for (i = 0; i < priv->num_gphy_fw; i++) 1119 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1120 return err; 1121 } 1122 1123 static int gswip_remove(struct platform_device *pdev) 1124 { 1125 struct gswip_priv *priv = platform_get_drvdata(pdev); 1126 int i; 1127 1128 /* disable the switch */ 1129 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 1130 1131 dsa_unregister_switch(priv->ds); 1132 1133 if (priv->ds->slave_mii_bus) { 1134 mdiobus_unregister(priv->ds->slave_mii_bus); 1135 of_node_put(priv->ds->slave_mii_bus->dev.of_node); 1136 } 1137 1138 for (i = 0; i < priv->num_gphy_fw; i++) 1139 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1140 1141 return 0; 1142 } 1143 1144 static const struct gswip_hw_info gswip_xrx200 = { 1145 .max_ports = 7, 1146 .cpu_port = 6, 1147 }; 1148 1149 static const struct of_device_id gswip_of_match[] = { 1150 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 1151 {}, 1152 }; 1153 MODULE_DEVICE_TABLE(of, gswip_of_match); 1154 1155 static struct platform_driver gswip_driver = { 1156 .probe = gswip_probe, 1157 .remove = gswip_remove, 1158 .driver = { 1159 .name = "gswip", 1160 .of_match_table = gswip_of_match, 1161 }, 1162 }; 1163 1164 module_platform_driver(gswip_driver); 1165 1166 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 1167 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 1168 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 1169 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 1170 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 1171 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 1172 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 1173 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 1174 MODULE_LICENSE("GPL v2"); 1175