1 /* 2 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/regmap.h> 18 #include <linux/mutex.h> 19 #include <linux/mii.h> 20 21 #include "lan9303.h" 22 23 #define LAN9303_CHIP_REV 0x14 24 # define LAN9303_CHIP_ID 0x9303 25 #define LAN9303_IRQ_CFG 0x15 26 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8) 27 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4) 28 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0) 29 #define LAN9303_INT_STS 0x16 30 # define LAN9303_INT_STS_PHY_INT2 BIT(27) 31 # define LAN9303_INT_STS_PHY_INT1 BIT(26) 32 #define LAN9303_INT_EN 0x17 33 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27) 34 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26) 35 #define LAN9303_HW_CFG 0x1D 36 # define LAN9303_HW_CFG_READY BIT(27) 37 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26) 38 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25) 39 #define LAN9303_PMI_DATA 0x29 40 #define LAN9303_PMI_ACCESS 0x2A 41 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11) 42 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6) 43 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0) 44 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1) 45 #define LAN9303_MANUAL_FC_1 0x68 46 #define LAN9303_MANUAL_FC_2 0x69 47 #define LAN9303_MANUAL_FC_0 0x6a 48 #define LAN9303_SWITCH_CSR_DATA 0x6b 49 #define LAN9303_SWITCH_CSR_CMD 0x6c 50 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31) 51 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30) 52 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16)) 53 #define LAN9303_VIRT_PHY_BASE 0x70 54 #define LAN9303_VIRT_SPECIAL_CTRL 0x77 55 56 #define LAN9303_SW_DEV_ID 0x0000 57 #define LAN9303_SW_RESET 0x0001 58 #define LAN9303_SW_RESET_RESET BIT(0) 59 #define LAN9303_SW_IMR 0x0004 60 #define LAN9303_SW_IPR 0x0005 61 #define LAN9303_MAC_VER_ID_0 0x0400 62 #define LAN9303_MAC_RX_CFG_0 0x0401 63 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1) 64 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0) 65 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410 66 #define LAN9303_MAC_RX_64_CNT_0 0x0411 67 #define LAN9303_MAC_RX_127_CNT_0 0x0412 68 #define LAN9303_MAC_RX_255_CNT_0 0x413 69 #define LAN9303_MAC_RX_511_CNT_0 0x0414 70 #define LAN9303_MAC_RX_1023_CNT_0 0x0415 71 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416 72 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417 73 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418 74 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419 75 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a 76 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b 77 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c 78 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d 79 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e 80 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f 81 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420 82 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421 83 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422 84 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423 85 86 #define LAN9303_MAC_TX_CFG_0 0x0440 87 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2) 88 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1) 89 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0) 90 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451 91 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452 92 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453 93 #define LAN9303_MAC_TX_64_CNT_0 0x0454 94 #define LAN9303_MAC_TX_127_CNT_0 0x0455 95 #define LAN9303_MAC_TX_255_CNT_0 0x0456 96 #define LAN9303_MAC_TX_511_CNT_0 0x0457 97 #define LAN9303_MAC_TX_1023_CNT_0 0x0458 98 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459 99 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a 100 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c 101 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d 102 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e 103 #define LAN9303_MAC_TX_LATECOL_0 0x045f 104 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460 105 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461 106 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462 107 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463 108 109 #define LAN9303_MAC_VER_ID_1 0x0800 110 #define LAN9303_MAC_RX_CFG_1 0x0801 111 #define LAN9303_MAC_TX_CFG_1 0x0840 112 #define LAN9303_MAC_VER_ID_2 0x0c00 113 #define LAN9303_MAC_RX_CFG_2 0x0c01 114 #define LAN9303_MAC_TX_CFG_2 0x0c40 115 #define LAN9303_SWE_ALR_CMD 0x1800 116 #define LAN9303_SWE_VLAN_CMD 0x180b 117 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5) 118 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4) 119 #define LAN9303_SWE_VLAN_WR_DATA 0x180c 120 #define LAN9303_SWE_VLAN_RD_DATA 0x180e 121 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17) 122 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16) 123 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15) 124 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14) 125 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13) 126 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12) 127 #define LAN9303_SWE_VLAN_CMD_STS 0x1810 128 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840 129 #define LAN9303_SWE_PORT_STATE 0x1843 130 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0) 131 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5) 132 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4) 133 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0) 134 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3) 135 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2) 136 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0) 137 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1) 138 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0) 139 #define LAN9303_SWE_PORT_MIRROR 0x1846 140 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8) 141 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7) 142 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6) 143 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5) 144 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4) 145 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3) 146 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2) 147 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1) 148 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0) 149 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847 150 #define LAN9303_BM_CFG 0x1c00 151 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c 152 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16)) 153 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8)) 154 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0)) 155 156 #define LAN9303_PORT_0_OFFSET 0x400 157 #define LAN9303_PORT_1_OFFSET 0x800 158 #define LAN9303_PORT_2_OFFSET 0xc00 159 160 /* the built-in PHYs are of type LAN911X */ 161 #define MII_LAN911X_SPECIAL_MODES 0x12 162 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f 163 164 static const struct regmap_range lan9303_valid_regs[] = { 165 regmap_reg_range(0x14, 0x17), /* misc, interrupt */ 166 regmap_reg_range(0x19, 0x19), /* endian test */ 167 regmap_reg_range(0x1d, 0x1d), /* hardware config */ 168 regmap_reg_range(0x23, 0x24), /* general purpose timer */ 169 regmap_reg_range(0x27, 0x27), /* counter */ 170 regmap_reg_range(0x29, 0x2a), /* PMI index regs */ 171 regmap_reg_range(0x68, 0x6a), /* flow control */ 172 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */ 173 regmap_reg_range(0x6d, 0x6f), /* misc */ 174 regmap_reg_range(0x70, 0x77), /* virtual phy */ 175 regmap_reg_range(0x78, 0x7a), /* GPIO */ 176 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */ 177 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */ 178 }; 179 180 static const struct regmap_range lan9303_reserved_ranges[] = { 181 regmap_reg_range(0x00, 0x13), 182 regmap_reg_range(0x18, 0x18), 183 regmap_reg_range(0x1a, 0x1c), 184 regmap_reg_range(0x1e, 0x22), 185 regmap_reg_range(0x25, 0x26), 186 regmap_reg_range(0x28, 0x28), 187 regmap_reg_range(0x2b, 0x67), 188 regmap_reg_range(0x7b, 0x7b), 189 regmap_reg_range(0x7f, 0x7f), 190 regmap_reg_range(0xb8, 0xff), 191 }; 192 193 const struct regmap_access_table lan9303_register_set = { 194 .yes_ranges = lan9303_valid_regs, 195 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs), 196 .no_ranges = lan9303_reserved_ranges, 197 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges), 198 }; 199 EXPORT_SYMBOL(lan9303_register_set); 200 201 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg) 202 { 203 int ret, i; 204 205 /* we can lose arbitration for the I2C case, because the device 206 * tries to detect and read an external EEPROM after reset and acts as 207 * a master on the shared I2C bus itself. This conflicts with our 208 * attempts to access the device as a slave at the same moment. 209 */ 210 for (i = 0; i < 5; i++) { 211 ret = regmap_read(regmap, offset, reg); 212 if (!ret) 213 return 0; 214 if (ret != -EAGAIN) 215 break; 216 msleep(500); 217 } 218 219 return -EIO; 220 } 221 222 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum) 223 { 224 int ret; 225 u32 val; 226 227 if (regnum > MII_EXPANSION) 228 return -EINVAL; 229 230 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val); 231 if (ret) 232 return ret; 233 234 return val & 0xffff; 235 } 236 237 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val) 238 { 239 if (regnum > MII_EXPANSION) 240 return -EINVAL; 241 242 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val); 243 } 244 245 static int lan9303_port_phy_reg_wait_for_completion(struct lan9303 *chip) 246 { 247 int ret, i; 248 u32 reg; 249 250 for (i = 0; i < 25; i++) { 251 ret = lan9303_read(chip->regmap, LAN9303_PMI_ACCESS, ®); 252 if (ret) { 253 dev_err(chip->dev, 254 "Failed to read pmi access status: %d\n", ret); 255 return ret; 256 } 257 if (!(reg & LAN9303_PMI_ACCESS_MII_BUSY)) 258 return 0; 259 msleep(1); 260 } 261 262 return -EIO; 263 } 264 265 static int lan9303_port_phy_reg_read(struct lan9303 *chip, int addr, int regnum) 266 { 267 int ret; 268 u32 val; 269 270 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 271 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 272 273 mutex_lock(&chip->indirect_mutex); 274 275 ret = lan9303_port_phy_reg_wait_for_completion(chip); 276 if (ret) 277 goto on_error; 278 279 /* start the MII read cycle */ 280 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val); 281 if (ret) 282 goto on_error; 283 284 ret = lan9303_port_phy_reg_wait_for_completion(chip); 285 if (ret) 286 goto on_error; 287 288 /* read the result of this operation */ 289 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val); 290 if (ret) 291 goto on_error; 292 293 mutex_unlock(&chip->indirect_mutex); 294 295 return val & 0xffff; 296 297 on_error: 298 mutex_unlock(&chip->indirect_mutex); 299 return ret; 300 } 301 302 static int lan9303_phy_reg_write(struct lan9303 *chip, int addr, int regnum, 303 unsigned int val) 304 { 305 int ret; 306 u32 reg; 307 308 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 309 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 310 reg |= LAN9303_PMI_ACCESS_MII_WRITE; 311 312 mutex_lock(&chip->indirect_mutex); 313 314 ret = lan9303_port_phy_reg_wait_for_completion(chip); 315 if (ret) 316 goto on_error; 317 318 /* write the data first... */ 319 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val); 320 if (ret) 321 goto on_error; 322 323 /* ...then start the MII write cycle */ 324 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg); 325 326 on_error: 327 mutex_unlock(&chip->indirect_mutex); 328 return ret; 329 } 330 331 static int lan9303_switch_wait_for_completion(struct lan9303 *chip) 332 { 333 int ret, i; 334 u32 reg; 335 336 for (i = 0; i < 25; i++) { 337 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_CMD, ®); 338 if (ret) { 339 dev_err(chip->dev, 340 "Failed to read csr command status: %d\n", ret); 341 return ret; 342 } 343 if (!(reg & LAN9303_SWITCH_CSR_CMD_BUSY)) 344 return 0; 345 msleep(1); 346 } 347 348 return -EIO; 349 } 350 351 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val) 352 { 353 u32 reg; 354 int ret; 355 356 reg = regnum; 357 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 358 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 359 360 mutex_lock(&chip->indirect_mutex); 361 362 ret = lan9303_switch_wait_for_completion(chip); 363 if (ret) 364 goto on_error; 365 366 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 367 if (ret) { 368 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret); 369 goto on_error; 370 } 371 372 /* trigger write */ 373 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 374 if (ret) 375 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 376 ret); 377 378 on_error: 379 mutex_unlock(&chip->indirect_mutex); 380 return ret; 381 } 382 383 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val) 384 { 385 u32 reg; 386 int ret; 387 388 reg = regnum; 389 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 390 reg |= LAN9303_SWITCH_CSR_CMD_RW; 391 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 392 393 mutex_lock(&chip->indirect_mutex); 394 395 ret = lan9303_switch_wait_for_completion(chip); 396 if (ret) 397 goto on_error; 398 399 /* trigger read */ 400 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 401 if (ret) { 402 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 403 ret); 404 goto on_error; 405 } 406 407 ret = lan9303_switch_wait_for_completion(chip); 408 if (ret) 409 goto on_error; 410 411 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 412 if (ret) 413 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret); 414 on_error: 415 mutex_unlock(&chip->indirect_mutex); 416 return ret; 417 } 418 419 static int lan9303_detect_phy_setup(struct lan9303 *chip) 420 { 421 int reg; 422 423 /* depending on the 'phy_addr_sel_strap' setting, the three phys are 424 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the 425 * 'phy_addr_sel_strap' setting directly, so we need a test, which 426 * configuration is active: 427 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0 428 * and the IDs are 0-1-2, else it contains something different from 429 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3. 430 */ 431 reg = lan9303_port_phy_reg_read(chip, 3, MII_LAN911X_SPECIAL_MODES); 432 if (reg < 0) { 433 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg); 434 return reg; 435 } 436 437 if (reg != 0) 438 chip->phy_addr_sel_strap = 1; 439 else 440 chip->phy_addr_sel_strap = 0; 441 442 dev_dbg(chip->dev, "Phy setup '%s' detected\n", 443 chip->phy_addr_sel_strap ? "1-2-3" : "0-1-2"); 444 445 return 0; 446 } 447 448 #define LAN9303_MAC_RX_CFG_OFFS (LAN9303_MAC_RX_CFG_0 - LAN9303_PORT_0_OFFSET) 449 #define LAN9303_MAC_TX_CFG_OFFS (LAN9303_MAC_TX_CFG_0 - LAN9303_PORT_0_OFFSET) 450 451 static int lan9303_disable_packet_processing(struct lan9303 *chip, 452 unsigned int port) 453 { 454 int ret; 455 456 /* disable RX, but keep register reset default values else */ 457 ret = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_OFFS + port, 458 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES); 459 if (ret) 460 return ret; 461 462 /* disable TX, but keep register reset default values else */ 463 return lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_OFFS + port, 464 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 465 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE); 466 } 467 468 static int lan9303_enable_packet_processing(struct lan9303 *chip, 469 unsigned int port) 470 { 471 int ret; 472 473 /* enable RX and keep register reset default values else */ 474 ret = lan9303_write_switch_reg(chip, LAN9303_MAC_RX_CFG_OFFS + port, 475 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES | 476 LAN9303_MAC_RX_CFG_X_RX_ENABLE); 477 if (ret) 478 return ret; 479 480 /* enable TX and keep register reset default values else */ 481 return lan9303_write_switch_reg(chip, LAN9303_MAC_TX_CFG_OFFS + port, 482 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 483 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE | 484 LAN9303_MAC_TX_CFG_X_TX_ENABLE); 485 } 486 487 /* We want a special working switch: 488 * - do not forward packets between port 1 and 2 489 * - forward everything from port 1 to port 0 490 * - forward everything from port 2 to port 0 491 * - forward special tagged packets from port 0 to port 1 *or* port 2 492 */ 493 static int lan9303_separate_ports(struct lan9303 *chip) 494 { 495 int ret; 496 497 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 498 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 | 499 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 | 500 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 | 501 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING | 502 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL); 503 if (ret) 504 return ret; 505 506 /* enable defining the destination port via special VLAN tagging 507 * for port 0 508 */ 509 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE, 510 0x03); 511 if (ret) 512 return ret; 513 514 /* tag incoming packets at port 1 and 2 on their way to port 0 to be 515 * able to discover their source port 516 */ 517 ret = lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, 518 LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0); 519 if (ret) 520 return ret; 521 522 /* prevent port 1 and 2 from forwarding packets by their own */ 523 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 524 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 | 525 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 | 526 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2); 527 } 528 529 static int lan9303_handle_reset(struct lan9303 *chip) 530 { 531 if (!chip->reset_gpio) 532 return 0; 533 534 if (chip->reset_duration != 0) 535 msleep(chip->reset_duration); 536 537 /* release (deassert) reset and activate the device */ 538 gpiod_set_value_cansleep(chip->reset_gpio, 0); 539 540 return 0; 541 } 542 543 /* stop processing packets for all ports */ 544 static int lan9303_disable_processing(struct lan9303 *chip) 545 { 546 int ret; 547 548 ret = lan9303_disable_packet_processing(chip, LAN9303_PORT_0_OFFSET); 549 if (ret) 550 return ret; 551 ret = lan9303_disable_packet_processing(chip, LAN9303_PORT_1_OFFSET); 552 if (ret) 553 return ret; 554 return lan9303_disable_packet_processing(chip, LAN9303_PORT_2_OFFSET); 555 } 556 557 static int lan9303_check_device(struct lan9303 *chip) 558 { 559 int ret; 560 u32 reg; 561 562 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®); 563 if (ret) { 564 dev_err(chip->dev, "failed to read chip revision register: %d\n", 565 ret); 566 if (!chip->reset_gpio) { 567 dev_dbg(chip->dev, 568 "hint: maybe failed due to missing reset GPIO\n"); 569 } 570 return ret; 571 } 572 573 if ((reg >> 16) != LAN9303_CHIP_ID) { 574 dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n", 575 reg >> 16); 576 return ret; 577 } 578 579 /* The default state of the LAN9303 device is to forward packets between 580 * all ports (if not configured differently by an external EEPROM). 581 * The initial state of a DSA device must be forwarding packets only 582 * between the external and the internal ports and no forwarding 583 * between the external ports. In preparation we stop packet handling 584 * at all for now until the LAN9303 device is re-programmed accordingly. 585 */ 586 ret = lan9303_disable_processing(chip); 587 if (ret) 588 dev_warn(chip->dev, "failed to disable switching %d\n", ret); 589 590 dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff); 591 592 ret = lan9303_detect_phy_setup(chip); 593 if (ret) { 594 dev_err(chip->dev, 595 "failed to discover phy bootstrap setup: %d\n", ret); 596 return ret; 597 } 598 599 return 0; 600 } 601 602 /* ---------------------------- DSA -----------------------------------*/ 603 604 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds) 605 { 606 return DSA_TAG_PROTO_LAN9303; 607 } 608 609 static int lan9303_setup(struct dsa_switch *ds) 610 { 611 struct lan9303 *chip = ds->priv; 612 int ret; 613 614 /* Make sure that port 0 is the cpu port */ 615 if (!dsa_is_cpu_port(ds, 0)) { 616 dev_err(chip->dev, "port 0 is not the CPU port\n"); 617 return -EINVAL; 618 } 619 620 ret = lan9303_separate_ports(chip); 621 if (ret) 622 dev_err(chip->dev, "failed to separate ports %d\n", ret); 623 624 ret = lan9303_enable_packet_processing(chip, LAN9303_PORT_0_OFFSET); 625 if (ret) 626 dev_err(chip->dev, "failed to re-enable switching %d\n", ret); 627 628 return 0; 629 } 630 631 struct lan9303_mib_desc { 632 unsigned int offset; /* offset of first MAC */ 633 const char *name; 634 }; 635 636 static const struct lan9303_mib_desc lan9303_mib[] = { 637 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", }, 638 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", }, 639 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", }, 640 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", }, 641 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", }, 642 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", }, 643 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", }, 644 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", }, 645 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", }, 646 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", }, 647 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", }, 648 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", }, 649 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", }, 650 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", }, 651 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", }, 652 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", }, 653 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", }, 654 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", }, 655 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", }, 656 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", }, 657 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", }, 658 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", }, 659 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", }, 660 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", }, 661 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", }, 662 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", }, 663 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", }, 664 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", }, 665 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", }, 666 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", }, 667 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", }, 668 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", }, 669 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", }, 670 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", }, 671 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", }, 672 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", }, 673 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", }, 674 }; 675 676 static void lan9303_get_strings(struct dsa_switch *ds, int port, uint8_t *data) 677 { 678 unsigned int u; 679 680 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 681 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name, 682 ETH_GSTRING_LEN); 683 } 684 } 685 686 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port, 687 uint64_t *data) 688 { 689 struct lan9303 *chip = ds->priv; 690 u32 reg; 691 unsigned int u, poff; 692 int ret; 693 694 poff = port * 0x400; 695 696 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 697 ret = lan9303_read_switch_reg(chip, 698 lan9303_mib[u].offset + poff, 699 ®); 700 if (ret) 701 dev_warn(chip->dev, "Reading status reg %u failed\n", 702 lan9303_mib[u].offset + poff); 703 data[u] = reg; 704 } 705 } 706 707 static int lan9303_get_sset_count(struct dsa_switch *ds) 708 { 709 return ARRAY_SIZE(lan9303_mib); 710 } 711 712 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum) 713 { 714 struct lan9303 *chip = ds->priv; 715 int phy_base = chip->phy_addr_sel_strap; 716 717 if (phy == phy_base) 718 return lan9303_virt_phy_reg_read(chip, regnum); 719 if (phy > phy_base + 2) 720 return -ENODEV; 721 722 return lan9303_port_phy_reg_read(chip, phy, regnum); 723 } 724 725 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum, 726 u16 val) 727 { 728 struct lan9303 *chip = ds->priv; 729 int phy_base = chip->phy_addr_sel_strap; 730 731 if (phy == phy_base) 732 return lan9303_virt_phy_reg_write(chip, regnum, val); 733 if (phy > phy_base + 2) 734 return -ENODEV; 735 736 return lan9303_phy_reg_write(chip, phy, regnum, val); 737 } 738 739 static int lan9303_port_enable(struct dsa_switch *ds, int port, 740 struct phy_device *phy) 741 { 742 struct lan9303 *chip = ds->priv; 743 744 /* enable internal packet processing */ 745 switch (port) { 746 case 1: 747 return lan9303_enable_packet_processing(chip, 748 LAN9303_PORT_1_OFFSET); 749 case 2: 750 return lan9303_enable_packet_processing(chip, 751 LAN9303_PORT_2_OFFSET); 752 default: 753 dev_dbg(chip->dev, 754 "Error: request to power up invalid port %d\n", port); 755 } 756 757 return -ENODEV; 758 } 759 760 static void lan9303_port_disable(struct dsa_switch *ds, int port, 761 struct phy_device *phy) 762 { 763 struct lan9303 *chip = ds->priv; 764 765 /* disable internal packet processing */ 766 switch (port) { 767 case 1: 768 lan9303_disable_packet_processing(chip, LAN9303_PORT_1_OFFSET); 769 lan9303_phy_reg_write(chip, chip->phy_addr_sel_strap + 1, 770 MII_BMCR, BMCR_PDOWN); 771 break; 772 case 2: 773 lan9303_disable_packet_processing(chip, LAN9303_PORT_2_OFFSET); 774 lan9303_phy_reg_write(chip, chip->phy_addr_sel_strap + 2, 775 MII_BMCR, BMCR_PDOWN); 776 break; 777 default: 778 dev_dbg(chip->dev, 779 "Error: request to power down invalid port %d\n", port); 780 } 781 } 782 783 static struct dsa_switch_ops lan9303_switch_ops = { 784 .get_tag_protocol = lan9303_get_tag_protocol, 785 .setup = lan9303_setup, 786 .get_strings = lan9303_get_strings, 787 .phy_read = lan9303_phy_read, 788 .phy_write = lan9303_phy_write, 789 .get_ethtool_stats = lan9303_get_ethtool_stats, 790 .get_sset_count = lan9303_get_sset_count, 791 .port_enable = lan9303_port_enable, 792 .port_disable = lan9303_port_disable, 793 }; 794 795 static int lan9303_register_switch(struct lan9303 *chip) 796 { 797 chip->ds = dsa_switch_alloc(chip->dev, DSA_MAX_PORTS); 798 if (!chip->ds) 799 return -ENOMEM; 800 801 chip->ds->priv = chip; 802 chip->ds->ops = &lan9303_switch_ops; 803 chip->ds->phys_mii_mask = chip->phy_addr_sel_strap ? 0xe : 0x7; 804 805 return dsa_register_switch(chip->ds, chip->dev); 806 } 807 808 static void lan9303_probe_reset_gpio(struct lan9303 *chip, 809 struct device_node *np) 810 { 811 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset", 812 GPIOD_OUT_LOW); 813 814 if (!chip->reset_gpio) { 815 dev_dbg(chip->dev, "No reset GPIO defined\n"); 816 return; 817 } 818 819 chip->reset_duration = 200; 820 821 if (np) { 822 of_property_read_u32(np, "reset-duration", 823 &chip->reset_duration); 824 } else { 825 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n"); 826 } 827 828 /* A sane reset duration should not be longer than 1s */ 829 if (chip->reset_duration > 1000) 830 chip->reset_duration = 1000; 831 } 832 833 int lan9303_probe(struct lan9303 *chip, struct device_node *np) 834 { 835 int ret; 836 837 mutex_init(&chip->indirect_mutex); 838 839 lan9303_probe_reset_gpio(chip, np); 840 841 ret = lan9303_handle_reset(chip); 842 if (ret) 843 return ret; 844 845 ret = lan9303_check_device(chip); 846 if (ret) 847 return ret; 848 849 ret = lan9303_register_switch(chip); 850 if (ret) { 851 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret); 852 return ret; 853 } 854 855 return 0; 856 } 857 EXPORT_SYMBOL(lan9303_probe); 858 859 int lan9303_remove(struct lan9303 *chip) 860 { 861 int rc; 862 863 rc = lan9303_disable_processing(chip); 864 if (rc != 0) 865 dev_warn(chip->dev, "shutting down failed\n"); 866 867 dsa_unregister_switch(chip->ds); 868 869 /* assert reset to the whole device to prevent it from doing anything */ 870 gpiod_set_value_cansleep(chip->reset_gpio, 1); 871 gpiod_unexport(chip->reset_gpio); 872 873 return 0; 874 } 875 EXPORT_SYMBOL(lan9303_remove); 876 877 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>"); 878 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch"); 879 MODULE_LICENSE("GPL v2"); 880