1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de> 4 */ 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/regmap.h> 9 #include <linux/mutex.h> 10 #include <linux/mii.h> 11 #include <linux/phy.h> 12 #include <linux/if_bridge.h> 13 #include <linux/if_vlan.h> 14 #include <linux/etherdevice.h> 15 16 #include "lan9303.h" 17 18 #define LAN9303_NUM_PORTS 3 19 20 /* 13.2 System Control and Status Registers 21 * Multiply register number by 4 to get address offset. 22 */ 23 #define LAN9303_CHIP_REV 0x14 24 # define LAN9303_CHIP_ID 0x9303 25 #define LAN9303_IRQ_CFG 0x15 26 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8) 27 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4) 28 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0) 29 #define LAN9303_INT_STS 0x16 30 # define LAN9303_INT_STS_PHY_INT2 BIT(27) 31 # define LAN9303_INT_STS_PHY_INT1 BIT(26) 32 #define LAN9303_INT_EN 0x17 33 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27) 34 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26) 35 #define LAN9303_HW_CFG 0x1D 36 # define LAN9303_HW_CFG_READY BIT(27) 37 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26) 38 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25) 39 #define LAN9303_PMI_DATA 0x29 40 #define LAN9303_PMI_ACCESS 0x2A 41 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11) 42 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6) 43 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0) 44 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1) 45 #define LAN9303_MANUAL_FC_1 0x68 46 #define LAN9303_MANUAL_FC_2 0x69 47 #define LAN9303_MANUAL_FC_0 0x6a 48 #define LAN9303_SWITCH_CSR_DATA 0x6b 49 #define LAN9303_SWITCH_CSR_CMD 0x6c 50 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31) 51 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30) 52 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16)) 53 #define LAN9303_VIRT_PHY_BASE 0x70 54 #define LAN9303_VIRT_SPECIAL_CTRL 0x77 55 #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/ 56 57 /*13.4 Switch Fabric Control and Status Registers 58 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA. 59 */ 60 #define LAN9303_SW_DEV_ID 0x0000 61 #define LAN9303_SW_RESET 0x0001 62 #define LAN9303_SW_RESET_RESET BIT(0) 63 #define LAN9303_SW_IMR 0x0004 64 #define LAN9303_SW_IPR 0x0005 65 #define LAN9303_MAC_VER_ID_0 0x0400 66 #define LAN9303_MAC_RX_CFG_0 0x0401 67 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1) 68 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0) 69 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410 70 #define LAN9303_MAC_RX_64_CNT_0 0x0411 71 #define LAN9303_MAC_RX_127_CNT_0 0x0412 72 #define LAN9303_MAC_RX_255_CNT_0 0x413 73 #define LAN9303_MAC_RX_511_CNT_0 0x0414 74 #define LAN9303_MAC_RX_1023_CNT_0 0x0415 75 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416 76 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417 77 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418 78 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419 79 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a 80 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b 81 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c 82 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d 83 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e 84 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f 85 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420 86 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421 87 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422 88 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423 89 90 #define LAN9303_MAC_TX_CFG_0 0x0440 91 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2) 92 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1) 93 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0) 94 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451 95 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452 96 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453 97 #define LAN9303_MAC_TX_64_CNT_0 0x0454 98 #define LAN9303_MAC_TX_127_CNT_0 0x0455 99 #define LAN9303_MAC_TX_255_CNT_0 0x0456 100 #define LAN9303_MAC_TX_511_CNT_0 0x0457 101 #define LAN9303_MAC_TX_1023_CNT_0 0x0458 102 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459 103 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a 104 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c 105 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d 106 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e 107 #define LAN9303_MAC_TX_LATECOL_0 0x045f 108 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460 109 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461 110 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462 111 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463 112 113 #define LAN9303_MAC_VER_ID_1 0x0800 114 #define LAN9303_MAC_RX_CFG_1 0x0801 115 #define LAN9303_MAC_TX_CFG_1 0x0840 116 #define LAN9303_MAC_VER_ID_2 0x0c00 117 #define LAN9303_MAC_RX_CFG_2 0x0c01 118 #define LAN9303_MAC_TX_CFG_2 0x0c40 119 #define LAN9303_SWE_ALR_CMD 0x1800 120 # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2) 121 # define LAN9303_ALR_CMD_GET_FIRST BIT(1) 122 # define LAN9303_ALR_CMD_GET_NEXT BIT(0) 123 #define LAN9303_SWE_ALR_WR_DAT_0 0x1801 124 #define LAN9303_SWE_ALR_WR_DAT_1 0x1802 125 # define LAN9303_ALR_DAT1_VALID BIT(26) 126 # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25) 127 # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25) 128 # define LAN9303_ALR_DAT1_STATIC BIT(24) 129 # define LAN9303_ALR_DAT1_PORT_BITOFFS 16 130 # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS) 131 #define LAN9303_SWE_ALR_RD_DAT_0 0x1805 132 #define LAN9303_SWE_ALR_RD_DAT_1 0x1806 133 #define LAN9303_SWE_ALR_CMD_STS 0x1808 134 # define ALR_STS_MAKE_PEND BIT(0) 135 #define LAN9303_SWE_VLAN_CMD 0x180b 136 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5) 137 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4) 138 #define LAN9303_SWE_VLAN_WR_DATA 0x180c 139 #define LAN9303_SWE_VLAN_RD_DATA 0x180e 140 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17) 141 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16) 142 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15) 143 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14) 144 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13) 145 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12) 146 #define LAN9303_SWE_VLAN_CMD_STS 0x1810 147 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840 148 # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7) 149 # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p) 150 #define LAN9303_SWE_PORT_STATE 0x1843 151 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0) 152 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5) 153 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4) 154 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0) 155 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3) 156 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2) 157 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0) 158 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1) 159 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0) 160 # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3) 161 #define LAN9303_SWE_PORT_MIRROR 0x1846 162 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8) 163 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7) 164 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6) 165 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5) 166 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4) 167 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3) 168 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2) 169 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1) 170 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0) 171 # define LAN9303_SWE_PORT_MIRROR_DISABLED 0 172 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847 173 #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3 174 #define LAN9303_BM_CFG 0x1c00 175 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c 176 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16)) 177 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8)) 178 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0)) 179 180 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0)) 181 182 /* the built-in PHYs are of type LAN911X */ 183 #define MII_LAN911X_SPECIAL_MODES 0x12 184 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f 185 186 static const struct regmap_range lan9303_valid_regs[] = { 187 regmap_reg_range(0x14, 0x17), /* misc, interrupt */ 188 regmap_reg_range(0x19, 0x19), /* endian test */ 189 regmap_reg_range(0x1d, 0x1d), /* hardware config */ 190 regmap_reg_range(0x23, 0x24), /* general purpose timer */ 191 regmap_reg_range(0x27, 0x27), /* counter */ 192 regmap_reg_range(0x29, 0x2a), /* PMI index regs */ 193 regmap_reg_range(0x68, 0x6a), /* flow control */ 194 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */ 195 regmap_reg_range(0x6d, 0x6f), /* misc */ 196 regmap_reg_range(0x70, 0x77), /* virtual phy */ 197 regmap_reg_range(0x78, 0x7a), /* GPIO */ 198 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */ 199 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */ 200 }; 201 202 static const struct regmap_range lan9303_reserved_ranges[] = { 203 regmap_reg_range(0x00, 0x13), 204 regmap_reg_range(0x18, 0x18), 205 regmap_reg_range(0x1a, 0x1c), 206 regmap_reg_range(0x1e, 0x22), 207 regmap_reg_range(0x25, 0x26), 208 regmap_reg_range(0x28, 0x28), 209 regmap_reg_range(0x2b, 0x67), 210 regmap_reg_range(0x7b, 0x7b), 211 regmap_reg_range(0x7f, 0x7f), 212 regmap_reg_range(0xb8, 0xff), 213 }; 214 215 const struct regmap_access_table lan9303_register_set = { 216 .yes_ranges = lan9303_valid_regs, 217 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs), 218 .no_ranges = lan9303_reserved_ranges, 219 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges), 220 }; 221 EXPORT_SYMBOL(lan9303_register_set); 222 223 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg) 224 { 225 int ret, i; 226 227 /* we can lose arbitration for the I2C case, because the device 228 * tries to detect and read an external EEPROM after reset and acts as 229 * a master on the shared I2C bus itself. This conflicts with our 230 * attempts to access the device as a slave at the same moment. 231 */ 232 for (i = 0; i < 5; i++) { 233 ret = regmap_read(regmap, offset, reg); 234 if (!ret) 235 return 0; 236 if (ret != -EAGAIN) 237 break; 238 msleep(500); 239 } 240 241 return -EIO; 242 } 243 244 static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask) 245 { 246 int i; 247 248 for (i = 0; i < 25; i++) { 249 u32 reg; 250 int ret; 251 252 ret = lan9303_read(chip->regmap, offset, ®); 253 if (ret) { 254 dev_err(chip->dev, "%s failed to read offset %d: %d\n", 255 __func__, offset, ret); 256 return ret; 257 } 258 if (!(reg & mask)) 259 return 0; 260 usleep_range(1000, 2000); 261 } 262 263 return -ETIMEDOUT; 264 } 265 266 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum) 267 { 268 int ret; 269 u32 val; 270 271 if (regnum > MII_EXPANSION) 272 return -EINVAL; 273 274 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val); 275 if (ret) 276 return ret; 277 278 return val & 0xffff; 279 } 280 281 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val) 282 { 283 if (regnum > MII_EXPANSION) 284 return -EINVAL; 285 286 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val); 287 } 288 289 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip) 290 { 291 return lan9303_read_wait(chip, LAN9303_PMI_ACCESS, 292 LAN9303_PMI_ACCESS_MII_BUSY); 293 } 294 295 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum) 296 { 297 int ret; 298 u32 val; 299 300 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 301 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 302 303 mutex_lock(&chip->indirect_mutex); 304 305 ret = lan9303_indirect_phy_wait_for_completion(chip); 306 if (ret) 307 goto on_error; 308 309 /* start the MII read cycle */ 310 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val); 311 if (ret) 312 goto on_error; 313 314 ret = lan9303_indirect_phy_wait_for_completion(chip); 315 if (ret) 316 goto on_error; 317 318 /* read the result of this operation */ 319 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val); 320 if (ret) 321 goto on_error; 322 323 mutex_unlock(&chip->indirect_mutex); 324 325 return val & 0xffff; 326 327 on_error: 328 mutex_unlock(&chip->indirect_mutex); 329 return ret; 330 } 331 332 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr, 333 int regnum, u16 val) 334 { 335 int ret; 336 u32 reg; 337 338 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 339 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 340 reg |= LAN9303_PMI_ACCESS_MII_WRITE; 341 342 mutex_lock(&chip->indirect_mutex); 343 344 ret = lan9303_indirect_phy_wait_for_completion(chip); 345 if (ret) 346 goto on_error; 347 348 /* write the data first... */ 349 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val); 350 if (ret) 351 goto on_error; 352 353 /* ...then start the MII write cycle */ 354 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg); 355 356 on_error: 357 mutex_unlock(&chip->indirect_mutex); 358 return ret; 359 } 360 361 const struct lan9303_phy_ops lan9303_indirect_phy_ops = { 362 .phy_read = lan9303_indirect_phy_read, 363 .phy_write = lan9303_indirect_phy_write, 364 }; 365 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops); 366 367 static int lan9303_switch_wait_for_completion(struct lan9303 *chip) 368 { 369 return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD, 370 LAN9303_SWITCH_CSR_CMD_BUSY); 371 } 372 373 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val) 374 { 375 u32 reg; 376 int ret; 377 378 reg = regnum; 379 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 380 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 381 382 mutex_lock(&chip->indirect_mutex); 383 384 ret = lan9303_switch_wait_for_completion(chip); 385 if (ret) 386 goto on_error; 387 388 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 389 if (ret) { 390 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret); 391 goto on_error; 392 } 393 394 /* trigger write */ 395 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 396 if (ret) 397 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 398 ret); 399 400 on_error: 401 mutex_unlock(&chip->indirect_mutex); 402 return ret; 403 } 404 405 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val) 406 { 407 u32 reg; 408 int ret; 409 410 reg = regnum; 411 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 412 reg |= LAN9303_SWITCH_CSR_CMD_RW; 413 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 414 415 mutex_lock(&chip->indirect_mutex); 416 417 ret = lan9303_switch_wait_for_completion(chip); 418 if (ret) 419 goto on_error; 420 421 /* trigger read */ 422 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 423 if (ret) { 424 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 425 ret); 426 goto on_error; 427 } 428 429 ret = lan9303_switch_wait_for_completion(chip); 430 if (ret) 431 goto on_error; 432 433 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 434 if (ret) 435 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret); 436 on_error: 437 mutex_unlock(&chip->indirect_mutex); 438 return ret; 439 } 440 441 static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum, 442 u32 val, u32 mask) 443 { 444 int ret; 445 u32 reg; 446 447 ret = lan9303_read_switch_reg(chip, regnum, ®); 448 if (ret) 449 return ret; 450 451 reg = (reg & ~mask) | val; 452 453 return lan9303_write_switch_reg(chip, regnum, reg); 454 } 455 456 static int lan9303_write_switch_port(struct lan9303 *chip, int port, 457 u16 regnum, u32 val) 458 { 459 return lan9303_write_switch_reg( 460 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 461 } 462 463 static int lan9303_read_switch_port(struct lan9303 *chip, int port, 464 u16 regnum, u32 *val) 465 { 466 return lan9303_read_switch_reg( 467 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 468 } 469 470 static int lan9303_detect_phy_setup(struct lan9303 *chip) 471 { 472 int reg; 473 474 /* Calculate chip->phy_addr_base: 475 * Depending on the 'phy_addr_sel_strap' setting, the three phys are 476 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the 477 * 'phy_addr_sel_strap' setting directly, so we need a test, which 478 * configuration is active: 479 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0 480 * and the IDs are 0-1-2, else it contains something different from 481 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3. 482 * 0xffff is returned on MDIO read with no response. 483 */ 484 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES); 485 if (reg < 0) { 486 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg); 487 return reg; 488 } 489 490 chip->phy_addr_base = reg != 0 && reg != 0xffff; 491 492 dev_dbg(chip->dev, "Phy setup '%s' detected\n", 493 chip->phy_addr_base ? "1-2-3" : "0-1-2"); 494 495 return 0; 496 } 497 498 /* Map ALR-port bits to port bitmap, and back */ 499 static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 }; 500 static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 }; 501 502 /* Return pointer to first free ALR cache entry, return NULL if none */ 503 static struct lan9303_alr_cache_entry * 504 lan9303_alr_cache_find_free(struct lan9303 *chip) 505 { 506 int i; 507 struct lan9303_alr_cache_entry *entr = chip->alr_cache; 508 509 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) 510 if (entr->port_map == 0) 511 return entr; 512 513 return NULL; 514 } 515 516 /* Return pointer to ALR cache entry matching MAC address */ 517 static struct lan9303_alr_cache_entry * 518 lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr) 519 { 520 int i; 521 struct lan9303_alr_cache_entry *entr = chip->alr_cache; 522 523 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1, 524 "ether_addr_equal require u16 alignment"); 525 526 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) 527 if (ether_addr_equal(entr->mac_addr, mac_addr)) 528 return entr; 529 530 return NULL; 531 } 532 533 static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask) 534 { 535 int i; 536 537 for (i = 0; i < 25; i++) { 538 u32 reg; 539 540 lan9303_read_switch_reg(chip, regno, ®); 541 if (!(reg & mask)) 542 return 0; 543 usleep_range(1000, 2000); 544 } 545 546 return -ETIMEDOUT; 547 } 548 549 static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1) 550 { 551 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0); 552 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1); 553 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 554 LAN9303_ALR_CMD_MAKE_ENTRY); 555 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND); 556 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 557 558 return 0; 559 } 560 561 typedef int alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1, 562 int portmap, void *ctx); 563 564 static int lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx) 565 { 566 int ret = 0, i; 567 568 mutex_lock(&chip->alr_mutex); 569 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 570 LAN9303_ALR_CMD_GET_FIRST); 571 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 572 573 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) { 574 u32 dat0, dat1; 575 int alrport, portmap; 576 577 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0); 578 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1); 579 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL) 580 break; 581 582 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >> 583 LAN9303_ALR_DAT1_PORT_BITOFFS; 584 portmap = alrport_2_portmap[alrport]; 585 586 ret = cb(chip, dat0, dat1, portmap, ctx); 587 if (ret) 588 break; 589 590 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 591 LAN9303_ALR_CMD_GET_NEXT); 592 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 593 } 594 mutex_unlock(&chip->alr_mutex); 595 596 return ret; 597 } 598 599 static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6]) 600 { 601 mac[0] = (dat0 >> 0) & 0xff; 602 mac[1] = (dat0 >> 8) & 0xff; 603 mac[2] = (dat0 >> 16) & 0xff; 604 mac[3] = (dat0 >> 24) & 0xff; 605 mac[4] = (dat1 >> 0) & 0xff; 606 mac[5] = (dat1 >> 8) & 0xff; 607 } 608 609 struct del_port_learned_ctx { 610 int port; 611 }; 612 613 /* Clear learned (non-static) entry on given port */ 614 static int alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0, 615 u32 dat1, int portmap, void *ctx) 616 { 617 struct del_port_learned_ctx *del_ctx = ctx; 618 int port = del_ctx->port; 619 620 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC)) 621 return 0; 622 623 /* learned entries has only one port, we can just delete */ 624 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */ 625 lan9303_alr_make_entry_raw(chip, dat0, dat1); 626 627 return 0; 628 } 629 630 struct port_fdb_dump_ctx { 631 int port; 632 void *data; 633 dsa_fdb_dump_cb_t *cb; 634 }; 635 636 static int alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0, 637 u32 dat1, int portmap, void *ctx) 638 { 639 struct port_fdb_dump_ctx *dump_ctx = ctx; 640 u8 mac[ETH_ALEN]; 641 bool is_static; 642 643 if ((BIT(dump_ctx->port) & portmap) == 0) 644 return 0; 645 646 alr_reg_to_mac(dat0, dat1, mac); 647 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC); 648 return dump_ctx->cb(mac, 0, is_static, dump_ctx->data); 649 } 650 651 /* Set a static ALR entry. Delete entry if port_map is zero */ 652 static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac, 653 u8 port_map, bool stp_override) 654 { 655 u32 dat0, dat1, alr_port; 656 657 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map); 658 dat1 = LAN9303_ALR_DAT1_STATIC; 659 if (port_map) 660 dat1 |= LAN9303_ALR_DAT1_VALID; 661 /* otherwise no ports: delete entry */ 662 if (stp_override) 663 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID; 664 665 alr_port = portmap_2_alrport[port_map & 7]; 666 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK; 667 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS; 668 669 dat0 = 0; 670 dat0 |= (mac[0] << 0); 671 dat0 |= (mac[1] << 8); 672 dat0 |= (mac[2] << 16); 673 dat0 |= (mac[3] << 24); 674 675 dat1 |= (mac[4] << 0); 676 dat1 |= (mac[5] << 8); 677 678 lan9303_alr_make_entry_raw(chip, dat0, dat1); 679 } 680 681 /* Add port to static ALR entry, create new static entry if needed */ 682 static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port, 683 bool stp_override) 684 { 685 struct lan9303_alr_cache_entry *entr; 686 687 mutex_lock(&chip->alr_mutex); 688 entr = lan9303_alr_cache_find_mac(chip, mac); 689 if (!entr) { /*New entry */ 690 entr = lan9303_alr_cache_find_free(chip); 691 if (!entr) { 692 mutex_unlock(&chip->alr_mutex); 693 return -ENOSPC; 694 } 695 ether_addr_copy(entr->mac_addr, mac); 696 } 697 entr->port_map |= BIT(port); 698 entr->stp_override = stp_override; 699 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override); 700 mutex_unlock(&chip->alr_mutex); 701 702 return 0; 703 } 704 705 /* Delete static port from ALR entry, delete entry if last port */ 706 static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port) 707 { 708 struct lan9303_alr_cache_entry *entr; 709 710 mutex_lock(&chip->alr_mutex); 711 entr = lan9303_alr_cache_find_mac(chip, mac); 712 if (!entr) 713 goto out; /* no static entry found */ 714 715 entr->port_map &= ~BIT(port); 716 if (entr->port_map == 0) /* zero means its free again */ 717 eth_zero_addr(entr->mac_addr); 718 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override); 719 720 out: 721 mutex_unlock(&chip->alr_mutex); 722 return 0; 723 } 724 725 static int lan9303_disable_processing_port(struct lan9303 *chip, 726 unsigned int port) 727 { 728 int ret; 729 730 /* disable RX, but keep register reset default values else */ 731 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 732 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES); 733 if (ret) 734 return ret; 735 736 /* disable TX, but keep register reset default values else */ 737 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 738 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 739 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE); 740 } 741 742 static int lan9303_enable_processing_port(struct lan9303 *chip, 743 unsigned int port) 744 { 745 int ret; 746 747 /* enable RX and keep register reset default values else */ 748 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 749 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES | 750 LAN9303_MAC_RX_CFG_X_RX_ENABLE); 751 if (ret) 752 return ret; 753 754 /* enable TX and keep register reset default values else */ 755 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 756 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 757 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE | 758 LAN9303_MAC_TX_CFG_X_TX_ENABLE); 759 } 760 761 /* forward special tagged packets from port 0 to port 1 *or* port 2 */ 762 static int lan9303_setup_tagging(struct lan9303 *chip) 763 { 764 int ret; 765 u32 val; 766 /* enable defining the destination port via special VLAN tagging 767 * for port 0 768 */ 769 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE, 770 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN); 771 if (ret) 772 return ret; 773 774 /* tag incoming packets at port 1 and 2 on their way to port 0 to be 775 * able to discover their source port 776 */ 777 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0; 778 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val); 779 } 780 781 /* We want a special working switch: 782 * - do not forward packets between port 1 and 2 783 * - forward everything from port 1 to port 0 784 * - forward everything from port 2 to port 0 785 */ 786 static int lan9303_separate_ports(struct lan9303 *chip) 787 { 788 int ret; 789 790 lan9303_alr_del_port(chip, eth_stp_addr, 0); 791 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 792 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 | 793 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 | 794 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 | 795 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING | 796 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL); 797 if (ret) 798 return ret; 799 800 /* prevent port 1 and 2 from forwarding packets by their own */ 801 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 802 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 | 803 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 | 804 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2); 805 } 806 807 static void lan9303_bridge_ports(struct lan9303 *chip) 808 { 809 /* ports bridged: remove mirroring */ 810 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 811 LAN9303_SWE_PORT_MIRROR_DISABLED); 812 813 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 814 chip->swe_port_state); 815 lan9303_alr_add_port(chip, eth_stp_addr, 0, true); 816 } 817 818 static void lan9303_handle_reset(struct lan9303 *chip) 819 { 820 if (!chip->reset_gpio) 821 return; 822 823 if (chip->reset_duration != 0) 824 msleep(chip->reset_duration); 825 826 /* release (deassert) reset and activate the device */ 827 gpiod_set_value_cansleep(chip->reset_gpio, 0); 828 } 829 830 /* stop processing packets for all ports */ 831 static int lan9303_disable_processing(struct lan9303 *chip) 832 { 833 int p; 834 835 for (p = 1; p < LAN9303_NUM_PORTS; p++) { 836 int ret = lan9303_disable_processing_port(chip, p); 837 838 if (ret) 839 return ret; 840 } 841 842 return 0; 843 } 844 845 static int lan9303_check_device(struct lan9303 *chip) 846 { 847 int ret; 848 u32 reg; 849 850 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®); 851 if (ret) { 852 dev_err(chip->dev, "failed to read chip revision register: %d\n", 853 ret); 854 if (!chip->reset_gpio) { 855 dev_dbg(chip->dev, 856 "hint: maybe failed due to missing reset GPIO\n"); 857 } 858 return ret; 859 } 860 861 if ((reg >> 16) != LAN9303_CHIP_ID) { 862 dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n", 863 reg >> 16); 864 return -ENODEV; 865 } 866 867 /* The default state of the LAN9303 device is to forward packets between 868 * all ports (if not configured differently by an external EEPROM). 869 * The initial state of a DSA device must be forwarding packets only 870 * between the external and the internal ports and no forwarding 871 * between the external ports. In preparation we stop packet handling 872 * at all for now until the LAN9303 device is re-programmed accordingly. 873 */ 874 ret = lan9303_disable_processing(chip); 875 if (ret) 876 dev_warn(chip->dev, "failed to disable switching %d\n", ret); 877 878 dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff); 879 880 ret = lan9303_detect_phy_setup(chip); 881 if (ret) { 882 dev_err(chip->dev, 883 "failed to discover phy bootstrap setup: %d\n", ret); 884 return ret; 885 } 886 887 return 0; 888 } 889 890 /* ---------------------------- DSA -----------------------------------*/ 891 892 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds, 893 int port, 894 enum dsa_tag_protocol mp) 895 { 896 return DSA_TAG_PROTO_LAN9303; 897 } 898 899 static int lan9303_setup(struct dsa_switch *ds) 900 { 901 struct lan9303 *chip = ds->priv; 902 int ret; 903 904 /* Make sure that port 0 is the cpu port */ 905 if (!dsa_is_cpu_port(ds, 0)) { 906 dev_err(chip->dev, "port 0 is not the CPU port\n"); 907 return -EINVAL; 908 } 909 910 ret = lan9303_setup_tagging(chip); 911 if (ret) 912 dev_err(chip->dev, "failed to setup port tagging %d\n", ret); 913 914 ret = lan9303_separate_ports(chip); 915 if (ret) 916 dev_err(chip->dev, "failed to separate ports %d\n", ret); 917 918 ret = lan9303_enable_processing_port(chip, 0); 919 if (ret) 920 dev_err(chip->dev, "failed to re-enable switching %d\n", ret); 921 922 /* Trap IGMP to port 0 */ 923 ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG, 924 LAN9303_SWE_GLB_INGR_IGMP_TRAP | 925 LAN9303_SWE_GLB_INGR_IGMP_PORT(0), 926 LAN9303_SWE_GLB_INGR_IGMP_PORT(1) | 927 LAN9303_SWE_GLB_INGR_IGMP_PORT(2)); 928 if (ret) 929 dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret); 930 931 return 0; 932 } 933 934 struct lan9303_mib_desc { 935 unsigned int offset; /* offset of first MAC */ 936 const char *name; 937 }; 938 939 static const struct lan9303_mib_desc lan9303_mib[] = { 940 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", }, 941 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", }, 942 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", }, 943 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", }, 944 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", }, 945 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", }, 946 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", }, 947 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", }, 948 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", }, 949 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", }, 950 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", }, 951 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", }, 952 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", }, 953 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", }, 954 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", }, 955 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", }, 956 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", }, 957 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", }, 958 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", }, 959 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", }, 960 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", }, 961 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", }, 962 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", }, 963 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", }, 964 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", }, 965 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", }, 966 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", }, 967 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", }, 968 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", }, 969 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", }, 970 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", }, 971 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", }, 972 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", }, 973 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", }, 974 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", }, 975 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", }, 976 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", }, 977 }; 978 979 static void lan9303_get_strings(struct dsa_switch *ds, int port, 980 u32 stringset, uint8_t *data) 981 { 982 unsigned int u; 983 984 if (stringset != ETH_SS_STATS) 985 return; 986 987 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 988 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name, 989 ETH_GSTRING_LEN); 990 } 991 } 992 993 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port, 994 uint64_t *data) 995 { 996 struct lan9303 *chip = ds->priv; 997 unsigned int u; 998 999 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 1000 u32 reg; 1001 int ret; 1002 1003 ret = lan9303_read_switch_port( 1004 chip, port, lan9303_mib[u].offset, ®); 1005 1006 if (ret) 1007 dev_warn(chip->dev, "Reading status port %d reg %u failed\n", 1008 port, lan9303_mib[u].offset); 1009 data[u] = reg; 1010 } 1011 } 1012 1013 static int lan9303_get_sset_count(struct dsa_switch *ds, int port, int sset) 1014 { 1015 if (sset != ETH_SS_STATS) 1016 return 0; 1017 1018 return ARRAY_SIZE(lan9303_mib); 1019 } 1020 1021 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum) 1022 { 1023 struct lan9303 *chip = ds->priv; 1024 int phy_base = chip->phy_addr_base; 1025 1026 if (phy == phy_base) 1027 return lan9303_virt_phy_reg_read(chip, regnum); 1028 if (phy > phy_base + 2) 1029 return -ENODEV; 1030 1031 return chip->ops->phy_read(chip, phy, regnum); 1032 } 1033 1034 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum, 1035 u16 val) 1036 { 1037 struct lan9303 *chip = ds->priv; 1038 int phy_base = chip->phy_addr_base; 1039 1040 if (phy == phy_base) 1041 return lan9303_virt_phy_reg_write(chip, regnum, val); 1042 if (phy > phy_base + 2) 1043 return -ENODEV; 1044 1045 return chip->ops->phy_write(chip, phy, regnum, val); 1046 } 1047 1048 static void lan9303_adjust_link(struct dsa_switch *ds, int port, 1049 struct phy_device *phydev) 1050 { 1051 struct lan9303 *chip = ds->priv; 1052 int ctl; 1053 1054 if (!phy_is_pseudo_fixed_link(phydev)) 1055 return; 1056 1057 ctl = lan9303_phy_read(ds, port, MII_BMCR); 1058 1059 ctl &= ~BMCR_ANENABLE; 1060 1061 if (phydev->speed == SPEED_100) 1062 ctl |= BMCR_SPEED100; 1063 else if (phydev->speed == SPEED_10) 1064 ctl &= ~BMCR_SPEED100; 1065 else 1066 dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed); 1067 1068 if (phydev->duplex == DUPLEX_FULL) 1069 ctl |= BMCR_FULLDPLX; 1070 else 1071 ctl &= ~BMCR_FULLDPLX; 1072 1073 lan9303_phy_write(ds, port, MII_BMCR, ctl); 1074 1075 if (port == chip->phy_addr_base) { 1076 /* Virtual Phy: Remove Turbo 200Mbit mode */ 1077 lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl); 1078 1079 ctl &= ~LAN9303_VIRT_SPECIAL_TURBO; 1080 regmap_write(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, ctl); 1081 } 1082 } 1083 1084 static int lan9303_port_enable(struct dsa_switch *ds, int port, 1085 struct phy_device *phy) 1086 { 1087 struct dsa_port *dp = dsa_to_port(ds, port); 1088 struct lan9303 *chip = ds->priv; 1089 1090 if (!dsa_port_is_user(dp)) 1091 return 0; 1092 1093 vlan_vid_add(dp->cpu_dp->master, htons(ETH_P_8021Q), port); 1094 1095 return lan9303_enable_processing_port(chip, port); 1096 } 1097 1098 static void lan9303_port_disable(struct dsa_switch *ds, int port) 1099 { 1100 struct dsa_port *dp = dsa_to_port(ds, port); 1101 struct lan9303 *chip = ds->priv; 1102 1103 if (!dsa_port_is_user(dp)) 1104 return; 1105 1106 vlan_vid_del(dp->cpu_dp->master, htons(ETH_P_8021Q), port); 1107 1108 lan9303_disable_processing_port(chip, port); 1109 lan9303_phy_write(ds, chip->phy_addr_base + port, MII_BMCR, BMCR_PDOWN); 1110 } 1111 1112 static int lan9303_port_bridge_join(struct dsa_switch *ds, int port, 1113 struct dsa_bridge bridge, 1114 bool *tx_fwd_offload, 1115 struct netlink_ext_ack *extack) 1116 { 1117 struct lan9303 *chip = ds->priv; 1118 1119 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); 1120 if (dsa_port_bridge_same(dsa_to_port(ds, 1), dsa_to_port(ds, 2))) { 1121 lan9303_bridge_ports(chip); 1122 chip->is_bridged = true; /* unleash stp_state_set() */ 1123 } 1124 1125 return 0; 1126 } 1127 1128 static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port, 1129 struct dsa_bridge bridge) 1130 { 1131 struct lan9303 *chip = ds->priv; 1132 1133 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); 1134 if (chip->is_bridged) { 1135 lan9303_separate_ports(chip); 1136 chip->is_bridged = false; 1137 } 1138 } 1139 1140 static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port, 1141 u8 state) 1142 { 1143 int portmask, portstate; 1144 struct lan9303 *chip = ds->priv; 1145 1146 dev_dbg(chip->dev, "%s(port %d, state %d)\n", 1147 __func__, port, state); 1148 1149 switch (state) { 1150 case BR_STATE_DISABLED: 1151 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; 1152 break; 1153 case BR_STATE_BLOCKING: 1154 case BR_STATE_LISTENING: 1155 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0; 1156 break; 1157 case BR_STATE_LEARNING: 1158 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0; 1159 break; 1160 case BR_STATE_FORWARDING: 1161 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0; 1162 break; 1163 default: 1164 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; 1165 dev_err(chip->dev, "unknown stp state: port %d, state %d\n", 1166 port, state); 1167 } 1168 1169 portmask = 0x3 << (port * 2); 1170 portstate <<= (port * 2); 1171 1172 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate; 1173 1174 if (chip->is_bridged) 1175 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 1176 chip->swe_port_state); 1177 /* else: touching SWE_PORT_STATE would break port separation */ 1178 } 1179 1180 static void lan9303_port_fast_age(struct dsa_switch *ds, int port) 1181 { 1182 struct lan9303 *chip = ds->priv; 1183 struct del_port_learned_ctx del_ctx = { 1184 .port = port, 1185 }; 1186 1187 dev_dbg(chip->dev, "%s(%d)\n", __func__, port); 1188 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx); 1189 } 1190 1191 static int lan9303_port_fdb_add(struct dsa_switch *ds, int port, 1192 const unsigned char *addr, u16 vid, 1193 struct dsa_db db) 1194 { 1195 struct lan9303 *chip = ds->priv; 1196 1197 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); 1198 if (vid) 1199 return -EOPNOTSUPP; 1200 1201 return lan9303_alr_add_port(chip, addr, port, false); 1202 } 1203 1204 static int lan9303_port_fdb_del(struct dsa_switch *ds, int port, 1205 const unsigned char *addr, u16 vid, 1206 struct dsa_db db) 1207 { 1208 struct lan9303 *chip = ds->priv; 1209 1210 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); 1211 if (vid) 1212 return -EOPNOTSUPP; 1213 lan9303_alr_del_port(chip, addr, port); 1214 1215 return 0; 1216 } 1217 1218 static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port, 1219 dsa_fdb_dump_cb_t *cb, void *data) 1220 { 1221 struct lan9303 *chip = ds->priv; 1222 struct port_fdb_dump_ctx dump_ctx = { 1223 .port = port, 1224 .data = data, 1225 .cb = cb, 1226 }; 1227 1228 dev_dbg(chip->dev, "%s(%d)\n", __func__, port); 1229 return lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx); 1230 } 1231 1232 static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port, 1233 const struct switchdev_obj_port_mdb *mdb) 1234 { 1235 struct lan9303 *chip = ds->priv; 1236 1237 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1238 mdb->vid); 1239 if (mdb->vid) 1240 return -EOPNOTSUPP; 1241 if (lan9303_alr_cache_find_mac(chip, mdb->addr)) 1242 return 0; 1243 if (!lan9303_alr_cache_find_free(chip)) 1244 return -ENOSPC; 1245 1246 return 0; 1247 } 1248 1249 static int lan9303_port_mdb_add(struct dsa_switch *ds, int port, 1250 const struct switchdev_obj_port_mdb *mdb, 1251 struct dsa_db db) 1252 { 1253 struct lan9303 *chip = ds->priv; 1254 int err; 1255 1256 err = lan9303_port_mdb_prepare(ds, port, mdb); 1257 if (err) 1258 return err; 1259 1260 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1261 mdb->vid); 1262 return lan9303_alr_add_port(chip, mdb->addr, port, false); 1263 } 1264 1265 static int lan9303_port_mdb_del(struct dsa_switch *ds, int port, 1266 const struct switchdev_obj_port_mdb *mdb, 1267 struct dsa_db db) 1268 { 1269 struct lan9303 *chip = ds->priv; 1270 1271 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1272 mdb->vid); 1273 if (mdb->vid) 1274 return -EOPNOTSUPP; 1275 lan9303_alr_del_port(chip, mdb->addr, port); 1276 1277 return 0; 1278 } 1279 1280 static const struct dsa_switch_ops lan9303_switch_ops = { 1281 .get_tag_protocol = lan9303_get_tag_protocol, 1282 .setup = lan9303_setup, 1283 .get_strings = lan9303_get_strings, 1284 .phy_read = lan9303_phy_read, 1285 .phy_write = lan9303_phy_write, 1286 .adjust_link = lan9303_adjust_link, 1287 .get_ethtool_stats = lan9303_get_ethtool_stats, 1288 .get_sset_count = lan9303_get_sset_count, 1289 .port_enable = lan9303_port_enable, 1290 .port_disable = lan9303_port_disable, 1291 .port_bridge_join = lan9303_port_bridge_join, 1292 .port_bridge_leave = lan9303_port_bridge_leave, 1293 .port_stp_state_set = lan9303_port_stp_state_set, 1294 .port_fast_age = lan9303_port_fast_age, 1295 .port_fdb_add = lan9303_port_fdb_add, 1296 .port_fdb_del = lan9303_port_fdb_del, 1297 .port_fdb_dump = lan9303_port_fdb_dump, 1298 .port_mdb_add = lan9303_port_mdb_add, 1299 .port_mdb_del = lan9303_port_mdb_del, 1300 }; 1301 1302 static int lan9303_register_switch(struct lan9303 *chip) 1303 { 1304 int base; 1305 1306 chip->ds = devm_kzalloc(chip->dev, sizeof(*chip->ds), GFP_KERNEL); 1307 if (!chip->ds) 1308 return -ENOMEM; 1309 1310 chip->ds->dev = chip->dev; 1311 chip->ds->num_ports = LAN9303_NUM_PORTS; 1312 chip->ds->priv = chip; 1313 chip->ds->ops = &lan9303_switch_ops; 1314 base = chip->phy_addr_base; 1315 chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base); 1316 1317 return dsa_register_switch(chip->ds); 1318 } 1319 1320 static int lan9303_probe_reset_gpio(struct lan9303 *chip, 1321 struct device_node *np) 1322 { 1323 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset", 1324 GPIOD_OUT_HIGH); 1325 if (IS_ERR(chip->reset_gpio)) 1326 return PTR_ERR(chip->reset_gpio); 1327 1328 if (!chip->reset_gpio) { 1329 dev_dbg(chip->dev, "No reset GPIO defined\n"); 1330 return 0; 1331 } 1332 1333 chip->reset_duration = 200; 1334 1335 if (np) { 1336 of_property_read_u32(np, "reset-duration", 1337 &chip->reset_duration); 1338 } else { 1339 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n"); 1340 } 1341 1342 /* A sane reset duration should not be longer than 1s */ 1343 if (chip->reset_duration > 1000) 1344 chip->reset_duration = 1000; 1345 1346 return 0; 1347 } 1348 1349 int lan9303_probe(struct lan9303 *chip, struct device_node *np) 1350 { 1351 int ret; 1352 1353 mutex_init(&chip->indirect_mutex); 1354 mutex_init(&chip->alr_mutex); 1355 1356 ret = lan9303_probe_reset_gpio(chip, np); 1357 if (ret) 1358 return ret; 1359 1360 lan9303_handle_reset(chip); 1361 1362 ret = lan9303_check_device(chip); 1363 if (ret) 1364 return ret; 1365 1366 ret = lan9303_register_switch(chip); 1367 if (ret) { 1368 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret); 1369 return ret; 1370 } 1371 1372 return 0; 1373 } 1374 EXPORT_SYMBOL(lan9303_probe); 1375 1376 int lan9303_remove(struct lan9303 *chip) 1377 { 1378 int rc; 1379 1380 rc = lan9303_disable_processing(chip); 1381 if (rc != 0) 1382 dev_warn(chip->dev, "shutting down failed\n"); 1383 1384 dsa_unregister_switch(chip->ds); 1385 1386 /* assert reset to the whole device to prevent it from doing anything */ 1387 gpiod_set_value_cansleep(chip->reset_gpio, 1); 1388 gpiod_unexport(chip->reset_gpio); 1389 1390 return 0; 1391 } 1392 EXPORT_SYMBOL(lan9303_remove); 1393 1394 void lan9303_shutdown(struct lan9303 *chip) 1395 { 1396 dsa_switch_shutdown(chip->ds); 1397 } 1398 EXPORT_SYMBOL(lan9303_shutdown); 1399 1400 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>"); 1401 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch"); 1402 MODULE_LICENSE("GPL v2"); 1403