1 /* 2 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/regmap.h> 18 #include <linux/mutex.h> 19 #include <linux/mii.h> 20 21 #include "lan9303.h" 22 23 #define LAN9303_NUM_PORTS 3 24 25 /* 13.2 System Control and Status Registers 26 * Multiply register number by 4 to get address offset. 27 */ 28 #define LAN9303_CHIP_REV 0x14 29 # define LAN9303_CHIP_ID 0x9303 30 #define LAN9303_IRQ_CFG 0x15 31 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8) 32 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4) 33 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0) 34 #define LAN9303_INT_STS 0x16 35 # define LAN9303_INT_STS_PHY_INT2 BIT(27) 36 # define LAN9303_INT_STS_PHY_INT1 BIT(26) 37 #define LAN9303_INT_EN 0x17 38 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27) 39 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26) 40 #define LAN9303_HW_CFG 0x1D 41 # define LAN9303_HW_CFG_READY BIT(27) 42 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26) 43 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25) 44 #define LAN9303_PMI_DATA 0x29 45 #define LAN9303_PMI_ACCESS 0x2A 46 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11) 47 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6) 48 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0) 49 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1) 50 #define LAN9303_MANUAL_FC_1 0x68 51 #define LAN9303_MANUAL_FC_2 0x69 52 #define LAN9303_MANUAL_FC_0 0x6a 53 #define LAN9303_SWITCH_CSR_DATA 0x6b 54 #define LAN9303_SWITCH_CSR_CMD 0x6c 55 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31) 56 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30) 57 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16)) 58 #define LAN9303_VIRT_PHY_BASE 0x70 59 #define LAN9303_VIRT_SPECIAL_CTRL 0x77 60 61 /*13.4 Switch Fabric Control and Status Registers 62 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA. 63 */ 64 #define LAN9303_SW_DEV_ID 0x0000 65 #define LAN9303_SW_RESET 0x0001 66 #define LAN9303_SW_RESET_RESET BIT(0) 67 #define LAN9303_SW_IMR 0x0004 68 #define LAN9303_SW_IPR 0x0005 69 #define LAN9303_MAC_VER_ID_0 0x0400 70 #define LAN9303_MAC_RX_CFG_0 0x0401 71 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1) 72 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0) 73 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410 74 #define LAN9303_MAC_RX_64_CNT_0 0x0411 75 #define LAN9303_MAC_RX_127_CNT_0 0x0412 76 #define LAN9303_MAC_RX_255_CNT_0 0x413 77 #define LAN9303_MAC_RX_511_CNT_0 0x0414 78 #define LAN9303_MAC_RX_1023_CNT_0 0x0415 79 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416 80 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417 81 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418 82 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419 83 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a 84 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b 85 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c 86 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d 87 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e 88 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f 89 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420 90 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421 91 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422 92 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423 93 94 #define LAN9303_MAC_TX_CFG_0 0x0440 95 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2) 96 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1) 97 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0) 98 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451 99 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452 100 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453 101 #define LAN9303_MAC_TX_64_CNT_0 0x0454 102 #define LAN9303_MAC_TX_127_CNT_0 0x0455 103 #define LAN9303_MAC_TX_255_CNT_0 0x0456 104 #define LAN9303_MAC_TX_511_CNT_0 0x0457 105 #define LAN9303_MAC_TX_1023_CNT_0 0x0458 106 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459 107 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a 108 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c 109 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d 110 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e 111 #define LAN9303_MAC_TX_LATECOL_0 0x045f 112 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460 113 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461 114 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462 115 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463 116 117 #define LAN9303_MAC_VER_ID_1 0x0800 118 #define LAN9303_MAC_RX_CFG_1 0x0801 119 #define LAN9303_MAC_TX_CFG_1 0x0840 120 #define LAN9303_MAC_VER_ID_2 0x0c00 121 #define LAN9303_MAC_RX_CFG_2 0x0c01 122 #define LAN9303_MAC_TX_CFG_2 0x0c40 123 #define LAN9303_SWE_ALR_CMD 0x1800 124 #define LAN9303_SWE_VLAN_CMD 0x180b 125 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5) 126 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4) 127 #define LAN9303_SWE_VLAN_WR_DATA 0x180c 128 #define LAN9303_SWE_VLAN_RD_DATA 0x180e 129 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17) 130 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16) 131 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15) 132 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14) 133 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13) 134 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12) 135 #define LAN9303_SWE_VLAN_CMD_STS 0x1810 136 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840 137 #define LAN9303_SWE_PORT_STATE 0x1843 138 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0) 139 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5) 140 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4) 141 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0) 142 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3) 143 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2) 144 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0) 145 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1) 146 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0) 147 #define LAN9303_SWE_PORT_MIRROR 0x1846 148 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8) 149 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7) 150 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6) 151 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5) 152 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4) 153 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3) 154 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2) 155 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1) 156 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0) 157 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847 158 #define LAN9303_BM_CFG 0x1c00 159 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c 160 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16)) 161 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8)) 162 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0)) 163 164 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0)) 165 166 /* the built-in PHYs are of type LAN911X */ 167 #define MII_LAN911X_SPECIAL_MODES 0x12 168 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f 169 170 static const struct regmap_range lan9303_valid_regs[] = { 171 regmap_reg_range(0x14, 0x17), /* misc, interrupt */ 172 regmap_reg_range(0x19, 0x19), /* endian test */ 173 regmap_reg_range(0x1d, 0x1d), /* hardware config */ 174 regmap_reg_range(0x23, 0x24), /* general purpose timer */ 175 regmap_reg_range(0x27, 0x27), /* counter */ 176 regmap_reg_range(0x29, 0x2a), /* PMI index regs */ 177 regmap_reg_range(0x68, 0x6a), /* flow control */ 178 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */ 179 regmap_reg_range(0x6d, 0x6f), /* misc */ 180 regmap_reg_range(0x70, 0x77), /* virtual phy */ 181 regmap_reg_range(0x78, 0x7a), /* GPIO */ 182 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */ 183 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */ 184 }; 185 186 static const struct regmap_range lan9303_reserved_ranges[] = { 187 regmap_reg_range(0x00, 0x13), 188 regmap_reg_range(0x18, 0x18), 189 regmap_reg_range(0x1a, 0x1c), 190 regmap_reg_range(0x1e, 0x22), 191 regmap_reg_range(0x25, 0x26), 192 regmap_reg_range(0x28, 0x28), 193 regmap_reg_range(0x2b, 0x67), 194 regmap_reg_range(0x7b, 0x7b), 195 regmap_reg_range(0x7f, 0x7f), 196 regmap_reg_range(0xb8, 0xff), 197 }; 198 199 const struct regmap_access_table lan9303_register_set = { 200 .yes_ranges = lan9303_valid_regs, 201 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs), 202 .no_ranges = lan9303_reserved_ranges, 203 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges), 204 }; 205 EXPORT_SYMBOL(lan9303_register_set); 206 207 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg) 208 { 209 int ret, i; 210 211 /* we can lose arbitration for the I2C case, because the device 212 * tries to detect and read an external EEPROM after reset and acts as 213 * a master on the shared I2C bus itself. This conflicts with our 214 * attempts to access the device as a slave at the same moment. 215 */ 216 for (i = 0; i < 5; i++) { 217 ret = regmap_read(regmap, offset, reg); 218 if (!ret) 219 return 0; 220 if (ret != -EAGAIN) 221 break; 222 msleep(500); 223 } 224 225 return -EIO; 226 } 227 228 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum) 229 { 230 int ret; 231 u32 val; 232 233 if (regnum > MII_EXPANSION) 234 return -EINVAL; 235 236 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val); 237 if (ret) 238 return ret; 239 240 return val & 0xffff; 241 } 242 243 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val) 244 { 245 if (regnum > MII_EXPANSION) 246 return -EINVAL; 247 248 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val); 249 } 250 251 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip) 252 { 253 int ret, i; 254 u32 reg; 255 256 for (i = 0; i < 25; i++) { 257 ret = lan9303_read(chip->regmap, LAN9303_PMI_ACCESS, ®); 258 if (ret) { 259 dev_err(chip->dev, 260 "Failed to read pmi access status: %d\n", ret); 261 return ret; 262 } 263 if (!(reg & LAN9303_PMI_ACCESS_MII_BUSY)) 264 return 0; 265 msleep(1); 266 } 267 268 return -EIO; 269 } 270 271 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum) 272 { 273 int ret; 274 u32 val; 275 276 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 277 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 278 279 mutex_lock(&chip->indirect_mutex); 280 281 ret = lan9303_indirect_phy_wait_for_completion(chip); 282 if (ret) 283 goto on_error; 284 285 /* start the MII read cycle */ 286 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val); 287 if (ret) 288 goto on_error; 289 290 ret = lan9303_indirect_phy_wait_for_completion(chip); 291 if (ret) 292 goto on_error; 293 294 /* read the result of this operation */ 295 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val); 296 if (ret) 297 goto on_error; 298 299 mutex_unlock(&chip->indirect_mutex); 300 301 return val & 0xffff; 302 303 on_error: 304 mutex_unlock(&chip->indirect_mutex); 305 return ret; 306 } 307 308 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr, 309 int regnum, u16 val) 310 { 311 int ret; 312 u32 reg; 313 314 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 315 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 316 reg |= LAN9303_PMI_ACCESS_MII_WRITE; 317 318 mutex_lock(&chip->indirect_mutex); 319 320 ret = lan9303_indirect_phy_wait_for_completion(chip); 321 if (ret) 322 goto on_error; 323 324 /* write the data first... */ 325 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val); 326 if (ret) 327 goto on_error; 328 329 /* ...then start the MII write cycle */ 330 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg); 331 332 on_error: 333 mutex_unlock(&chip->indirect_mutex); 334 return ret; 335 } 336 337 const struct lan9303_phy_ops lan9303_indirect_phy_ops = { 338 .phy_read = lan9303_indirect_phy_read, 339 .phy_write = lan9303_indirect_phy_write, 340 }; 341 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops); 342 343 static int lan9303_switch_wait_for_completion(struct lan9303 *chip) 344 { 345 int ret, i; 346 u32 reg; 347 348 for (i = 0; i < 25; i++) { 349 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_CMD, ®); 350 if (ret) { 351 dev_err(chip->dev, 352 "Failed to read csr command status: %d\n", ret); 353 return ret; 354 } 355 if (!(reg & LAN9303_SWITCH_CSR_CMD_BUSY)) 356 return 0; 357 msleep(1); 358 } 359 360 return -EIO; 361 } 362 363 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val) 364 { 365 u32 reg; 366 int ret; 367 368 reg = regnum; 369 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 370 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 371 372 mutex_lock(&chip->indirect_mutex); 373 374 ret = lan9303_switch_wait_for_completion(chip); 375 if (ret) 376 goto on_error; 377 378 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 379 if (ret) { 380 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret); 381 goto on_error; 382 } 383 384 /* trigger write */ 385 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 386 if (ret) 387 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 388 ret); 389 390 on_error: 391 mutex_unlock(&chip->indirect_mutex); 392 return ret; 393 } 394 395 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val) 396 { 397 u32 reg; 398 int ret; 399 400 reg = regnum; 401 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 402 reg |= LAN9303_SWITCH_CSR_CMD_RW; 403 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 404 405 mutex_lock(&chip->indirect_mutex); 406 407 ret = lan9303_switch_wait_for_completion(chip); 408 if (ret) 409 goto on_error; 410 411 /* trigger read */ 412 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 413 if (ret) { 414 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 415 ret); 416 goto on_error; 417 } 418 419 ret = lan9303_switch_wait_for_completion(chip); 420 if (ret) 421 goto on_error; 422 423 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 424 if (ret) 425 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret); 426 on_error: 427 mutex_unlock(&chip->indirect_mutex); 428 return ret; 429 } 430 431 static int lan9303_write_switch_port(struct lan9303 *chip, int port, 432 u16 regnum, u32 val) 433 { 434 return lan9303_write_switch_reg( 435 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 436 } 437 438 static int lan9303_read_switch_port(struct lan9303 *chip, int port, 439 u16 regnum, u32 *val) 440 { 441 return lan9303_read_switch_reg( 442 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 443 } 444 445 static int lan9303_detect_phy_setup(struct lan9303 *chip) 446 { 447 int reg; 448 449 /* depending on the 'phy_addr_sel_strap' setting, the three phys are 450 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the 451 * 'phy_addr_sel_strap' setting directly, so we need a test, which 452 * configuration is active: 453 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0 454 * and the IDs are 0-1-2, else it contains something different from 455 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3. 456 * 0xffff is returned on MDIO read with no response. 457 */ 458 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES); 459 if (reg < 0) { 460 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg); 461 return reg; 462 } 463 464 if ((reg != 0) && (reg != 0xffff)) 465 chip->phy_addr_sel_strap = 1; 466 else 467 chip->phy_addr_sel_strap = 0; 468 469 dev_dbg(chip->dev, "Phy setup '%s' detected\n", 470 chip->phy_addr_sel_strap ? "1-2-3" : "0-1-2"); 471 472 return 0; 473 } 474 475 static int lan9303_disable_processing_port(struct lan9303 *chip, 476 unsigned int port) 477 { 478 int ret; 479 480 /* disable RX, but keep register reset default values else */ 481 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 482 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES); 483 if (ret) 484 return ret; 485 486 /* disable TX, but keep register reset default values else */ 487 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 488 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 489 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE); 490 } 491 492 static int lan9303_enable_processing_port(struct lan9303 *chip, 493 unsigned int port) 494 { 495 int ret; 496 497 /* enable RX and keep register reset default values else */ 498 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 499 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES | 500 LAN9303_MAC_RX_CFG_X_RX_ENABLE); 501 if (ret) 502 return ret; 503 504 /* enable TX and keep register reset default values else */ 505 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 506 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 507 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE | 508 LAN9303_MAC_TX_CFG_X_TX_ENABLE); 509 } 510 511 /* We want a special working switch: 512 * - do not forward packets between port 1 and 2 513 * - forward everything from port 1 to port 0 514 * - forward everything from port 2 to port 0 515 * - forward special tagged packets from port 0 to port 1 *or* port 2 516 */ 517 static int lan9303_separate_ports(struct lan9303 *chip) 518 { 519 int ret; 520 521 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 522 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 | 523 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 | 524 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 | 525 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING | 526 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL); 527 if (ret) 528 return ret; 529 530 /* enable defining the destination port via special VLAN tagging 531 * for port 0 532 */ 533 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE, 534 0x03); 535 if (ret) 536 return ret; 537 538 /* tag incoming packets at port 1 and 2 on their way to port 0 to be 539 * able to discover their source port 540 */ 541 ret = lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, 542 LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0); 543 if (ret) 544 return ret; 545 546 /* prevent port 1 and 2 from forwarding packets by their own */ 547 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 548 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 | 549 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 | 550 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2); 551 } 552 553 static int lan9303_handle_reset(struct lan9303 *chip) 554 { 555 if (!chip->reset_gpio) 556 return 0; 557 558 if (chip->reset_duration != 0) 559 msleep(chip->reset_duration); 560 561 /* release (deassert) reset and activate the device */ 562 gpiod_set_value_cansleep(chip->reset_gpio, 0); 563 564 return 0; 565 } 566 567 /* stop processing packets for all ports */ 568 static int lan9303_disable_processing(struct lan9303 *chip) 569 { 570 int p; 571 572 for (p = 0; p < LAN9303_NUM_PORTS; p++) { 573 int ret = lan9303_disable_processing_port(chip, p); 574 575 if (ret) 576 return ret; 577 } 578 579 return 0; 580 } 581 582 static int lan9303_check_device(struct lan9303 *chip) 583 { 584 int ret; 585 u32 reg; 586 587 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®); 588 if (ret) { 589 dev_err(chip->dev, "failed to read chip revision register: %d\n", 590 ret); 591 if (!chip->reset_gpio) { 592 dev_dbg(chip->dev, 593 "hint: maybe failed due to missing reset GPIO\n"); 594 } 595 return ret; 596 } 597 598 if ((reg >> 16) != LAN9303_CHIP_ID) { 599 dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n", 600 reg >> 16); 601 return ret; 602 } 603 604 /* The default state of the LAN9303 device is to forward packets between 605 * all ports (if not configured differently by an external EEPROM). 606 * The initial state of a DSA device must be forwarding packets only 607 * between the external and the internal ports and no forwarding 608 * between the external ports. In preparation we stop packet handling 609 * at all for now until the LAN9303 device is re-programmed accordingly. 610 */ 611 ret = lan9303_disable_processing(chip); 612 if (ret) 613 dev_warn(chip->dev, "failed to disable switching %d\n", ret); 614 615 dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff); 616 617 ret = lan9303_detect_phy_setup(chip); 618 if (ret) { 619 dev_err(chip->dev, 620 "failed to discover phy bootstrap setup: %d\n", ret); 621 return ret; 622 } 623 624 return 0; 625 } 626 627 /* ---------------------------- DSA -----------------------------------*/ 628 629 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds) 630 { 631 return DSA_TAG_PROTO_LAN9303; 632 } 633 634 static int lan9303_setup(struct dsa_switch *ds) 635 { 636 struct lan9303 *chip = ds->priv; 637 int ret; 638 639 /* Make sure that port 0 is the cpu port */ 640 if (!dsa_is_cpu_port(ds, 0)) { 641 dev_err(chip->dev, "port 0 is not the CPU port\n"); 642 return -EINVAL; 643 } 644 645 ret = lan9303_separate_ports(chip); 646 if (ret) 647 dev_err(chip->dev, "failed to separate ports %d\n", ret); 648 649 ret = lan9303_enable_processing_port(chip, 0); 650 if (ret) 651 dev_err(chip->dev, "failed to re-enable switching %d\n", ret); 652 653 return 0; 654 } 655 656 struct lan9303_mib_desc { 657 unsigned int offset; /* offset of first MAC */ 658 const char *name; 659 }; 660 661 static const struct lan9303_mib_desc lan9303_mib[] = { 662 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", }, 663 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", }, 664 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", }, 665 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", }, 666 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", }, 667 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", }, 668 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", }, 669 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", }, 670 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", }, 671 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", }, 672 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", }, 673 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", }, 674 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", }, 675 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", }, 676 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", }, 677 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", }, 678 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", }, 679 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", }, 680 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", }, 681 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", }, 682 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", }, 683 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", }, 684 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", }, 685 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", }, 686 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", }, 687 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", }, 688 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", }, 689 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", }, 690 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", }, 691 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", }, 692 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", }, 693 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", }, 694 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", }, 695 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", }, 696 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", }, 697 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", }, 698 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", }, 699 }; 700 701 static void lan9303_get_strings(struct dsa_switch *ds, int port, uint8_t *data) 702 { 703 unsigned int u; 704 705 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 706 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name, 707 ETH_GSTRING_LEN); 708 } 709 } 710 711 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port, 712 uint64_t *data) 713 { 714 struct lan9303 *chip = ds->priv; 715 unsigned int u; 716 717 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 718 u32 reg; 719 int ret; 720 721 ret = lan9303_read_switch_port( 722 chip, port, lan9303_mib[u].offset, ®); 723 724 if (ret) 725 dev_warn(chip->dev, "Reading status port %d reg %u failed\n", 726 port, lan9303_mib[u].offset); 727 data[u] = reg; 728 } 729 } 730 731 static int lan9303_get_sset_count(struct dsa_switch *ds) 732 { 733 return ARRAY_SIZE(lan9303_mib); 734 } 735 736 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum) 737 { 738 struct lan9303 *chip = ds->priv; 739 int phy_base = chip->phy_addr_sel_strap; 740 741 if (phy == phy_base) 742 return lan9303_virt_phy_reg_read(chip, regnum); 743 if (phy > phy_base + 2) 744 return -ENODEV; 745 746 return chip->ops->phy_read(chip, phy, regnum); 747 } 748 749 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum, 750 u16 val) 751 { 752 struct lan9303 *chip = ds->priv; 753 int phy_base = chip->phy_addr_sel_strap; 754 755 if (phy == phy_base) 756 return lan9303_virt_phy_reg_write(chip, regnum, val); 757 if (phy > phy_base + 2) 758 return -ENODEV; 759 760 return chip->ops->phy_write(chip, phy, regnum, val); 761 } 762 763 static int lan9303_port_enable(struct dsa_switch *ds, int port, 764 struct phy_device *phy) 765 { 766 struct lan9303 *chip = ds->priv; 767 768 /* enable internal packet processing */ 769 switch (port) { 770 case 1: 771 case 2: 772 return lan9303_enable_processing_port(chip, port); 773 default: 774 dev_dbg(chip->dev, 775 "Error: request to power up invalid port %d\n", port); 776 } 777 778 return -ENODEV; 779 } 780 781 static void lan9303_port_disable(struct dsa_switch *ds, int port, 782 struct phy_device *phy) 783 { 784 struct lan9303 *chip = ds->priv; 785 786 /* disable internal packet processing */ 787 switch (port) { 788 case 1: 789 case 2: 790 lan9303_disable_processing_port(chip, port); 791 lan9303_phy_write(ds, chip->phy_addr_sel_strap + port, 792 MII_BMCR, BMCR_PDOWN); 793 break; 794 default: 795 dev_dbg(chip->dev, 796 "Error: request to power down invalid port %d\n", port); 797 } 798 } 799 800 static const struct dsa_switch_ops lan9303_switch_ops = { 801 .get_tag_protocol = lan9303_get_tag_protocol, 802 .setup = lan9303_setup, 803 .get_strings = lan9303_get_strings, 804 .phy_read = lan9303_phy_read, 805 .phy_write = lan9303_phy_write, 806 .get_ethtool_stats = lan9303_get_ethtool_stats, 807 .get_sset_count = lan9303_get_sset_count, 808 .port_enable = lan9303_port_enable, 809 .port_disable = lan9303_port_disable, 810 }; 811 812 static int lan9303_register_switch(struct lan9303 *chip) 813 { 814 chip->ds = dsa_switch_alloc(chip->dev, LAN9303_NUM_PORTS); 815 if (!chip->ds) 816 return -ENOMEM; 817 818 chip->ds->priv = chip; 819 chip->ds->ops = &lan9303_switch_ops; 820 chip->ds->phys_mii_mask = chip->phy_addr_sel_strap ? 0xe : 0x7; 821 822 return dsa_register_switch(chip->ds); 823 } 824 825 static void lan9303_probe_reset_gpio(struct lan9303 *chip, 826 struct device_node *np) 827 { 828 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset", 829 GPIOD_OUT_LOW); 830 831 if (!chip->reset_gpio) { 832 dev_dbg(chip->dev, "No reset GPIO defined\n"); 833 return; 834 } 835 836 chip->reset_duration = 200; 837 838 if (np) { 839 of_property_read_u32(np, "reset-duration", 840 &chip->reset_duration); 841 } else { 842 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n"); 843 } 844 845 /* A sane reset duration should not be longer than 1s */ 846 if (chip->reset_duration > 1000) 847 chip->reset_duration = 1000; 848 } 849 850 int lan9303_probe(struct lan9303 *chip, struct device_node *np) 851 { 852 int ret; 853 854 mutex_init(&chip->indirect_mutex); 855 856 lan9303_probe_reset_gpio(chip, np); 857 858 ret = lan9303_handle_reset(chip); 859 if (ret) 860 return ret; 861 862 ret = lan9303_check_device(chip); 863 if (ret) 864 return ret; 865 866 ret = lan9303_register_switch(chip); 867 if (ret) { 868 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret); 869 return ret; 870 } 871 872 return 0; 873 } 874 EXPORT_SYMBOL(lan9303_probe); 875 876 int lan9303_remove(struct lan9303 *chip) 877 { 878 int rc; 879 880 rc = lan9303_disable_processing(chip); 881 if (rc != 0) 882 dev_warn(chip->dev, "shutting down failed\n"); 883 884 dsa_unregister_switch(chip->ds); 885 886 /* assert reset to the whole device to prevent it from doing anything */ 887 gpiod_set_value_cansleep(chip->reset_gpio, 1); 888 gpiod_unexport(chip->reset_gpio); 889 890 return 0; 891 } 892 EXPORT_SYMBOL(lan9303_remove); 893 894 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>"); 895 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch"); 896 MODULE_LICENSE("GPL v2"); 897