1 /* 2 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/regmap.h> 18 #include <linux/mutex.h> 19 #include <linux/mii.h> 20 #include <linux/phy.h> 21 #include <linux/if_bridge.h> 22 #include <linux/etherdevice.h> 23 24 #include "lan9303.h" 25 26 #define LAN9303_NUM_PORTS 3 27 28 /* 13.2 System Control and Status Registers 29 * Multiply register number by 4 to get address offset. 30 */ 31 #define LAN9303_CHIP_REV 0x14 32 # define LAN9303_CHIP_ID 0x9303 33 #define LAN9303_IRQ_CFG 0x15 34 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8) 35 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4) 36 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0) 37 #define LAN9303_INT_STS 0x16 38 # define LAN9303_INT_STS_PHY_INT2 BIT(27) 39 # define LAN9303_INT_STS_PHY_INT1 BIT(26) 40 #define LAN9303_INT_EN 0x17 41 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27) 42 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26) 43 #define LAN9303_HW_CFG 0x1D 44 # define LAN9303_HW_CFG_READY BIT(27) 45 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26) 46 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25) 47 #define LAN9303_PMI_DATA 0x29 48 #define LAN9303_PMI_ACCESS 0x2A 49 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11) 50 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6) 51 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0) 52 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1) 53 #define LAN9303_MANUAL_FC_1 0x68 54 #define LAN9303_MANUAL_FC_2 0x69 55 #define LAN9303_MANUAL_FC_0 0x6a 56 #define LAN9303_SWITCH_CSR_DATA 0x6b 57 #define LAN9303_SWITCH_CSR_CMD 0x6c 58 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31) 59 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30) 60 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16)) 61 #define LAN9303_VIRT_PHY_BASE 0x70 62 #define LAN9303_VIRT_SPECIAL_CTRL 0x77 63 #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/ 64 65 /*13.4 Switch Fabric Control and Status Registers 66 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA. 67 */ 68 #define LAN9303_SW_DEV_ID 0x0000 69 #define LAN9303_SW_RESET 0x0001 70 #define LAN9303_SW_RESET_RESET BIT(0) 71 #define LAN9303_SW_IMR 0x0004 72 #define LAN9303_SW_IPR 0x0005 73 #define LAN9303_MAC_VER_ID_0 0x0400 74 #define LAN9303_MAC_RX_CFG_0 0x0401 75 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1) 76 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0) 77 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410 78 #define LAN9303_MAC_RX_64_CNT_0 0x0411 79 #define LAN9303_MAC_RX_127_CNT_0 0x0412 80 #define LAN9303_MAC_RX_255_CNT_0 0x413 81 #define LAN9303_MAC_RX_511_CNT_0 0x0414 82 #define LAN9303_MAC_RX_1023_CNT_0 0x0415 83 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416 84 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417 85 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418 86 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419 87 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a 88 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b 89 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c 90 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d 91 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e 92 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f 93 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420 94 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421 95 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422 96 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423 97 98 #define LAN9303_MAC_TX_CFG_0 0x0440 99 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2) 100 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1) 101 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0) 102 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451 103 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452 104 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453 105 #define LAN9303_MAC_TX_64_CNT_0 0x0454 106 #define LAN9303_MAC_TX_127_CNT_0 0x0455 107 #define LAN9303_MAC_TX_255_CNT_0 0x0456 108 #define LAN9303_MAC_TX_511_CNT_0 0x0457 109 #define LAN9303_MAC_TX_1023_CNT_0 0x0458 110 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459 111 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a 112 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c 113 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d 114 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e 115 #define LAN9303_MAC_TX_LATECOL_0 0x045f 116 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460 117 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461 118 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462 119 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463 120 121 #define LAN9303_MAC_VER_ID_1 0x0800 122 #define LAN9303_MAC_RX_CFG_1 0x0801 123 #define LAN9303_MAC_TX_CFG_1 0x0840 124 #define LAN9303_MAC_VER_ID_2 0x0c00 125 #define LAN9303_MAC_RX_CFG_2 0x0c01 126 #define LAN9303_MAC_TX_CFG_2 0x0c40 127 #define LAN9303_SWE_ALR_CMD 0x1800 128 # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2) 129 # define LAN9303_ALR_CMD_GET_FIRST BIT(1) 130 # define LAN9303_ALR_CMD_GET_NEXT BIT(0) 131 #define LAN9303_SWE_ALR_WR_DAT_0 0x1801 132 #define LAN9303_SWE_ALR_WR_DAT_1 0x1802 133 # define LAN9303_ALR_DAT1_VALID BIT(26) 134 # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25) 135 # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25) 136 # define LAN9303_ALR_DAT1_STATIC BIT(24) 137 # define LAN9303_ALR_DAT1_PORT_BITOFFS 16 138 # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS) 139 #define LAN9303_SWE_ALR_RD_DAT_0 0x1805 140 #define LAN9303_SWE_ALR_RD_DAT_1 0x1806 141 #define LAN9303_SWE_ALR_CMD_STS 0x1808 142 # define ALR_STS_MAKE_PEND BIT(0) 143 #define LAN9303_SWE_VLAN_CMD 0x180b 144 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5) 145 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4) 146 #define LAN9303_SWE_VLAN_WR_DATA 0x180c 147 #define LAN9303_SWE_VLAN_RD_DATA 0x180e 148 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17) 149 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16) 150 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15) 151 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14) 152 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13) 153 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12) 154 #define LAN9303_SWE_VLAN_CMD_STS 0x1810 155 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840 156 #define LAN9303_SWE_PORT_STATE 0x1843 157 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0) 158 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5) 159 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4) 160 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0) 161 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3) 162 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2) 163 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0) 164 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1) 165 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0) 166 # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3) 167 #define LAN9303_SWE_PORT_MIRROR 0x1846 168 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8) 169 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7) 170 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6) 171 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5) 172 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4) 173 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3) 174 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2) 175 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1) 176 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0) 177 # define LAN9303_SWE_PORT_MIRROR_DISABLED 0 178 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847 179 #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3 180 #define LAN9303_BM_CFG 0x1c00 181 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c 182 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16)) 183 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8)) 184 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0)) 185 186 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0)) 187 188 /* the built-in PHYs are of type LAN911X */ 189 #define MII_LAN911X_SPECIAL_MODES 0x12 190 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f 191 192 static const struct regmap_range lan9303_valid_regs[] = { 193 regmap_reg_range(0x14, 0x17), /* misc, interrupt */ 194 regmap_reg_range(0x19, 0x19), /* endian test */ 195 regmap_reg_range(0x1d, 0x1d), /* hardware config */ 196 regmap_reg_range(0x23, 0x24), /* general purpose timer */ 197 regmap_reg_range(0x27, 0x27), /* counter */ 198 regmap_reg_range(0x29, 0x2a), /* PMI index regs */ 199 regmap_reg_range(0x68, 0x6a), /* flow control */ 200 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */ 201 regmap_reg_range(0x6d, 0x6f), /* misc */ 202 regmap_reg_range(0x70, 0x77), /* virtual phy */ 203 regmap_reg_range(0x78, 0x7a), /* GPIO */ 204 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */ 205 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */ 206 }; 207 208 static const struct regmap_range lan9303_reserved_ranges[] = { 209 regmap_reg_range(0x00, 0x13), 210 regmap_reg_range(0x18, 0x18), 211 regmap_reg_range(0x1a, 0x1c), 212 regmap_reg_range(0x1e, 0x22), 213 regmap_reg_range(0x25, 0x26), 214 regmap_reg_range(0x28, 0x28), 215 regmap_reg_range(0x2b, 0x67), 216 regmap_reg_range(0x7b, 0x7b), 217 regmap_reg_range(0x7f, 0x7f), 218 regmap_reg_range(0xb8, 0xff), 219 }; 220 221 const struct regmap_access_table lan9303_register_set = { 222 .yes_ranges = lan9303_valid_regs, 223 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs), 224 .no_ranges = lan9303_reserved_ranges, 225 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges), 226 }; 227 EXPORT_SYMBOL(lan9303_register_set); 228 229 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg) 230 { 231 int ret, i; 232 233 /* we can lose arbitration for the I2C case, because the device 234 * tries to detect and read an external EEPROM after reset and acts as 235 * a master on the shared I2C bus itself. This conflicts with our 236 * attempts to access the device as a slave at the same moment. 237 */ 238 for (i = 0; i < 5; i++) { 239 ret = regmap_read(regmap, offset, reg); 240 if (!ret) 241 return 0; 242 if (ret != -EAGAIN) 243 break; 244 msleep(500); 245 } 246 247 return -EIO; 248 } 249 250 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum) 251 { 252 int ret; 253 u32 val; 254 255 if (regnum > MII_EXPANSION) 256 return -EINVAL; 257 258 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val); 259 if (ret) 260 return ret; 261 262 return val & 0xffff; 263 } 264 265 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val) 266 { 267 if (regnum > MII_EXPANSION) 268 return -EINVAL; 269 270 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val); 271 } 272 273 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip) 274 { 275 int ret, i; 276 u32 reg; 277 278 for (i = 0; i < 25; i++) { 279 ret = lan9303_read(chip->regmap, LAN9303_PMI_ACCESS, ®); 280 if (ret) { 281 dev_err(chip->dev, 282 "Failed to read pmi access status: %d\n", ret); 283 return ret; 284 } 285 if (!(reg & LAN9303_PMI_ACCESS_MII_BUSY)) 286 return 0; 287 usleep_range(1000, 2000); 288 } 289 290 return -EIO; 291 } 292 293 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum) 294 { 295 int ret; 296 u32 val; 297 298 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 299 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 300 301 mutex_lock(&chip->indirect_mutex); 302 303 ret = lan9303_indirect_phy_wait_for_completion(chip); 304 if (ret) 305 goto on_error; 306 307 /* start the MII read cycle */ 308 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val); 309 if (ret) 310 goto on_error; 311 312 ret = lan9303_indirect_phy_wait_for_completion(chip); 313 if (ret) 314 goto on_error; 315 316 /* read the result of this operation */ 317 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val); 318 if (ret) 319 goto on_error; 320 321 mutex_unlock(&chip->indirect_mutex); 322 323 return val & 0xffff; 324 325 on_error: 326 mutex_unlock(&chip->indirect_mutex); 327 return ret; 328 } 329 330 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr, 331 int regnum, u16 val) 332 { 333 int ret; 334 u32 reg; 335 336 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 337 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 338 reg |= LAN9303_PMI_ACCESS_MII_WRITE; 339 340 mutex_lock(&chip->indirect_mutex); 341 342 ret = lan9303_indirect_phy_wait_for_completion(chip); 343 if (ret) 344 goto on_error; 345 346 /* write the data first... */ 347 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val); 348 if (ret) 349 goto on_error; 350 351 /* ...then start the MII write cycle */ 352 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg); 353 354 on_error: 355 mutex_unlock(&chip->indirect_mutex); 356 return ret; 357 } 358 359 const struct lan9303_phy_ops lan9303_indirect_phy_ops = { 360 .phy_read = lan9303_indirect_phy_read, 361 .phy_write = lan9303_indirect_phy_write, 362 }; 363 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops); 364 365 static int lan9303_switch_wait_for_completion(struct lan9303 *chip) 366 { 367 int ret, i; 368 u32 reg; 369 370 for (i = 0; i < 25; i++) { 371 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_CMD, ®); 372 if (ret) { 373 dev_err(chip->dev, 374 "Failed to read csr command status: %d\n", ret); 375 return ret; 376 } 377 if (!(reg & LAN9303_SWITCH_CSR_CMD_BUSY)) 378 return 0; 379 usleep_range(1000, 2000); 380 } 381 382 return -EIO; 383 } 384 385 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val) 386 { 387 u32 reg; 388 int ret; 389 390 reg = regnum; 391 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 392 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 393 394 mutex_lock(&chip->indirect_mutex); 395 396 ret = lan9303_switch_wait_for_completion(chip); 397 if (ret) 398 goto on_error; 399 400 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 401 if (ret) { 402 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret); 403 goto on_error; 404 } 405 406 /* trigger write */ 407 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 408 if (ret) 409 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 410 ret); 411 412 on_error: 413 mutex_unlock(&chip->indirect_mutex); 414 return ret; 415 } 416 417 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val) 418 { 419 u32 reg; 420 int ret; 421 422 reg = regnum; 423 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 424 reg |= LAN9303_SWITCH_CSR_CMD_RW; 425 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 426 427 mutex_lock(&chip->indirect_mutex); 428 429 ret = lan9303_switch_wait_for_completion(chip); 430 if (ret) 431 goto on_error; 432 433 /* trigger read */ 434 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 435 if (ret) { 436 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 437 ret); 438 goto on_error; 439 } 440 441 ret = lan9303_switch_wait_for_completion(chip); 442 if (ret) 443 goto on_error; 444 445 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 446 if (ret) 447 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret); 448 on_error: 449 mutex_unlock(&chip->indirect_mutex); 450 return ret; 451 } 452 453 static int lan9303_write_switch_port(struct lan9303 *chip, int port, 454 u16 regnum, u32 val) 455 { 456 return lan9303_write_switch_reg( 457 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 458 } 459 460 static int lan9303_read_switch_port(struct lan9303 *chip, int port, 461 u16 regnum, u32 *val) 462 { 463 return lan9303_read_switch_reg( 464 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 465 } 466 467 static int lan9303_detect_phy_setup(struct lan9303 *chip) 468 { 469 int reg; 470 471 /* depending on the 'phy_addr_sel_strap' setting, the three phys are 472 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the 473 * 'phy_addr_sel_strap' setting directly, so we need a test, which 474 * configuration is active: 475 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0 476 * and the IDs are 0-1-2, else it contains something different from 477 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3. 478 * 0xffff is returned on MDIO read with no response. 479 */ 480 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES); 481 if (reg < 0) { 482 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg); 483 return reg; 484 } 485 486 if ((reg != 0) && (reg != 0xffff)) 487 chip->phy_addr_sel_strap = 1; 488 else 489 chip->phy_addr_sel_strap = 0; 490 491 dev_dbg(chip->dev, "Phy setup '%s' detected\n", 492 chip->phy_addr_sel_strap ? "1-2-3" : "0-1-2"); 493 494 return 0; 495 } 496 497 /* Map ALR-port bits to port bitmap, and back */ 498 static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 }; 499 static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 }; 500 501 /* Return pointer to first free ALR cache entry, return NULL if none */ 502 static struct lan9303_alr_cache_entry * 503 lan9303_alr_cache_find_free(struct lan9303 *chip) 504 { 505 int i; 506 struct lan9303_alr_cache_entry *entr = chip->alr_cache; 507 508 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) 509 if (entr->port_map == 0) 510 return entr; 511 512 return NULL; 513 } 514 515 /* Return pointer to ALR cache entry matching MAC address */ 516 static struct lan9303_alr_cache_entry * 517 lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr) 518 { 519 int i; 520 struct lan9303_alr_cache_entry *entr = chip->alr_cache; 521 522 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1, 523 "ether_addr_equal require u16 alignment"); 524 525 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) 526 if (ether_addr_equal(entr->mac_addr, mac_addr)) 527 return entr; 528 529 return NULL; 530 } 531 532 /* Wait a while until mask & reg == value. Otherwise return timeout. */ 533 static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, 534 int mask, char value) 535 { 536 int i; 537 538 for (i = 0; i < 0x1000; i++) { 539 u32 reg; 540 541 lan9303_read_switch_reg(chip, regno, ®); 542 if ((reg & mask) == value) 543 return 0; 544 usleep_range(1000, 2000); 545 } 546 return -ETIMEDOUT; 547 } 548 549 static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1) 550 { 551 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0); 552 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1); 553 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 554 LAN9303_ALR_CMD_MAKE_ENTRY); 555 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND, 556 0); 557 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 558 559 return 0; 560 } 561 562 typedef void alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1, 563 int portmap, void *ctx); 564 565 static void lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx) 566 { 567 int i; 568 569 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 570 LAN9303_ALR_CMD_GET_FIRST); 571 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 572 573 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) { 574 u32 dat0, dat1; 575 int alrport, portmap; 576 577 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0); 578 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1); 579 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL) 580 break; 581 582 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >> 583 LAN9303_ALR_DAT1_PORT_BITOFFS; 584 portmap = alrport_2_portmap[alrport]; 585 586 cb(chip, dat0, dat1, portmap, ctx); 587 588 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 589 LAN9303_ALR_CMD_GET_NEXT); 590 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 591 } 592 } 593 594 static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6]) 595 { 596 mac[0] = (dat0 >> 0) & 0xff; 597 mac[1] = (dat0 >> 8) & 0xff; 598 mac[2] = (dat0 >> 16) & 0xff; 599 mac[3] = (dat0 >> 24) & 0xff; 600 mac[4] = (dat1 >> 0) & 0xff; 601 mac[5] = (dat1 >> 8) & 0xff; 602 } 603 604 struct del_port_learned_ctx { 605 int port; 606 }; 607 608 /* Clear learned (non-static) entry on given port */ 609 static void alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0, 610 u32 dat1, int portmap, void *ctx) 611 { 612 struct del_port_learned_ctx *del_ctx = ctx; 613 int port = del_ctx->port; 614 615 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC)) 616 return; 617 618 /* learned entries has only one port, we can just delete */ 619 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */ 620 lan9303_alr_make_entry_raw(chip, dat0, dat1); 621 } 622 623 struct port_fdb_dump_ctx { 624 int port; 625 void *data; 626 dsa_fdb_dump_cb_t *cb; 627 }; 628 629 static void alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0, 630 u32 dat1, int portmap, void *ctx) 631 { 632 struct port_fdb_dump_ctx *dump_ctx = ctx; 633 u8 mac[ETH_ALEN]; 634 bool is_static; 635 636 if ((BIT(dump_ctx->port) & portmap) == 0) 637 return; 638 639 alr_reg_to_mac(dat0, dat1, mac); 640 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC); 641 dump_ctx->cb(mac, 0, is_static, dump_ctx->data); 642 } 643 644 /* Set a static ALR entry. Delete entry if port_map is zero */ 645 static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac, 646 u8 port_map, bool stp_override) 647 { 648 u32 dat0, dat1, alr_port; 649 650 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map); 651 dat1 = LAN9303_ALR_DAT1_STATIC; 652 if (port_map) 653 dat1 |= LAN9303_ALR_DAT1_VALID; 654 /* otherwise no ports: delete entry */ 655 if (stp_override) 656 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID; 657 658 alr_port = portmap_2_alrport[port_map & 7]; 659 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK; 660 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS; 661 662 dat0 = 0; 663 dat0 |= (mac[0] << 0); 664 dat0 |= (mac[1] << 8); 665 dat0 |= (mac[2] << 16); 666 dat0 |= (mac[3] << 24); 667 668 dat1 |= (mac[4] << 0); 669 dat1 |= (mac[5] << 8); 670 671 lan9303_alr_make_entry_raw(chip, dat0, dat1); 672 } 673 674 /* Add port to static ALR entry, create new static entry if needed */ 675 static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port, 676 bool stp_override) 677 { 678 struct lan9303_alr_cache_entry *entr; 679 680 entr = lan9303_alr_cache_find_mac(chip, mac); 681 if (!entr) { /*New entry */ 682 entr = lan9303_alr_cache_find_free(chip); 683 if (!entr) 684 return -ENOSPC; 685 ether_addr_copy(entr->mac_addr, mac); 686 } 687 entr->port_map |= BIT(port); 688 entr->stp_override = stp_override; 689 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override); 690 691 return 0; 692 } 693 694 /* Delete static port from ALR entry, delete entry if last port */ 695 static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port) 696 { 697 struct lan9303_alr_cache_entry *entr; 698 699 entr = lan9303_alr_cache_find_mac(chip, mac); 700 if (!entr) 701 return 0; /* no static entry found */ 702 703 entr->port_map &= ~BIT(port); 704 if (entr->port_map == 0) /* zero means its free again */ 705 eth_zero_addr(&entr->port_map); 706 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override); 707 708 return 0; 709 } 710 711 static int lan9303_disable_processing_port(struct lan9303 *chip, 712 unsigned int port) 713 { 714 int ret; 715 716 /* disable RX, but keep register reset default values else */ 717 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 718 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES); 719 if (ret) 720 return ret; 721 722 /* disable TX, but keep register reset default values else */ 723 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 724 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 725 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE); 726 } 727 728 static int lan9303_enable_processing_port(struct lan9303 *chip, 729 unsigned int port) 730 { 731 int ret; 732 733 /* enable RX and keep register reset default values else */ 734 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 735 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES | 736 LAN9303_MAC_RX_CFG_X_RX_ENABLE); 737 if (ret) 738 return ret; 739 740 /* enable TX and keep register reset default values else */ 741 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 742 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 743 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE | 744 LAN9303_MAC_TX_CFG_X_TX_ENABLE); 745 } 746 747 /* forward special tagged packets from port 0 to port 1 *or* port 2 */ 748 static int lan9303_setup_tagging(struct lan9303 *chip) 749 { 750 int ret; 751 u32 val; 752 /* enable defining the destination port via special VLAN tagging 753 * for port 0 754 */ 755 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE, 756 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN); 757 if (ret) 758 return ret; 759 760 /* tag incoming packets at port 1 and 2 on their way to port 0 to be 761 * able to discover their source port 762 */ 763 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0; 764 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val); 765 } 766 767 /* We want a special working switch: 768 * - do not forward packets between port 1 and 2 769 * - forward everything from port 1 to port 0 770 * - forward everything from port 2 to port 0 771 */ 772 static int lan9303_separate_ports(struct lan9303 *chip) 773 { 774 int ret; 775 776 lan9303_alr_del_port(chip, eth_stp_addr, 0); 777 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 778 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 | 779 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 | 780 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 | 781 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING | 782 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL); 783 if (ret) 784 return ret; 785 786 /* prevent port 1 and 2 from forwarding packets by their own */ 787 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 788 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 | 789 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 | 790 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2); 791 } 792 793 static void lan9303_bridge_ports(struct lan9303 *chip) 794 { 795 /* ports bridged: remove mirroring */ 796 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 797 LAN9303_SWE_PORT_MIRROR_DISABLED); 798 799 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 800 chip->swe_port_state); 801 lan9303_alr_add_port(chip, eth_stp_addr, 0, true); 802 } 803 804 static int lan9303_handle_reset(struct lan9303 *chip) 805 { 806 if (!chip->reset_gpio) 807 return 0; 808 809 if (chip->reset_duration != 0) 810 msleep(chip->reset_duration); 811 812 /* release (deassert) reset and activate the device */ 813 gpiod_set_value_cansleep(chip->reset_gpio, 0); 814 815 return 0; 816 } 817 818 /* stop processing packets for all ports */ 819 static int lan9303_disable_processing(struct lan9303 *chip) 820 { 821 int p; 822 823 for (p = 1; p < LAN9303_NUM_PORTS; p++) { 824 int ret = lan9303_disable_processing_port(chip, p); 825 826 if (ret) 827 return ret; 828 } 829 830 return 0; 831 } 832 833 static int lan9303_check_device(struct lan9303 *chip) 834 { 835 int ret; 836 u32 reg; 837 838 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®); 839 if (ret) { 840 dev_err(chip->dev, "failed to read chip revision register: %d\n", 841 ret); 842 if (!chip->reset_gpio) { 843 dev_dbg(chip->dev, 844 "hint: maybe failed due to missing reset GPIO\n"); 845 } 846 return ret; 847 } 848 849 if ((reg >> 16) != LAN9303_CHIP_ID) { 850 dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n", 851 reg >> 16); 852 return ret; 853 } 854 855 /* The default state of the LAN9303 device is to forward packets between 856 * all ports (if not configured differently by an external EEPROM). 857 * The initial state of a DSA device must be forwarding packets only 858 * between the external and the internal ports and no forwarding 859 * between the external ports. In preparation we stop packet handling 860 * at all for now until the LAN9303 device is re-programmed accordingly. 861 */ 862 ret = lan9303_disable_processing(chip); 863 if (ret) 864 dev_warn(chip->dev, "failed to disable switching %d\n", ret); 865 866 dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff); 867 868 ret = lan9303_detect_phy_setup(chip); 869 if (ret) { 870 dev_err(chip->dev, 871 "failed to discover phy bootstrap setup: %d\n", ret); 872 return ret; 873 } 874 875 return 0; 876 } 877 878 /* ---------------------------- DSA -----------------------------------*/ 879 880 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds) 881 { 882 return DSA_TAG_PROTO_LAN9303; 883 } 884 885 static int lan9303_setup(struct dsa_switch *ds) 886 { 887 struct lan9303 *chip = ds->priv; 888 int ret; 889 890 /* Make sure that port 0 is the cpu port */ 891 if (!dsa_is_cpu_port(ds, 0)) { 892 dev_err(chip->dev, "port 0 is not the CPU port\n"); 893 return -EINVAL; 894 } 895 896 ret = lan9303_setup_tagging(chip); 897 if (ret) 898 dev_err(chip->dev, "failed to setup port tagging %d\n", ret); 899 900 ret = lan9303_separate_ports(chip); 901 if (ret) 902 dev_err(chip->dev, "failed to separate ports %d\n", ret); 903 904 ret = lan9303_enable_processing_port(chip, 0); 905 if (ret) 906 dev_err(chip->dev, "failed to re-enable switching %d\n", ret); 907 908 return 0; 909 } 910 911 struct lan9303_mib_desc { 912 unsigned int offset; /* offset of first MAC */ 913 const char *name; 914 }; 915 916 static const struct lan9303_mib_desc lan9303_mib[] = { 917 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", }, 918 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", }, 919 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", }, 920 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", }, 921 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", }, 922 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", }, 923 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", }, 924 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", }, 925 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", }, 926 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", }, 927 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", }, 928 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", }, 929 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", }, 930 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", }, 931 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", }, 932 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", }, 933 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", }, 934 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", }, 935 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", }, 936 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", }, 937 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", }, 938 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", }, 939 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", }, 940 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", }, 941 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", }, 942 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", }, 943 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", }, 944 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", }, 945 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", }, 946 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", }, 947 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", }, 948 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", }, 949 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", }, 950 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", }, 951 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", }, 952 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", }, 953 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", }, 954 }; 955 956 static void lan9303_get_strings(struct dsa_switch *ds, int port, uint8_t *data) 957 { 958 unsigned int u; 959 960 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 961 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name, 962 ETH_GSTRING_LEN); 963 } 964 } 965 966 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port, 967 uint64_t *data) 968 { 969 struct lan9303 *chip = ds->priv; 970 unsigned int u; 971 972 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 973 u32 reg; 974 int ret; 975 976 ret = lan9303_read_switch_port( 977 chip, port, lan9303_mib[u].offset, ®); 978 979 if (ret) 980 dev_warn(chip->dev, "Reading status port %d reg %u failed\n", 981 port, lan9303_mib[u].offset); 982 data[u] = reg; 983 } 984 } 985 986 static int lan9303_get_sset_count(struct dsa_switch *ds) 987 { 988 return ARRAY_SIZE(lan9303_mib); 989 } 990 991 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum) 992 { 993 struct lan9303 *chip = ds->priv; 994 int phy_base = chip->phy_addr_sel_strap; 995 996 if (phy == phy_base) 997 return lan9303_virt_phy_reg_read(chip, regnum); 998 if (phy > phy_base + 2) 999 return -ENODEV; 1000 1001 return chip->ops->phy_read(chip, phy, regnum); 1002 } 1003 1004 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum, 1005 u16 val) 1006 { 1007 struct lan9303 *chip = ds->priv; 1008 int phy_base = chip->phy_addr_sel_strap; 1009 1010 if (phy == phy_base) 1011 return lan9303_virt_phy_reg_write(chip, regnum, val); 1012 if (phy > phy_base + 2) 1013 return -ENODEV; 1014 1015 return chip->ops->phy_write(chip, phy, regnum, val); 1016 } 1017 1018 static void lan9303_adjust_link(struct dsa_switch *ds, int port, 1019 struct phy_device *phydev) 1020 { 1021 struct lan9303 *chip = ds->priv; 1022 int ctl, res; 1023 1024 if (!phy_is_pseudo_fixed_link(phydev)) 1025 return; 1026 1027 ctl = lan9303_phy_read(ds, port, MII_BMCR); 1028 1029 ctl &= ~BMCR_ANENABLE; 1030 1031 if (phydev->speed == SPEED_100) 1032 ctl |= BMCR_SPEED100; 1033 else if (phydev->speed == SPEED_10) 1034 ctl &= ~BMCR_SPEED100; 1035 else 1036 dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed); 1037 1038 if (phydev->duplex == DUPLEX_FULL) 1039 ctl |= BMCR_FULLDPLX; 1040 else 1041 ctl &= ~BMCR_FULLDPLX; 1042 1043 res = lan9303_phy_write(ds, port, MII_BMCR, ctl); 1044 1045 if (port == chip->phy_addr_sel_strap) { 1046 /* Virtual Phy: Remove Turbo 200Mbit mode */ 1047 lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl); 1048 1049 ctl &= ~LAN9303_VIRT_SPECIAL_TURBO; 1050 res = regmap_write(chip->regmap, 1051 LAN9303_VIRT_SPECIAL_CTRL, ctl); 1052 } 1053 } 1054 1055 static int lan9303_port_enable(struct dsa_switch *ds, int port, 1056 struct phy_device *phy) 1057 { 1058 struct lan9303 *chip = ds->priv; 1059 1060 return lan9303_enable_processing_port(chip, port); 1061 } 1062 1063 static void lan9303_port_disable(struct dsa_switch *ds, int port, 1064 struct phy_device *phy) 1065 { 1066 struct lan9303 *chip = ds->priv; 1067 1068 lan9303_disable_processing_port(chip, port); 1069 lan9303_phy_write(ds, chip->phy_addr_sel_strap + port, 1070 MII_BMCR, BMCR_PDOWN); 1071 } 1072 1073 static int lan9303_port_bridge_join(struct dsa_switch *ds, int port, 1074 struct net_device *br) 1075 { 1076 struct lan9303 *chip = ds->priv; 1077 1078 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); 1079 if (dsa_to_port(ds, 1)->bridge_dev == dsa_to_port(ds, 2)->bridge_dev) { 1080 lan9303_bridge_ports(chip); 1081 chip->is_bridged = true; /* unleash stp_state_set() */ 1082 } 1083 1084 return 0; 1085 } 1086 1087 static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port, 1088 struct net_device *br) 1089 { 1090 struct lan9303 *chip = ds->priv; 1091 1092 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); 1093 if (chip->is_bridged) { 1094 lan9303_separate_ports(chip); 1095 chip->is_bridged = false; 1096 } 1097 } 1098 1099 static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port, 1100 u8 state) 1101 { 1102 int portmask, portstate; 1103 struct lan9303 *chip = ds->priv; 1104 1105 dev_dbg(chip->dev, "%s(port %d, state %d)\n", 1106 __func__, port, state); 1107 1108 switch (state) { 1109 case BR_STATE_DISABLED: 1110 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; 1111 break; 1112 case BR_STATE_BLOCKING: 1113 case BR_STATE_LISTENING: 1114 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0; 1115 break; 1116 case BR_STATE_LEARNING: 1117 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0; 1118 break; 1119 case BR_STATE_FORWARDING: 1120 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0; 1121 break; 1122 default: 1123 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; 1124 dev_err(chip->dev, "unknown stp state: port %d, state %d\n", 1125 port, state); 1126 } 1127 1128 portmask = 0x3 << (port * 2); 1129 portstate <<= (port * 2); 1130 1131 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate; 1132 1133 if (chip->is_bridged) 1134 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 1135 chip->swe_port_state); 1136 /* else: touching SWE_PORT_STATE would break port separation */ 1137 } 1138 1139 static void lan9303_port_fast_age(struct dsa_switch *ds, int port) 1140 { 1141 struct lan9303 *chip = ds->priv; 1142 struct del_port_learned_ctx del_ctx = { 1143 .port = port, 1144 }; 1145 1146 dev_dbg(chip->dev, "%s(%d)\n", __func__, port); 1147 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx); 1148 } 1149 1150 static int lan9303_port_fdb_add(struct dsa_switch *ds, int port, 1151 const unsigned char *addr, u16 vid) 1152 { 1153 struct lan9303 *chip = ds->priv; 1154 1155 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); 1156 if (vid) 1157 return -EOPNOTSUPP; 1158 1159 return lan9303_alr_add_port(chip, addr, port, false); 1160 } 1161 1162 static int lan9303_port_fdb_del(struct dsa_switch *ds, int port, 1163 const unsigned char *addr, u16 vid) 1164 1165 { 1166 struct lan9303 *chip = ds->priv; 1167 1168 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); 1169 if (vid) 1170 return -EOPNOTSUPP; 1171 lan9303_alr_del_port(chip, addr, port); 1172 1173 return 0; 1174 } 1175 1176 static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port, 1177 dsa_fdb_dump_cb_t *cb, void *data) 1178 { 1179 struct lan9303 *chip = ds->priv; 1180 struct port_fdb_dump_ctx dump_ctx = { 1181 .port = port, 1182 .data = data, 1183 .cb = cb, 1184 }; 1185 1186 dev_dbg(chip->dev, "%s(%d)\n", __func__, port); 1187 lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx); 1188 1189 return 0; 1190 } 1191 1192 static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port, 1193 const struct switchdev_obj_port_mdb *mdb, 1194 struct switchdev_trans *trans) 1195 { 1196 struct lan9303 *chip = ds->priv; 1197 1198 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1199 mdb->vid); 1200 if (mdb->vid) 1201 return -EOPNOTSUPP; 1202 if (lan9303_alr_cache_find_mac(chip, mdb->addr)) 1203 return 0; 1204 if (!lan9303_alr_cache_find_free(chip)) 1205 return -ENOSPC; 1206 1207 return 0; 1208 } 1209 1210 static void lan9303_port_mdb_add(struct dsa_switch *ds, int port, 1211 const struct switchdev_obj_port_mdb *mdb, 1212 struct switchdev_trans *trans) 1213 { 1214 struct lan9303 *chip = ds->priv; 1215 1216 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1217 mdb->vid); 1218 lan9303_alr_add_port(chip, mdb->addr, port, false); 1219 } 1220 1221 static int lan9303_port_mdb_del(struct dsa_switch *ds, int port, 1222 const struct switchdev_obj_port_mdb *mdb) 1223 { 1224 struct lan9303 *chip = ds->priv; 1225 1226 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1227 mdb->vid); 1228 if (mdb->vid) 1229 return -EOPNOTSUPP; 1230 lan9303_alr_del_port(chip, mdb->addr, port); 1231 1232 return 0; 1233 } 1234 1235 static const struct dsa_switch_ops lan9303_switch_ops = { 1236 .get_tag_protocol = lan9303_get_tag_protocol, 1237 .setup = lan9303_setup, 1238 .get_strings = lan9303_get_strings, 1239 .phy_read = lan9303_phy_read, 1240 .phy_write = lan9303_phy_write, 1241 .adjust_link = lan9303_adjust_link, 1242 .get_ethtool_stats = lan9303_get_ethtool_stats, 1243 .get_sset_count = lan9303_get_sset_count, 1244 .port_enable = lan9303_port_enable, 1245 .port_disable = lan9303_port_disable, 1246 .port_bridge_join = lan9303_port_bridge_join, 1247 .port_bridge_leave = lan9303_port_bridge_leave, 1248 .port_stp_state_set = lan9303_port_stp_state_set, 1249 .port_fast_age = lan9303_port_fast_age, 1250 .port_fdb_add = lan9303_port_fdb_add, 1251 .port_fdb_del = lan9303_port_fdb_del, 1252 .port_fdb_dump = lan9303_port_fdb_dump, 1253 .port_mdb_prepare = lan9303_port_mdb_prepare, 1254 .port_mdb_add = lan9303_port_mdb_add, 1255 .port_mdb_del = lan9303_port_mdb_del, 1256 }; 1257 1258 static int lan9303_register_switch(struct lan9303 *chip) 1259 { 1260 chip->ds = dsa_switch_alloc(chip->dev, LAN9303_NUM_PORTS); 1261 if (!chip->ds) 1262 return -ENOMEM; 1263 1264 chip->ds->priv = chip; 1265 chip->ds->ops = &lan9303_switch_ops; 1266 chip->ds->phys_mii_mask = chip->phy_addr_sel_strap ? 0xe : 0x7; 1267 1268 return dsa_register_switch(chip->ds); 1269 } 1270 1271 static void lan9303_probe_reset_gpio(struct lan9303 *chip, 1272 struct device_node *np) 1273 { 1274 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset", 1275 GPIOD_OUT_LOW); 1276 1277 if (!chip->reset_gpio) { 1278 dev_dbg(chip->dev, "No reset GPIO defined\n"); 1279 return; 1280 } 1281 1282 chip->reset_duration = 200; 1283 1284 if (np) { 1285 of_property_read_u32(np, "reset-duration", 1286 &chip->reset_duration); 1287 } else { 1288 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n"); 1289 } 1290 1291 /* A sane reset duration should not be longer than 1s */ 1292 if (chip->reset_duration > 1000) 1293 chip->reset_duration = 1000; 1294 } 1295 1296 int lan9303_probe(struct lan9303 *chip, struct device_node *np) 1297 { 1298 int ret; 1299 1300 mutex_init(&chip->indirect_mutex); 1301 1302 lan9303_probe_reset_gpio(chip, np); 1303 1304 ret = lan9303_handle_reset(chip); 1305 if (ret) 1306 return ret; 1307 1308 ret = lan9303_check_device(chip); 1309 if (ret) 1310 return ret; 1311 1312 ret = lan9303_register_switch(chip); 1313 if (ret) { 1314 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret); 1315 return ret; 1316 } 1317 1318 return 0; 1319 } 1320 EXPORT_SYMBOL(lan9303_probe); 1321 1322 int lan9303_remove(struct lan9303 *chip) 1323 { 1324 int rc; 1325 1326 rc = lan9303_disable_processing(chip); 1327 if (rc != 0) 1328 dev_warn(chip->dev, "shutting down failed\n"); 1329 1330 dsa_unregister_switch(chip->ds); 1331 1332 /* assert reset to the whole device to prevent it from doing anything */ 1333 gpiod_set_value_cansleep(chip->reset_gpio, 1); 1334 gpiod_unexport(chip->reset_gpio); 1335 1336 return 0; 1337 } 1338 EXPORT_SYMBOL(lan9303_remove); 1339 1340 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>"); 1341 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch"); 1342 MODULE_LICENSE("GPL v2"); 1343