1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de> 4 */ 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/regmap.h> 9 #include <linux/mutex.h> 10 #include <linux/mii.h> 11 #include <linux/phy.h> 12 #include <linux/if_bridge.h> 13 #include <linux/if_vlan.h> 14 #include <linux/etherdevice.h> 15 16 #include "lan9303.h" 17 18 #define LAN9303_NUM_PORTS 3 19 20 /* 13.2 System Control and Status Registers 21 * Multiply register number by 4 to get address offset. 22 */ 23 #define LAN9303_CHIP_REV 0x14 24 # define LAN9303_CHIP_ID 0x9303 25 # define LAN9352_CHIP_ID 0x9352 26 # define LAN9353_CHIP_ID 0x9353 27 # define LAN9354_CHIP_ID 0x9354 28 # define LAN9355_CHIP_ID 0x9355 29 #define LAN9303_IRQ_CFG 0x15 30 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8) 31 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4) 32 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0) 33 #define LAN9303_INT_STS 0x16 34 # define LAN9303_INT_STS_PHY_INT2 BIT(27) 35 # define LAN9303_INT_STS_PHY_INT1 BIT(26) 36 #define LAN9303_INT_EN 0x17 37 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27) 38 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26) 39 #define LAN9303_BYTE_ORDER 0x19 40 #define LAN9303_HW_CFG 0x1D 41 # define LAN9303_HW_CFG_READY BIT(27) 42 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26) 43 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25) 44 #define LAN9303_PMI_DATA 0x29 45 #define LAN9303_PMI_ACCESS 0x2A 46 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11) 47 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6) 48 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0) 49 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1) 50 #define LAN9303_MANUAL_FC_1 0x68 51 #define LAN9303_MANUAL_FC_2 0x69 52 #define LAN9303_MANUAL_FC_0 0x6a 53 #define LAN9303_SWITCH_CSR_DATA 0x6b 54 #define LAN9303_SWITCH_CSR_CMD 0x6c 55 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31) 56 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30) 57 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16)) 58 #define LAN9303_VIRT_PHY_BASE 0x70 59 #define LAN9303_VIRT_SPECIAL_CTRL 0x77 60 #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/ 61 62 /*13.4 Switch Fabric Control and Status Registers 63 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA. 64 */ 65 #define LAN9303_SW_DEV_ID 0x0000 66 #define LAN9303_SW_RESET 0x0001 67 #define LAN9303_SW_RESET_RESET BIT(0) 68 #define LAN9303_SW_IMR 0x0004 69 #define LAN9303_SW_IPR 0x0005 70 #define LAN9303_MAC_VER_ID_0 0x0400 71 #define LAN9303_MAC_RX_CFG_0 0x0401 72 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1) 73 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0) 74 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410 75 #define LAN9303_MAC_RX_64_CNT_0 0x0411 76 #define LAN9303_MAC_RX_127_CNT_0 0x0412 77 #define LAN9303_MAC_RX_255_CNT_0 0x413 78 #define LAN9303_MAC_RX_511_CNT_0 0x0414 79 #define LAN9303_MAC_RX_1023_CNT_0 0x0415 80 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416 81 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417 82 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418 83 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419 84 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a 85 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b 86 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c 87 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d 88 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e 89 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f 90 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420 91 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421 92 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422 93 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423 94 95 #define LAN9303_MAC_TX_CFG_0 0x0440 96 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2) 97 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1) 98 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0) 99 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451 100 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452 101 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453 102 #define LAN9303_MAC_TX_64_CNT_0 0x0454 103 #define LAN9303_MAC_TX_127_CNT_0 0x0455 104 #define LAN9303_MAC_TX_255_CNT_0 0x0456 105 #define LAN9303_MAC_TX_511_CNT_0 0x0457 106 #define LAN9303_MAC_TX_1023_CNT_0 0x0458 107 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459 108 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a 109 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c 110 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d 111 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e 112 #define LAN9303_MAC_TX_LATECOL_0 0x045f 113 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460 114 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461 115 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462 116 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463 117 118 #define LAN9303_MAC_VER_ID_1 0x0800 119 #define LAN9303_MAC_RX_CFG_1 0x0801 120 #define LAN9303_MAC_TX_CFG_1 0x0840 121 #define LAN9303_MAC_VER_ID_2 0x0c00 122 #define LAN9303_MAC_RX_CFG_2 0x0c01 123 #define LAN9303_MAC_TX_CFG_2 0x0c40 124 #define LAN9303_SWE_ALR_CMD 0x1800 125 # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2) 126 # define LAN9303_ALR_CMD_GET_FIRST BIT(1) 127 # define LAN9303_ALR_CMD_GET_NEXT BIT(0) 128 #define LAN9303_SWE_ALR_WR_DAT_0 0x1801 129 #define LAN9303_SWE_ALR_WR_DAT_1 0x1802 130 # define LAN9303_ALR_DAT1_VALID BIT(26) 131 # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25) 132 # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25) 133 # define LAN9303_ALR_DAT1_STATIC BIT(24) 134 # define LAN9303_ALR_DAT1_PORT_BITOFFS 16 135 # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS) 136 #define LAN9303_SWE_ALR_RD_DAT_0 0x1805 137 #define LAN9303_SWE_ALR_RD_DAT_1 0x1806 138 #define LAN9303_SWE_ALR_CMD_STS 0x1808 139 # define ALR_STS_MAKE_PEND BIT(0) 140 #define LAN9303_SWE_VLAN_CMD 0x180b 141 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5) 142 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4) 143 #define LAN9303_SWE_VLAN_WR_DATA 0x180c 144 #define LAN9303_SWE_VLAN_RD_DATA 0x180e 145 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17) 146 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16) 147 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15) 148 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14) 149 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13) 150 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12) 151 #define LAN9303_SWE_VLAN_CMD_STS 0x1810 152 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840 153 # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7) 154 # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p) 155 #define LAN9303_SWE_PORT_STATE 0x1843 156 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0) 157 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5) 158 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4) 159 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0) 160 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3) 161 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2) 162 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0) 163 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1) 164 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0) 165 # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3) 166 #define LAN9303_SWE_PORT_MIRROR 0x1846 167 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8) 168 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7) 169 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6) 170 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5) 171 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4) 172 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3) 173 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2) 174 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1) 175 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0) 176 # define LAN9303_SWE_PORT_MIRROR_DISABLED 0 177 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847 178 #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3 179 #define LAN9303_BM_CFG 0x1c00 180 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c 181 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16)) 182 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8)) 183 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0)) 184 185 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0)) 186 187 /* the built-in PHYs are of type LAN911X */ 188 #define MII_LAN911X_SPECIAL_MODES 0x12 189 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f 190 191 static const struct regmap_range lan9303_valid_regs[] = { 192 regmap_reg_range(0x14, 0x17), /* misc, interrupt */ 193 regmap_reg_range(0x19, 0x19), /* endian test */ 194 regmap_reg_range(0x1d, 0x1d), /* hardware config */ 195 regmap_reg_range(0x23, 0x24), /* general purpose timer */ 196 regmap_reg_range(0x27, 0x27), /* counter */ 197 regmap_reg_range(0x29, 0x2a), /* PMI index regs */ 198 regmap_reg_range(0x68, 0x6a), /* flow control */ 199 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */ 200 regmap_reg_range(0x6d, 0x6f), /* misc */ 201 regmap_reg_range(0x70, 0x77), /* virtual phy */ 202 regmap_reg_range(0x78, 0x7a), /* GPIO */ 203 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */ 204 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */ 205 }; 206 207 static const struct regmap_range lan9303_reserved_ranges[] = { 208 regmap_reg_range(0x00, 0x13), 209 regmap_reg_range(0x18, 0x18), 210 regmap_reg_range(0x1a, 0x1c), 211 regmap_reg_range(0x1e, 0x22), 212 regmap_reg_range(0x25, 0x26), 213 regmap_reg_range(0x28, 0x28), 214 regmap_reg_range(0x2b, 0x67), 215 regmap_reg_range(0x7b, 0x7b), 216 regmap_reg_range(0x7f, 0x7f), 217 regmap_reg_range(0xb8, 0xff), 218 }; 219 220 const struct regmap_access_table lan9303_register_set = { 221 .yes_ranges = lan9303_valid_regs, 222 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs), 223 .no_ranges = lan9303_reserved_ranges, 224 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges), 225 }; 226 EXPORT_SYMBOL(lan9303_register_set); 227 228 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg) 229 { 230 int ret, i; 231 232 /* we can lose arbitration for the I2C case, because the device 233 * tries to detect and read an external EEPROM after reset and acts as 234 * a master on the shared I2C bus itself. This conflicts with our 235 * attempts to access the device as a slave at the same moment. 236 */ 237 for (i = 0; i < 5; i++) { 238 ret = regmap_read(regmap, offset, reg); 239 if (!ret) 240 return 0; 241 if (ret != -EAGAIN) 242 break; 243 msleep(500); 244 } 245 246 return -EIO; 247 } 248 249 static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask) 250 { 251 int i; 252 253 for (i = 0; i < 25; i++) { 254 u32 reg; 255 int ret; 256 257 ret = lan9303_read(chip->regmap, offset, ®); 258 if (ret) { 259 dev_err(chip->dev, "%s failed to read offset %d: %d\n", 260 __func__, offset, ret); 261 return ret; 262 } 263 if (!(reg & mask)) 264 return 0; 265 usleep_range(1000, 2000); 266 } 267 268 return -ETIMEDOUT; 269 } 270 271 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum) 272 { 273 int ret; 274 u32 val; 275 276 if (regnum > MII_EXPANSION) 277 return -EINVAL; 278 279 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val); 280 if (ret) 281 return ret; 282 283 return val & 0xffff; 284 } 285 286 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val) 287 { 288 if (regnum > MII_EXPANSION) 289 return -EINVAL; 290 291 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val); 292 } 293 294 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip) 295 { 296 return lan9303_read_wait(chip, LAN9303_PMI_ACCESS, 297 LAN9303_PMI_ACCESS_MII_BUSY); 298 } 299 300 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum) 301 { 302 int ret; 303 u32 val; 304 305 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 306 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 307 308 mutex_lock(&chip->indirect_mutex); 309 310 ret = lan9303_indirect_phy_wait_for_completion(chip); 311 if (ret) 312 goto on_error; 313 314 /* start the MII read cycle */ 315 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val); 316 if (ret) 317 goto on_error; 318 319 ret = lan9303_indirect_phy_wait_for_completion(chip); 320 if (ret) 321 goto on_error; 322 323 /* read the result of this operation */ 324 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val); 325 if (ret) 326 goto on_error; 327 328 mutex_unlock(&chip->indirect_mutex); 329 330 return val & 0xffff; 331 332 on_error: 333 mutex_unlock(&chip->indirect_mutex); 334 return ret; 335 } 336 337 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr, 338 int regnum, u16 val) 339 { 340 int ret; 341 u32 reg; 342 343 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr); 344 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); 345 reg |= LAN9303_PMI_ACCESS_MII_WRITE; 346 347 mutex_lock(&chip->indirect_mutex); 348 349 ret = lan9303_indirect_phy_wait_for_completion(chip); 350 if (ret) 351 goto on_error; 352 353 /* write the data first... */ 354 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val); 355 if (ret) 356 goto on_error; 357 358 /* ...then start the MII write cycle */ 359 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg); 360 361 on_error: 362 mutex_unlock(&chip->indirect_mutex); 363 return ret; 364 } 365 366 const struct lan9303_phy_ops lan9303_indirect_phy_ops = { 367 .phy_read = lan9303_indirect_phy_read, 368 .phy_write = lan9303_indirect_phy_write, 369 }; 370 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops); 371 372 static int lan9303_switch_wait_for_completion(struct lan9303 *chip) 373 { 374 return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD, 375 LAN9303_SWITCH_CSR_CMD_BUSY); 376 } 377 378 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val) 379 { 380 u32 reg; 381 int ret; 382 383 reg = regnum; 384 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 385 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 386 387 mutex_lock(&chip->indirect_mutex); 388 389 ret = lan9303_switch_wait_for_completion(chip); 390 if (ret) 391 goto on_error; 392 393 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 394 if (ret) { 395 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret); 396 goto on_error; 397 } 398 399 /* trigger write */ 400 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 401 if (ret) 402 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 403 ret); 404 405 on_error: 406 mutex_unlock(&chip->indirect_mutex); 407 return ret; 408 } 409 410 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val) 411 { 412 u32 reg; 413 int ret; 414 415 reg = regnum; 416 reg |= LAN9303_SWITCH_CSR_CMD_LANES; 417 reg |= LAN9303_SWITCH_CSR_CMD_RW; 418 reg |= LAN9303_SWITCH_CSR_CMD_BUSY; 419 420 mutex_lock(&chip->indirect_mutex); 421 422 ret = lan9303_switch_wait_for_completion(chip); 423 if (ret) 424 goto on_error; 425 426 /* trigger read */ 427 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); 428 if (ret) { 429 dev_err(chip->dev, "Failed to write csr command reg: %d\n", 430 ret); 431 goto on_error; 432 } 433 434 ret = lan9303_switch_wait_for_completion(chip); 435 if (ret) 436 goto on_error; 437 438 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); 439 if (ret) 440 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret); 441 on_error: 442 mutex_unlock(&chip->indirect_mutex); 443 return ret; 444 } 445 446 static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum, 447 u32 val, u32 mask) 448 { 449 int ret; 450 u32 reg; 451 452 ret = lan9303_read_switch_reg(chip, regnum, ®); 453 if (ret) 454 return ret; 455 456 reg = (reg & ~mask) | val; 457 458 return lan9303_write_switch_reg(chip, regnum, reg); 459 } 460 461 static int lan9303_write_switch_port(struct lan9303 *chip, int port, 462 u16 regnum, u32 val) 463 { 464 return lan9303_write_switch_reg( 465 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 466 } 467 468 static int lan9303_read_switch_port(struct lan9303 *chip, int port, 469 u16 regnum, u32 *val) 470 { 471 return lan9303_read_switch_reg( 472 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); 473 } 474 475 static int lan9303_detect_phy_setup(struct lan9303 *chip) 476 { 477 int reg; 478 479 /* Calculate chip->phy_addr_base: 480 * Depending on the 'phy_addr_sel_strap' setting, the three phys are 481 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the 482 * 'phy_addr_sel_strap' setting directly, so we need a test, which 483 * configuration is active: 484 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0 485 * and the IDs are 0-1-2, else it contains something different from 486 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3. 487 * 0xffff is returned on MDIO read with no response. 488 */ 489 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES); 490 if (reg < 0) { 491 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg); 492 return reg; 493 } 494 495 chip->phy_addr_base = reg != 0 && reg != 0xffff; 496 497 dev_dbg(chip->dev, "Phy setup '%s' detected\n", 498 chip->phy_addr_base ? "1-2-3" : "0-1-2"); 499 500 return 0; 501 } 502 503 /* Map ALR-port bits to port bitmap, and back */ 504 static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 }; 505 static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 }; 506 507 /* Return pointer to first free ALR cache entry, return NULL if none */ 508 static struct lan9303_alr_cache_entry * 509 lan9303_alr_cache_find_free(struct lan9303 *chip) 510 { 511 int i; 512 struct lan9303_alr_cache_entry *entr = chip->alr_cache; 513 514 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) 515 if (entr->port_map == 0) 516 return entr; 517 518 return NULL; 519 } 520 521 /* Return pointer to ALR cache entry matching MAC address */ 522 static struct lan9303_alr_cache_entry * 523 lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr) 524 { 525 int i; 526 struct lan9303_alr_cache_entry *entr = chip->alr_cache; 527 528 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1, 529 "ether_addr_equal require u16 alignment"); 530 531 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) 532 if (ether_addr_equal(entr->mac_addr, mac_addr)) 533 return entr; 534 535 return NULL; 536 } 537 538 static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask) 539 { 540 int i; 541 542 for (i = 0; i < 25; i++) { 543 u32 reg; 544 545 lan9303_read_switch_reg(chip, regno, ®); 546 if (!(reg & mask)) 547 return 0; 548 usleep_range(1000, 2000); 549 } 550 551 return -ETIMEDOUT; 552 } 553 554 static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1) 555 { 556 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0); 557 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1); 558 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 559 LAN9303_ALR_CMD_MAKE_ENTRY); 560 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND); 561 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 562 563 return 0; 564 } 565 566 typedef int alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1, 567 int portmap, void *ctx); 568 569 static int lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx) 570 { 571 int ret = 0, i; 572 573 mutex_lock(&chip->alr_mutex); 574 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 575 LAN9303_ALR_CMD_GET_FIRST); 576 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 577 578 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) { 579 u32 dat0, dat1; 580 int alrport, portmap; 581 582 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0); 583 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1); 584 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL) 585 break; 586 587 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >> 588 LAN9303_ALR_DAT1_PORT_BITOFFS; 589 portmap = alrport_2_portmap[alrport]; 590 591 ret = cb(chip, dat0, dat1, portmap, ctx); 592 if (ret) 593 break; 594 595 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 596 LAN9303_ALR_CMD_GET_NEXT); 597 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); 598 } 599 mutex_unlock(&chip->alr_mutex); 600 601 return ret; 602 } 603 604 static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6]) 605 { 606 mac[0] = (dat0 >> 0) & 0xff; 607 mac[1] = (dat0 >> 8) & 0xff; 608 mac[2] = (dat0 >> 16) & 0xff; 609 mac[3] = (dat0 >> 24) & 0xff; 610 mac[4] = (dat1 >> 0) & 0xff; 611 mac[5] = (dat1 >> 8) & 0xff; 612 } 613 614 struct del_port_learned_ctx { 615 int port; 616 }; 617 618 /* Clear learned (non-static) entry on given port */ 619 static int alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0, 620 u32 dat1, int portmap, void *ctx) 621 { 622 struct del_port_learned_ctx *del_ctx = ctx; 623 int port = del_ctx->port; 624 625 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC)) 626 return 0; 627 628 /* learned entries has only one port, we can just delete */ 629 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */ 630 lan9303_alr_make_entry_raw(chip, dat0, dat1); 631 632 return 0; 633 } 634 635 struct port_fdb_dump_ctx { 636 int port; 637 void *data; 638 dsa_fdb_dump_cb_t *cb; 639 }; 640 641 static int alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0, 642 u32 dat1, int portmap, void *ctx) 643 { 644 struct port_fdb_dump_ctx *dump_ctx = ctx; 645 u8 mac[ETH_ALEN]; 646 bool is_static; 647 648 if ((BIT(dump_ctx->port) & portmap) == 0) 649 return 0; 650 651 alr_reg_to_mac(dat0, dat1, mac); 652 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC); 653 return dump_ctx->cb(mac, 0, is_static, dump_ctx->data); 654 } 655 656 /* Set a static ALR entry. Delete entry if port_map is zero */ 657 static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac, 658 u8 port_map, bool stp_override) 659 { 660 u32 dat0, dat1, alr_port; 661 662 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map); 663 dat1 = LAN9303_ALR_DAT1_STATIC; 664 if (port_map) 665 dat1 |= LAN9303_ALR_DAT1_VALID; 666 /* otherwise no ports: delete entry */ 667 if (stp_override) 668 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID; 669 670 alr_port = portmap_2_alrport[port_map & 7]; 671 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK; 672 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS; 673 674 dat0 = 0; 675 dat0 |= (mac[0] << 0); 676 dat0 |= (mac[1] << 8); 677 dat0 |= (mac[2] << 16); 678 dat0 |= (mac[3] << 24); 679 680 dat1 |= (mac[4] << 0); 681 dat1 |= (mac[5] << 8); 682 683 lan9303_alr_make_entry_raw(chip, dat0, dat1); 684 } 685 686 /* Add port to static ALR entry, create new static entry if needed */ 687 static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port, 688 bool stp_override) 689 { 690 struct lan9303_alr_cache_entry *entr; 691 692 mutex_lock(&chip->alr_mutex); 693 entr = lan9303_alr_cache_find_mac(chip, mac); 694 if (!entr) { /*New entry */ 695 entr = lan9303_alr_cache_find_free(chip); 696 if (!entr) { 697 mutex_unlock(&chip->alr_mutex); 698 return -ENOSPC; 699 } 700 ether_addr_copy(entr->mac_addr, mac); 701 } 702 entr->port_map |= BIT(port); 703 entr->stp_override = stp_override; 704 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override); 705 mutex_unlock(&chip->alr_mutex); 706 707 return 0; 708 } 709 710 /* Delete static port from ALR entry, delete entry if last port */ 711 static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port) 712 { 713 struct lan9303_alr_cache_entry *entr; 714 715 mutex_lock(&chip->alr_mutex); 716 entr = lan9303_alr_cache_find_mac(chip, mac); 717 if (!entr) 718 goto out; /* no static entry found */ 719 720 entr->port_map &= ~BIT(port); 721 if (entr->port_map == 0) /* zero means its free again */ 722 eth_zero_addr(entr->mac_addr); 723 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override); 724 725 out: 726 mutex_unlock(&chip->alr_mutex); 727 return 0; 728 } 729 730 static int lan9303_disable_processing_port(struct lan9303 *chip, 731 unsigned int port) 732 { 733 int ret; 734 735 /* disable RX, but keep register reset default values else */ 736 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 737 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES); 738 if (ret) 739 return ret; 740 741 /* disable TX, but keep register reset default values else */ 742 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 743 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 744 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE); 745 } 746 747 static int lan9303_enable_processing_port(struct lan9303 *chip, 748 unsigned int port) 749 { 750 int ret; 751 752 /* enable RX and keep register reset default values else */ 753 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, 754 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES | 755 LAN9303_MAC_RX_CFG_X_RX_ENABLE); 756 if (ret) 757 return ret; 758 759 /* enable TX and keep register reset default values else */ 760 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, 761 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | 762 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE | 763 LAN9303_MAC_TX_CFG_X_TX_ENABLE); 764 } 765 766 /* forward special tagged packets from port 0 to port 1 *or* port 2 */ 767 static int lan9303_setup_tagging(struct lan9303 *chip) 768 { 769 int ret; 770 u32 val; 771 /* enable defining the destination port via special VLAN tagging 772 * for port 0 773 */ 774 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE, 775 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN); 776 if (ret) 777 return ret; 778 779 /* tag incoming packets at port 1 and 2 on their way to port 0 to be 780 * able to discover their source port 781 */ 782 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0; 783 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val); 784 } 785 786 /* We want a special working switch: 787 * - do not forward packets between port 1 and 2 788 * - forward everything from port 1 to port 0 789 * - forward everything from port 2 to port 0 790 */ 791 static int lan9303_separate_ports(struct lan9303 *chip) 792 { 793 int ret; 794 795 lan9303_alr_del_port(chip, eth_stp_addr, 0); 796 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 797 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 | 798 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 | 799 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 | 800 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING | 801 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL); 802 if (ret) 803 return ret; 804 805 /* prevent port 1 and 2 from forwarding packets by their own */ 806 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 807 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 | 808 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 | 809 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2); 810 } 811 812 static void lan9303_bridge_ports(struct lan9303 *chip) 813 { 814 /* ports bridged: remove mirroring */ 815 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, 816 LAN9303_SWE_PORT_MIRROR_DISABLED); 817 818 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 819 chip->swe_port_state); 820 lan9303_alr_add_port(chip, eth_stp_addr, 0, true); 821 } 822 823 static void lan9303_handle_reset(struct lan9303 *chip) 824 { 825 if (!chip->reset_gpio) 826 return; 827 828 if (chip->reset_duration != 0) 829 msleep(chip->reset_duration); 830 831 /* release (deassert) reset and activate the device */ 832 gpiod_set_value_cansleep(chip->reset_gpio, 0); 833 } 834 835 /* stop processing packets for all ports */ 836 static int lan9303_disable_processing(struct lan9303 *chip) 837 { 838 int p; 839 840 for (p = 1; p < LAN9303_NUM_PORTS; p++) { 841 int ret = lan9303_disable_processing_port(chip, p); 842 843 if (ret) 844 return ret; 845 } 846 847 return 0; 848 } 849 850 static int lan9303_check_device(struct lan9303 *chip) 851 { 852 int ret; 853 u32 reg; 854 855 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®); 856 if (ret) { 857 dev_err(chip->dev, "failed to read chip revision register: %d\n", 858 ret); 859 return ret; 860 } 861 862 if (((reg >> 16) != LAN9303_CHIP_ID) && 863 ((reg >> 16) != LAN9354_CHIP_ID)) { 864 dev_err(chip->dev, "unexpected device found: LAN%4.4X\n", 865 reg >> 16); 866 return -ENODEV; 867 } 868 869 /* The default state of the LAN9303 device is to forward packets between 870 * all ports (if not configured differently by an external EEPROM). 871 * The initial state of a DSA device must be forwarding packets only 872 * between the external and the internal ports and no forwarding 873 * between the external ports. In preparation we stop packet handling 874 * at all for now until the LAN9303 device is re-programmed accordingly. 875 */ 876 ret = lan9303_disable_processing(chip); 877 if (ret) 878 dev_warn(chip->dev, "failed to disable switching %d\n", ret); 879 880 dev_info(chip->dev, "Found LAN%4.4X rev. %u\n", (reg >> 16), reg & 0xffff); 881 882 ret = lan9303_detect_phy_setup(chip); 883 if (ret) { 884 dev_err(chip->dev, 885 "failed to discover phy bootstrap setup: %d\n", ret); 886 return ret; 887 } 888 889 return 0; 890 } 891 892 /* ---------------------------- DSA -----------------------------------*/ 893 894 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds, 895 int port, 896 enum dsa_tag_protocol mp) 897 { 898 return DSA_TAG_PROTO_LAN9303; 899 } 900 901 static int lan9303_setup(struct dsa_switch *ds) 902 { 903 struct lan9303 *chip = ds->priv; 904 int ret; 905 906 /* Make sure that port 0 is the cpu port */ 907 if (!dsa_is_cpu_port(ds, 0)) { 908 dev_err(chip->dev, "port 0 is not the CPU port\n"); 909 return -EINVAL; 910 } 911 912 ret = lan9303_setup_tagging(chip); 913 if (ret) 914 dev_err(chip->dev, "failed to setup port tagging %d\n", ret); 915 916 ret = lan9303_separate_ports(chip); 917 if (ret) 918 dev_err(chip->dev, "failed to separate ports %d\n", ret); 919 920 ret = lan9303_enable_processing_port(chip, 0); 921 if (ret) 922 dev_err(chip->dev, "failed to re-enable switching %d\n", ret); 923 924 /* Trap IGMP to port 0 */ 925 ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG, 926 LAN9303_SWE_GLB_INGR_IGMP_TRAP | 927 LAN9303_SWE_GLB_INGR_IGMP_PORT(0), 928 LAN9303_SWE_GLB_INGR_IGMP_PORT(1) | 929 LAN9303_SWE_GLB_INGR_IGMP_PORT(2)); 930 if (ret) 931 dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret); 932 933 return 0; 934 } 935 936 struct lan9303_mib_desc { 937 unsigned int offset; /* offset of first MAC */ 938 const char *name; 939 }; 940 941 static const struct lan9303_mib_desc lan9303_mib[] = { 942 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", }, 943 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", }, 944 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", }, 945 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", }, 946 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", }, 947 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", }, 948 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", }, 949 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", }, 950 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", }, 951 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", }, 952 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", }, 953 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", }, 954 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", }, 955 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", }, 956 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", }, 957 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", }, 958 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", }, 959 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", }, 960 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", }, 961 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", }, 962 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", }, 963 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", }, 964 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "RxShort", }, 965 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", }, 966 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", }, 967 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", }, 968 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", }, 969 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", }, 970 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", }, 971 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", }, 972 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", }, 973 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", }, 974 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", }, 975 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", }, 976 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", }, 977 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", }, 978 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", }, 979 }; 980 981 static void lan9303_get_strings(struct dsa_switch *ds, int port, 982 u32 stringset, uint8_t *data) 983 { 984 unsigned int u; 985 986 if (stringset != ETH_SS_STATS) 987 return; 988 989 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 990 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name, 991 ETH_GSTRING_LEN); 992 } 993 } 994 995 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port, 996 uint64_t *data) 997 { 998 struct lan9303 *chip = ds->priv; 999 unsigned int u; 1000 1001 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { 1002 u32 reg; 1003 int ret; 1004 1005 ret = lan9303_read_switch_port( 1006 chip, port, lan9303_mib[u].offset, ®); 1007 1008 if (ret) { 1009 dev_warn(chip->dev, "Reading status port %d reg %u failed\n", 1010 port, lan9303_mib[u].offset); 1011 reg = 0; 1012 } 1013 data[u] = reg; 1014 } 1015 } 1016 1017 static int lan9303_get_sset_count(struct dsa_switch *ds, int port, int sset) 1018 { 1019 if (sset != ETH_SS_STATS) 1020 return 0; 1021 1022 return ARRAY_SIZE(lan9303_mib); 1023 } 1024 1025 static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum) 1026 { 1027 struct lan9303 *chip = ds->priv; 1028 int phy_base = chip->phy_addr_base; 1029 1030 if (phy == phy_base) 1031 return lan9303_virt_phy_reg_read(chip, regnum); 1032 if (phy > phy_base + 2) 1033 return -ENODEV; 1034 1035 return chip->ops->phy_read(chip, phy, regnum); 1036 } 1037 1038 static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum, 1039 u16 val) 1040 { 1041 struct lan9303 *chip = ds->priv; 1042 int phy_base = chip->phy_addr_base; 1043 1044 if (phy == phy_base) 1045 return lan9303_virt_phy_reg_write(chip, regnum, val); 1046 if (phy > phy_base + 2) 1047 return -ENODEV; 1048 1049 return chip->ops->phy_write(chip, phy, regnum, val); 1050 } 1051 1052 static void lan9303_adjust_link(struct dsa_switch *ds, int port, 1053 struct phy_device *phydev) 1054 { 1055 struct lan9303 *chip = ds->priv; 1056 int ctl; 1057 1058 if (!phy_is_pseudo_fixed_link(phydev)) 1059 return; 1060 1061 ctl = lan9303_phy_read(ds, port, MII_BMCR); 1062 1063 ctl &= ~BMCR_ANENABLE; 1064 1065 if (phydev->speed == SPEED_100) 1066 ctl |= BMCR_SPEED100; 1067 else if (phydev->speed == SPEED_10) 1068 ctl &= ~BMCR_SPEED100; 1069 else 1070 dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed); 1071 1072 if (phydev->duplex == DUPLEX_FULL) 1073 ctl |= BMCR_FULLDPLX; 1074 else 1075 ctl &= ~BMCR_FULLDPLX; 1076 1077 lan9303_phy_write(ds, port, MII_BMCR, ctl); 1078 1079 if (port == chip->phy_addr_base) { 1080 /* Virtual Phy: Remove Turbo 200Mbit mode */ 1081 lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl); 1082 1083 ctl &= ~LAN9303_VIRT_SPECIAL_TURBO; 1084 regmap_write(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, ctl); 1085 } 1086 } 1087 1088 static int lan9303_port_enable(struct dsa_switch *ds, int port, 1089 struct phy_device *phy) 1090 { 1091 struct dsa_port *dp = dsa_to_port(ds, port); 1092 struct lan9303 *chip = ds->priv; 1093 1094 if (!dsa_port_is_user(dp)) 1095 return 0; 1096 1097 vlan_vid_add(dsa_port_to_master(dp), htons(ETH_P_8021Q), port); 1098 1099 return lan9303_enable_processing_port(chip, port); 1100 } 1101 1102 static void lan9303_port_disable(struct dsa_switch *ds, int port) 1103 { 1104 struct dsa_port *dp = dsa_to_port(ds, port); 1105 struct lan9303 *chip = ds->priv; 1106 1107 if (!dsa_port_is_user(dp)) 1108 return; 1109 1110 vlan_vid_del(dsa_port_to_master(dp), htons(ETH_P_8021Q), port); 1111 1112 lan9303_disable_processing_port(chip, port); 1113 lan9303_phy_write(ds, chip->phy_addr_base + port, MII_BMCR, BMCR_PDOWN); 1114 } 1115 1116 static int lan9303_port_bridge_join(struct dsa_switch *ds, int port, 1117 struct dsa_bridge bridge, 1118 bool *tx_fwd_offload, 1119 struct netlink_ext_ack *extack) 1120 { 1121 struct lan9303 *chip = ds->priv; 1122 1123 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); 1124 if (dsa_port_bridge_same(dsa_to_port(ds, 1), dsa_to_port(ds, 2))) { 1125 lan9303_bridge_ports(chip); 1126 chip->is_bridged = true; /* unleash stp_state_set() */ 1127 } 1128 1129 return 0; 1130 } 1131 1132 static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port, 1133 struct dsa_bridge bridge) 1134 { 1135 struct lan9303 *chip = ds->priv; 1136 1137 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); 1138 if (chip->is_bridged) { 1139 lan9303_separate_ports(chip); 1140 chip->is_bridged = false; 1141 } 1142 } 1143 1144 static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port, 1145 u8 state) 1146 { 1147 int portmask, portstate; 1148 struct lan9303 *chip = ds->priv; 1149 1150 dev_dbg(chip->dev, "%s(port %d, state %d)\n", 1151 __func__, port, state); 1152 1153 switch (state) { 1154 case BR_STATE_DISABLED: 1155 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; 1156 break; 1157 case BR_STATE_BLOCKING: 1158 case BR_STATE_LISTENING: 1159 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0; 1160 break; 1161 case BR_STATE_LEARNING: 1162 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0; 1163 break; 1164 case BR_STATE_FORWARDING: 1165 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0; 1166 break; 1167 default: 1168 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; 1169 dev_err(chip->dev, "unknown stp state: port %d, state %d\n", 1170 port, state); 1171 } 1172 1173 portmask = 0x3 << (port * 2); 1174 portstate <<= (port * 2); 1175 1176 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate; 1177 1178 if (chip->is_bridged) 1179 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, 1180 chip->swe_port_state); 1181 /* else: touching SWE_PORT_STATE would break port separation */ 1182 } 1183 1184 static void lan9303_port_fast_age(struct dsa_switch *ds, int port) 1185 { 1186 struct lan9303 *chip = ds->priv; 1187 struct del_port_learned_ctx del_ctx = { 1188 .port = port, 1189 }; 1190 1191 dev_dbg(chip->dev, "%s(%d)\n", __func__, port); 1192 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx); 1193 } 1194 1195 static int lan9303_port_fdb_add(struct dsa_switch *ds, int port, 1196 const unsigned char *addr, u16 vid, 1197 struct dsa_db db) 1198 { 1199 struct lan9303 *chip = ds->priv; 1200 1201 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); 1202 if (vid) 1203 return -EOPNOTSUPP; 1204 1205 return lan9303_alr_add_port(chip, addr, port, false); 1206 } 1207 1208 static int lan9303_port_fdb_del(struct dsa_switch *ds, int port, 1209 const unsigned char *addr, u16 vid, 1210 struct dsa_db db) 1211 { 1212 struct lan9303 *chip = ds->priv; 1213 1214 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); 1215 if (vid) 1216 return -EOPNOTSUPP; 1217 lan9303_alr_del_port(chip, addr, port); 1218 1219 return 0; 1220 } 1221 1222 static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port, 1223 dsa_fdb_dump_cb_t *cb, void *data) 1224 { 1225 struct lan9303 *chip = ds->priv; 1226 struct port_fdb_dump_ctx dump_ctx = { 1227 .port = port, 1228 .data = data, 1229 .cb = cb, 1230 }; 1231 1232 dev_dbg(chip->dev, "%s(%d)\n", __func__, port); 1233 return lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx); 1234 } 1235 1236 static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port, 1237 const struct switchdev_obj_port_mdb *mdb) 1238 { 1239 struct lan9303 *chip = ds->priv; 1240 1241 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1242 mdb->vid); 1243 if (mdb->vid) 1244 return -EOPNOTSUPP; 1245 if (lan9303_alr_cache_find_mac(chip, mdb->addr)) 1246 return 0; 1247 if (!lan9303_alr_cache_find_free(chip)) 1248 return -ENOSPC; 1249 1250 return 0; 1251 } 1252 1253 static int lan9303_port_mdb_add(struct dsa_switch *ds, int port, 1254 const struct switchdev_obj_port_mdb *mdb, 1255 struct dsa_db db) 1256 { 1257 struct lan9303 *chip = ds->priv; 1258 int err; 1259 1260 err = lan9303_port_mdb_prepare(ds, port, mdb); 1261 if (err) 1262 return err; 1263 1264 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1265 mdb->vid); 1266 return lan9303_alr_add_port(chip, mdb->addr, port, false); 1267 } 1268 1269 static int lan9303_port_mdb_del(struct dsa_switch *ds, int port, 1270 const struct switchdev_obj_port_mdb *mdb, 1271 struct dsa_db db) 1272 { 1273 struct lan9303 *chip = ds->priv; 1274 1275 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, 1276 mdb->vid); 1277 if (mdb->vid) 1278 return -EOPNOTSUPP; 1279 lan9303_alr_del_port(chip, mdb->addr, port); 1280 1281 return 0; 1282 } 1283 1284 static const struct dsa_switch_ops lan9303_switch_ops = { 1285 .get_tag_protocol = lan9303_get_tag_protocol, 1286 .setup = lan9303_setup, 1287 .get_strings = lan9303_get_strings, 1288 .phy_read = lan9303_phy_read, 1289 .phy_write = lan9303_phy_write, 1290 .adjust_link = lan9303_adjust_link, 1291 .get_ethtool_stats = lan9303_get_ethtool_stats, 1292 .get_sset_count = lan9303_get_sset_count, 1293 .port_enable = lan9303_port_enable, 1294 .port_disable = lan9303_port_disable, 1295 .port_bridge_join = lan9303_port_bridge_join, 1296 .port_bridge_leave = lan9303_port_bridge_leave, 1297 .port_stp_state_set = lan9303_port_stp_state_set, 1298 .port_fast_age = lan9303_port_fast_age, 1299 .port_fdb_add = lan9303_port_fdb_add, 1300 .port_fdb_del = lan9303_port_fdb_del, 1301 .port_fdb_dump = lan9303_port_fdb_dump, 1302 .port_mdb_add = lan9303_port_mdb_add, 1303 .port_mdb_del = lan9303_port_mdb_del, 1304 }; 1305 1306 static int lan9303_register_switch(struct lan9303 *chip) 1307 { 1308 int base; 1309 1310 chip->ds = devm_kzalloc(chip->dev, sizeof(*chip->ds), GFP_KERNEL); 1311 if (!chip->ds) 1312 return -ENOMEM; 1313 1314 chip->ds->dev = chip->dev; 1315 chip->ds->num_ports = LAN9303_NUM_PORTS; 1316 chip->ds->priv = chip; 1317 chip->ds->ops = &lan9303_switch_ops; 1318 base = chip->phy_addr_base; 1319 chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base); 1320 1321 return dsa_register_switch(chip->ds); 1322 } 1323 1324 static int lan9303_probe_reset_gpio(struct lan9303 *chip, 1325 struct device_node *np) 1326 { 1327 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset", 1328 GPIOD_OUT_HIGH); 1329 if (IS_ERR(chip->reset_gpio)) 1330 return PTR_ERR(chip->reset_gpio); 1331 1332 if (!chip->reset_gpio) { 1333 dev_dbg(chip->dev, "No reset GPIO defined\n"); 1334 return 0; 1335 } 1336 1337 chip->reset_duration = 200; 1338 1339 if (np) { 1340 of_property_read_u32(np, "reset-duration", 1341 &chip->reset_duration); 1342 } else { 1343 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n"); 1344 } 1345 1346 /* A sane reset duration should not be longer than 1s */ 1347 if (chip->reset_duration > 1000) 1348 chip->reset_duration = 1000; 1349 1350 return 0; 1351 } 1352 1353 int lan9303_probe(struct lan9303 *chip, struct device_node *np) 1354 { 1355 int ret; 1356 u32 reg; 1357 1358 mutex_init(&chip->indirect_mutex); 1359 mutex_init(&chip->alr_mutex); 1360 1361 ret = lan9303_probe_reset_gpio(chip, np); 1362 if (ret) 1363 return ret; 1364 1365 lan9303_handle_reset(chip); 1366 1367 /* First read to the device. This is a Dummy read to ensure MDIO */ 1368 /* access is in 32-bit sync. */ 1369 ret = lan9303_read(chip->regmap, LAN9303_BYTE_ORDER, ®); 1370 if (ret) { 1371 dev_err(chip->dev, "failed to access the device: %d\n", 1372 ret); 1373 if (!chip->reset_gpio) { 1374 dev_dbg(chip->dev, 1375 "hint: maybe failed due to missing reset GPIO\n"); 1376 } 1377 return ret; 1378 } 1379 1380 ret = lan9303_check_device(chip); 1381 if (ret) 1382 return ret; 1383 1384 ret = lan9303_register_switch(chip); 1385 if (ret) { 1386 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret); 1387 return ret; 1388 } 1389 1390 return 0; 1391 } 1392 EXPORT_SYMBOL(lan9303_probe); 1393 1394 int lan9303_remove(struct lan9303 *chip) 1395 { 1396 int rc; 1397 1398 rc = lan9303_disable_processing(chip); 1399 if (rc != 0) 1400 dev_warn(chip->dev, "shutting down failed\n"); 1401 1402 dsa_unregister_switch(chip->ds); 1403 1404 /* assert reset to the whole device to prevent it from doing anything */ 1405 gpiod_set_value_cansleep(chip->reset_gpio, 1); 1406 gpiod_unexport(chip->reset_gpio); 1407 1408 return 0; 1409 } 1410 EXPORT_SYMBOL(lan9303_remove); 1411 1412 void lan9303_shutdown(struct lan9303 *chip) 1413 { 1414 dsa_switch_shutdown(chip->ds); 1415 } 1416 EXPORT_SYMBOL(lan9303_shutdown); 1417 1418 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>"); 1419 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch"); 1420 MODULE_LICENSE("GPL v2"); 1421