1ddd56dfeSKamil Alkhouri /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2ddd56dfeSKamil Alkhouri /*
3ddd56dfeSKamil Alkhouri  * DSA driver for:
4ddd56dfeSKamil Alkhouri  * Hirschmann Hellcreek TSN switch.
5ddd56dfeSKamil Alkhouri  *
6ddd56dfeSKamil Alkhouri  * Copyright (C) 2019,2020 Hochschule Offenburg
7ddd56dfeSKamil Alkhouri  * Copyright (C) 2019,2020 Linutronix GmbH
8ddd56dfeSKamil Alkhouri  * Authors: Kurt Kanzenbach <kurt@linutronix.de>
9ddd56dfeSKamil Alkhouri  *	    Kamil Alkhouri <kamil.alkhouri@hs-offenburg.de>
10ddd56dfeSKamil Alkhouri  */
11ddd56dfeSKamil Alkhouri 
12ddd56dfeSKamil Alkhouri #ifndef _HELLCREEK_PTP_H_
13ddd56dfeSKamil Alkhouri #define _HELLCREEK_PTP_H_
14ddd56dfeSKamil Alkhouri 
15ddd56dfeSKamil Alkhouri #include <linux/bitops.h>
16ddd56dfeSKamil Alkhouri #include <linux/ptp_clock_kernel.h>
17ddd56dfeSKamil Alkhouri 
18ddd56dfeSKamil Alkhouri #include "hellcreek.h"
19ddd56dfeSKamil Alkhouri 
20ddd56dfeSKamil Alkhouri /* Every jump in time is 7 ns */
21ddd56dfeSKamil Alkhouri #define MAX_NS_PER_STEP			7L
22ddd56dfeSKamil Alkhouri 
23ddd56dfeSKamil Alkhouri /* Correct offset at every clock cycle */
24ddd56dfeSKamil Alkhouri #define MIN_CLK_CYCLES_BETWEEN_STEPS	0
25ddd56dfeSKamil Alkhouri 
26ddd56dfeSKamil Alkhouri /* Maximum available slow offset resources */
27ddd56dfeSKamil Alkhouri #define MAX_SLOW_OFFSET_ADJ					\
28ddd56dfeSKamil Alkhouri 	((unsigned long long)((1 << 30) - 1) * MAX_NS_PER_STEP)
29ddd56dfeSKamil Alkhouri 
30ddd56dfeSKamil Alkhouri /* four times a second overflow check */
31ddd56dfeSKamil Alkhouri #define HELLCREEK_OVERFLOW_PERIOD	(HZ / 4)
32ddd56dfeSKamil Alkhouri 
33ddd56dfeSKamil Alkhouri /* PTP Register */
34ddd56dfeSKamil Alkhouri #define PR_SETTINGS_C			(0x09 * 2)
35ddd56dfeSKamil Alkhouri #define PR_SETTINGS_C_RES3TS		BIT(4)
36ddd56dfeSKamil Alkhouri #define PR_SETTINGS_C_TS_SRC_TK_SHIFT	8
37ddd56dfeSKamil Alkhouri #define PR_SETTINGS_C_TS_SRC_TK_MASK	GENMASK(9, 8)
38ddd56dfeSKamil Alkhouri #define PR_COMMAND_C			(0x0a * 2)
39ddd56dfeSKamil Alkhouri #define PR_COMMAND_C_SS			BIT(0)
40ddd56dfeSKamil Alkhouri 
41ddd56dfeSKamil Alkhouri #define PR_CLOCK_STATUS_C		(0x0c * 2)
42ddd56dfeSKamil Alkhouri #define PR_CLOCK_STATUS_C_ENA_DRIFT	BIT(12)
43ddd56dfeSKamil Alkhouri #define PR_CLOCK_STATUS_C_OFS_ACT	BIT(13)
44ddd56dfeSKamil Alkhouri #define PR_CLOCK_STATUS_C_ENA_OFS	BIT(14)
45ddd56dfeSKamil Alkhouri 
46ddd56dfeSKamil Alkhouri #define PR_CLOCK_READ_C			(0x0d * 2)
47ddd56dfeSKamil Alkhouri #define PR_CLOCK_WRITE_C		(0x0e * 2)
48ddd56dfeSKamil Alkhouri #define PR_CLOCK_OFFSET_C		(0x0f * 2)
49ddd56dfeSKamil Alkhouri #define PR_CLOCK_DRIFT_C		(0x10 * 2)
50ddd56dfeSKamil Alkhouri 
51ddd56dfeSKamil Alkhouri #define PR_SS_FREE_DATA_C		(0x12 * 2)
52ddd56dfeSKamil Alkhouri #define PR_SS_SYNT_DATA_C		(0x14 * 2)
53ddd56dfeSKamil Alkhouri #define PR_SS_SYNC_DATA_C		(0x16 * 2)
54ddd56dfeSKamil Alkhouri #define PR_SS_DRAC_DATA_C		(0x18 * 2)
55ddd56dfeSKamil Alkhouri 
56ddd56dfeSKamil Alkhouri #define STATUS_OUT			(0x60 * 2)
57ddd56dfeSKamil Alkhouri #define STATUS_OUT_SYNC_GOOD		BIT(0)
58ddd56dfeSKamil Alkhouri #define STATUS_OUT_IS_GM		BIT(1)
59ddd56dfeSKamil Alkhouri 
60ddd56dfeSKamil Alkhouri int hellcreek_ptp_setup(struct hellcreek *hellcreek);
61ddd56dfeSKamil Alkhouri void hellcreek_ptp_free(struct hellcreek *hellcreek);
62*f0d4ba9eSKamil Alkhouri u16 hellcreek_ptp_read(struct hellcreek *hellcreek, unsigned int offset);
63*f0d4ba9eSKamil Alkhouri void hellcreek_ptp_write(struct hellcreek *hellcreek, u16 data,
64*f0d4ba9eSKamil Alkhouri 			 unsigned int offset);
65*f0d4ba9eSKamil Alkhouri u64 hellcreek_ptp_gettime_seconds(struct hellcreek *hellcreek, u64 ns);
66ddd56dfeSKamil Alkhouri 
67ddd56dfeSKamil Alkhouri #define ptp_to_hellcreek(ptp)					\
68ddd56dfeSKamil Alkhouri 	container_of(ptp, struct hellcreek, ptp_clock_info)
69ddd56dfeSKamil Alkhouri 
70ddd56dfeSKamil Alkhouri #define dw_overflow_to_hellcreek(dw)				\
71ddd56dfeSKamil Alkhouri 	container_of(dw, struct hellcreek, overflow_work)
72ddd56dfeSKamil Alkhouri 
73ddd56dfeSKamil Alkhouri #endif /* _HELLCREEK_PTP_H_ */
74