1 /* SPDX-License-Identifier: (GPL-2.0 or MIT) */
2 /*
3  * DSA driver for:
4  * Hirschmann Hellcreek TSN switch.
5  *
6  * Copyright (C) 2019,2020 Linutronix GmbH
7  * Author Kurt Kanzenbach <kurt@linutronix.de>
8  */
9 
10 #ifndef _HELLCREEK_H_
11 #define _HELLCREEK_H_
12 
13 #include <linux/bitmap.h>
14 #include <linux/bitops.h>
15 #include <linux/device.h>
16 #include <linux/kernel.h>
17 #include <linux/mutex.h>
18 #include <linux/workqueue.h>
19 #include <linux/leds.h>
20 #include <linux/platform_data/hirschmann-hellcreek.h>
21 #include <linux/ptp_clock_kernel.h>
22 #include <linux/timecounter.h>
23 #include <net/dsa.h>
24 
25 /* Ports:
26  *  - 0: CPU
27  *  - 1: Tunnel
28  *  - 2: TSN front port 1
29  *  - 3: TSN front port 2
30  *  - ...
31  */
32 #define CPU_PORT			0
33 #define TUNNEL_PORT			1
34 
35 #define HELLCREEK_VLAN_NO_MEMBER	0x0
36 #define HELLCREEK_VLAN_UNTAGGED_MEMBER	0x1
37 #define HELLCREEK_VLAN_TAGGED_MEMBER	0x3
38 #define HELLCREEK_NUM_EGRESS_QUEUES	8
39 
40 /* Register definitions */
41 #define HR_MODID_C			(0 * 2)
42 #define HR_REL_L_C			(1 * 2)
43 #define HR_REL_H_C			(2 * 2)
44 #define HR_BLD_L_C			(3 * 2)
45 #define HR_BLD_H_C			(4 * 2)
46 #define HR_CTRL_C			(5 * 2)
47 #define HR_CTRL_C_READY			BIT(14)
48 #define HR_CTRL_C_TRANSITION		BIT(13)
49 #define HR_CTRL_C_ENABLE		BIT(0)
50 
51 #define HR_PSEL				(0xa6 * 2)
52 #define HR_PSEL_PTWSEL_SHIFT		4
53 #define HR_PSEL_PTWSEL_MASK		GENMASK(5, 4)
54 #define HR_PSEL_PRTCWSEL_SHIFT		0
55 #define HR_PSEL_PRTCWSEL_MASK		GENMASK(2, 0)
56 
57 #define HR_PTCFG			(0xa7 * 2)
58 #define HR_PTCFG_MLIMIT_EN		BIT(13)
59 #define HR_PTCFG_UMC_FLT		BIT(10)
60 #define HR_PTCFG_UUC_FLT		BIT(9)
61 #define HR_PTCFG_UNTRUST		BIT(8)
62 #define HR_PTCFG_TAG_REQUIRED		BIT(7)
63 #define HR_PTCFG_PPRIO_SHIFT		4
64 #define HR_PTCFG_PPRIO_MASK		GENMASK(6, 4)
65 #define HR_PTCFG_INGRESSFLT		BIT(3)
66 #define HR_PTCFG_BLOCKED		BIT(2)
67 #define HR_PTCFG_LEARNING_EN		BIT(1)
68 #define HR_PTCFG_ADMIN_EN		BIT(0)
69 
70 #define HR_PRTCCFG			(0xa8 * 2)
71 #define HR_PRTCCFG_PCP_TC_MAP_SHIFT	0
72 #define HR_PRTCCFG_PCP_TC_MAP_MASK	GENMASK(2, 0)
73 
74 #define HR_CSEL				(0x8d * 2)
75 #define HR_CSEL_SHIFT			0
76 #define HR_CSEL_MASK			GENMASK(7, 0)
77 #define HR_CRDL				(0x8e * 2)
78 #define HR_CRDH				(0x8f * 2)
79 
80 #define HR_SWTRC_CFG			(0x90 * 2)
81 #define HR_SWTRC0			(0x91 * 2)
82 #define HR_SWTRC1			(0x92 * 2)
83 #define HR_PFREE			(0x93 * 2)
84 #define HR_MFREE			(0x94 * 2)
85 
86 #define HR_FDBAGE			(0x97 * 2)
87 #define HR_FDBMAX			(0x98 * 2)
88 #define HR_FDBRDL			(0x99 * 2)
89 #define HR_FDBRDM			(0x9a * 2)
90 #define HR_FDBRDH			(0x9b * 2)
91 
92 #define HR_FDBMDRD			(0x9c * 2)
93 #define HR_FDBMDRD_PORTMASK_SHIFT	0
94 #define HR_FDBMDRD_PORTMASK_MASK	GENMASK(3, 0)
95 #define HR_FDBMDRD_AGE_SHIFT		4
96 #define HR_FDBMDRD_AGE_MASK		GENMASK(7, 4)
97 #define HR_FDBMDRD_OBT			BIT(8)
98 #define HR_FDBMDRD_PASS_BLOCKED		BIT(9)
99 #define HR_FDBMDRD_STATIC		BIT(11)
100 #define HR_FDBMDRD_REPRIO_TC_SHIFT	12
101 #define HR_FDBMDRD_REPRIO_TC_MASK	GENMASK(14, 12)
102 #define HR_FDBMDRD_REPRIO_EN		BIT(15)
103 
104 #define HR_FDBWDL			(0x9d * 2)
105 #define HR_FDBWDM			(0x9e * 2)
106 #define HR_FDBWDH			(0x9f * 2)
107 #define HR_FDBWRM0			(0xa0 * 2)
108 #define HR_FDBWRM0_PORTMASK_SHIFT	0
109 #define HR_FDBWRM0_PORTMASK_MASK	GENMASK(3, 0)
110 #define HR_FDBWRM0_OBT			BIT(8)
111 #define HR_FDBWRM0_PASS_BLOCKED		BIT(9)
112 #define HR_FDBWRM0_REPRIO_TC_SHIFT	12
113 #define HR_FDBWRM0_REPRIO_TC_MASK	GENMASK(14, 12)
114 #define HR_FDBWRM0_REPRIO_EN		BIT(15)
115 #define HR_FDBWRM1			(0xa1 * 2)
116 
117 #define HR_FDBWRCMD			(0xa2 * 2)
118 #define HR_FDBWRCMD_FDBDEL		BIT(9)
119 
120 #define HR_SWCFG			(0xa3 * 2)
121 #define HR_SWCFG_GM_STATEMD		BIT(15)
122 #define HR_SWCFG_LAS_MODE_SHIFT		12
123 #define HR_SWCFG_LAS_MODE_MASK		GENMASK(13, 12)
124 #define HR_SWCFG_LAS_OFF		(0x00)
125 #define HR_SWCFG_LAS_ON			(0x01)
126 #define HR_SWCFG_LAS_STATIC		(0x10)
127 #define HR_SWCFG_CT_EN			BIT(11)
128 #define HR_SWCFG_VLAN_UNAWARE		BIT(10)
129 #define HR_SWCFG_ALWAYS_OBT		BIT(9)
130 #define HR_SWCFG_FDBAGE_EN		BIT(5)
131 #define HR_SWCFG_FDBLRN_EN		BIT(4)
132 
133 #define HR_SWSTAT			(0xa4 * 2)
134 #define HR_SWSTAT_FAIL			BIT(4)
135 #define HR_SWSTAT_BUSY			BIT(0)
136 
137 #define HR_SWCMD			(0xa5 * 2)
138 #define HW_SWCMD_FLUSH			BIT(0)
139 
140 #define HR_VIDCFG			(0xaa * 2)
141 #define HR_VIDCFG_VID_SHIFT		0
142 #define HR_VIDCFG_VID_MASK		GENMASK(11, 0)
143 #define HR_VIDCFG_PVID			BIT(12)
144 
145 #define HR_VIDMBRCFG			(0xab * 2)
146 #define HR_VIDMBRCFG_P0MBR_SHIFT	0
147 #define HR_VIDMBRCFG_P0MBR_MASK		GENMASK(1, 0)
148 #define HR_VIDMBRCFG_P1MBR_SHIFT	2
149 #define HR_VIDMBRCFG_P1MBR_MASK		GENMASK(3, 2)
150 #define HR_VIDMBRCFG_P2MBR_SHIFT	4
151 #define HR_VIDMBRCFG_P2MBR_MASK		GENMASK(5, 4)
152 #define HR_VIDMBRCFG_P3MBR_SHIFT	6
153 #define HR_VIDMBRCFG_P3MBR_MASK		GENMASK(7, 6)
154 
155 #define HR_FEABITS0			(0xac * 2)
156 #define HR_FEABITS0_FDBBINS_SHIFT	4
157 #define HR_FEABITS0_FDBBINS_MASK	GENMASK(7, 4)
158 #define HR_FEABITS0_PCNT_SHIFT		8
159 #define HR_FEABITS0_PCNT_MASK		GENMASK(11, 8)
160 #define HR_FEABITS0_MCNT_SHIFT		12
161 #define HR_FEABITS0_MCNT_MASK		GENMASK(15, 12)
162 
163 #define TR_QTRACK			(0xb1 * 2)
164 #define TR_TGDVER			(0xb3 * 2)
165 #define TR_TGDVER_REV_MIN_MASK		GENMASK(7, 0)
166 #define TR_TGDVER_REV_MIN_SHIFT		0
167 #define TR_TGDVER_REV_MAJ_MASK		GENMASK(15, 8)
168 #define TR_TGDVER_REV_MAJ_SHIFT		8
169 #define TR_TGDSEL			(0xb4 * 2)
170 #define TR_TGDSEL_TDGSEL_MASK		GENMASK(1, 0)
171 #define TR_TGDSEL_TDGSEL_SHIFT		0
172 #define TR_TGDCTRL			(0xb5 * 2)
173 #define TR_TGDCTRL_GATE_EN		BIT(0)
174 #define TR_TGDCTRL_CYC_SNAP		BIT(4)
175 #define TR_TGDCTRL_SNAP_EST		BIT(5)
176 #define TR_TGDCTRL_ADMINGATESTATES_MASK	GENMASK(15, 8)
177 #define TR_TGDCTRL_ADMINGATESTATES_SHIFT	8
178 #define TR_TGDSTAT0			(0xb6 * 2)
179 #define TR_TGDSTAT1			(0xb7 * 2)
180 #define TR_ESTWRL			(0xb8 * 2)
181 #define TR_ESTWRH			(0xb9 * 2)
182 #define TR_ESTCMD			(0xba * 2)
183 #define TR_ESTCMD_ESTSEC_MASK		GENMASK(2, 0)
184 #define TR_ESTCMD_ESTSEC_SHIFT		0
185 #define TR_ESTCMD_ESTARM		BIT(4)
186 #define TR_ESTCMD_ESTSWCFG		BIT(5)
187 #define TR_EETWRL			(0xbb * 2)
188 #define TR_EETWRH			(0xbc * 2)
189 #define TR_EETCMD			(0xbd * 2)
190 #define TR_EETCMD_EETSEC_MASK		GEMASK(2, 0)
191 #define TR_EETCMD_EETSEC_SHIFT		0
192 #define TR_EETCMD_EETARM		BIT(4)
193 #define TR_CTWRL			(0xbe * 2)
194 #define TR_CTWRH			(0xbf * 2)
195 #define TR_LCNSL			(0xc1 * 2)
196 #define TR_LCNSH			(0xc2 * 2)
197 #define TR_LCS				(0xc3 * 2)
198 #define TR_GCLDAT			(0xc4 * 2)
199 #define TR_GCLDAT_GCLWRGATES_MASK	GENMASK(7, 0)
200 #define TR_GCLDAT_GCLWRGATES_SHIFT	0
201 #define TR_GCLDAT_GCLWRLAST		BIT(8)
202 #define TR_GCLDAT_GCLOVRI		BIT(9)
203 #define TR_GCLTIL			(0xc5 * 2)
204 #define TR_GCLTIH			(0xc6 * 2)
205 #define TR_GCLCMD			(0xc7 * 2)
206 #define TR_GCLCMD_GCLWRADR_MASK		GENMASK(7, 0)
207 #define TR_GCLCMD_GCLWRADR_SHIFT	0
208 #define TR_GCLCMD_INIT_GATE_STATES_MASK	GENMASK(15, 8)
209 #define TR_GCLCMD_INIT_GATE_STATES_SHIFT	8
210 
211 struct hellcreek_counter {
212 	u8 offset;
213 	const char *name;
214 };
215 
216 struct hellcreek;
217 
218 /* State flags for hellcreek_port_hwtstamp::state */
219 enum {
220 	HELLCREEK_HWTSTAMP_ENABLED,
221 	HELLCREEK_HWTSTAMP_TX_IN_PROGRESS,
222 };
223 
224 /* A structure to hold hardware timestamping information per port */
225 struct hellcreek_port_hwtstamp {
226 	/* Timestamping state */
227 	unsigned long state;
228 
229 	/* Resources for receive timestamping */
230 	struct sk_buff_head rx_queue; /* For synchronization messages */
231 
232 	/* Resources for transmit timestamping */
233 	unsigned long tx_tstamp_start;
234 	struct sk_buff *tx_skb;
235 
236 	/* Current timestamp configuration */
237 	struct hwtstamp_config tstamp_config;
238 };
239 
240 struct hellcreek_port {
241 	struct hellcreek *hellcreek;
242 	unsigned long *vlan_dev_bitmap;
243 	int port;
244 	u16 ptcfg;		/* ptcfg shadow */
245 	u64 *counter_values;
246 
247 	/* Per-port timestamping resources */
248 	struct hellcreek_port_hwtstamp port_hwtstamp;
249 };
250 
251 struct hellcreek_fdb_entry {
252 	size_t idx;
253 	unsigned char mac[ETH_ALEN];
254 	u8 portmask;
255 	u8 age;
256 	u8 is_obt;
257 	u8 pass_blocked;
258 	u8 is_static;
259 	u8 reprio_tc;
260 	u8 reprio_en;
261 };
262 
263 struct hellcreek {
264 	const struct hellcreek_platform_data *pdata;
265 	struct device *dev;
266 	struct dsa_switch *ds;
267 	struct ptp_clock *ptp_clock;
268 	struct ptp_clock_info ptp_clock_info;
269 	struct hellcreek_port *ports;
270 	struct delayed_work overflow_work;
271 	struct led_classdev led_is_gm;
272 	struct led_classdev led_sync_good;
273 	struct mutex reg_lock;	/* Switch IP register lock */
274 	struct mutex vlan_lock;	/* VLAN bitmaps lock */
275 	struct mutex ptp_lock;	/* PTP IP register lock */
276 	void __iomem *base;
277 	void __iomem *ptp_base;
278 	u16 swcfg;		/* swcfg shadow */
279 	u8 *vidmbrcfg;		/* vidmbrcfg shadow */
280 	u64 seconds;		/* PTP seconds */
281 	u64 last_ts;		/* Used for overflow detection */
282 	u16 status_out;		/* ptp.status_out shadow */
283 	size_t fdb_entries;
284 };
285 
286 #endif /* _HELLCREEK_H_ */
287