1e4b27ebcSKurt Kanzenbach /* SPDX-License-Identifier: (GPL-2.0 or MIT) */ 2e4b27ebcSKurt Kanzenbach /* 3e4b27ebcSKurt Kanzenbach * DSA driver for: 4e4b27ebcSKurt Kanzenbach * Hirschmann Hellcreek TSN switch. 5e4b27ebcSKurt Kanzenbach * 624dfc6ebSKurt Kanzenbach * Copyright (C) 2019-2021 Linutronix GmbH 7e4b27ebcSKurt Kanzenbach * Author Kurt Kanzenbach <kurt@linutronix.de> 8e4b27ebcSKurt Kanzenbach */ 9e4b27ebcSKurt Kanzenbach 10e4b27ebcSKurt Kanzenbach #ifndef _HELLCREEK_H_ 11e4b27ebcSKurt Kanzenbach #define _HELLCREEK_H_ 12e4b27ebcSKurt Kanzenbach 13e4b27ebcSKurt Kanzenbach #include <linux/bitmap.h> 14e4b27ebcSKurt Kanzenbach #include <linux/bitops.h> 15e4b27ebcSKurt Kanzenbach #include <linux/device.h> 16e4b27ebcSKurt Kanzenbach #include <linux/kernel.h> 17e4b27ebcSKurt Kanzenbach #include <linux/mutex.h> 18ddd56dfeSKamil Alkhouri #include <linux/workqueue.h> 197d9ee2e8SKurt Kanzenbach #include <linux/leds.h> 20e4b27ebcSKurt Kanzenbach #include <linux/platform_data/hirschmann-hellcreek.h> 21e4b27ebcSKurt Kanzenbach #include <linux/ptp_clock_kernel.h> 22e4b27ebcSKurt Kanzenbach #include <linux/timecounter.h> 23e4b27ebcSKurt Kanzenbach #include <net/dsa.h> 2424dfc6ebSKurt Kanzenbach #include <net/pkt_sched.h> 25e4b27ebcSKurt Kanzenbach 26e4b27ebcSKurt Kanzenbach /* Ports: 27e4b27ebcSKurt Kanzenbach * - 0: CPU 28e4b27ebcSKurt Kanzenbach * - 1: Tunnel 29e4b27ebcSKurt Kanzenbach * - 2: TSN front port 1 30e4b27ebcSKurt Kanzenbach * - 3: TSN front port 2 31e4b27ebcSKurt Kanzenbach * - ... 32e4b27ebcSKurt Kanzenbach */ 33e4b27ebcSKurt Kanzenbach #define CPU_PORT 0 34e4b27ebcSKurt Kanzenbach #define TUNNEL_PORT 1 35e4b27ebcSKurt Kanzenbach 36e4b27ebcSKurt Kanzenbach #define HELLCREEK_VLAN_NO_MEMBER 0x0 37e4b27ebcSKurt Kanzenbach #define HELLCREEK_VLAN_UNTAGGED_MEMBER 0x1 38e4b27ebcSKurt Kanzenbach #define HELLCREEK_VLAN_TAGGED_MEMBER 0x3 39e4b27ebcSKurt Kanzenbach #define HELLCREEK_NUM_EGRESS_QUEUES 8 40e4b27ebcSKurt Kanzenbach 41e4b27ebcSKurt Kanzenbach /* Register definitions */ 42e4b27ebcSKurt Kanzenbach #define HR_MODID_C (0 * 2) 43e4b27ebcSKurt Kanzenbach #define HR_REL_L_C (1 * 2) 44e4b27ebcSKurt Kanzenbach #define HR_REL_H_C (2 * 2) 45e4b27ebcSKurt Kanzenbach #define HR_BLD_L_C (3 * 2) 46e4b27ebcSKurt Kanzenbach #define HR_BLD_H_C (4 * 2) 47e4b27ebcSKurt Kanzenbach #define HR_CTRL_C (5 * 2) 48e4b27ebcSKurt Kanzenbach #define HR_CTRL_C_READY BIT(14) 49e4b27ebcSKurt Kanzenbach #define HR_CTRL_C_TRANSITION BIT(13) 50e4b27ebcSKurt Kanzenbach #define HR_CTRL_C_ENABLE BIT(0) 51e4b27ebcSKurt Kanzenbach 52e4b27ebcSKurt Kanzenbach #define HR_PSEL (0xa6 * 2) 53e4b27ebcSKurt Kanzenbach #define HR_PSEL_PTWSEL_SHIFT 4 54e4b27ebcSKurt Kanzenbach #define HR_PSEL_PTWSEL_MASK GENMASK(5, 4) 55e4b27ebcSKurt Kanzenbach #define HR_PSEL_PRTCWSEL_SHIFT 0 56e4b27ebcSKurt Kanzenbach #define HR_PSEL_PRTCWSEL_MASK GENMASK(2, 0) 57e4b27ebcSKurt Kanzenbach 58e4b27ebcSKurt Kanzenbach #define HR_PTCFG (0xa7 * 2) 59e4b27ebcSKurt Kanzenbach #define HR_PTCFG_MLIMIT_EN BIT(13) 60e4b27ebcSKurt Kanzenbach #define HR_PTCFG_UMC_FLT BIT(10) 61e4b27ebcSKurt Kanzenbach #define HR_PTCFG_UUC_FLT BIT(9) 62e4b27ebcSKurt Kanzenbach #define HR_PTCFG_UNTRUST BIT(8) 63e4b27ebcSKurt Kanzenbach #define HR_PTCFG_TAG_REQUIRED BIT(7) 64e4b27ebcSKurt Kanzenbach #define HR_PTCFG_PPRIO_SHIFT 4 65e4b27ebcSKurt Kanzenbach #define HR_PTCFG_PPRIO_MASK GENMASK(6, 4) 66e4b27ebcSKurt Kanzenbach #define HR_PTCFG_INGRESSFLT BIT(3) 67e4b27ebcSKurt Kanzenbach #define HR_PTCFG_BLOCKED BIT(2) 68e4b27ebcSKurt Kanzenbach #define HR_PTCFG_LEARNING_EN BIT(1) 69e4b27ebcSKurt Kanzenbach #define HR_PTCFG_ADMIN_EN BIT(0) 70e4b27ebcSKurt Kanzenbach 71e4b27ebcSKurt Kanzenbach #define HR_PRTCCFG (0xa8 * 2) 72e4b27ebcSKurt Kanzenbach #define HR_PRTCCFG_PCP_TC_MAP_SHIFT 0 73e4b27ebcSKurt Kanzenbach #define HR_PRTCCFG_PCP_TC_MAP_MASK GENMASK(2, 0) 74e4b27ebcSKurt Kanzenbach 75e4b27ebcSKurt Kanzenbach #define HR_CSEL (0x8d * 2) 76e4b27ebcSKurt Kanzenbach #define HR_CSEL_SHIFT 0 77e4b27ebcSKurt Kanzenbach #define HR_CSEL_MASK GENMASK(7, 0) 78e4b27ebcSKurt Kanzenbach #define HR_CRDL (0x8e * 2) 79e4b27ebcSKurt Kanzenbach #define HR_CRDH (0x8f * 2) 80e4b27ebcSKurt Kanzenbach 81e4b27ebcSKurt Kanzenbach #define HR_SWTRC_CFG (0x90 * 2) 82e4b27ebcSKurt Kanzenbach #define HR_SWTRC0 (0x91 * 2) 83e4b27ebcSKurt Kanzenbach #define HR_SWTRC1 (0x92 * 2) 84e4b27ebcSKurt Kanzenbach #define HR_PFREE (0x93 * 2) 85e4b27ebcSKurt Kanzenbach #define HR_MFREE (0x94 * 2) 86e4b27ebcSKurt Kanzenbach 87e4b27ebcSKurt Kanzenbach #define HR_FDBAGE (0x97 * 2) 88e4b27ebcSKurt Kanzenbach #define HR_FDBMAX (0x98 * 2) 89e4b27ebcSKurt Kanzenbach #define HR_FDBRDL (0x99 * 2) 90e4b27ebcSKurt Kanzenbach #define HR_FDBRDM (0x9a * 2) 91e4b27ebcSKurt Kanzenbach #define HR_FDBRDH (0x9b * 2) 92e4b27ebcSKurt Kanzenbach 93e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD (0x9c * 2) 94e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD_PORTMASK_SHIFT 0 95e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD_PORTMASK_MASK GENMASK(3, 0) 96e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD_AGE_SHIFT 4 97e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD_AGE_MASK GENMASK(7, 4) 98e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD_OBT BIT(8) 99e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD_PASS_BLOCKED BIT(9) 100e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD_STATIC BIT(11) 101e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD_REPRIO_TC_SHIFT 12 102e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD_REPRIO_TC_MASK GENMASK(14, 12) 103e4b27ebcSKurt Kanzenbach #define HR_FDBMDRD_REPRIO_EN BIT(15) 104e4b27ebcSKurt Kanzenbach 105e4b27ebcSKurt Kanzenbach #define HR_FDBWDL (0x9d * 2) 106e4b27ebcSKurt Kanzenbach #define HR_FDBWDM (0x9e * 2) 107e4b27ebcSKurt Kanzenbach #define HR_FDBWDH (0x9f * 2) 108e4b27ebcSKurt Kanzenbach #define HR_FDBWRM0 (0xa0 * 2) 109e4b27ebcSKurt Kanzenbach #define HR_FDBWRM0_PORTMASK_SHIFT 0 110e4b27ebcSKurt Kanzenbach #define HR_FDBWRM0_PORTMASK_MASK GENMASK(3, 0) 111e4b27ebcSKurt Kanzenbach #define HR_FDBWRM0_OBT BIT(8) 112e4b27ebcSKurt Kanzenbach #define HR_FDBWRM0_PASS_BLOCKED BIT(9) 113e4b27ebcSKurt Kanzenbach #define HR_FDBWRM0_REPRIO_TC_SHIFT 12 114e4b27ebcSKurt Kanzenbach #define HR_FDBWRM0_REPRIO_TC_MASK GENMASK(14, 12) 115e4b27ebcSKurt Kanzenbach #define HR_FDBWRM0_REPRIO_EN BIT(15) 116e4b27ebcSKurt Kanzenbach #define HR_FDBWRM1 (0xa1 * 2) 117e4b27ebcSKurt Kanzenbach 118e4b27ebcSKurt Kanzenbach #define HR_FDBWRCMD (0xa2 * 2) 119e4b27ebcSKurt Kanzenbach #define HR_FDBWRCMD_FDBDEL BIT(9) 120e4b27ebcSKurt Kanzenbach 121e4b27ebcSKurt Kanzenbach #define HR_SWCFG (0xa3 * 2) 122e4b27ebcSKurt Kanzenbach #define HR_SWCFG_GM_STATEMD BIT(15) 123e4b27ebcSKurt Kanzenbach #define HR_SWCFG_LAS_MODE_SHIFT 12 124e4b27ebcSKurt Kanzenbach #define HR_SWCFG_LAS_MODE_MASK GENMASK(13, 12) 125e4b27ebcSKurt Kanzenbach #define HR_SWCFG_LAS_OFF (0x00) 126e4b27ebcSKurt Kanzenbach #define HR_SWCFG_LAS_ON (0x01) 127e4b27ebcSKurt Kanzenbach #define HR_SWCFG_LAS_STATIC (0x10) 128e4b27ebcSKurt Kanzenbach #define HR_SWCFG_CT_EN BIT(11) 129e4b27ebcSKurt Kanzenbach #define HR_SWCFG_VLAN_UNAWARE BIT(10) 130e4b27ebcSKurt Kanzenbach #define HR_SWCFG_ALWAYS_OBT BIT(9) 131e4b27ebcSKurt Kanzenbach #define HR_SWCFG_FDBAGE_EN BIT(5) 132e4b27ebcSKurt Kanzenbach #define HR_SWCFG_FDBLRN_EN BIT(4) 133e4b27ebcSKurt Kanzenbach 134e4b27ebcSKurt Kanzenbach #define HR_SWSTAT (0xa4 * 2) 135e4b27ebcSKurt Kanzenbach #define HR_SWSTAT_FAIL BIT(4) 136e4b27ebcSKurt Kanzenbach #define HR_SWSTAT_BUSY BIT(0) 137e4b27ebcSKurt Kanzenbach 138e4b27ebcSKurt Kanzenbach #define HR_SWCMD (0xa5 * 2) 139e4b27ebcSKurt Kanzenbach #define HW_SWCMD_FLUSH BIT(0) 140e4b27ebcSKurt Kanzenbach 141e4b27ebcSKurt Kanzenbach #define HR_VIDCFG (0xaa * 2) 142e4b27ebcSKurt Kanzenbach #define HR_VIDCFG_VID_SHIFT 0 143e4b27ebcSKurt Kanzenbach #define HR_VIDCFG_VID_MASK GENMASK(11, 0) 144e4b27ebcSKurt Kanzenbach #define HR_VIDCFG_PVID BIT(12) 145e4b27ebcSKurt Kanzenbach 146e4b27ebcSKurt Kanzenbach #define HR_VIDMBRCFG (0xab * 2) 147e4b27ebcSKurt Kanzenbach #define HR_VIDMBRCFG_P0MBR_SHIFT 0 148e4b27ebcSKurt Kanzenbach #define HR_VIDMBRCFG_P0MBR_MASK GENMASK(1, 0) 149e4b27ebcSKurt Kanzenbach #define HR_VIDMBRCFG_P1MBR_SHIFT 2 150e4b27ebcSKurt Kanzenbach #define HR_VIDMBRCFG_P1MBR_MASK GENMASK(3, 2) 151e4b27ebcSKurt Kanzenbach #define HR_VIDMBRCFG_P2MBR_SHIFT 4 152e4b27ebcSKurt Kanzenbach #define HR_VIDMBRCFG_P2MBR_MASK GENMASK(5, 4) 153e4b27ebcSKurt Kanzenbach #define HR_VIDMBRCFG_P3MBR_SHIFT 6 154e4b27ebcSKurt Kanzenbach #define HR_VIDMBRCFG_P3MBR_MASK GENMASK(7, 6) 155e4b27ebcSKurt Kanzenbach 156e4b27ebcSKurt Kanzenbach #define HR_FEABITS0 (0xac * 2) 157e4b27ebcSKurt Kanzenbach #define HR_FEABITS0_FDBBINS_SHIFT 4 158e4b27ebcSKurt Kanzenbach #define HR_FEABITS0_FDBBINS_MASK GENMASK(7, 4) 159e4b27ebcSKurt Kanzenbach #define HR_FEABITS0_PCNT_SHIFT 8 160e4b27ebcSKurt Kanzenbach #define HR_FEABITS0_PCNT_MASK GENMASK(11, 8) 161e4b27ebcSKurt Kanzenbach #define HR_FEABITS0_MCNT_SHIFT 12 162e4b27ebcSKurt Kanzenbach #define HR_FEABITS0_MCNT_MASK GENMASK(15, 12) 163e4b27ebcSKurt Kanzenbach 164e4b27ebcSKurt Kanzenbach #define TR_QTRACK (0xb1 * 2) 165e4b27ebcSKurt Kanzenbach #define TR_TGDVER (0xb3 * 2) 166e4b27ebcSKurt Kanzenbach #define TR_TGDVER_REV_MIN_MASK GENMASK(7, 0) 167e4b27ebcSKurt Kanzenbach #define TR_TGDVER_REV_MIN_SHIFT 0 168e4b27ebcSKurt Kanzenbach #define TR_TGDVER_REV_MAJ_MASK GENMASK(15, 8) 169e4b27ebcSKurt Kanzenbach #define TR_TGDVER_REV_MAJ_SHIFT 8 170e4b27ebcSKurt Kanzenbach #define TR_TGDSEL (0xb4 * 2) 171e4b27ebcSKurt Kanzenbach #define TR_TGDSEL_TDGSEL_MASK GENMASK(1, 0) 172e4b27ebcSKurt Kanzenbach #define TR_TGDSEL_TDGSEL_SHIFT 0 173e4b27ebcSKurt Kanzenbach #define TR_TGDCTRL (0xb5 * 2) 174e4b27ebcSKurt Kanzenbach #define TR_TGDCTRL_GATE_EN BIT(0) 175e4b27ebcSKurt Kanzenbach #define TR_TGDCTRL_CYC_SNAP BIT(4) 176e4b27ebcSKurt Kanzenbach #define TR_TGDCTRL_SNAP_EST BIT(5) 177e4b27ebcSKurt Kanzenbach #define TR_TGDCTRL_ADMINGATESTATES_MASK GENMASK(15, 8) 178e4b27ebcSKurt Kanzenbach #define TR_TGDCTRL_ADMINGATESTATES_SHIFT 8 179e4b27ebcSKurt Kanzenbach #define TR_TGDSTAT0 (0xb6 * 2) 180e4b27ebcSKurt Kanzenbach #define TR_TGDSTAT1 (0xb7 * 2) 181e4b27ebcSKurt Kanzenbach #define TR_ESTWRL (0xb8 * 2) 182e4b27ebcSKurt Kanzenbach #define TR_ESTWRH (0xb9 * 2) 183e4b27ebcSKurt Kanzenbach #define TR_ESTCMD (0xba * 2) 184e4b27ebcSKurt Kanzenbach #define TR_ESTCMD_ESTSEC_MASK GENMASK(2, 0) 185e4b27ebcSKurt Kanzenbach #define TR_ESTCMD_ESTSEC_SHIFT 0 186e4b27ebcSKurt Kanzenbach #define TR_ESTCMD_ESTARM BIT(4) 187e4b27ebcSKurt Kanzenbach #define TR_ESTCMD_ESTSWCFG BIT(5) 188e4b27ebcSKurt Kanzenbach #define TR_EETWRL (0xbb * 2) 189e4b27ebcSKurt Kanzenbach #define TR_EETWRH (0xbc * 2) 190e4b27ebcSKurt Kanzenbach #define TR_EETCMD (0xbd * 2) 191e4b27ebcSKurt Kanzenbach #define TR_EETCMD_EETSEC_MASK GEMASK(2, 0) 192e4b27ebcSKurt Kanzenbach #define TR_EETCMD_EETSEC_SHIFT 0 193e4b27ebcSKurt Kanzenbach #define TR_EETCMD_EETARM BIT(4) 194e4b27ebcSKurt Kanzenbach #define TR_CTWRL (0xbe * 2) 195e4b27ebcSKurt Kanzenbach #define TR_CTWRH (0xbf * 2) 196e4b27ebcSKurt Kanzenbach #define TR_LCNSL (0xc1 * 2) 197e4b27ebcSKurt Kanzenbach #define TR_LCNSH (0xc2 * 2) 198e4b27ebcSKurt Kanzenbach #define TR_LCS (0xc3 * 2) 199e4b27ebcSKurt Kanzenbach #define TR_GCLDAT (0xc4 * 2) 200e4b27ebcSKurt Kanzenbach #define TR_GCLDAT_GCLWRGATES_MASK GENMASK(7, 0) 201e4b27ebcSKurt Kanzenbach #define TR_GCLDAT_GCLWRGATES_SHIFT 0 202e4b27ebcSKurt Kanzenbach #define TR_GCLDAT_GCLWRLAST BIT(8) 203e4b27ebcSKurt Kanzenbach #define TR_GCLDAT_GCLOVRI BIT(9) 204e4b27ebcSKurt Kanzenbach #define TR_GCLTIL (0xc5 * 2) 205e4b27ebcSKurt Kanzenbach #define TR_GCLTIH (0xc6 * 2) 206e4b27ebcSKurt Kanzenbach #define TR_GCLCMD (0xc7 * 2) 207e4b27ebcSKurt Kanzenbach #define TR_GCLCMD_GCLWRADR_MASK GENMASK(7, 0) 208e4b27ebcSKurt Kanzenbach #define TR_GCLCMD_GCLWRADR_SHIFT 0 209e4b27ebcSKurt Kanzenbach #define TR_GCLCMD_INIT_GATE_STATES_MASK GENMASK(15, 8) 210e4b27ebcSKurt Kanzenbach #define TR_GCLCMD_INIT_GATE_STATES_SHIFT 8 211e4b27ebcSKurt Kanzenbach 212e4b27ebcSKurt Kanzenbach struct hellcreek_counter { 213e4b27ebcSKurt Kanzenbach u8 offset; 214e4b27ebcSKurt Kanzenbach const char *name; 215e4b27ebcSKurt Kanzenbach }; 216e4b27ebcSKurt Kanzenbach 217e4b27ebcSKurt Kanzenbach struct hellcreek; 218e4b27ebcSKurt Kanzenbach 219f0d4ba9eSKamil Alkhouri /* State flags for hellcreek_port_hwtstamp::state */ 220f0d4ba9eSKamil Alkhouri enum { 221f0d4ba9eSKamil Alkhouri HELLCREEK_HWTSTAMP_ENABLED, 222f0d4ba9eSKamil Alkhouri HELLCREEK_HWTSTAMP_TX_IN_PROGRESS, 223f0d4ba9eSKamil Alkhouri }; 224f0d4ba9eSKamil Alkhouri 225f0d4ba9eSKamil Alkhouri /* A structure to hold hardware timestamping information per port */ 226f0d4ba9eSKamil Alkhouri struct hellcreek_port_hwtstamp { 227f0d4ba9eSKamil Alkhouri /* Timestamping state */ 228f0d4ba9eSKamil Alkhouri unsigned long state; 229f0d4ba9eSKamil Alkhouri 230f0d4ba9eSKamil Alkhouri /* Resources for receive timestamping */ 231f0d4ba9eSKamil Alkhouri struct sk_buff_head rx_queue; /* For synchronization messages */ 232f0d4ba9eSKamil Alkhouri 233f0d4ba9eSKamil Alkhouri /* Resources for transmit timestamping */ 234f0d4ba9eSKamil Alkhouri unsigned long tx_tstamp_start; 235f0d4ba9eSKamil Alkhouri struct sk_buff *tx_skb; 236f0d4ba9eSKamil Alkhouri 237f0d4ba9eSKamil Alkhouri /* Current timestamp configuration */ 238f0d4ba9eSKamil Alkhouri struct hwtstamp_config tstamp_config; 239f0d4ba9eSKamil Alkhouri }; 240f0d4ba9eSKamil Alkhouri 241e4b27ebcSKurt Kanzenbach struct hellcreek_port { 242e4b27ebcSKurt Kanzenbach struct hellcreek *hellcreek; 243e4b27ebcSKurt Kanzenbach unsigned long *vlan_dev_bitmap; 244e4b27ebcSKurt Kanzenbach int port; 245e4b27ebcSKurt Kanzenbach u16 ptcfg; /* ptcfg shadow */ 246e4b27ebcSKurt Kanzenbach u64 *counter_values; 247f0d4ba9eSKamil Alkhouri 248f0d4ba9eSKamil Alkhouri /* Per-port timestamping resources */ 249f0d4ba9eSKamil Alkhouri struct hellcreek_port_hwtstamp port_hwtstamp; 25024dfc6ebSKurt Kanzenbach 25124dfc6ebSKurt Kanzenbach /* Per-port Qbv schedule information */ 25224dfc6ebSKurt Kanzenbach struct tc_taprio_qopt_offload *current_schedule; 25324dfc6ebSKurt Kanzenbach struct delayed_work schedule_work; 254e4b27ebcSKurt Kanzenbach }; 255e4b27ebcSKurt Kanzenbach 256e4b27ebcSKurt Kanzenbach struct hellcreek_fdb_entry { 257e4b27ebcSKurt Kanzenbach size_t idx; 258e4b27ebcSKurt Kanzenbach unsigned char mac[ETH_ALEN]; 259e4b27ebcSKurt Kanzenbach u8 portmask; 260e4b27ebcSKurt Kanzenbach u8 age; 261e4b27ebcSKurt Kanzenbach u8 is_obt; 262e4b27ebcSKurt Kanzenbach u8 pass_blocked; 263e4b27ebcSKurt Kanzenbach u8 is_static; 264e4b27ebcSKurt Kanzenbach u8 reprio_tc; 265e4b27ebcSKurt Kanzenbach u8 reprio_en; 266e4b27ebcSKurt Kanzenbach }; 267e4b27ebcSKurt Kanzenbach 268e4b27ebcSKurt Kanzenbach struct hellcreek { 269e4b27ebcSKurt Kanzenbach const struct hellcreek_platform_data *pdata; 270e4b27ebcSKurt Kanzenbach struct device *dev; 271e4b27ebcSKurt Kanzenbach struct dsa_switch *ds; 272ddd56dfeSKamil Alkhouri struct ptp_clock *ptp_clock; 273ddd56dfeSKamil Alkhouri struct ptp_clock_info ptp_clock_info; 274e4b27ebcSKurt Kanzenbach struct hellcreek_port *ports; 275ddd56dfeSKamil Alkhouri struct delayed_work overflow_work; 2767d9ee2e8SKurt Kanzenbach struct led_classdev led_is_gm; 2777d9ee2e8SKurt Kanzenbach struct led_classdev led_sync_good; 278e4b27ebcSKurt Kanzenbach struct mutex reg_lock; /* Switch IP register lock */ 279e4b27ebcSKurt Kanzenbach struct mutex vlan_lock; /* VLAN bitmaps lock */ 280ddd56dfeSKamil Alkhouri struct mutex ptp_lock; /* PTP IP register lock */ 281ba2d1c28SKurt Kanzenbach struct devlink_region *vlan_region; 282*292cd449SKurt Kanzenbach struct devlink_region *fdb_region; 283e4b27ebcSKurt Kanzenbach void __iomem *base; 284ddd56dfeSKamil Alkhouri void __iomem *ptp_base; 285e4b27ebcSKurt Kanzenbach u16 swcfg; /* swcfg shadow */ 286e4b27ebcSKurt Kanzenbach u8 *vidmbrcfg; /* vidmbrcfg shadow */ 287ddd56dfeSKamil Alkhouri u64 seconds; /* PTP seconds */ 288ddd56dfeSKamil Alkhouri u64 last_ts; /* Used for overflow detection */ 2897d9ee2e8SKurt Kanzenbach u16 status_out; /* ptp.status_out shadow */ 290e4b27ebcSKurt Kanzenbach size_t fdb_entries; 291e4b27ebcSKurt Kanzenbach }; 292e4b27ebcSKurt Kanzenbach 29324dfc6ebSKurt Kanzenbach /* A Qbv schedule can only started up to 8 seconds in the future. If the delta 29424dfc6ebSKurt Kanzenbach * between the base time and the current ptp time is larger than 8 seconds, then 29524dfc6ebSKurt Kanzenbach * use periodic work to check for the schedule to be started. The delayed work 29624dfc6ebSKurt Kanzenbach * cannot be armed directly to $base_time - 8 + X, because for large deltas the 29724dfc6ebSKurt Kanzenbach * PTP frequency matters. 29824dfc6ebSKurt Kanzenbach */ 29924dfc6ebSKurt Kanzenbach #define HELLCREEK_SCHEDULE_PERIOD (2 * HZ) 30024dfc6ebSKurt Kanzenbach #define dw_to_hellcreek_port(dw) \ 30124dfc6ebSKurt Kanzenbach container_of(dw, struct hellcreek_port, schedule_work) 30224dfc6ebSKurt Kanzenbach 3037f976d5cSKurt Kanzenbach /* Devlink resources */ 3047f976d5cSKurt Kanzenbach enum hellcreek_devlink_resource_id { 3057f976d5cSKurt Kanzenbach HELLCREEK_DEVLINK_PARAM_ID_VLAN_TABLE, 3068486e83fSKurt Kanzenbach HELLCREEK_DEVLINK_PARAM_ID_FDB_TABLE, 3077f976d5cSKurt Kanzenbach }; 3087f976d5cSKurt Kanzenbach 309ba2d1c28SKurt Kanzenbach struct hellcreek_devlink_vlan_entry { 310ba2d1c28SKurt Kanzenbach u16 vid; 311ba2d1c28SKurt Kanzenbach u16 member; 312ba2d1c28SKurt Kanzenbach }; 313ba2d1c28SKurt Kanzenbach 314e4b27ebcSKurt Kanzenbach #endif /* _HELLCREEK_H_ */ 315