1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Broadcom Starfighter 2 switch register defines 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 #ifndef __BCM_SF2_REGS_H 8 #define __BCM_SF2_REGS_H 9 10 /* Register set relative to 'REG' */ 11 12 enum bcm_sf2_reg_offs { 13 REG_SWITCH_CNTRL = 0, 14 REG_SWITCH_STATUS, 15 REG_DIR_DATA_WRITE, 16 REG_DIR_DATA_READ, 17 REG_SWITCH_REVISION, 18 REG_PHY_REVISION, 19 REG_SPHY_CNTRL, 20 REG_CROSSBAR, 21 REG_RGMII_0_CNTRL, 22 REG_RGMII_1_CNTRL, 23 REG_RGMII_2_CNTRL, 24 REG_LED_0_CNTRL, 25 REG_LED_1_CNTRL, 26 REG_LED_2_CNTRL, 27 REG_SWITCH_REG_MAX, 28 }; 29 30 /* Relative to REG_SWITCH_CNTRL */ 31 #define MDIO_MASTER_SEL (1 << 0) 32 33 /* Relative to REG_SWITCH_REVISION */ 34 #define SF2_REV_MASK 0xffff 35 #define SWITCH_TOP_REV_SHIFT 16 36 #define SWITCH_TOP_REV_MASK 0xffff 37 38 /* Relative to REG_PHY_REVISION */ 39 #define PHY_REVISION_MASK 0xffff 40 41 /* Relative to REG_SPHY_CNTRL */ 42 #define IDDQ_BIAS (1 << 0) 43 #define EXT_PWR_DOWN (1 << 1) 44 #define FORCE_DLL_EN (1 << 2) 45 #define IDDQ_GLOBAL_PWR (1 << 3) 46 #define CK25_DIS (1 << 4) 47 #define PHY_RESET (1 << 5) 48 #define PHY_PHYAD_SHIFT 8 49 #define PHY_PHYAD_MASK 0x1F 50 51 #define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x)) 52 53 /* Relative to REG_RGMII_CNTRL */ 54 #define RGMII_MODE_EN (1 << 0) 55 #define ID_MODE_DIS (1 << 1) 56 #define PORT_MODE_SHIFT 2 57 #define INT_EPHY (0 << PORT_MODE_SHIFT) 58 #define INT_GPHY (1 << PORT_MODE_SHIFT) 59 #define EXT_EPHY (2 << PORT_MODE_SHIFT) 60 #define EXT_GPHY (3 << PORT_MODE_SHIFT) 61 #define EXT_REVMII (4 << PORT_MODE_SHIFT) 62 #define PORT_MODE_MASK 0x7 63 #define RVMII_REF_SEL (1 << 5) 64 #define RX_PAUSE_EN (1 << 6) 65 #define TX_PAUSE_EN (1 << 7) 66 #define TX_CLK_STOP_EN (1 << 8) 67 #define LPI_COUNT_SHIFT 9 68 #define LPI_COUNT_MASK 0x3F 69 70 #define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x)) 71 72 #define SPDLNK_SRC_SEL (1 << 24) 73 74 /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */ 75 #define INTRL2_CPU_STATUS 0x00 76 #define INTRL2_CPU_SET 0x04 77 #define INTRL2_CPU_CLEAR 0x08 78 #define INTRL2_CPU_MASK_STATUS 0x0c 79 #define INTRL2_CPU_MASK_SET 0x10 80 #define INTRL2_CPU_MASK_CLEAR 0x14 81 82 /* Shared INTRL2_0 and INTRL2_ interrupt sources macros */ 83 #define P_LINK_UP_IRQ(x) (1 << (0 + (x))) 84 #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x))) 85 #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x))) 86 #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x))) 87 #define P_GPHY_IRQ(x) (1 << (4 + (x))) 88 #define P_NUM_IRQ 5 89 #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \ 90 P_LINK_DOWN_IRQ((x)) | \ 91 P_ENERGY_ON_IRQ((x)) | \ 92 P_ENERGY_OFF_IRQ((x)) | \ 93 P_GPHY_IRQ((x))) 94 95 /* INTRL2_0 interrupt sources */ 96 #define P0_IRQ_OFF 0 97 #define MEM_DOUBLE_IRQ (1 << 5) 98 #define EEE_LPI_IRQ (1 << 6) 99 #define P5_CPU_WAKE_IRQ (1 << 7) 100 #define P8_CPU_WAKE_IRQ (1 << 8) 101 #define P7_CPU_WAKE_IRQ (1 << 9) 102 #define IEEE1588_IRQ (1 << 10) 103 #define MDIO_ERR_IRQ (1 << 11) 104 #define MDIO_DONE_IRQ (1 << 12) 105 #define GISB_ERR_IRQ (1 << 13) 106 #define UBUS_ERR_IRQ (1 << 14) 107 #define FAILOVER_ON_IRQ (1 << 15) 108 #define FAILOVER_OFF_IRQ (1 << 16) 109 #define TCAM_SOFT_ERR_IRQ (1 << 17) 110 111 /* INTRL2_1 interrupt sources */ 112 #define P7_IRQ_OFF 0 113 #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ) 114 115 /* Register set relative to 'ACB' */ 116 #define ACB_CONTROL 0x00 117 #define ACB_EN (1 << 0) 118 #define ACB_ALGORITHM (1 << 1) 119 #define ACB_FLUSH_SHIFT 2 120 #define ACB_FLUSH_MASK 0x3 121 122 #define ACB_QUEUE_0_CFG 0x08 123 #define XOFF_THRESHOLD_MASK 0x7ff 124 #define XON_EN (1 << 11) 125 #define TOTAL_XOFF_THRESHOLD_SHIFT 12 126 #define TOTAL_XOFF_THRESHOLD_MASK 0x7ff 127 #define TOTAL_XOFF_EN (1 << 23) 128 #define TOTAL_XON_EN (1 << 24) 129 #define PKTLEN_SHIFT 25 130 #define PKTLEN_MASK 0x3f 131 #define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4)) 132 133 /* Register set relative to 'CORE' */ 134 #define CORE_G_PCTL_PORT0 0x00000 135 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4)) 136 #define CORE_IMP_CTL 0x00020 137 #define RX_DIS (1 << 0) 138 #define TX_DIS (1 << 1) 139 #define RX_BCST_EN (1 << 2) 140 #define RX_MCST_EN (1 << 3) 141 #define RX_UCST_EN (1 << 4) 142 143 #define CORE_SWMODE 0x0002c 144 #define SW_FWDG_MODE (1 << 0) 145 #define SW_FWDG_EN (1 << 1) 146 #define RTRY_LMT_DIS (1 << 2) 147 148 #define CORE_STS_OVERRIDE_IMP 0x00038 149 #define GMII_SPEED_UP_2G (1 << 6) 150 #define MII_SW_OR (1 << 7) 151 152 /* Alternate layout for e.g: 7278 */ 153 #define CORE_STS_OVERRIDE_IMP2 0x39040 154 155 #define CORE_NEW_CTRL 0x00084 156 #define IP_MC (1 << 0) 157 #define OUTRANGEERR_DISCARD (1 << 1) 158 #define INRANGEERR_DISCARD (1 << 2) 159 #define CABLE_DIAG_LEN (1 << 3) 160 #define OVERRIDE_AUTO_PD_WAR (1 << 4) 161 #define EN_AUTO_PD_WAR (1 << 5) 162 #define UC_FWD_EN (1 << 6) 163 #define MC_FWD_EN (1 << 7) 164 165 #define CORE_SWITCH_CTRL 0x00088 166 #define MII_DUMB_FWDG_EN (1 << 6) 167 168 #define CORE_DIS_LEARN 0x000f0 169 170 #define CORE_SFT_LRN_CTRL 0x000f8 171 #define SW_LEARN_CNTL(x) (1 << (x)) 172 173 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4) 174 #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8) 175 #define LINK_STS (1 << 0) 176 #define DUPLX_MODE (1 << 1) 177 #define SPEED_SHIFT 2 178 #define SPEED_MASK 0x3 179 #define RXFLOW_CNTL (1 << 4) 180 #define TXFLOW_CNTL (1 << 5) 181 #define SW_OVERRIDE (1 << 6) 182 183 #define CORE_WATCHDOG_CTRL 0x001e4 184 #define SOFTWARE_RESET (1 << 7) 185 #define EN_CHIP_RST (1 << 6) 186 #define EN_SW_RESET (1 << 4) 187 188 #define CORE_FAST_AGE_CTRL 0x00220 189 #define EN_FAST_AGE_STATIC (1 << 0) 190 #define EN_AGE_DYNAMIC (1 << 1) 191 #define EN_AGE_PORT (1 << 2) 192 #define EN_AGE_VLAN (1 << 3) 193 #define EN_AGE_SPT (1 << 4) 194 #define EN_AGE_MCAST (1 << 5) 195 #define FAST_AGE_STR_DONE (1 << 7) 196 197 #define CORE_FAST_AGE_PORT 0x00224 198 #define AGE_PORT_MASK 0xf 199 200 #define CORE_FAST_AGE_VID 0x00228 201 #define AGE_VID_MASK 0x3fff 202 203 #define CORE_LNKSTS 0x00400 204 #define LNK_STS_MASK 0x1ff 205 206 #define CORE_SPDSTS 0x00410 207 #define SPDSTS_10 0 208 #define SPDSTS_100 1 209 #define SPDSTS_1000 2 210 #define SPDSTS_SHIFT 2 211 #define SPDSTS_MASK 0x3 212 213 #define CORE_DUPSTS 0x00420 214 #define CORE_DUPSTS_MASK 0x1ff 215 216 #define CORE_PAUSESTS 0x00428 217 #define PAUSESTS_TX_PAUSE_SHIFT 9 218 219 #define CORE_GMNCFGCFG 0x0800 220 #define RST_MIB_CNT (1 << 0) 221 #define RXBPDU_EN (1 << 1) 222 223 #define CORE_IMP0_PRT_ID 0x0804 224 225 #define CORE_RST_MIB_CNT_EN 0x0950 226 227 #define CORE_ARLA_VTBL_RWCTRL 0x1600 228 #define ARLA_VTBL_CMD_WRITE 0 229 #define ARLA_VTBL_CMD_READ 1 230 #define ARLA_VTBL_CMD_CLEAR 2 231 #define ARLA_VTBL_STDN (1 << 7) 232 233 #define CORE_ARLA_VTBL_ADDR 0x1604 234 #define VTBL_ADDR_INDEX_MASK 0xfff 235 236 #define CORE_ARLA_VTBL_ENTRY 0x160c 237 #define FWD_MAP_MASK 0x1ff 238 #define UNTAG_MAP_MASK 0x1ff 239 #define UNTAG_MAP_SHIFT 9 240 #define MSTP_INDEX_MASK 0x7 241 #define MSTP_INDEX_SHIFT 18 242 #define FWD_MODE (1 << 21) 243 244 #define CORE_MEM_PSM_VDD_CTRL 0x2380 245 #define P_TXQ_PSM_VDD_SHIFT 2 246 #define P_TXQ_PSM_VDD_MASK 0x3 247 #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \ 248 ((x) * P_TXQ_PSM_VDD_SHIFT)) 249 250 #define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10)) 251 #define PRT_TO_QID_MASK 0x3 252 #define PRT_TO_QID_SHIFT 3 253 254 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8)) 255 #define PORT_VLAN_CTRL_MASK 0x1ff 256 257 #define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80 258 #define TXQ_PAUSE_THD_MASK 0x7ff 259 #define CORE_TXQ_THD_PAUSE_QN_PORT(x) (CORE_TXQ_THD_PAUSE_QN_PORT_0 + \ 260 (x) * 0x8) 261 262 #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8)) 263 #define CFI_SHIFT 12 264 #define PRI_SHIFT 13 265 #define PRI_MASK 0x7 266 267 #define CORE_JOIN_ALL_VLAN_EN 0xd140 268 269 #define CORE_CFP_ACC 0x28000 270 #define OP_STR_DONE (1 << 0) 271 #define OP_SEL_SHIFT 1 272 #define OP_SEL_READ (1 << OP_SEL_SHIFT) 273 #define OP_SEL_WRITE (2 << OP_SEL_SHIFT) 274 #define OP_SEL_SEARCH (4 << OP_SEL_SHIFT) 275 #define OP_SEL_MASK (7 << OP_SEL_SHIFT) 276 #define CFP_RAM_CLEAR (1 << 4) 277 #define RAM_SEL_SHIFT 10 278 #define TCAM_SEL (1 << RAM_SEL_SHIFT) 279 #define ACT_POL_RAM (2 << RAM_SEL_SHIFT) 280 #define RATE_METER_RAM (4 << RAM_SEL_SHIFT) 281 #define GREEN_STAT_RAM (8 << RAM_SEL_SHIFT) 282 #define YELLOW_STAT_RAM (16 << RAM_SEL_SHIFT) 283 #define RED_STAT_RAM (24 << RAM_SEL_SHIFT) 284 #define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT) 285 #define TCAM_RESET (1 << 15) 286 #define XCESS_ADDR_SHIFT 16 287 #define XCESS_ADDR_MASK 0xff 288 #define SEARCH_STS (1 << 27) 289 #define RD_STS_SHIFT 28 290 #define RD_STS_TCAM (1 << RD_STS_SHIFT) 291 #define RD_STS_ACT_POL_RAM (2 << RD_STS_SHIFT) 292 #define RD_STS_RATE_METER_RAM (4 << RD_STS_SHIFT) 293 #define RD_STS_STAT_RAM (8 << RD_STS_SHIFT) 294 295 #define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010 296 297 #define CORE_CFP_DATA_PORT_0 0x28040 298 #define CORE_CFP_DATA_PORT(x) (CORE_CFP_DATA_PORT_0 + \ 299 (x) * 0x10) 300 301 /* UDF_DATA7 */ 302 #define L3_FRAMING_SHIFT 24 303 #define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT) 304 #define IPTOS_SHIFT 16 305 #define IPTOS_MASK 0xff 306 #define IPPROTO_SHIFT 8 307 #define IPPROTO_MASK (0xff << IPPROTO_SHIFT) 308 #define IP_FRAG_SHIFT 7 309 #define IP_FRAG (1 << IP_FRAG_SHIFT) 310 311 /* UDF_DATA0 */ 312 #define SLICE_VALID 3 313 #define SLICE_NUM_SHIFT 2 314 #define SLICE_NUM(x) ((x) << SLICE_NUM_SHIFT) 315 #define SLICE_NUM_MASK 0x3 316 317 #define CORE_CFP_MASK_PORT_0 0x280c0 318 319 #define CORE_CFP_MASK_PORT(x) (CORE_CFP_MASK_PORT_0 + \ 320 (x) * 0x10) 321 322 #define CORE_ACT_POL_DATA0 0x28140 323 #define VLAN_BYP (1 << 0) 324 #define EAP_BYP (1 << 1) 325 #define STP_BYP (1 << 2) 326 #define REASON_CODE_SHIFT 3 327 #define REASON_CODE_MASK 0x3f 328 #define LOOP_BK_EN (1 << 9) 329 #define NEW_TC_SHIFT 10 330 #define NEW_TC_MASK 0x7 331 #define CHANGE_TC (1 << 13) 332 #define DST_MAP_IB_SHIFT 14 333 #define DST_MAP_IB_MASK 0x1ff 334 #define CHANGE_FWRD_MAP_IB_SHIFT 24 335 #define CHANGE_FWRD_MAP_IB_MASK 0x3 336 #define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT) 337 #define CHANGE_FWRD_MAP_IB_REM_ARL (1 << CHANGE_FWRD_MAP_IB_SHIFT) 338 #define CHANGE_FWRD_MAP_IB_REP_ARL (2 << CHANGE_FWRD_MAP_IB_SHIFT) 339 #define CHANGE_FWRD_MAP_IB_ADD_DST (3 << CHANGE_FWRD_MAP_IB_SHIFT) 340 #define NEW_DSCP_IB_SHIFT 26 341 #define NEW_DSCP_IB_MASK 0x3f 342 343 #define CORE_ACT_POL_DATA1 0x28150 344 #define CHANGE_DSCP_IB (1 << 0) 345 #define DST_MAP_OB_SHIFT 1 346 #define DST_MAP_OB_MASK 0x3ff 347 #define CHANGE_FWRD_MAP_OB_SHIT 11 348 #define CHANGE_FWRD_MAP_OB_MASK 0x3 349 #define NEW_DSCP_OB_SHIFT 13 350 #define NEW_DSCP_OB_MASK 0x3f 351 #define CHANGE_DSCP_OB (1 << 19) 352 #define CHAIN_ID_SHIFT 20 353 #define CHAIN_ID_MASK 0xff 354 #define CHANGE_COLOR (1 << 28) 355 #define NEW_COLOR_SHIFT 29 356 #define NEW_COLOR_MASK 0x3 357 #define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT) 358 #define NEW_COLOR_YELLOW (1 << NEW_COLOR_SHIFT) 359 #define NEW_COLOR_RED (2 << NEW_COLOR_SHIFT) 360 #define RED_DEFAULT (1 << 31) 361 362 #define CORE_ACT_POL_DATA2 0x28160 363 #define MAC_LIMIT_BYPASS (1 << 0) 364 #define CHANGE_TC_O (1 << 1) 365 #define NEW_TC_O_SHIFT 2 366 #define NEW_TC_O_MASK 0x7 367 #define SPCP_RMK_DISABLE (1 << 5) 368 #define CPCP_RMK_DISABLE (1 << 6) 369 #define DEI_RMK_DISABLE (1 << 7) 370 371 #define CORE_RATE_METER0 0x28180 372 #define COLOR_MODE (1 << 0) 373 #define POLICER_ACTION (1 << 1) 374 #define COUPLING_FLAG (1 << 2) 375 #define POLICER_MODE_SHIFT 3 376 #define POLICER_MODE_MASK 0x3 377 #define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT) 378 #define POLICER_MODE_RFC4115 (1 << POLICER_MODE_SHIFT) 379 #define POLICER_MODE_MEF (2 << POLICER_MODE_SHIFT) 380 #define POLICER_MODE_DISABLE (3 << POLICER_MODE_SHIFT) 381 382 #define CORE_RATE_METER1 0x28190 383 #define EIR_TK_BKT_MASK 0x7fffff 384 385 #define CORE_RATE_METER2 0x281a0 386 #define EIR_BKT_SIZE_MASK 0xfffff 387 388 #define CORE_RATE_METER3 0x281b0 389 #define EIR_REF_CNT_MASK 0x7ffff 390 391 #define CORE_RATE_METER4 0x281c0 392 #define CIR_TK_BKT_MASK 0x7fffff 393 394 #define CORE_RATE_METER5 0x281d0 395 #define CIR_BKT_SIZE_MASK 0xfffff 396 397 #define CORE_RATE_METER6 0x281e0 398 #define CIR_REF_CNT_MASK 0x7ffff 399 400 #define CORE_STAT_GREEN_CNTR 0x28200 401 #define CORE_STAT_YELLOW_CNTR 0x28210 402 #define CORE_STAT_RED_CNTR 0x28220 403 404 #define CORE_CFP_CTL_REG 0x28400 405 #define CFP_EN_MAP_MASK 0x1ff 406 407 /* IPv4 slices, 3 of them */ 408 #define CORE_UDF_0_A_0_8_PORT_0 0x28440 409 #define CFG_UDF_OFFSET_MASK 0x1f 410 #define CFG_UDF_OFFSET_BASE_SHIFT 5 411 #define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT) 412 #define CFG_UDF_EOL2 (2 << CFG_UDF_OFFSET_BASE_SHIFT) 413 #define CFG_UDF_EOL3 (3 << CFG_UDF_OFFSET_BASE_SHIFT) 414 415 /* IPv6 slices */ 416 #define CORE_UDF_0_B_0_8_PORT_0 0x28500 417 418 /* IPv6 chained slices */ 419 #define CORE_UDF_0_D_0_11_PORT_0 0x28680 420 421 /* Number of slices for IPv4, IPv6 and non-IP */ 422 #define UDF_NUM_SLICES 4 423 #define UDFS_PER_SLICE 9 424 425 /* Spacing between different slices */ 426 #define UDF_SLICE_OFFSET 0x40 427 428 #define CFP_NUM_RULES 256 429 430 /* Number of egress queues per port */ 431 #define SF2_NUM_EGRESS_QUEUES 8 432 433 #endif /* __BCM_SF2_REGS_H */ 434