1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Broadcom Starfighter 2 switch register defines 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 #ifndef __BCM_SF2_REGS_H 8 #define __BCM_SF2_REGS_H 9 10 /* Register set relative to 'REG' */ 11 12 enum bcm_sf2_reg_offs { 13 REG_SWITCH_CNTRL = 0, 14 REG_SWITCH_STATUS, 15 REG_DIR_DATA_WRITE, 16 REG_DIR_DATA_READ, 17 REG_SWITCH_REVISION, 18 REG_PHY_REVISION, 19 REG_SPHY_CNTRL, 20 REG_CROSSBAR, 21 REG_RGMII_0_CNTRL, 22 REG_RGMII_1_CNTRL, 23 REG_RGMII_2_CNTRL, 24 REG_RGMII_11_CNTRL, 25 REG_LED_0_CNTRL, 26 REG_LED_1_CNTRL, 27 REG_LED_2_CNTRL, 28 REG_LED_3_CNTRL, 29 REG_LED_4_CNTRL, 30 REG_LED_5_CNTRL, 31 REG_LED_AGGREGATE_CTRL, 32 REG_SWITCH_REG_MAX, 33 }; 34 35 /* Relative to REG_SWITCH_CNTRL */ 36 #define MDIO_MASTER_SEL (1 << 0) 37 38 /* Relative to REG_SWITCH_REVISION */ 39 #define SF2_REV_MASK 0xffff 40 #define SWITCH_TOP_REV_SHIFT 16 41 #define SWITCH_TOP_REV_MASK 0xffff 42 43 /* Relative to REG_PHY_REVISION */ 44 #define PHY_REVISION_MASK 0xffff 45 46 /* Relative to REG_SPHY_CNTRL */ 47 #define IDDQ_BIAS (1 << 0) 48 #define EXT_PWR_DOWN (1 << 1) 49 #define FORCE_DLL_EN (1 << 2) 50 #define IDDQ_GLOBAL_PWR (1 << 3) 51 #define CK25_DIS (1 << 4) 52 #define PHY_RESET (1 << 5) 53 #define PHY_PHYAD_SHIFT 8 54 #define PHY_PHYAD_MASK 0x1F 55 56 /* Relative to REG_CROSSBAR */ 57 #define CROSSBAR_BCM4908_INT_P7 0 58 #define CROSSBAR_BCM4908_INT_RUNNER 1 59 #define CROSSBAR_BCM4908_EXT_SERDES 0 60 #define CROSSBAR_BCM4908_EXT_GPHY4 1 61 #define CROSSBAR_BCM4908_EXT_RGMII 2 62 63 /* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */ 64 #define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0 65 #define LED_CNTRL_M10_ENCODE_SHIFT 2 66 #define LED_CNTRL_M100_ENCODE_SHIFT 4 67 #define LED_CNTRL_M1000_ENCODE_SHIFT 6 68 #define LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT 8 69 #define LED_CNTRL_SEL_10M_ENCODE_SHIFT 10 70 #define LED_CNTRL_SEL_100M_ENCODE_SHIFT 12 71 #define LED_CNTRL_SEL_1000M_ENCODE_SHIFT 14 72 #define LED_CNTRL_RX_DV_EN (1 << 16) 73 #define LED_CNTRL_TX_EN_EN (1 << 17) 74 #define LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT 18 75 #define LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT 20 76 #define LED_CNTRL_ACT_LED_ACT_SEL_SHIFT 22 77 #define LED_CNTRL_SPDLNK_SRC_SEL (1 << 24) 78 #define LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL (1 << 25) 79 #define LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL (1 << 26) 80 #define LED_CNTRL_ACT_LED_POL_SEL (1 << 27) 81 #define LED_CNTRL_MASK 0x3 82 83 /* Register relative to REG_LED_*_CNTRL (BCM4908) */ 84 #define REG_LED_CTRL 0x0 85 #define LED_CTRL_RX_ACT_EN 0x00000001 86 #define LED_CTRL_TX_ACT_EN 0x00000002 87 #define LED_CTRL_SPDLNK_LED0_ACT_SEL 0x00000004 88 #define LED_CTRL_SPDLNK_LED1_ACT_SEL 0x00000008 89 #define LED_CTRL_SPDLNK_LED2_ACT_SEL 0x00000010 90 #define LED_CTRL_ACT_LED_ACT_SEL 0x00000020 91 #define LED_CTRL_SPDLNK_LED0_ACT_POL_SEL 0x00000040 92 #define LED_CTRL_SPDLNK_LED1_ACT_POL_SEL 0x00000080 93 #define LED_CTRL_SPDLNK_LED2_ACT_POL_SEL 0x00000100 94 #define LED_CTRL_ACT_LED_POL_SEL 0x00000200 95 #define LED_CTRL_LED_SPD_OVRD 0x00001c00 96 #define LED_CTRL_LNK_STATUS_OVRD 0x00002000 97 #define LED_CTRL_SPD_OVRD_EN 0x00004000 98 #define LED_CTRL_LNK_OVRD_EN 0x00008000 99 100 /* Register relative to REG_LED_*_CNTRL (BCM4908) */ 101 #define REG_LED_LINK_SPEED_ENC_SEL 0x4 102 #define LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT 0 103 #define LED_LINK_SPEED_ENC_SEL_10M_SHIFT 3 104 #define LED_LINK_SPEED_ENC_SEL_100M_SHIFT 6 105 #define LED_LINK_SPEED_ENC_SEL_1000M_SHIFT 9 106 #define LED_LINK_SPEED_ENC_SEL_2500M_SHIFT 12 107 #define LED_LINK_SPEED_ENC_SEL_10G_SHIFT 15 108 #define LED_LINK_SPEED_ENC_SEL_MASK 0x7 109 110 /* Register relative to REG_LED_*_CNTRL (BCM4908) */ 111 #define REG_LED_LINK_SPEED_ENC 0x8 112 #define LED_LINK_SPEED_ENC_NO_LINK_SHIFT 0 113 #define LED_LINK_SPEED_ENC_M10_SHIFT 3 114 #define LED_LINK_SPEED_ENC_M100_SHIFT 6 115 #define LED_LINK_SPEED_ENC_M1000_SHIFT 9 116 #define LED_LINK_SPEED_ENC_M2500_SHIFT 12 117 #define LED_LINK_SPEED_ENC_M10G_SHIFT 15 118 #define LED_LINK_SPEED_ENC_MASK 0x7 119 120 /* Relative to REG_RGMII_CNTRL */ 121 #define RGMII_MODE_EN (1 << 0) 122 #define ID_MODE_DIS (1 << 1) 123 #define PORT_MODE_SHIFT 2 124 #define INT_EPHY (0 << PORT_MODE_SHIFT) 125 #define INT_GPHY (1 << PORT_MODE_SHIFT) 126 #define EXT_EPHY (2 << PORT_MODE_SHIFT) 127 #define EXT_GPHY (3 << PORT_MODE_SHIFT) 128 #define EXT_REVMII (4 << PORT_MODE_SHIFT) 129 #define PORT_MODE_MASK 0x7 130 #define RVMII_REF_SEL (1 << 5) 131 #define RX_PAUSE_EN (1 << 6) 132 #define TX_PAUSE_EN (1 << 7) 133 #define TX_CLK_STOP_EN (1 << 8) 134 #define LPI_COUNT_SHIFT 9 135 #define LPI_COUNT_MASK 0x3F 136 137 /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */ 138 #define INTRL2_CPU_STATUS 0x00 139 #define INTRL2_CPU_SET 0x04 140 #define INTRL2_CPU_CLEAR 0x08 141 #define INTRL2_CPU_MASK_STATUS 0x0c 142 #define INTRL2_CPU_MASK_SET 0x10 143 #define INTRL2_CPU_MASK_CLEAR 0x14 144 145 /* Shared INTRL2_0 and INTRL2_ interrupt sources macros */ 146 #define P_LINK_UP_IRQ(x) (1 << (0 + (x))) 147 #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x))) 148 #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x))) 149 #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x))) 150 #define P_GPHY_IRQ(x) (1 << (4 + (x))) 151 #define P_NUM_IRQ 5 152 #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \ 153 P_LINK_DOWN_IRQ((x)) | \ 154 P_ENERGY_ON_IRQ((x)) | \ 155 P_ENERGY_OFF_IRQ((x)) | \ 156 P_GPHY_IRQ((x))) 157 158 /* INTRL2_0 interrupt sources */ 159 #define P0_IRQ_OFF 0 160 #define MEM_DOUBLE_IRQ (1 << 5) 161 #define EEE_LPI_IRQ (1 << 6) 162 #define P5_CPU_WAKE_IRQ (1 << 7) 163 #define P8_CPU_WAKE_IRQ (1 << 8) 164 #define P7_CPU_WAKE_IRQ (1 << 9) 165 #define IEEE1588_IRQ (1 << 10) 166 #define MDIO_ERR_IRQ (1 << 11) 167 #define MDIO_DONE_IRQ (1 << 12) 168 #define GISB_ERR_IRQ (1 << 13) 169 #define UBUS_ERR_IRQ (1 << 14) 170 #define FAILOVER_ON_IRQ (1 << 15) 171 #define FAILOVER_OFF_IRQ (1 << 16) 172 #define TCAM_SOFT_ERR_IRQ (1 << 17) 173 174 /* INTRL2_1 interrupt sources */ 175 #define P7_IRQ_OFF 0 176 #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ) 177 178 /* Register set relative to 'ACB' */ 179 #define ACB_CONTROL 0x00 180 #define ACB_EN (1 << 0) 181 #define ACB_ALGORITHM (1 << 1) 182 #define ACB_FLUSH_SHIFT 2 183 #define ACB_FLUSH_MASK 0x3 184 185 #define ACB_QUEUE_0_CFG 0x08 186 #define XOFF_THRESHOLD_MASK 0x7ff 187 #define XON_EN (1 << 11) 188 #define TOTAL_XOFF_THRESHOLD_SHIFT 12 189 #define TOTAL_XOFF_THRESHOLD_MASK 0x7ff 190 #define TOTAL_XOFF_EN (1 << 23) 191 #define TOTAL_XON_EN (1 << 24) 192 #define PKTLEN_SHIFT 25 193 #define PKTLEN_MASK 0x3f 194 #define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4)) 195 196 /* Register set relative to 'CORE' */ 197 #define CORE_G_PCTL_PORT0 0x00000 198 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4)) 199 #define CORE_IMP_CTL 0x00020 200 #define RX_DIS (1 << 0) 201 #define TX_DIS (1 << 1) 202 #define RX_BCST_EN (1 << 2) 203 #define RX_MCST_EN (1 << 3) 204 #define RX_UCST_EN (1 << 4) 205 206 #define CORE_SWMODE 0x0002c 207 #define SW_FWDG_MODE (1 << 0) 208 #define SW_FWDG_EN (1 << 1) 209 #define RTRY_LMT_DIS (1 << 2) 210 211 #define CORE_STS_OVERRIDE_IMP 0x00038 212 #define GMII_SPEED_UP_2G (1 << 6) 213 #define MII_SW_OR (1 << 7) 214 215 /* Alternate layout for e.g: 7278 */ 216 #define CORE_STS_OVERRIDE_IMP2 0x39040 217 218 #define CORE_NEW_CTRL 0x00084 219 #define IP_MC (1 << 0) 220 #define OUTRANGEERR_DISCARD (1 << 1) 221 #define INRANGEERR_DISCARD (1 << 2) 222 #define CABLE_DIAG_LEN (1 << 3) 223 #define OVERRIDE_AUTO_PD_WAR (1 << 4) 224 #define EN_AUTO_PD_WAR (1 << 5) 225 #define UC_FWD_EN (1 << 6) 226 #define MC_FWD_EN (1 << 7) 227 228 #define CORE_SWITCH_CTRL 0x00088 229 #define MII_DUMB_FWDG_EN (1 << 6) 230 231 #define CORE_DIS_LEARN 0x000f0 232 233 #define CORE_SFT_LRN_CTRL 0x000f8 234 #define SW_LEARN_CNTL(x) (1 << (x)) 235 236 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4) 237 #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8) 238 #define LINK_STS (1 << 0) 239 #define DUPLX_MODE (1 << 1) 240 #define SPEED_SHIFT 2 241 #define SPEED_MASK 0x3 242 #define RXFLOW_CNTL (1 << 4) 243 #define TXFLOW_CNTL (1 << 5) 244 #define SW_OVERRIDE (1 << 6) 245 246 #define CORE_WATCHDOG_CTRL 0x001e4 247 #define SOFTWARE_RESET (1 << 7) 248 #define EN_CHIP_RST (1 << 6) 249 #define EN_SW_RESET (1 << 4) 250 251 #define CORE_FAST_AGE_CTRL 0x00220 252 #define EN_FAST_AGE_STATIC (1 << 0) 253 #define EN_AGE_DYNAMIC (1 << 1) 254 #define EN_AGE_PORT (1 << 2) 255 #define EN_AGE_VLAN (1 << 3) 256 #define EN_AGE_SPT (1 << 4) 257 #define EN_AGE_MCAST (1 << 5) 258 #define FAST_AGE_STR_DONE (1 << 7) 259 260 #define CORE_FAST_AGE_PORT 0x00224 261 #define AGE_PORT_MASK 0xf 262 263 #define CORE_FAST_AGE_VID 0x00228 264 #define AGE_VID_MASK 0x3fff 265 266 #define CORE_LNKSTS 0x00400 267 #define LNK_STS_MASK 0x1ff 268 269 #define CORE_SPDSTS 0x00410 270 #define SPDSTS_10 0 271 #define SPDSTS_100 1 272 #define SPDSTS_1000 2 273 #define SPDSTS_SHIFT 2 274 #define SPDSTS_MASK 0x3 275 276 #define CORE_DUPSTS 0x00420 277 #define CORE_DUPSTS_MASK 0x1ff 278 279 #define CORE_PAUSESTS 0x00428 280 #define PAUSESTS_TX_PAUSE_SHIFT 9 281 282 #define CORE_GMNCFGCFG 0x0800 283 #define RST_MIB_CNT (1 << 0) 284 #define RXBPDU_EN (1 << 1) 285 286 #define CORE_IMP0_PRT_ID 0x0804 287 288 #define CORE_RST_MIB_CNT_EN 0x0950 289 290 #define CORE_ARLA_VTBL_RWCTRL 0x1600 291 #define ARLA_VTBL_CMD_WRITE 0 292 #define ARLA_VTBL_CMD_READ 1 293 #define ARLA_VTBL_CMD_CLEAR 2 294 #define ARLA_VTBL_STDN (1 << 7) 295 296 #define CORE_ARLA_VTBL_ADDR 0x1604 297 #define VTBL_ADDR_INDEX_MASK 0xfff 298 299 #define CORE_ARLA_VTBL_ENTRY 0x160c 300 #define FWD_MAP_MASK 0x1ff 301 #define UNTAG_MAP_MASK 0x1ff 302 #define UNTAG_MAP_SHIFT 9 303 #define MSTP_INDEX_MASK 0x7 304 #define MSTP_INDEX_SHIFT 18 305 #define FWD_MODE (1 << 21) 306 307 #define CORE_MEM_PSM_VDD_CTRL 0x2380 308 #define P_TXQ_PSM_VDD_SHIFT 2 309 #define P_TXQ_PSM_VDD_MASK 0x3 310 #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \ 311 ((x) * P_TXQ_PSM_VDD_SHIFT)) 312 313 #define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10)) 314 #define PRT_TO_QID_MASK 0x3 315 #define PRT_TO_QID_SHIFT 3 316 317 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8)) 318 #define PORT_VLAN_CTRL_MASK 0x1ff 319 320 #define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80 321 #define TXQ_PAUSE_THD_MASK 0x7ff 322 #define CORE_TXQ_THD_PAUSE_QN_PORT(x) (CORE_TXQ_THD_PAUSE_QN_PORT_0 + \ 323 (x) * 0x8) 324 325 #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8)) 326 #define CFI_SHIFT 12 327 #define PRI_SHIFT 13 328 #define PRI_MASK 0x7 329 330 #define CORE_JOIN_ALL_VLAN_EN 0xd140 331 332 #define CORE_CFP_ACC 0x28000 333 #define OP_STR_DONE (1 << 0) 334 #define OP_SEL_SHIFT 1 335 #define OP_SEL_READ (1 << OP_SEL_SHIFT) 336 #define OP_SEL_WRITE (2 << OP_SEL_SHIFT) 337 #define OP_SEL_SEARCH (4 << OP_SEL_SHIFT) 338 #define OP_SEL_MASK (7 << OP_SEL_SHIFT) 339 #define CFP_RAM_CLEAR (1 << 4) 340 #define RAM_SEL_SHIFT 10 341 #define TCAM_SEL (1 << RAM_SEL_SHIFT) 342 #define ACT_POL_RAM (2 << RAM_SEL_SHIFT) 343 #define RATE_METER_RAM (4 << RAM_SEL_SHIFT) 344 #define GREEN_STAT_RAM (8 << RAM_SEL_SHIFT) 345 #define YELLOW_STAT_RAM (16 << RAM_SEL_SHIFT) 346 #define RED_STAT_RAM (24 << RAM_SEL_SHIFT) 347 #define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT) 348 #define TCAM_RESET (1 << 15) 349 #define XCESS_ADDR_SHIFT 16 350 #define XCESS_ADDR_MASK 0xff 351 #define SEARCH_STS (1 << 27) 352 #define RD_STS_SHIFT 28 353 #define RD_STS_TCAM (1 << RD_STS_SHIFT) 354 #define RD_STS_ACT_POL_RAM (2 << RD_STS_SHIFT) 355 #define RD_STS_RATE_METER_RAM (4 << RD_STS_SHIFT) 356 #define RD_STS_STAT_RAM (8 << RD_STS_SHIFT) 357 358 #define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010 359 360 #define CORE_CFP_DATA_PORT_0 0x28040 361 #define CORE_CFP_DATA_PORT(x) (CORE_CFP_DATA_PORT_0 + \ 362 (x) * 0x10) 363 364 /* UDF_DATA7 */ 365 #define L3_FRAMING_SHIFT 24 366 #define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT) 367 #define IPTOS_SHIFT 16 368 #define IPTOS_MASK 0xff 369 #define IPPROTO_SHIFT 8 370 #define IPPROTO_MASK (0xff << IPPROTO_SHIFT) 371 #define IP_FRAG_SHIFT 7 372 #define IP_FRAG (1 << IP_FRAG_SHIFT) 373 374 /* UDF_DATA0 */ 375 #define SLICE_VALID 3 376 #define SLICE_NUM_SHIFT 2 377 #define SLICE_NUM(x) ((x) << SLICE_NUM_SHIFT) 378 #define SLICE_NUM_MASK 0x3 379 380 #define CORE_CFP_MASK_PORT_0 0x280c0 381 382 #define CORE_CFP_MASK_PORT(x) (CORE_CFP_MASK_PORT_0 + \ 383 (x) * 0x10) 384 385 #define CORE_ACT_POL_DATA0 0x28140 386 #define VLAN_BYP (1 << 0) 387 #define EAP_BYP (1 << 1) 388 #define STP_BYP (1 << 2) 389 #define REASON_CODE_SHIFT 3 390 #define REASON_CODE_MASK 0x3f 391 #define LOOP_BK_EN (1 << 9) 392 #define NEW_TC_SHIFT 10 393 #define NEW_TC_MASK 0x7 394 #define CHANGE_TC (1 << 13) 395 #define DST_MAP_IB_SHIFT 14 396 #define DST_MAP_IB_MASK 0x1ff 397 #define CHANGE_FWRD_MAP_IB_SHIFT 24 398 #define CHANGE_FWRD_MAP_IB_MASK 0x3 399 #define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT) 400 #define CHANGE_FWRD_MAP_IB_REM_ARL (1 << CHANGE_FWRD_MAP_IB_SHIFT) 401 #define CHANGE_FWRD_MAP_IB_REP_ARL (2 << CHANGE_FWRD_MAP_IB_SHIFT) 402 #define CHANGE_FWRD_MAP_IB_ADD_DST (3 << CHANGE_FWRD_MAP_IB_SHIFT) 403 #define NEW_DSCP_IB_SHIFT 26 404 #define NEW_DSCP_IB_MASK 0x3f 405 406 #define CORE_ACT_POL_DATA1 0x28150 407 #define CHANGE_DSCP_IB (1 << 0) 408 #define DST_MAP_OB_SHIFT 1 409 #define DST_MAP_OB_MASK 0x3ff 410 #define CHANGE_FWRD_MAP_OB_SHIT 11 411 #define CHANGE_FWRD_MAP_OB_MASK 0x3 412 #define NEW_DSCP_OB_SHIFT 13 413 #define NEW_DSCP_OB_MASK 0x3f 414 #define CHANGE_DSCP_OB (1 << 19) 415 #define CHAIN_ID_SHIFT 20 416 #define CHAIN_ID_MASK 0xff 417 #define CHANGE_COLOR (1 << 28) 418 #define NEW_COLOR_SHIFT 29 419 #define NEW_COLOR_MASK 0x3 420 #define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT) 421 #define NEW_COLOR_YELLOW (1 << NEW_COLOR_SHIFT) 422 #define NEW_COLOR_RED (2 << NEW_COLOR_SHIFT) 423 #define RED_DEFAULT (1 << 31) 424 425 #define CORE_ACT_POL_DATA2 0x28160 426 #define MAC_LIMIT_BYPASS (1 << 0) 427 #define CHANGE_TC_O (1 << 1) 428 #define NEW_TC_O_SHIFT 2 429 #define NEW_TC_O_MASK 0x7 430 #define SPCP_RMK_DISABLE (1 << 5) 431 #define CPCP_RMK_DISABLE (1 << 6) 432 #define DEI_RMK_DISABLE (1 << 7) 433 434 #define CORE_RATE_METER0 0x28180 435 #define COLOR_MODE (1 << 0) 436 #define POLICER_ACTION (1 << 1) 437 #define COUPLING_FLAG (1 << 2) 438 #define POLICER_MODE_SHIFT 3 439 #define POLICER_MODE_MASK 0x3 440 #define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT) 441 #define POLICER_MODE_RFC4115 (1 << POLICER_MODE_SHIFT) 442 #define POLICER_MODE_MEF (2 << POLICER_MODE_SHIFT) 443 #define POLICER_MODE_DISABLE (3 << POLICER_MODE_SHIFT) 444 445 #define CORE_RATE_METER1 0x28190 446 #define EIR_TK_BKT_MASK 0x7fffff 447 448 #define CORE_RATE_METER2 0x281a0 449 #define EIR_BKT_SIZE_MASK 0xfffff 450 451 #define CORE_RATE_METER3 0x281b0 452 #define EIR_REF_CNT_MASK 0x7ffff 453 454 #define CORE_RATE_METER4 0x281c0 455 #define CIR_TK_BKT_MASK 0x7fffff 456 457 #define CORE_RATE_METER5 0x281d0 458 #define CIR_BKT_SIZE_MASK 0xfffff 459 460 #define CORE_RATE_METER6 0x281e0 461 #define CIR_REF_CNT_MASK 0x7ffff 462 463 #define CORE_STAT_GREEN_CNTR 0x28200 464 #define CORE_STAT_YELLOW_CNTR 0x28210 465 #define CORE_STAT_RED_CNTR 0x28220 466 467 #define CORE_CFP_CTL_REG 0x28400 468 #define CFP_EN_MAP_MASK 0x1ff 469 470 /* IPv4 slices, 3 of them */ 471 #define CORE_UDF_0_A_0_8_PORT_0 0x28440 472 #define CFG_UDF_OFFSET_MASK 0x1f 473 #define CFG_UDF_OFFSET_BASE_SHIFT 5 474 #define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT) 475 #define CFG_UDF_EOL2 (2 << CFG_UDF_OFFSET_BASE_SHIFT) 476 #define CFG_UDF_EOL3 (3 << CFG_UDF_OFFSET_BASE_SHIFT) 477 478 /* IPv6 slices */ 479 #define CORE_UDF_0_B_0_8_PORT_0 0x28500 480 481 /* IPv6 chained slices */ 482 #define CORE_UDF_0_D_0_11_PORT_0 0x28680 483 484 /* Number of slices for IPv4, IPv6 and non-IP */ 485 #define UDF_NUM_SLICES 4 486 #define UDFS_PER_SLICE 9 487 488 /* Spacing between different slices */ 489 #define UDF_SLICE_OFFSET 0x40 490 491 #define CFP_NUM_RULES 256 492 493 /* Number of egress queues per port */ 494 #define SF2_NUM_EGRESS_QUEUES 8 495 496 #endif /* __BCM_SF2_REGS_H */ 497