1 /* 2 * Broadcom Starfighter 2 switch register defines 3 * 4 * Copyright (C) 2014, Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 #ifndef __BCM_SF2_REGS_H 12 #define __BCM_SF2_REGS_H 13 14 /* Register set relative to 'REG' */ 15 16 enum bcm_sf2_reg_offs { 17 REG_SWITCH_CNTRL = 0, 18 REG_SWITCH_STATUS, 19 REG_DIR_DATA_WRITE, 20 REG_DIR_DATA_READ, 21 REG_SWITCH_REVISION, 22 REG_PHY_REVISION, 23 REG_SPHY_CNTRL, 24 REG_RGMII_0_CNTRL, 25 REG_RGMII_1_CNTRL, 26 REG_RGMII_2_CNTRL, 27 REG_LED_0_CNTRL, 28 REG_LED_1_CNTRL, 29 REG_LED_2_CNTRL, 30 REG_SWITCH_REG_MAX, 31 }; 32 33 /* Relative to REG_SWITCH_CNTRL */ 34 #define MDIO_MASTER_SEL (1 << 0) 35 36 /* Relative to REG_SWITCH_REVISION */ 37 #define SF2_REV_MASK 0xffff 38 #define SWITCH_TOP_REV_SHIFT 16 39 #define SWITCH_TOP_REV_MASK 0xffff 40 41 /* Relative to REG_PHY_REVISION */ 42 #define PHY_REVISION_MASK 0xffff 43 44 /* Relative to REG_SPHY_CNTRL */ 45 #define IDDQ_BIAS (1 << 0) 46 #define EXT_PWR_DOWN (1 << 1) 47 #define FORCE_DLL_EN (1 << 2) 48 #define IDDQ_GLOBAL_PWR (1 << 3) 49 #define CK25_DIS (1 << 4) 50 #define PHY_RESET (1 << 5) 51 #define PHY_PHYAD_SHIFT 8 52 #define PHY_PHYAD_MASK 0x1F 53 54 #define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x)) 55 56 /* Relative to REG_RGMII_CNTRL */ 57 #define RGMII_MODE_EN (1 << 0) 58 #define ID_MODE_DIS (1 << 1) 59 #define PORT_MODE_SHIFT 2 60 #define INT_EPHY (0 << PORT_MODE_SHIFT) 61 #define INT_GPHY (1 << PORT_MODE_SHIFT) 62 #define EXT_EPHY (2 << PORT_MODE_SHIFT) 63 #define EXT_GPHY (3 << PORT_MODE_SHIFT) 64 #define EXT_REVMII (4 << PORT_MODE_SHIFT) 65 #define PORT_MODE_MASK 0x7 66 #define RVMII_REF_SEL (1 << 5) 67 #define RX_PAUSE_EN (1 << 6) 68 #define TX_PAUSE_EN (1 << 7) 69 #define TX_CLK_STOP_EN (1 << 8) 70 #define LPI_COUNT_SHIFT 9 71 #define LPI_COUNT_MASK 0x3F 72 73 #define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x)) 74 75 #define SPDLNK_SRC_SEL (1 << 24) 76 77 /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */ 78 #define INTRL2_CPU_STATUS 0x00 79 #define INTRL2_CPU_SET 0x04 80 #define INTRL2_CPU_CLEAR 0x08 81 #define INTRL2_CPU_MASK_STATUS 0x0c 82 #define INTRL2_CPU_MASK_SET 0x10 83 #define INTRL2_CPU_MASK_CLEAR 0x14 84 85 /* Shared INTRL2_0 and INTRL2_ interrupt sources macros */ 86 #define P_LINK_UP_IRQ(x) (1 << (0 + (x))) 87 #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x))) 88 #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x))) 89 #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x))) 90 #define P_GPHY_IRQ(x) (1 << (4 + (x))) 91 #define P_NUM_IRQ 5 92 #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \ 93 P_LINK_DOWN_IRQ((x)) | \ 94 P_ENERGY_ON_IRQ((x)) | \ 95 P_ENERGY_OFF_IRQ((x)) | \ 96 P_GPHY_IRQ((x))) 97 98 /* INTRL2_0 interrupt sources */ 99 #define P0_IRQ_OFF 0 100 #define MEM_DOUBLE_IRQ (1 << 5) 101 #define EEE_LPI_IRQ (1 << 6) 102 #define P5_CPU_WAKE_IRQ (1 << 7) 103 #define P8_CPU_WAKE_IRQ (1 << 8) 104 #define P7_CPU_WAKE_IRQ (1 << 9) 105 #define IEEE1588_IRQ (1 << 10) 106 #define MDIO_ERR_IRQ (1 << 11) 107 #define MDIO_DONE_IRQ (1 << 12) 108 #define GISB_ERR_IRQ (1 << 13) 109 #define UBUS_ERR_IRQ (1 << 14) 110 #define FAILOVER_ON_IRQ (1 << 15) 111 #define FAILOVER_OFF_IRQ (1 << 16) 112 #define TCAM_SOFT_ERR_IRQ (1 << 17) 113 114 /* INTRL2_1 interrupt sources */ 115 #define P7_IRQ_OFF 0 116 #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ) 117 118 /* Register set relative to 'ACB' */ 119 #define ACB_CONTROL 0x00 120 #define ACB_EN (1 << 0) 121 #define ACB_ALGORITHM (1 << 1) 122 #define ACB_FLUSH_SHIFT 2 123 #define ACB_FLUSH_MASK 0x3 124 125 #define ACB_QUEUE_0_CFG 0x08 126 #define XOFF_THRESHOLD_MASK 0x7ff 127 #define XON_EN (1 << 11) 128 #define TOTAL_XOFF_THRESHOLD_SHIFT 12 129 #define TOTAL_XOFF_THRESHOLD_MASK 0x7ff 130 #define TOTAL_XOFF_EN (1 << 23) 131 #define TOTAL_XON_EN (1 << 24) 132 #define PKTLEN_SHIFT 25 133 #define PKTLEN_MASK 0x3f 134 #define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4)) 135 136 /* Register set relative to 'CORE' */ 137 #define CORE_G_PCTL_PORT0 0x00000 138 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4)) 139 #define CORE_IMP_CTL 0x00020 140 #define RX_DIS (1 << 0) 141 #define TX_DIS (1 << 1) 142 #define RX_BCST_EN (1 << 2) 143 #define RX_MCST_EN (1 << 3) 144 #define RX_UCST_EN (1 << 4) 145 146 #define CORE_SWMODE 0x0002c 147 #define SW_FWDG_MODE (1 << 0) 148 #define SW_FWDG_EN (1 << 1) 149 #define RTRY_LMT_DIS (1 << 2) 150 151 #define CORE_STS_OVERRIDE_IMP 0x00038 152 #define GMII_SPEED_UP_2G (1 << 6) 153 #define MII_SW_OR (1 << 7) 154 155 /* Alternate layout for e.g: 7278 */ 156 #define CORE_STS_OVERRIDE_IMP2 0x39040 157 158 #define CORE_NEW_CTRL 0x00084 159 #define IP_MC (1 << 0) 160 #define OUTRANGEERR_DISCARD (1 << 1) 161 #define INRANGEERR_DISCARD (1 << 2) 162 #define CABLE_DIAG_LEN (1 << 3) 163 #define OVERRIDE_AUTO_PD_WAR (1 << 4) 164 #define EN_AUTO_PD_WAR (1 << 5) 165 #define UC_FWD_EN (1 << 6) 166 #define MC_FWD_EN (1 << 7) 167 168 #define CORE_SWITCH_CTRL 0x00088 169 #define MII_DUMB_FWDG_EN (1 << 6) 170 171 #define CORE_DIS_LEARN 0x000f0 172 173 #define CORE_SFT_LRN_CTRL 0x000f8 174 #define SW_LEARN_CNTL(x) (1 << (x)) 175 176 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4) 177 #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8) 178 #define LINK_STS (1 << 0) 179 #define DUPLX_MODE (1 << 1) 180 #define SPEED_SHIFT 2 181 #define SPEED_MASK 0x3 182 #define RXFLOW_CNTL (1 << 4) 183 #define TXFLOW_CNTL (1 << 5) 184 #define SW_OVERRIDE (1 << 6) 185 186 #define CORE_WATCHDOG_CTRL 0x001e4 187 #define SOFTWARE_RESET (1 << 7) 188 #define EN_CHIP_RST (1 << 6) 189 #define EN_SW_RESET (1 << 4) 190 191 #define CORE_FAST_AGE_CTRL 0x00220 192 #define EN_FAST_AGE_STATIC (1 << 0) 193 #define EN_AGE_DYNAMIC (1 << 1) 194 #define EN_AGE_PORT (1 << 2) 195 #define EN_AGE_VLAN (1 << 3) 196 #define EN_AGE_SPT (1 << 4) 197 #define EN_AGE_MCAST (1 << 5) 198 #define FAST_AGE_STR_DONE (1 << 7) 199 200 #define CORE_FAST_AGE_PORT 0x00224 201 #define AGE_PORT_MASK 0xf 202 203 #define CORE_FAST_AGE_VID 0x00228 204 #define AGE_VID_MASK 0x3fff 205 206 #define CORE_LNKSTS 0x00400 207 #define LNK_STS_MASK 0x1ff 208 209 #define CORE_SPDSTS 0x00410 210 #define SPDSTS_10 0 211 #define SPDSTS_100 1 212 #define SPDSTS_1000 2 213 #define SPDSTS_SHIFT 2 214 #define SPDSTS_MASK 0x3 215 216 #define CORE_DUPSTS 0x00420 217 #define CORE_DUPSTS_MASK 0x1ff 218 219 #define CORE_PAUSESTS 0x00428 220 #define PAUSESTS_TX_PAUSE_SHIFT 9 221 222 #define CORE_GMNCFGCFG 0x0800 223 #define RST_MIB_CNT (1 << 0) 224 #define RXBPDU_EN (1 << 1) 225 226 #define CORE_IMP0_PRT_ID 0x0804 227 228 #define CORE_RST_MIB_CNT_EN 0x0950 229 230 #define CORE_ARLA_VTBL_RWCTRL 0x1600 231 #define ARLA_VTBL_CMD_WRITE 0 232 #define ARLA_VTBL_CMD_READ 1 233 #define ARLA_VTBL_CMD_CLEAR 2 234 #define ARLA_VTBL_STDN (1 << 7) 235 236 #define CORE_ARLA_VTBL_ADDR 0x1604 237 #define VTBL_ADDR_INDEX_MASK 0xfff 238 239 #define CORE_ARLA_VTBL_ENTRY 0x160c 240 #define FWD_MAP_MASK 0x1ff 241 #define UNTAG_MAP_MASK 0x1ff 242 #define UNTAG_MAP_SHIFT 9 243 #define MSTP_INDEX_MASK 0x7 244 #define MSTP_INDEX_SHIFT 18 245 #define FWD_MODE (1 << 21) 246 247 #define CORE_MEM_PSM_VDD_CTRL 0x2380 248 #define P_TXQ_PSM_VDD_SHIFT 2 249 #define P_TXQ_PSM_VDD_MASK 0x3 250 #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \ 251 ((x) * P_TXQ_PSM_VDD_SHIFT)) 252 253 #define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10)) 254 #define PRT_TO_QID_MASK 0x3 255 #define PRT_TO_QID_SHIFT 3 256 257 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8)) 258 #define PORT_VLAN_CTRL_MASK 0x1ff 259 260 #define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80 261 #define TXQ_PAUSE_THD_MASK 0x7ff 262 #define CORE_TXQ_THD_PAUSE_QN_PORT(x) (CORE_TXQ_THD_PAUSE_QN_PORT_0 + \ 263 (x) * 0x8) 264 265 #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8)) 266 #define CFI_SHIFT 12 267 #define PRI_SHIFT 13 268 #define PRI_MASK 0x7 269 270 #define CORE_JOIN_ALL_VLAN_EN 0xd140 271 272 #define CORE_CFP_ACC 0x28000 273 #define OP_STR_DONE (1 << 0) 274 #define OP_SEL_SHIFT 1 275 #define OP_SEL_READ (1 << OP_SEL_SHIFT) 276 #define OP_SEL_WRITE (2 << OP_SEL_SHIFT) 277 #define OP_SEL_SEARCH (4 << OP_SEL_SHIFT) 278 #define OP_SEL_MASK (7 << OP_SEL_SHIFT) 279 #define CFP_RAM_CLEAR (1 << 4) 280 #define RAM_SEL_SHIFT 10 281 #define TCAM_SEL (1 << RAM_SEL_SHIFT) 282 #define ACT_POL_RAM (2 << RAM_SEL_SHIFT) 283 #define RATE_METER_RAM (4 << RAM_SEL_SHIFT) 284 #define GREEN_STAT_RAM (8 << RAM_SEL_SHIFT) 285 #define YELLOW_STAT_RAM (16 << RAM_SEL_SHIFT) 286 #define RED_STAT_RAM (24 << RAM_SEL_SHIFT) 287 #define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT) 288 #define TCAM_RESET (1 << 15) 289 #define XCESS_ADDR_SHIFT 16 290 #define XCESS_ADDR_MASK 0xff 291 #define SEARCH_STS (1 << 27) 292 #define RD_STS_SHIFT 28 293 #define RD_STS_TCAM (1 << RD_STS_SHIFT) 294 #define RD_STS_ACT_POL_RAM (2 << RD_STS_SHIFT) 295 #define RD_STS_RATE_METER_RAM (4 << RD_STS_SHIFT) 296 #define RD_STS_STAT_RAM (8 << RD_STS_SHIFT) 297 298 #define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010 299 300 #define CORE_CFP_DATA_PORT_0 0x28040 301 #define CORE_CFP_DATA_PORT(x) (CORE_CFP_DATA_PORT_0 + \ 302 (x) * 0x10) 303 304 /* UDF_DATA7 */ 305 #define L3_FRAMING_SHIFT 24 306 #define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT) 307 #define IPTOS_SHIFT 16 308 #define IPTOS_MASK 0xff 309 #define IPPROTO_SHIFT 8 310 #define IPPROTO_MASK (0xff << IPPROTO_SHIFT) 311 #define IP_FRAG_SHIFT 7 312 #define IP_FRAG (1 << IP_FRAG_SHIFT) 313 314 /* UDF_DATA0 */ 315 #define SLICE_VALID 3 316 #define SLICE_NUM_SHIFT 2 317 #define SLICE_NUM(x) ((x) << SLICE_NUM_SHIFT) 318 #define SLICE_NUM_MASK 0x3 319 320 #define CORE_CFP_MASK_PORT_0 0x280c0 321 322 #define CORE_CFP_MASK_PORT(x) (CORE_CFP_MASK_PORT_0 + \ 323 (x) * 0x10) 324 325 #define CORE_ACT_POL_DATA0 0x28140 326 #define VLAN_BYP (1 << 0) 327 #define EAP_BYP (1 << 1) 328 #define STP_BYP (1 << 2) 329 #define REASON_CODE_SHIFT 3 330 #define REASON_CODE_MASK 0x3f 331 #define LOOP_BK_EN (1 << 9) 332 #define NEW_TC_SHIFT 10 333 #define NEW_TC_MASK 0x7 334 #define CHANGE_TC (1 << 13) 335 #define DST_MAP_IB_SHIFT 14 336 #define DST_MAP_IB_MASK 0x1ff 337 #define CHANGE_FWRD_MAP_IB_SHIFT 24 338 #define CHANGE_FWRD_MAP_IB_MASK 0x3 339 #define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT) 340 #define CHANGE_FWRD_MAP_IB_REM_ARL (1 << CHANGE_FWRD_MAP_IB_SHIFT) 341 #define CHANGE_FWRD_MAP_IB_REP_ARL (2 << CHANGE_FWRD_MAP_IB_SHIFT) 342 #define CHANGE_FWRD_MAP_IB_ADD_DST (3 << CHANGE_FWRD_MAP_IB_SHIFT) 343 #define NEW_DSCP_IB_SHIFT 26 344 #define NEW_DSCP_IB_MASK 0x3f 345 346 #define CORE_ACT_POL_DATA1 0x28150 347 #define CHANGE_DSCP_IB (1 << 0) 348 #define DST_MAP_OB_SHIFT 1 349 #define DST_MAP_OB_MASK 0x3ff 350 #define CHANGE_FWRD_MAP_OB_SHIT 11 351 #define CHANGE_FWRD_MAP_OB_MASK 0x3 352 #define NEW_DSCP_OB_SHIFT 13 353 #define NEW_DSCP_OB_MASK 0x3f 354 #define CHANGE_DSCP_OB (1 << 19) 355 #define CHAIN_ID_SHIFT 20 356 #define CHAIN_ID_MASK 0xff 357 #define CHANGE_COLOR (1 << 28) 358 #define NEW_COLOR_SHIFT 29 359 #define NEW_COLOR_MASK 0x3 360 #define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT) 361 #define NEW_COLOR_YELLOW (1 << NEW_COLOR_SHIFT) 362 #define NEW_COLOR_RED (2 << NEW_COLOR_SHIFT) 363 #define RED_DEFAULT (1 << 31) 364 365 #define CORE_ACT_POL_DATA2 0x28160 366 #define MAC_LIMIT_BYPASS (1 << 0) 367 #define CHANGE_TC_O (1 << 1) 368 #define NEW_TC_O_SHIFT 2 369 #define NEW_TC_O_MASK 0x7 370 #define SPCP_RMK_DISABLE (1 << 5) 371 #define CPCP_RMK_DISABLE (1 << 6) 372 #define DEI_RMK_DISABLE (1 << 7) 373 374 #define CORE_RATE_METER0 0x28180 375 #define COLOR_MODE (1 << 0) 376 #define POLICER_ACTION (1 << 1) 377 #define COUPLING_FLAG (1 << 2) 378 #define POLICER_MODE_SHIFT 3 379 #define POLICER_MODE_MASK 0x3 380 #define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT) 381 #define POLICER_MODE_RFC4115 (1 << POLICER_MODE_SHIFT) 382 #define POLICER_MODE_MEF (2 << POLICER_MODE_SHIFT) 383 #define POLICER_MODE_DISABLE (3 << POLICER_MODE_SHIFT) 384 385 #define CORE_RATE_METER1 0x28190 386 #define EIR_TK_BKT_MASK 0x7fffff 387 388 #define CORE_RATE_METER2 0x281a0 389 #define EIR_BKT_SIZE_MASK 0xfffff 390 391 #define CORE_RATE_METER3 0x281b0 392 #define EIR_REF_CNT_MASK 0x7ffff 393 394 #define CORE_RATE_METER4 0x281c0 395 #define CIR_TK_BKT_MASK 0x7fffff 396 397 #define CORE_RATE_METER5 0x281d0 398 #define CIR_BKT_SIZE_MASK 0xfffff 399 400 #define CORE_RATE_METER6 0x281e0 401 #define CIR_REF_CNT_MASK 0x7ffff 402 403 #define CORE_CFP_CTL_REG 0x28400 404 #define CFP_EN_MAP_MASK 0x1ff 405 406 /* IPv4 slices, 3 of them */ 407 #define CORE_UDF_0_A_0_8_PORT_0 0x28440 408 #define CFG_UDF_OFFSET_MASK 0x1f 409 #define CFG_UDF_OFFSET_BASE_SHIFT 5 410 #define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT) 411 #define CFG_UDF_EOL2 (2 << CFG_UDF_OFFSET_BASE_SHIFT) 412 #define CFG_UDF_EOL3 (3 << CFG_UDF_OFFSET_BASE_SHIFT) 413 414 /* IPv6 slices */ 415 #define CORE_UDF_0_B_0_8_PORT_0 0x28500 416 417 /* IPv6 chained slices */ 418 #define CORE_UDF_0_D_0_11_PORT_0 0x28680 419 420 /* Number of slices for IPv4, IPv6 and non-IP */ 421 #define UDF_NUM_SLICES 4 422 #define UDFS_PER_SLICE 9 423 424 /* Spacing between different slices */ 425 #define UDF_SLICE_OFFSET 0x40 426 427 #define CFP_NUM_RULES 256 428 429 /* Number of egress queues per port */ 430 #define SF2_NUM_EGRESS_QUEUES 8 431 432 #endif /* __BCM_SF2_REGS_H */ 433