12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
27318166cSFlorian Fainelli /*
37318166cSFlorian Fainelli * Broadcom Starfighter 2 DSA switch CFP support
47318166cSFlorian Fainelli *
57318166cSFlorian Fainelli * Copyright (C) 2016, Broadcom
67318166cSFlorian Fainelli */
77318166cSFlorian Fainelli
87318166cSFlorian Fainelli #include <linux/list.h>
97318166cSFlorian Fainelli #include <linux/ethtool.h>
107318166cSFlorian Fainelli #include <linux/if_ether.h>
117318166cSFlorian Fainelli #include <linux/in.h>
12c6e970a0SAndrew Lunn #include <linux/netdevice.h>
13c6e970a0SAndrew Lunn #include <net/dsa.h>
147318166cSFlorian Fainelli #include <linux/bitmap.h>
15e4f7ef54SPablo Neira Ayuso #include <net/flow_offload.h>
168b3abe30SFlorian Fainelli #include <net/switchdev.h>
178b3abe30SFlorian Fainelli #include <uapi/linux/if_bridge.h>
187318166cSFlorian Fainelli
197318166cSFlorian Fainelli #include "bcm_sf2.h"
207318166cSFlorian Fainelli #include "bcm_sf2_regs.h"
217318166cSFlorian Fainelli
22ae7a5affSFlorian Fainelli struct cfp_rule {
23ae7a5affSFlorian Fainelli int port;
24ae7a5affSFlorian Fainelli struct ethtool_rx_flow_spec fs;
25ae7a5affSFlorian Fainelli struct list_head next;
26ae7a5affSFlorian Fainelli };
27ae7a5affSFlorian Fainelli
285d80bcbbSFlorian Fainelli struct cfp_udf_slice_layout {
295d80bcbbSFlorian Fainelli u8 slices[UDFS_PER_SLICE];
307318166cSFlorian Fainelli u32 mask_value;
315d80bcbbSFlorian Fainelli u32 base_offset;
327318166cSFlorian Fainelli };
337318166cSFlorian Fainelli
345d80bcbbSFlorian Fainelli struct cfp_udf_layout {
355d80bcbbSFlorian Fainelli struct cfp_udf_slice_layout udfs[UDF_NUM_SLICES];
365d80bcbbSFlorian Fainelli };
375d80bcbbSFlorian Fainelli
385d80bcbbSFlorian Fainelli static const u8 zero_slice[UDFS_PER_SLICE] = { };
395d80bcbbSFlorian Fainelli
407318166cSFlorian Fainelli /* UDF slices layout for a TCPv4/UDPv4 specification */
417318166cSFlorian Fainelli static const struct cfp_udf_layout udf_tcpip4_layout = {
425d80bcbbSFlorian Fainelli .udfs = {
435d80bcbbSFlorian Fainelli [1] = {
447318166cSFlorian Fainelli .slices = {
457318166cSFlorian Fainelli /* End of L2, byte offset 12, src IP[0:15] */
467318166cSFlorian Fainelli CFG_UDF_EOL2 | 6,
477318166cSFlorian Fainelli /* End of L2, byte offset 14, src IP[16:31] */
487318166cSFlorian Fainelli CFG_UDF_EOL2 | 7,
497318166cSFlorian Fainelli /* End of L2, byte offset 16, dst IP[0:15] */
507318166cSFlorian Fainelli CFG_UDF_EOL2 | 8,
517318166cSFlorian Fainelli /* End of L2, byte offset 18, dst IP[16:31] */
527318166cSFlorian Fainelli CFG_UDF_EOL2 | 9,
537318166cSFlorian Fainelli /* End of L3, byte offset 0, src port */
547318166cSFlorian Fainelli CFG_UDF_EOL3 | 0,
557318166cSFlorian Fainelli /* End of L3, byte offset 2, dst port */
567318166cSFlorian Fainelli CFG_UDF_EOL3 | 1,
577318166cSFlorian Fainelli 0, 0, 0
587318166cSFlorian Fainelli },
597318166cSFlorian Fainelli .mask_value = L3_FRAMING_MASK | IPPROTO_MASK | IP_FRAG,
605d80bcbbSFlorian Fainelli .base_offset = CORE_UDF_0_A_0_8_PORT_0 + UDF_SLICE_OFFSET,
615d80bcbbSFlorian Fainelli },
625d80bcbbSFlorian Fainelli },
637318166cSFlorian Fainelli };
647318166cSFlorian Fainelli
65ba0696c2SFlorian Fainelli /* UDF slices layout for a TCPv6/UDPv6 specification */
66ba0696c2SFlorian Fainelli static const struct cfp_udf_layout udf_tcpip6_layout = {
67ba0696c2SFlorian Fainelli .udfs = {
68ba0696c2SFlorian Fainelli [0] = {
69ba0696c2SFlorian Fainelli .slices = {
70ba0696c2SFlorian Fainelli /* End of L2, byte offset 8, src IP[0:15] */
71ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 4,
72ba0696c2SFlorian Fainelli /* End of L2, byte offset 10, src IP[16:31] */
73ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 5,
74ba0696c2SFlorian Fainelli /* End of L2, byte offset 12, src IP[32:47] */
75ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 6,
76ba0696c2SFlorian Fainelli /* End of L2, byte offset 14, src IP[48:63] */
77ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 7,
78ba0696c2SFlorian Fainelli /* End of L2, byte offset 16, src IP[64:79] */
79ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 8,
80ba0696c2SFlorian Fainelli /* End of L2, byte offset 18, src IP[80:95] */
81ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 9,
82ba0696c2SFlorian Fainelli /* End of L2, byte offset 20, src IP[96:111] */
83ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 10,
84ba0696c2SFlorian Fainelli /* End of L2, byte offset 22, src IP[112:127] */
85ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 11,
86ba0696c2SFlorian Fainelli /* End of L3, byte offset 0, src port */
87ba0696c2SFlorian Fainelli CFG_UDF_EOL3 | 0,
88ba0696c2SFlorian Fainelli },
89ba0696c2SFlorian Fainelli .mask_value = L3_FRAMING_MASK | IPPROTO_MASK | IP_FRAG,
90ba0696c2SFlorian Fainelli .base_offset = CORE_UDF_0_B_0_8_PORT_0,
91ba0696c2SFlorian Fainelli },
92ba0696c2SFlorian Fainelli [3] = {
93ba0696c2SFlorian Fainelli .slices = {
94ba0696c2SFlorian Fainelli /* End of L2, byte offset 24, dst IP[0:15] */
95ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 12,
96ba0696c2SFlorian Fainelli /* End of L2, byte offset 26, dst IP[16:31] */
97ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 13,
98ba0696c2SFlorian Fainelli /* End of L2, byte offset 28, dst IP[32:47] */
99ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 14,
100ba0696c2SFlorian Fainelli /* End of L2, byte offset 30, dst IP[48:63] */
101ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 15,
102ba0696c2SFlorian Fainelli /* End of L2, byte offset 32, dst IP[64:79] */
103ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 16,
104ba0696c2SFlorian Fainelli /* End of L2, byte offset 34, dst IP[80:95] */
105ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 17,
106ba0696c2SFlorian Fainelli /* End of L2, byte offset 36, dst IP[96:111] */
107ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 18,
108ba0696c2SFlorian Fainelli /* End of L2, byte offset 38, dst IP[112:127] */
109ba0696c2SFlorian Fainelli CFG_UDF_EOL2 | 19,
110ba0696c2SFlorian Fainelli /* End of L3, byte offset 2, dst port */
111ba0696c2SFlorian Fainelli CFG_UDF_EOL3 | 1,
112ba0696c2SFlorian Fainelli },
113ba0696c2SFlorian Fainelli .mask_value = L3_FRAMING_MASK | IPPROTO_MASK | IP_FRAG,
114ba0696c2SFlorian Fainelli .base_offset = CORE_UDF_0_D_0_11_PORT_0,
115ba0696c2SFlorian Fainelli },
116ba0696c2SFlorian Fainelli },
117ba0696c2SFlorian Fainelli };
118ba0696c2SFlorian Fainelli
bcm_sf2_get_num_udf_slices(const u8 * layout)1197318166cSFlorian Fainelli static inline unsigned int bcm_sf2_get_num_udf_slices(const u8 *layout)
1207318166cSFlorian Fainelli {
1217318166cSFlorian Fainelli unsigned int i, count = 0;
1227318166cSFlorian Fainelli
1235d80bcbbSFlorian Fainelli for (i = 0; i < UDFS_PER_SLICE; i++) {
1247318166cSFlorian Fainelli if (layout[i] != 0)
1257318166cSFlorian Fainelli count++;
1267318166cSFlorian Fainelli }
1277318166cSFlorian Fainelli
1287318166cSFlorian Fainelli return count;
1297318166cSFlorian Fainelli }
1307318166cSFlorian Fainelli
udf_upper_bits(int num_udf)131c226e271SAndrew Lunn static inline u32 udf_upper_bits(int num_udf)
1327318166cSFlorian Fainelli {
1335d80bcbbSFlorian Fainelli return GENMASK(num_udf - 1, 0) >> (UDFS_PER_SLICE - 1);
1345d80bcbbSFlorian Fainelli }
1355d80bcbbSFlorian Fainelli
udf_lower_bits(int num_udf)136c226e271SAndrew Lunn static inline u32 udf_lower_bits(int num_udf)
1375d80bcbbSFlorian Fainelli {
1385d80bcbbSFlorian Fainelli return (u8)GENMASK(num_udf - 1, 0);
1395d80bcbbSFlorian Fainelli }
1405d80bcbbSFlorian Fainelli
bcm_sf2_get_slice_number(const struct cfp_udf_layout * l,unsigned int start)1415d80bcbbSFlorian Fainelli static unsigned int bcm_sf2_get_slice_number(const struct cfp_udf_layout *l,
1425d80bcbbSFlorian Fainelli unsigned int start)
1435d80bcbbSFlorian Fainelli {
1445d80bcbbSFlorian Fainelli const struct cfp_udf_slice_layout *slice_layout;
1455d80bcbbSFlorian Fainelli unsigned int slice_idx;
1465d80bcbbSFlorian Fainelli
1475d80bcbbSFlorian Fainelli for (slice_idx = start; slice_idx < UDF_NUM_SLICES; slice_idx++) {
1485d80bcbbSFlorian Fainelli slice_layout = &l->udfs[slice_idx];
1495d80bcbbSFlorian Fainelli if (memcmp(slice_layout->slices, zero_slice,
1505d80bcbbSFlorian Fainelli sizeof(zero_slice)))
1515d80bcbbSFlorian Fainelli break;
1525d80bcbbSFlorian Fainelli }
1535d80bcbbSFlorian Fainelli
1545d80bcbbSFlorian Fainelli return slice_idx;
1555d80bcbbSFlorian Fainelli }
1565d80bcbbSFlorian Fainelli
bcm_sf2_cfp_udf_set(struct bcm_sf2_priv * priv,const struct cfp_udf_layout * layout,unsigned int slice_num)1575d80bcbbSFlorian Fainelli static void bcm_sf2_cfp_udf_set(struct bcm_sf2_priv *priv,
1585d80bcbbSFlorian Fainelli const struct cfp_udf_layout *layout,
1595d80bcbbSFlorian Fainelli unsigned int slice_num)
1605d80bcbbSFlorian Fainelli {
1615d80bcbbSFlorian Fainelli u32 offset = layout->udfs[slice_num].base_offset;
1627318166cSFlorian Fainelli unsigned int i;
1637318166cSFlorian Fainelli
1645d80bcbbSFlorian Fainelli for (i = 0; i < UDFS_PER_SLICE; i++)
1655d80bcbbSFlorian Fainelli core_writel(priv, layout->udfs[slice_num].slices[i],
1665d80bcbbSFlorian Fainelli offset + i * 4);
1677318166cSFlorian Fainelli }
1687318166cSFlorian Fainelli
bcm_sf2_cfp_op(struct bcm_sf2_priv * priv,unsigned int op)1697318166cSFlorian Fainelli static int bcm_sf2_cfp_op(struct bcm_sf2_priv *priv, unsigned int op)
1707318166cSFlorian Fainelli {
1717318166cSFlorian Fainelli unsigned int timeout = 1000;
1727318166cSFlorian Fainelli u32 reg;
1737318166cSFlorian Fainelli
1747318166cSFlorian Fainelli reg = core_readl(priv, CORE_CFP_ACC);
1757318166cSFlorian Fainelli reg &= ~(OP_SEL_MASK | RAM_SEL_MASK);
1767318166cSFlorian Fainelli reg |= OP_STR_DONE | op;
1777318166cSFlorian Fainelli core_writel(priv, reg, CORE_CFP_ACC);
1787318166cSFlorian Fainelli
1797318166cSFlorian Fainelli do {
1807318166cSFlorian Fainelli reg = core_readl(priv, CORE_CFP_ACC);
1817318166cSFlorian Fainelli if (!(reg & OP_STR_DONE))
1827318166cSFlorian Fainelli break;
1837318166cSFlorian Fainelli
1847318166cSFlorian Fainelli cpu_relax();
1857318166cSFlorian Fainelli } while (timeout--);
1867318166cSFlorian Fainelli
1877318166cSFlorian Fainelli if (!timeout)
1887318166cSFlorian Fainelli return -ETIMEDOUT;
1897318166cSFlorian Fainelli
1907318166cSFlorian Fainelli return 0;
1917318166cSFlorian Fainelli }
1927318166cSFlorian Fainelli
bcm_sf2_cfp_rule_addr_set(struct bcm_sf2_priv * priv,unsigned int addr)1937318166cSFlorian Fainelli static inline void bcm_sf2_cfp_rule_addr_set(struct bcm_sf2_priv *priv,
1947318166cSFlorian Fainelli unsigned int addr)
1957318166cSFlorian Fainelli {
1967318166cSFlorian Fainelli u32 reg;
1977318166cSFlorian Fainelli
198df191632SFlorian Fainelli WARN_ON(addr >= priv->num_cfp_rules);
1997318166cSFlorian Fainelli
2007318166cSFlorian Fainelli reg = core_readl(priv, CORE_CFP_ACC);
2017318166cSFlorian Fainelli reg &= ~(XCESS_ADDR_MASK << XCESS_ADDR_SHIFT);
2027318166cSFlorian Fainelli reg |= addr << XCESS_ADDR_SHIFT;
2037318166cSFlorian Fainelli core_writel(priv, reg, CORE_CFP_ACC);
2047318166cSFlorian Fainelli }
2057318166cSFlorian Fainelli
bcm_sf2_cfp_rule_size(struct bcm_sf2_priv * priv)2067318166cSFlorian Fainelli static inline unsigned int bcm_sf2_cfp_rule_size(struct bcm_sf2_priv *priv)
2077318166cSFlorian Fainelli {
2087318166cSFlorian Fainelli /* Entry #0 is reserved */
209df191632SFlorian Fainelli return priv->num_cfp_rules - 1;
2107318166cSFlorian Fainelli }
2117318166cSFlorian Fainelli
bcm_sf2_cfp_act_pol_set(struct bcm_sf2_priv * priv,unsigned int rule_index,int src_port,unsigned int port_num,unsigned int queue_num,bool fwd_map_change)21233061458SFlorian Fainelli static int bcm_sf2_cfp_act_pol_set(struct bcm_sf2_priv *priv,
21333061458SFlorian Fainelli unsigned int rule_index,
214db78ed27SFlorian Fainelli int src_port,
21533061458SFlorian Fainelli unsigned int port_num,
216ba0696c2SFlorian Fainelli unsigned int queue_num,
217ba0696c2SFlorian Fainelli bool fwd_map_change)
21833061458SFlorian Fainelli {
21933061458SFlorian Fainelli int ret;
22033061458SFlorian Fainelli u32 reg;
22133061458SFlorian Fainelli
22233061458SFlorian Fainelli /* Replace ARL derived destination with DST_MAP derived, define
22333061458SFlorian Fainelli * which port and queue this should be forwarded to.
22433061458SFlorian Fainelli */
225ba0696c2SFlorian Fainelli if (fwd_map_change)
226ba0696c2SFlorian Fainelli reg = CHANGE_FWRD_MAP_IB_REP_ARL |
227ba0696c2SFlorian Fainelli BIT(port_num + DST_MAP_IB_SHIFT) |
22833061458SFlorian Fainelli CHANGE_TC | queue_num << NEW_TC_SHIFT;
229ba0696c2SFlorian Fainelli else
230ba0696c2SFlorian Fainelli reg = 0;
23133061458SFlorian Fainelli
232db78ed27SFlorian Fainelli /* Enable looping back to the original port */
233db78ed27SFlorian Fainelli if (src_port == port_num)
234db78ed27SFlorian Fainelli reg |= LOOP_BK_EN;
235db78ed27SFlorian Fainelli
23633061458SFlorian Fainelli core_writel(priv, reg, CORE_ACT_POL_DATA0);
23733061458SFlorian Fainelli
23833061458SFlorian Fainelli /* Set classification ID that needs to be put in Broadcom tag */
239ba0696c2SFlorian Fainelli core_writel(priv, rule_index << CHAIN_ID_SHIFT, CORE_ACT_POL_DATA1);
24033061458SFlorian Fainelli
24133061458SFlorian Fainelli core_writel(priv, 0, CORE_ACT_POL_DATA2);
24233061458SFlorian Fainelli
24333061458SFlorian Fainelli /* Configure policer RAM now */
24433061458SFlorian Fainelli ret = bcm_sf2_cfp_op(priv, OP_SEL_WRITE | ACT_POL_RAM);
24533061458SFlorian Fainelli if (ret) {
24633061458SFlorian Fainelli pr_err("Policer entry at %d failed\n", rule_index);
24733061458SFlorian Fainelli return ret;
24833061458SFlorian Fainelli }
24933061458SFlorian Fainelli
25033061458SFlorian Fainelli /* Disable the policer */
25133061458SFlorian Fainelli core_writel(priv, POLICER_MODE_DISABLE, CORE_RATE_METER0);
25233061458SFlorian Fainelli
25333061458SFlorian Fainelli /* Now the rate meter */
25433061458SFlorian Fainelli ret = bcm_sf2_cfp_op(priv, OP_SEL_WRITE | RATE_METER_RAM);
25533061458SFlorian Fainelli if (ret) {
25633061458SFlorian Fainelli pr_err("Meter entry at %d failed\n", rule_index);
25733061458SFlorian Fainelli return ret;
25833061458SFlorian Fainelli }
25933061458SFlorian Fainelli
26033061458SFlorian Fainelli return 0;
26133061458SFlorian Fainelli }
26233061458SFlorian Fainelli
bcm_sf2_cfp_slice_ipv4(struct bcm_sf2_priv * priv,struct flow_dissector_key_ipv4_addrs * addrs,struct flow_dissector_key_ports * ports,const __be16 vlan_tci,unsigned int slice_num,u8 num_udf,bool mask)263bc3fc44cSFlorian Fainelli static void bcm_sf2_cfp_slice_ipv4(struct bcm_sf2_priv *priv,
264e4f7ef54SPablo Neira Ayuso struct flow_dissector_key_ipv4_addrs *addrs,
265e4f7ef54SPablo Neira Ayuso struct flow_dissector_key_ports *ports,
2667555020cSFlorian Fainelli const __be16 vlan_tci,
267c2d639d1SFlorian Fainelli unsigned int slice_num, u8 num_udf,
268bc3fc44cSFlorian Fainelli bool mask)
269bc3fc44cSFlorian Fainelli {
270bc3fc44cSFlorian Fainelli u32 reg, offset;
271bc3fc44cSFlorian Fainelli
272c2d639d1SFlorian Fainelli /* UDF_Valid[7:0] [31:24]
273c2d639d1SFlorian Fainelli * S-Tag [23:8]
274c2d639d1SFlorian Fainelli * C-Tag [7:0]
275c2d639d1SFlorian Fainelli */
2767555020cSFlorian Fainelli reg = udf_lower_bits(num_udf) << 24 | be16_to_cpu(vlan_tci) >> 8;
277c2d639d1SFlorian Fainelli if (mask)
2787555020cSFlorian Fainelli core_writel(priv, reg, CORE_CFP_MASK_PORT(5));
279c2d639d1SFlorian Fainelli else
2807555020cSFlorian Fainelli core_writel(priv, reg, CORE_CFP_DATA_PORT(5));
281c2d639d1SFlorian Fainelli
282bc3fc44cSFlorian Fainelli /* C-Tag [31:24]
283bc3fc44cSFlorian Fainelli * UDF_n_A8 [23:8]
284bc3fc44cSFlorian Fainelli * UDF_n_A7 [7:0]
285bc3fc44cSFlorian Fainelli */
2867555020cSFlorian Fainelli reg = (u32)(be16_to_cpu(vlan_tci) & 0xff) << 24;
287bc3fc44cSFlorian Fainelli if (mask)
288bc3fc44cSFlorian Fainelli offset = CORE_CFP_MASK_PORT(4);
289bc3fc44cSFlorian Fainelli else
290bc3fc44cSFlorian Fainelli offset = CORE_CFP_DATA_PORT(4);
291bc3fc44cSFlorian Fainelli core_writel(priv, reg, offset);
292bc3fc44cSFlorian Fainelli
293bc3fc44cSFlorian Fainelli /* UDF_n_A7 [31:24]
294bc3fc44cSFlorian Fainelli * UDF_n_A6 [23:8]
295bc3fc44cSFlorian Fainelli * UDF_n_A5 [7:0]
296bc3fc44cSFlorian Fainelli */
297e4f7ef54SPablo Neira Ayuso reg = be16_to_cpu(ports->dst) >> 8;
298bc3fc44cSFlorian Fainelli if (mask)
299bc3fc44cSFlorian Fainelli offset = CORE_CFP_MASK_PORT(3);
300bc3fc44cSFlorian Fainelli else
301bc3fc44cSFlorian Fainelli offset = CORE_CFP_DATA_PORT(3);
302bc3fc44cSFlorian Fainelli core_writel(priv, reg, offset);
303bc3fc44cSFlorian Fainelli
304bc3fc44cSFlorian Fainelli /* UDF_n_A5 [31:24]
305bc3fc44cSFlorian Fainelli * UDF_n_A4 [23:8]
306bc3fc44cSFlorian Fainelli * UDF_n_A3 [7:0]
307bc3fc44cSFlorian Fainelli */
308e4f7ef54SPablo Neira Ayuso reg = (be16_to_cpu(ports->dst) & 0xff) << 24 |
309e4f7ef54SPablo Neira Ayuso (u32)be16_to_cpu(ports->src) << 8 |
310e4f7ef54SPablo Neira Ayuso (be32_to_cpu(addrs->dst) & 0x0000ff00) >> 8;
311bc3fc44cSFlorian Fainelli if (mask)
312bc3fc44cSFlorian Fainelli offset = CORE_CFP_MASK_PORT(2);
313bc3fc44cSFlorian Fainelli else
314bc3fc44cSFlorian Fainelli offset = CORE_CFP_DATA_PORT(2);
315bc3fc44cSFlorian Fainelli core_writel(priv, reg, offset);
316bc3fc44cSFlorian Fainelli
317bc3fc44cSFlorian Fainelli /* UDF_n_A3 [31:24]
318bc3fc44cSFlorian Fainelli * UDF_n_A2 [23:8]
319bc3fc44cSFlorian Fainelli * UDF_n_A1 [7:0]
320bc3fc44cSFlorian Fainelli */
321e4f7ef54SPablo Neira Ayuso reg = (u32)(be32_to_cpu(addrs->dst) & 0xff) << 24 |
322e4f7ef54SPablo Neira Ayuso (u32)(be32_to_cpu(addrs->dst) >> 16) << 8 |
323e4f7ef54SPablo Neira Ayuso (be32_to_cpu(addrs->src) & 0x0000ff00) >> 8;
324bc3fc44cSFlorian Fainelli if (mask)
325bc3fc44cSFlorian Fainelli offset = CORE_CFP_MASK_PORT(1);
326bc3fc44cSFlorian Fainelli else
327bc3fc44cSFlorian Fainelli offset = CORE_CFP_DATA_PORT(1);
328bc3fc44cSFlorian Fainelli core_writel(priv, reg, offset);
329bc3fc44cSFlorian Fainelli
330bc3fc44cSFlorian Fainelli /* UDF_n_A1 [31:24]
331bc3fc44cSFlorian Fainelli * UDF_n_A0 [23:8]
332bc3fc44cSFlorian Fainelli * Reserved [7:4]
333bc3fc44cSFlorian Fainelli * Slice ID [3:2]
334bc3fc44cSFlorian Fainelli * Slice valid [1:0]
335bc3fc44cSFlorian Fainelli */
336e4f7ef54SPablo Neira Ayuso reg = (u32)(be32_to_cpu(addrs->src) & 0xff) << 24 |
337e4f7ef54SPablo Neira Ayuso (u32)(be32_to_cpu(addrs->src) >> 16) << 8 |
338bc3fc44cSFlorian Fainelli SLICE_NUM(slice_num) | SLICE_VALID;
339bc3fc44cSFlorian Fainelli if (mask)
340bc3fc44cSFlorian Fainelli offset = CORE_CFP_MASK_PORT(0);
341bc3fc44cSFlorian Fainelli else
342bc3fc44cSFlorian Fainelli offset = CORE_CFP_DATA_PORT(0);
343bc3fc44cSFlorian Fainelli core_writel(priv, reg, offset);
344bc3fc44cSFlorian Fainelli }
345bc3fc44cSFlorian Fainelli
bcm_sf2_cfp_ipv4_rule_set(struct bcm_sf2_priv * priv,int port,unsigned int port_num,unsigned int queue_num,struct ethtool_rx_flow_spec * fs)34633061458SFlorian Fainelli static int bcm_sf2_cfp_ipv4_rule_set(struct bcm_sf2_priv *priv, int port,
34733061458SFlorian Fainelli unsigned int port_num,
34833061458SFlorian Fainelli unsigned int queue_num,
3497318166cSFlorian Fainelli struct ethtool_rx_flow_spec *fs)
3507318166cSFlorian Fainelli {
351f76b6ef1SAndrew Lunn __be16 vlan_tci = 0, vlan_m_tci = htons(0xffff);
352e4f7ef54SPablo Neira Ayuso struct ethtool_rx_flow_spec_input input = {};
3537318166cSFlorian Fainelli const struct cfp_udf_layout *layout;
3547318166cSFlorian Fainelli unsigned int slice_num, rule_index;
355e4f7ef54SPablo Neira Ayuso struct ethtool_rx_flow_rule *flow;
356e4f7ef54SPablo Neira Ayuso struct flow_match_ipv4_addrs ipv4;
357e4f7ef54SPablo Neira Ayuso struct flow_match_ports ports;
358e4f7ef54SPablo Neira Ayuso struct flow_match_ip ip;
3597318166cSFlorian Fainelli u8 ip_proto, ip_frag;
3607318166cSFlorian Fainelli u8 num_udf;
3617318166cSFlorian Fainelli u32 reg;
3627318166cSFlorian Fainelli int ret;
3637318166cSFlorian Fainelli
3647318166cSFlorian Fainelli switch (fs->flow_type & ~FLOW_EXT) {
3657318166cSFlorian Fainelli case TCP_V4_FLOW:
3667318166cSFlorian Fainelli ip_proto = IPPROTO_TCP;
3677318166cSFlorian Fainelli break;
3687318166cSFlorian Fainelli case UDP_V4_FLOW:
3697318166cSFlorian Fainelli ip_proto = IPPROTO_UDP;
3707318166cSFlorian Fainelli break;
3717318166cSFlorian Fainelli default:
3727318166cSFlorian Fainelli return -EINVAL;
3737318166cSFlorian Fainelli }
3747318166cSFlorian Fainelli
3757c3125f0SFlorian Fainelli ip_frag = !!(be32_to_cpu(fs->h_ext.data[0]) & 1);
37633061458SFlorian Fainelli
3777555020cSFlorian Fainelli /* Extract VLAN TCI */
3787555020cSFlorian Fainelli if (fs->flow_type & FLOW_EXT) {
3797555020cSFlorian Fainelli vlan_tci = fs->h_ext.vlan_tci;
3807555020cSFlorian Fainelli vlan_m_tci = fs->m_ext.vlan_tci;
3817555020cSFlorian Fainelli }
3827555020cSFlorian Fainelli
38333061458SFlorian Fainelli /* Locate the first rule available */
38433061458SFlorian Fainelli if (fs->location == RX_CLS_LOC_ANY)
38533061458SFlorian Fainelli rule_index = find_first_zero_bit(priv->cfp.used,
38643a5e00fSFlorian Fainelli priv->num_cfp_rules);
38733061458SFlorian Fainelli else
38833061458SFlorian Fainelli rule_index = fs->location;
38933061458SFlorian Fainelli
39043a5e00fSFlorian Fainelli if (rule_index > bcm_sf2_cfp_rule_size(priv))
39143a5e00fSFlorian Fainelli return -ENOSPC;
39243a5e00fSFlorian Fainelli
393e4f7ef54SPablo Neira Ayuso input.fs = fs;
394e4f7ef54SPablo Neira Ayuso flow = ethtool_rx_flow_rule_create(&input);
395e4f7ef54SPablo Neira Ayuso if (IS_ERR(flow))
396e4f7ef54SPablo Neira Ayuso return PTR_ERR(flow);
397e4f7ef54SPablo Neira Ayuso
398e4f7ef54SPablo Neira Ayuso flow_rule_match_ipv4_addrs(flow->rule, &ipv4);
399e4f7ef54SPablo Neira Ayuso flow_rule_match_ports(flow->rule, &ports);
400e4f7ef54SPablo Neira Ayuso flow_rule_match_ip(flow->rule, &ip);
401e4f7ef54SPablo Neira Ayuso
4027318166cSFlorian Fainelli layout = &udf_tcpip4_layout;
4035d80bcbbSFlorian Fainelli /* We only use one UDF slice for now */
4045d80bcbbSFlorian Fainelli slice_num = bcm_sf2_get_slice_number(layout, 0);
405e4f7ef54SPablo Neira Ayuso if (slice_num == UDF_NUM_SLICES) {
406e4f7ef54SPablo Neira Ayuso ret = -EINVAL;
407e4f7ef54SPablo Neira Ayuso goto out_err_flow_rule;
408e4f7ef54SPablo Neira Ayuso }
4095d80bcbbSFlorian Fainelli
4105d80bcbbSFlorian Fainelli num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices);
4117318166cSFlorian Fainelli
4127318166cSFlorian Fainelli /* Apply the UDF layout for this filter */
4135d80bcbbSFlorian Fainelli bcm_sf2_cfp_udf_set(priv, layout, slice_num);
4147318166cSFlorian Fainelli
4157318166cSFlorian Fainelli /* Apply to all packets received through this port */
4167318166cSFlorian Fainelli core_writel(priv, BIT(port), CORE_CFP_DATA_PORT(7));
4177318166cSFlorian Fainelli
41833061458SFlorian Fainelli /* Source port map match */
41933061458SFlorian Fainelli core_writel(priv, 0xff, CORE_CFP_MASK_PORT(7));
42033061458SFlorian Fainelli
4217318166cSFlorian Fainelli /* S-Tag status [31:30]
4227318166cSFlorian Fainelli * C-Tag status [29:28]
4237318166cSFlorian Fainelli * L2 framing [27:26]
4247318166cSFlorian Fainelli * L3 framing [25:24]
4257318166cSFlorian Fainelli * IP ToS [23:16]
4267318166cSFlorian Fainelli * IP proto [15:08]
4277318166cSFlorian Fainelli * IP Fragm [7]
4287318166cSFlorian Fainelli * Non 1st frag [6]
4297318166cSFlorian Fainelli * IP Authen [5]
4307318166cSFlorian Fainelli * TTL range [4:3]
4317318166cSFlorian Fainelli * PPPoE session [2]
4327318166cSFlorian Fainelli * Reserved [1]
4337318166cSFlorian Fainelli * UDF_Valid[8] [0]
4347318166cSFlorian Fainelli */
435e4f7ef54SPablo Neira Ayuso core_writel(priv, ip.key->tos << IPTOS_SHIFT |
4365d80bcbbSFlorian Fainelli ip_proto << IPPROTO_SHIFT | ip_frag << IP_FRAG_SHIFT |
4375d80bcbbSFlorian Fainelli udf_upper_bits(num_udf),
4387318166cSFlorian Fainelli CORE_CFP_DATA_PORT(6));
4397318166cSFlorian Fainelli
440bc3fc44cSFlorian Fainelli /* Mask with the specific layout for IPv4 packets */
441bc3fc44cSFlorian Fainelli core_writel(priv, layout->udfs[slice_num].mask_value |
442bc3fc44cSFlorian Fainelli udf_upper_bits(num_udf), CORE_CFP_MASK_PORT(6));
443bc3fc44cSFlorian Fainelli
444bc3fc44cSFlorian Fainelli /* Program the match and the mask */
4457555020cSFlorian Fainelli bcm_sf2_cfp_slice_ipv4(priv, ipv4.key, ports.key, vlan_tci,
4467555020cSFlorian Fainelli slice_num, num_udf, false);
4477555020cSFlorian Fainelli bcm_sf2_cfp_slice_ipv4(priv, ipv4.mask, ports.mask, vlan_m_tci,
4487555020cSFlorian Fainelli SLICE_NUM_MASK, num_udf, true);
4497318166cSFlorian Fainelli
4507318166cSFlorian Fainelli /* Insert into TCAM now */
4517318166cSFlorian Fainelli bcm_sf2_cfp_rule_addr_set(priv, rule_index);
4527318166cSFlorian Fainelli
4537318166cSFlorian Fainelli ret = bcm_sf2_cfp_op(priv, OP_SEL_WRITE | TCAM_SEL);
4547318166cSFlorian Fainelli if (ret) {
4557318166cSFlorian Fainelli pr_err("TCAM entry at addr %d failed\n", rule_index);
456e4f7ef54SPablo Neira Ayuso goto out_err_flow_rule;
4577318166cSFlorian Fainelli }
4587318166cSFlorian Fainelli
45933061458SFlorian Fainelli /* Insert into Action and policer RAMs now */
460db78ed27SFlorian Fainelli ret = bcm_sf2_cfp_act_pol_set(priv, rule_index, port, port_num,
461ba0696c2SFlorian Fainelli queue_num, true);
46233061458SFlorian Fainelli if (ret)
463e4f7ef54SPablo Neira Ayuso goto out_err_flow_rule;
4647318166cSFlorian Fainelli
4657318166cSFlorian Fainelli /* Turn on CFP for this rule now */
4667318166cSFlorian Fainelli reg = core_readl(priv, CORE_CFP_CTL_REG);
4677318166cSFlorian Fainelli reg |= BIT(port);
4687318166cSFlorian Fainelli core_writel(priv, reg, CORE_CFP_CTL_REG);
4697318166cSFlorian Fainelli
4707318166cSFlorian Fainelli /* Flag the rule as being used and return it */
4717318166cSFlorian Fainelli set_bit(rule_index, priv->cfp.used);
472ba0696c2SFlorian Fainelli set_bit(rule_index, priv->cfp.unique);
4737318166cSFlorian Fainelli fs->location = rule_index;
4747318166cSFlorian Fainelli
4757318166cSFlorian Fainelli return 0;
476e4f7ef54SPablo Neira Ayuso
477e4f7ef54SPablo Neira Ayuso out_err_flow_rule:
478e4f7ef54SPablo Neira Ayuso ethtool_rx_flow_rule_destroy(flow);
479e4f7ef54SPablo Neira Ayuso return ret;
4807318166cSFlorian Fainelli }
4817318166cSFlorian Fainelli
bcm_sf2_cfp_slice_ipv6(struct bcm_sf2_priv * priv,const __be32 * ip6_addr,const __be16 port,const __be16 vlan_tci,unsigned int slice_num,u32 udf_bits,bool mask)482ba0696c2SFlorian Fainelli static void bcm_sf2_cfp_slice_ipv6(struct bcm_sf2_priv *priv,
483ba0696c2SFlorian Fainelli const __be32 *ip6_addr, const __be16 port,
4847555020cSFlorian Fainelli const __be16 vlan_tci,
485c2d639d1SFlorian Fainelli unsigned int slice_num, u32 udf_bits,
486dd8eff68SFlorian Fainelli bool mask)
487ba0696c2SFlorian Fainelli {
488dd8eff68SFlorian Fainelli u32 reg, tmp, val, offset;
489ba0696c2SFlorian Fainelli
490c2d639d1SFlorian Fainelli /* UDF_Valid[7:0] [31:24]
491c2d639d1SFlorian Fainelli * S-Tag [23:8]
492c2d639d1SFlorian Fainelli * C-Tag [7:0]
493c2d639d1SFlorian Fainelli */
4947555020cSFlorian Fainelli reg = udf_bits << 24 | be16_to_cpu(vlan_tci) >> 8;
495c2d639d1SFlorian Fainelli if (mask)
4967555020cSFlorian Fainelli core_writel(priv, reg, CORE_CFP_MASK_PORT(5));
497c2d639d1SFlorian Fainelli else
4987555020cSFlorian Fainelli core_writel(priv, reg, CORE_CFP_DATA_PORT(5));
499c2d639d1SFlorian Fainelli
500ba0696c2SFlorian Fainelli /* C-Tag [31:24]
501ba0696c2SFlorian Fainelli * UDF_n_B8 [23:8] (port)
502ba0696c2SFlorian Fainelli * UDF_n_B7 (upper) [7:0] (addr[15:8])
503ba0696c2SFlorian Fainelli */
504ba0696c2SFlorian Fainelli reg = be32_to_cpu(ip6_addr[3]);
505ba0696c2SFlorian Fainelli val = (u32)be16_to_cpu(port) << 8 | ((reg >> 8) & 0xff);
5067555020cSFlorian Fainelli val |= (u32)(be16_to_cpu(vlan_tci) & 0xff) << 24;
507dd8eff68SFlorian Fainelli if (mask)
508dd8eff68SFlorian Fainelli offset = CORE_CFP_MASK_PORT(4);
509dd8eff68SFlorian Fainelli else
510dd8eff68SFlorian Fainelli offset = CORE_CFP_DATA_PORT(4);
511dd8eff68SFlorian Fainelli core_writel(priv, val, offset);
512ba0696c2SFlorian Fainelli
513ba0696c2SFlorian Fainelli /* UDF_n_B7 (lower) [31:24] (addr[7:0])
514ba0696c2SFlorian Fainelli * UDF_n_B6 [23:8] (addr[31:16])
515ba0696c2SFlorian Fainelli * UDF_n_B5 (upper) [7:0] (addr[47:40])
516ba0696c2SFlorian Fainelli */
517ba0696c2SFlorian Fainelli tmp = be32_to_cpu(ip6_addr[2]);
518ba0696c2SFlorian Fainelli val = (u32)(reg & 0xff) << 24 | (u32)(reg >> 16) << 8 |
519ba0696c2SFlorian Fainelli ((tmp >> 8) & 0xff);
520dd8eff68SFlorian Fainelli if (mask)
521dd8eff68SFlorian Fainelli offset = CORE_CFP_MASK_PORT(3);
522dd8eff68SFlorian Fainelli else
523dd8eff68SFlorian Fainelli offset = CORE_CFP_DATA_PORT(3);
524dd8eff68SFlorian Fainelli core_writel(priv, val, offset);
525ba0696c2SFlorian Fainelli
526ba0696c2SFlorian Fainelli /* UDF_n_B5 (lower) [31:24] (addr[39:32])
527ba0696c2SFlorian Fainelli * UDF_n_B4 [23:8] (addr[63:48])
528ba0696c2SFlorian Fainelli * UDF_n_B3 (upper) [7:0] (addr[79:72])
529ba0696c2SFlorian Fainelli */
530ba0696c2SFlorian Fainelli reg = be32_to_cpu(ip6_addr[1]);
531ba0696c2SFlorian Fainelli val = (u32)(tmp & 0xff) << 24 | (u32)(tmp >> 16) << 8 |
532ba0696c2SFlorian Fainelli ((reg >> 8) & 0xff);
533dd8eff68SFlorian Fainelli if (mask)
534dd8eff68SFlorian Fainelli offset = CORE_CFP_MASK_PORT(2);
535dd8eff68SFlorian Fainelli else
536dd8eff68SFlorian Fainelli offset = CORE_CFP_DATA_PORT(2);
537dd8eff68SFlorian Fainelli core_writel(priv, val, offset);
538ba0696c2SFlorian Fainelli
539ba0696c2SFlorian Fainelli /* UDF_n_B3 (lower) [31:24] (addr[71:64])
540ba0696c2SFlorian Fainelli * UDF_n_B2 [23:8] (addr[95:80])
541ba0696c2SFlorian Fainelli * UDF_n_B1 (upper) [7:0] (addr[111:104])
542ba0696c2SFlorian Fainelli */
543ba0696c2SFlorian Fainelli tmp = be32_to_cpu(ip6_addr[0]);
544ba0696c2SFlorian Fainelli val = (u32)(reg & 0xff) << 24 | (u32)(reg >> 16) << 8 |
545ba0696c2SFlorian Fainelli ((tmp >> 8) & 0xff);
546dd8eff68SFlorian Fainelli if (mask)
547dd8eff68SFlorian Fainelli offset = CORE_CFP_MASK_PORT(1);
548dd8eff68SFlorian Fainelli else
549dd8eff68SFlorian Fainelli offset = CORE_CFP_DATA_PORT(1);
550dd8eff68SFlorian Fainelli core_writel(priv, val, offset);
551ba0696c2SFlorian Fainelli
552ba0696c2SFlorian Fainelli /* UDF_n_B1 (lower) [31:24] (addr[103:96])
553ba0696c2SFlorian Fainelli * UDF_n_B0 [23:8] (addr[127:112])
554ba0696c2SFlorian Fainelli * Reserved [7:4]
555ba0696c2SFlorian Fainelli * Slice ID [3:2]
556ba0696c2SFlorian Fainelli * Slice valid [1:0]
557ba0696c2SFlorian Fainelli */
558ba0696c2SFlorian Fainelli reg = (u32)(tmp & 0xff) << 24 | (u32)(tmp >> 16) << 8 |
559ba0696c2SFlorian Fainelli SLICE_NUM(slice_num) | SLICE_VALID;
560dd8eff68SFlorian Fainelli if (mask)
561dd8eff68SFlorian Fainelli offset = CORE_CFP_MASK_PORT(0);
562dd8eff68SFlorian Fainelli else
563dd8eff68SFlorian Fainelli offset = CORE_CFP_DATA_PORT(0);
564dd8eff68SFlorian Fainelli core_writel(priv, reg, offset);
565ba0696c2SFlorian Fainelli }
566ba0696c2SFlorian Fainelli
bcm_sf2_cfp_rule_find(struct bcm_sf2_priv * priv,int port,u32 location)567ae7a5affSFlorian Fainelli static struct cfp_rule *bcm_sf2_cfp_rule_find(struct bcm_sf2_priv *priv,
568ae7a5affSFlorian Fainelli int port, u32 location)
569ae7a5affSFlorian Fainelli {
5706da69b1dSXiaomeng Tong struct cfp_rule *rule;
571ae7a5affSFlorian Fainelli
572ae7a5affSFlorian Fainelli list_for_each_entry(rule, &priv->cfp.rules_list, next) {
573ae7a5affSFlorian Fainelli if (rule->port == port && rule->fs.location == location)
5746da69b1dSXiaomeng Tong return rule;
575f9086200Skbuild test robot }
576ae7a5affSFlorian Fainelli
5776da69b1dSXiaomeng Tong return NULL;
578ae7a5affSFlorian Fainelli }
579ae7a5affSFlorian Fainelli
bcm_sf2_cfp_rule_cmp(struct bcm_sf2_priv * priv,int port,struct ethtool_rx_flow_spec * fs)580ae7a5affSFlorian Fainelli static int bcm_sf2_cfp_rule_cmp(struct bcm_sf2_priv *priv, int port,
581ae7a5affSFlorian Fainelli struct ethtool_rx_flow_spec *fs)
582ae7a5affSFlorian Fainelli {
583ae7a5affSFlorian Fainelli struct cfp_rule *rule = NULL;
584ae7a5affSFlorian Fainelli size_t fs_size = 0;
585ae7a5affSFlorian Fainelli int ret = 1;
586ae7a5affSFlorian Fainelli
587ae7a5affSFlorian Fainelli if (list_empty(&priv->cfp.rules_list))
588ae7a5affSFlorian Fainelli return ret;
589ae7a5affSFlorian Fainelli
590ae7a5affSFlorian Fainelli list_for_each_entry(rule, &priv->cfp.rules_list, next) {
591ae7a5affSFlorian Fainelli ret = 1;
592ae7a5affSFlorian Fainelli if (rule->port != port)
593ae7a5affSFlorian Fainelli continue;
594ae7a5affSFlorian Fainelli
595ae7a5affSFlorian Fainelli if (rule->fs.flow_type != fs->flow_type ||
596ae7a5affSFlorian Fainelli rule->fs.ring_cookie != fs->ring_cookie ||
5977c3125f0SFlorian Fainelli rule->fs.h_ext.data[0] != fs->h_ext.data[0])
598ae7a5affSFlorian Fainelli continue;
599ae7a5affSFlorian Fainelli
600ae7a5affSFlorian Fainelli switch (fs->flow_type & ~FLOW_EXT) {
601ae7a5affSFlorian Fainelli case TCP_V6_FLOW:
602ae7a5affSFlorian Fainelli case UDP_V6_FLOW:
603ae7a5affSFlorian Fainelli fs_size = sizeof(struct ethtool_tcpip6_spec);
604ae7a5affSFlorian Fainelli break;
605ae7a5affSFlorian Fainelli case TCP_V4_FLOW:
606ae7a5affSFlorian Fainelli case UDP_V4_FLOW:
607ae7a5affSFlorian Fainelli fs_size = sizeof(struct ethtool_tcpip4_spec);
608ae7a5affSFlorian Fainelli break;
609ae7a5affSFlorian Fainelli default:
610ae7a5affSFlorian Fainelli continue;
611ae7a5affSFlorian Fainelli }
612ae7a5affSFlorian Fainelli
613ae7a5affSFlorian Fainelli ret = memcmp(&rule->fs.h_u, &fs->h_u, fs_size);
614ae7a5affSFlorian Fainelli ret |= memcmp(&rule->fs.m_u, &fs->m_u, fs_size);
6157555020cSFlorian Fainelli /* Compare VLAN TCI values as well */
6167555020cSFlorian Fainelli if (rule->fs.flow_type & FLOW_EXT) {
6177555020cSFlorian Fainelli ret |= rule->fs.h_ext.vlan_tci != fs->h_ext.vlan_tci;
6187555020cSFlorian Fainelli ret |= rule->fs.m_ext.vlan_tci != fs->m_ext.vlan_tci;
6197555020cSFlorian Fainelli }
620ae7a5affSFlorian Fainelli if (ret == 0)
621ae7a5affSFlorian Fainelli break;
622ae7a5affSFlorian Fainelli }
623ae7a5affSFlorian Fainelli
624ae7a5affSFlorian Fainelli return ret;
625ae7a5affSFlorian Fainelli }
626ae7a5affSFlorian Fainelli
bcm_sf2_cfp_ipv6_rule_set(struct bcm_sf2_priv * priv,int port,unsigned int port_num,unsigned int queue_num,struct ethtool_rx_flow_spec * fs)627ba0696c2SFlorian Fainelli static int bcm_sf2_cfp_ipv6_rule_set(struct bcm_sf2_priv *priv, int port,
628ba0696c2SFlorian Fainelli unsigned int port_num,
629ba0696c2SFlorian Fainelli unsigned int queue_num,
630ba0696c2SFlorian Fainelli struct ethtool_rx_flow_spec *fs)
631ba0696c2SFlorian Fainelli {
632f76b6ef1SAndrew Lunn __be16 vlan_tci = 0, vlan_m_tci = htons(0xffff);
633e4f7ef54SPablo Neira Ayuso struct ethtool_rx_flow_spec_input input = {};
634ba0696c2SFlorian Fainelli unsigned int slice_num, rule_index[2];
635ba0696c2SFlorian Fainelli const struct cfp_udf_layout *layout;
636e4f7ef54SPablo Neira Ayuso struct ethtool_rx_flow_rule *flow;
637e4f7ef54SPablo Neira Ayuso struct flow_match_ipv6_addrs ipv6;
638e4f7ef54SPablo Neira Ayuso struct flow_match_ports ports;
639ba0696c2SFlorian Fainelli u8 ip_proto, ip_frag;
640ba0696c2SFlorian Fainelli int ret = 0;
641ba0696c2SFlorian Fainelli u8 num_udf;
642ba0696c2SFlorian Fainelli u32 reg;
643ba0696c2SFlorian Fainelli
644ba0696c2SFlorian Fainelli switch (fs->flow_type & ~FLOW_EXT) {
645ba0696c2SFlorian Fainelli case TCP_V6_FLOW:
646ba0696c2SFlorian Fainelli ip_proto = IPPROTO_TCP;
647ba0696c2SFlorian Fainelli break;
648ba0696c2SFlorian Fainelli case UDP_V6_FLOW:
649ba0696c2SFlorian Fainelli ip_proto = IPPROTO_UDP;
650ba0696c2SFlorian Fainelli break;
651ba0696c2SFlorian Fainelli default:
652ba0696c2SFlorian Fainelli return -EINVAL;
653ba0696c2SFlorian Fainelli }
654ba0696c2SFlorian Fainelli
6557c3125f0SFlorian Fainelli ip_frag = !!(be32_to_cpu(fs->h_ext.data[0]) & 1);
656ba0696c2SFlorian Fainelli
6577555020cSFlorian Fainelli /* Extract VLAN TCI */
6587555020cSFlorian Fainelli if (fs->flow_type & FLOW_EXT) {
6597555020cSFlorian Fainelli vlan_tci = fs->h_ext.vlan_tci;
6607555020cSFlorian Fainelli vlan_m_tci = fs->m_ext.vlan_tci;
6617555020cSFlorian Fainelli }
6627555020cSFlorian Fainelli
663ba0696c2SFlorian Fainelli layout = &udf_tcpip6_layout;
664ba0696c2SFlorian Fainelli slice_num = bcm_sf2_get_slice_number(layout, 0);
665ba0696c2SFlorian Fainelli if (slice_num == UDF_NUM_SLICES)
666ba0696c2SFlorian Fainelli return -EINVAL;
667ba0696c2SFlorian Fainelli
668ba0696c2SFlorian Fainelli num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices);
669ba0696c2SFlorian Fainelli
670ba0696c2SFlorian Fainelli /* Negotiate two indexes, one for the second half which we are chained
671ba0696c2SFlorian Fainelli * from, which is what we will return to user-space, and a second one
672ba0696c2SFlorian Fainelli * which is used to store its first half. That first half does not
673ba0696c2SFlorian Fainelli * allow any choice of placement, so it just needs to find the next
674ba0696c2SFlorian Fainelli * available bit. We return the second half as fs->location because
675ba0696c2SFlorian Fainelli * that helps with the rule lookup later on since the second half is
676ba0696c2SFlorian Fainelli * chained from its first half, we can easily identify IPv6 CFP rules
677ba0696c2SFlorian Fainelli * by looking whether they carry a CHAIN_ID.
678ba0696c2SFlorian Fainelli *
679ba0696c2SFlorian Fainelli * We also want the second half to have a lower rule_index than its
680ba0696c2SFlorian Fainelli * first half because the HW search is by incrementing addresses.
681ba0696c2SFlorian Fainelli */
682ba0696c2SFlorian Fainelli if (fs->location == RX_CLS_LOC_ANY)
6836c05561cSFlorian Fainelli rule_index[1] = find_first_zero_bit(priv->cfp.used,
6846c05561cSFlorian Fainelli priv->num_cfp_rules);
685ba0696c2SFlorian Fainelli else
6866c05561cSFlorian Fainelli rule_index[1] = fs->location;
6876c05561cSFlorian Fainelli if (rule_index[1] > bcm_sf2_cfp_rule_size(priv))
6886c05561cSFlorian Fainelli return -ENOSPC;
689ba0696c2SFlorian Fainelli
690ba0696c2SFlorian Fainelli /* Flag it as used (cleared on error path) such that we can immediately
691ba0696c2SFlorian Fainelli * obtain a second one to chain from.
692ba0696c2SFlorian Fainelli */
6936c05561cSFlorian Fainelli set_bit(rule_index[1], priv->cfp.used);
694ba0696c2SFlorian Fainelli
6956c05561cSFlorian Fainelli rule_index[0] = find_first_zero_bit(priv->cfp.used,
6966c05561cSFlorian Fainelli priv->num_cfp_rules);
6976c05561cSFlorian Fainelli if (rule_index[0] > bcm_sf2_cfp_rule_size(priv)) {
698ba0696c2SFlorian Fainelli ret = -ENOSPC;
699ba0696c2SFlorian Fainelli goto out_err;
700ba0696c2SFlorian Fainelli }
701ba0696c2SFlorian Fainelli
702e4f7ef54SPablo Neira Ayuso input.fs = fs;
703e4f7ef54SPablo Neira Ayuso flow = ethtool_rx_flow_rule_create(&input);
704e4f7ef54SPablo Neira Ayuso if (IS_ERR(flow)) {
705e4f7ef54SPablo Neira Ayuso ret = PTR_ERR(flow);
706e4f7ef54SPablo Neira Ayuso goto out_err;
707e4f7ef54SPablo Neira Ayuso }
708e4f7ef54SPablo Neira Ayuso flow_rule_match_ipv6_addrs(flow->rule, &ipv6);
709e4f7ef54SPablo Neira Ayuso flow_rule_match_ports(flow->rule, &ports);
710e4f7ef54SPablo Neira Ayuso
711ba0696c2SFlorian Fainelli /* Apply the UDF layout for this filter */
712ba0696c2SFlorian Fainelli bcm_sf2_cfp_udf_set(priv, layout, slice_num);
713ba0696c2SFlorian Fainelli
714ba0696c2SFlorian Fainelli /* Apply to all packets received through this port */
715ba0696c2SFlorian Fainelli core_writel(priv, BIT(port), CORE_CFP_DATA_PORT(7));
716ba0696c2SFlorian Fainelli
717ba0696c2SFlorian Fainelli /* Source port map match */
718ba0696c2SFlorian Fainelli core_writel(priv, 0xff, CORE_CFP_MASK_PORT(7));
719ba0696c2SFlorian Fainelli
720ba0696c2SFlorian Fainelli /* S-Tag status [31:30]
721ba0696c2SFlorian Fainelli * C-Tag status [29:28]
722ba0696c2SFlorian Fainelli * L2 framing [27:26]
723ba0696c2SFlorian Fainelli * L3 framing [25:24]
724ba0696c2SFlorian Fainelli * IP ToS [23:16]
725ba0696c2SFlorian Fainelli * IP proto [15:08]
726ba0696c2SFlorian Fainelli * IP Fragm [7]
727ba0696c2SFlorian Fainelli * Non 1st frag [6]
728ba0696c2SFlorian Fainelli * IP Authen [5]
729ba0696c2SFlorian Fainelli * TTL range [4:3]
730ba0696c2SFlorian Fainelli * PPPoE session [2]
731ba0696c2SFlorian Fainelli * Reserved [1]
732ba0696c2SFlorian Fainelli * UDF_Valid[8] [0]
733ba0696c2SFlorian Fainelli */
734ba0696c2SFlorian Fainelli reg = 1 << L3_FRAMING_SHIFT | ip_proto << IPPROTO_SHIFT |
735ba0696c2SFlorian Fainelli ip_frag << IP_FRAG_SHIFT | udf_upper_bits(num_udf);
736ba0696c2SFlorian Fainelli core_writel(priv, reg, CORE_CFP_DATA_PORT(6));
737ba0696c2SFlorian Fainelli
738ba0696c2SFlorian Fainelli /* Mask with the specific layout for IPv6 packets including
739ba0696c2SFlorian Fainelli * UDF_Valid[8]
740ba0696c2SFlorian Fainelli */
741ba0696c2SFlorian Fainelli reg = layout->udfs[slice_num].mask_value | udf_upper_bits(num_udf);
742ba0696c2SFlorian Fainelli core_writel(priv, reg, CORE_CFP_MASK_PORT(6));
743ba0696c2SFlorian Fainelli
744ba0696c2SFlorian Fainelli /* Slice the IPv6 source address and port */
745e4f7ef54SPablo Neira Ayuso bcm_sf2_cfp_slice_ipv6(priv, ipv6.key->src.in6_u.u6_addr32,
7467555020cSFlorian Fainelli ports.key->src, vlan_tci, slice_num,
747c2d639d1SFlorian Fainelli udf_lower_bits(num_udf), false);
748e4f7ef54SPablo Neira Ayuso bcm_sf2_cfp_slice_ipv6(priv, ipv6.mask->src.in6_u.u6_addr32,
7497555020cSFlorian Fainelli ports.mask->src, vlan_m_tci, SLICE_NUM_MASK,
750c2d639d1SFlorian Fainelli udf_lower_bits(num_udf), true);
751ba0696c2SFlorian Fainelli
752ba0696c2SFlorian Fainelli /* Insert into TCAM now because we need to insert a second rule */
753ba0696c2SFlorian Fainelli bcm_sf2_cfp_rule_addr_set(priv, rule_index[0]);
754ba0696c2SFlorian Fainelli
755ba0696c2SFlorian Fainelli ret = bcm_sf2_cfp_op(priv, OP_SEL_WRITE | TCAM_SEL);
756ba0696c2SFlorian Fainelli if (ret) {
757ba0696c2SFlorian Fainelli pr_err("TCAM entry at addr %d failed\n", rule_index[0]);
758e4f7ef54SPablo Neira Ayuso goto out_err_flow_rule;
759ba0696c2SFlorian Fainelli }
760ba0696c2SFlorian Fainelli
761ba0696c2SFlorian Fainelli /* Insert into Action and policer RAMs now */
762db78ed27SFlorian Fainelli ret = bcm_sf2_cfp_act_pol_set(priv, rule_index[0], port, port_num,
763ba0696c2SFlorian Fainelli queue_num, false);
764ba0696c2SFlorian Fainelli if (ret)
765e4f7ef54SPablo Neira Ayuso goto out_err_flow_rule;
766ba0696c2SFlorian Fainelli
767ba0696c2SFlorian Fainelli /* Now deal with the second slice to chain this rule */
768ba0696c2SFlorian Fainelli slice_num = bcm_sf2_get_slice_number(layout, slice_num + 1);
769ba0696c2SFlorian Fainelli if (slice_num == UDF_NUM_SLICES) {
770ba0696c2SFlorian Fainelli ret = -EINVAL;
771e4f7ef54SPablo Neira Ayuso goto out_err_flow_rule;
772ba0696c2SFlorian Fainelli }
773ba0696c2SFlorian Fainelli
774ba0696c2SFlorian Fainelli num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices);
775ba0696c2SFlorian Fainelli
776ba0696c2SFlorian Fainelli /* Apply the UDF layout for this filter */
777ba0696c2SFlorian Fainelli bcm_sf2_cfp_udf_set(priv, layout, slice_num);
778ba0696c2SFlorian Fainelli
779ba0696c2SFlorian Fainelli /* Chained rule, source port match is coming from the rule we are
780ba0696c2SFlorian Fainelli * chained from.
781ba0696c2SFlorian Fainelli */
782ba0696c2SFlorian Fainelli core_writel(priv, 0, CORE_CFP_DATA_PORT(7));
783ba0696c2SFlorian Fainelli core_writel(priv, 0, CORE_CFP_MASK_PORT(7));
784ba0696c2SFlorian Fainelli
785ba0696c2SFlorian Fainelli /*
786ba0696c2SFlorian Fainelli * CHAIN ID [31:24] chain to previous slice
787ba0696c2SFlorian Fainelli * Reserved [23:20]
788ba0696c2SFlorian Fainelli * UDF_Valid[11:8] [19:16]
789ba0696c2SFlorian Fainelli * UDF_Valid[7:0] [15:8]
790ba0696c2SFlorian Fainelli * UDF_n_D11 [7:0]
791ba0696c2SFlorian Fainelli */
792ba0696c2SFlorian Fainelli reg = rule_index[0] << 24 | udf_upper_bits(num_udf) << 16 |
793ba0696c2SFlorian Fainelli udf_lower_bits(num_udf) << 8;
794ba0696c2SFlorian Fainelli core_writel(priv, reg, CORE_CFP_DATA_PORT(6));
795ba0696c2SFlorian Fainelli
796ba0696c2SFlorian Fainelli /* Mask all except chain ID, UDF Valid[8] and UDF Valid[7:0] */
797ba0696c2SFlorian Fainelli reg = XCESS_ADDR_MASK << 24 | udf_upper_bits(num_udf) << 16 |
798ba0696c2SFlorian Fainelli udf_lower_bits(num_udf) << 8;
799ba0696c2SFlorian Fainelli core_writel(priv, reg, CORE_CFP_MASK_PORT(6));
800ba0696c2SFlorian Fainelli
801e4f7ef54SPablo Neira Ayuso bcm_sf2_cfp_slice_ipv6(priv, ipv6.key->dst.in6_u.u6_addr32,
8027555020cSFlorian Fainelli ports.key->dst, 0, slice_num,
803c2d639d1SFlorian Fainelli 0, false);
804e4f7ef54SPablo Neira Ayuso bcm_sf2_cfp_slice_ipv6(priv, ipv6.mask->dst.in6_u.u6_addr32,
8057555020cSFlorian Fainelli ports.key->dst, 0, SLICE_NUM_MASK,
806c2d639d1SFlorian Fainelli 0, true);
807ba0696c2SFlorian Fainelli
808ba0696c2SFlorian Fainelli /* Insert into TCAM now */
809ba0696c2SFlorian Fainelli bcm_sf2_cfp_rule_addr_set(priv, rule_index[1]);
810ba0696c2SFlorian Fainelli
811ba0696c2SFlorian Fainelli ret = bcm_sf2_cfp_op(priv, OP_SEL_WRITE | TCAM_SEL);
812ba0696c2SFlorian Fainelli if (ret) {
813ba0696c2SFlorian Fainelli pr_err("TCAM entry at addr %d failed\n", rule_index[1]);
814e4f7ef54SPablo Neira Ayuso goto out_err_flow_rule;
815ba0696c2SFlorian Fainelli }
816ba0696c2SFlorian Fainelli
817ba0696c2SFlorian Fainelli /* Insert into Action and policer RAMs now, set chain ID to
818ba0696c2SFlorian Fainelli * the one we are chained to
819ba0696c2SFlorian Fainelli */
820db78ed27SFlorian Fainelli ret = bcm_sf2_cfp_act_pol_set(priv, rule_index[1], port, port_num,
821ba0696c2SFlorian Fainelli queue_num, true);
822ba0696c2SFlorian Fainelli if (ret)
823e4f7ef54SPablo Neira Ayuso goto out_err_flow_rule;
824ba0696c2SFlorian Fainelli
825ba0696c2SFlorian Fainelli /* Turn on CFP for this rule now */
826ba0696c2SFlorian Fainelli reg = core_readl(priv, CORE_CFP_CTL_REG);
827ba0696c2SFlorian Fainelli reg |= BIT(port);
828ba0696c2SFlorian Fainelli core_writel(priv, reg, CORE_CFP_CTL_REG);
829ba0696c2SFlorian Fainelli
830ba0696c2SFlorian Fainelli /* Flag the second half rule as being used now, return it as the
831ba0696c2SFlorian Fainelli * location, and flag it as unique while dumping rules
832ba0696c2SFlorian Fainelli */
8336c05561cSFlorian Fainelli set_bit(rule_index[0], priv->cfp.used);
834ba0696c2SFlorian Fainelli set_bit(rule_index[1], priv->cfp.unique);
835ba0696c2SFlorian Fainelli fs->location = rule_index[1];
836ba0696c2SFlorian Fainelli
837ba0696c2SFlorian Fainelli return ret;
838ba0696c2SFlorian Fainelli
839e4f7ef54SPablo Neira Ayuso out_err_flow_rule:
840e4f7ef54SPablo Neira Ayuso ethtool_rx_flow_rule_destroy(flow);
841ba0696c2SFlorian Fainelli out_err:
8426c05561cSFlorian Fainelli clear_bit(rule_index[1], priv->cfp.used);
843ba0696c2SFlorian Fainelli return ret;
844ba0696c2SFlorian Fainelli }
845ba0696c2SFlorian Fainelli
bcm_sf2_cfp_rule_insert(struct dsa_switch * ds,int port,struct ethtool_rx_flow_spec * fs)846ce24b08aSFlorian Fainelli static int bcm_sf2_cfp_rule_insert(struct dsa_switch *ds, int port,
84733061458SFlorian Fainelli struct ethtool_rx_flow_spec *fs)
84833061458SFlorian Fainelli {
84933061458SFlorian Fainelli struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
85068bb8ea8SVivien Didelot s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
8518a75f4f2SFlorian Fainelli __u64 ring_cookie = fs->ring_cookie;
8528b3abe30SFlorian Fainelli struct switchdev_obj_port_vlan vlan;
85333061458SFlorian Fainelli unsigned int queue_num, port_num;
8548b3abe30SFlorian Fainelli u16 vid;
855ce24b08aSFlorian Fainelli int ret;
856ae7a5affSFlorian Fainelli
8578a75f4f2SFlorian Fainelli /* This rule is a Wake-on-LAN filter and we must specifically
8588a75f4f2SFlorian Fainelli * target the CPU port in order for it to be working.
8598a75f4f2SFlorian Fainelli */
8608a75f4f2SFlorian Fainelli if (ring_cookie == RX_CLS_FLOW_WAKE)
8618a75f4f2SFlorian Fainelli ring_cookie = cpu_port * SF2_NUM_EGRESS_QUEUES;
8628a75f4f2SFlorian Fainelli
86333061458SFlorian Fainelli /* We do not support discarding packets, check that the
86433061458SFlorian Fainelli * destination port is enabled and that we are within the
86533061458SFlorian Fainelli * number of ports supported by the switch
86633061458SFlorian Fainelli */
8678a75f4f2SFlorian Fainelli port_num = ring_cookie / SF2_NUM_EGRESS_QUEUES;
86833061458SFlorian Fainelli
8698a75f4f2SFlorian Fainelli if (ring_cookie == RX_CLS_FLOW_DISC ||
8702104bc0aSFlorian Fainelli !(dsa_is_user_port(ds, port_num) ||
8712104bc0aSFlorian Fainelli dsa_is_cpu_port(ds, port_num)) ||
87233061458SFlorian Fainelli port_num >= priv->hw_params.num_ports)
87333061458SFlorian Fainelli return -EINVAL;
8748b3abe30SFlorian Fainelli
8758b3abe30SFlorian Fainelli /* If the rule is matching a particular VLAN, make sure that we honor
8768b3abe30SFlorian Fainelli * the matching and have it tagged or untagged on the destination port,
8778b3abe30SFlorian Fainelli * we do this on egress with a VLAN entry. The egress tagging attribute
8788b3abe30SFlorian Fainelli * is expected to be provided in h_ext.data[1] bit 0. A 1 means untagged,
8798b3abe30SFlorian Fainelli * a 0 means tagged.
8808b3abe30SFlorian Fainelli */
8818b3abe30SFlorian Fainelli if (fs->flow_type & FLOW_EXT) {
8828b3abe30SFlorian Fainelli /* We cannot support matching multiple VLAN IDs yet */
8838b3abe30SFlorian Fainelli if ((be16_to_cpu(fs->m_ext.vlan_tci) & VLAN_VID_MASK) !=
8848b3abe30SFlorian Fainelli VLAN_VID_MASK)
8858b3abe30SFlorian Fainelli return -EINVAL;
8868b3abe30SFlorian Fainelli
8878b3abe30SFlorian Fainelli vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
888b7a9e0daSVladimir Oltean vlan.vid = vid;
889b53014f0SVladimir Oltean if (be32_to_cpu(fs->h_ext.data[1]) & 1)
8908b3abe30SFlorian Fainelli vlan.flags = BRIDGE_VLAN_INFO_UNTAGGED;
8918b3abe30SFlorian Fainelli else
8928b3abe30SFlorian Fainelli vlan.flags = 0;
8938b3abe30SFlorian Fainelli
89431046a5fSVladimir Oltean ret = ds->ops->port_vlan_add(ds, port_num, &vlan, NULL);
8958b3abe30SFlorian Fainelli if (ret)
8968b3abe30SFlorian Fainelli return ret;
8978b3abe30SFlorian Fainelli }
8988b3abe30SFlorian Fainelli
89933061458SFlorian Fainelli /*
90033061458SFlorian Fainelli * We have a small oddity where Port 6 just does not have a
90133061458SFlorian Fainelli * valid bit here (so we substract by one).
90233061458SFlorian Fainelli */
9038a75f4f2SFlorian Fainelli queue_num = ring_cookie % SF2_NUM_EGRESS_QUEUES;
90433061458SFlorian Fainelli if (port_num >= 7)
90533061458SFlorian Fainelli port_num -= 1;
90633061458SFlorian Fainelli
907ba0696c2SFlorian Fainelli switch (fs->flow_type & ~FLOW_EXT) {
908ba0696c2SFlorian Fainelli case TCP_V4_FLOW:
909ba0696c2SFlorian Fainelli case UDP_V4_FLOW:
910ba0696c2SFlorian Fainelli ret = bcm_sf2_cfp_ipv4_rule_set(priv, port, port_num,
911ba0696c2SFlorian Fainelli queue_num, fs);
912ba0696c2SFlorian Fainelli break;
913ba0696c2SFlorian Fainelli case TCP_V6_FLOW:
914ba0696c2SFlorian Fainelli case UDP_V6_FLOW:
915ba0696c2SFlorian Fainelli ret = bcm_sf2_cfp_ipv6_rule_set(priv, port, port_num,
916ba0696c2SFlorian Fainelli queue_num, fs);
917ba0696c2SFlorian Fainelli break;
918ba0696c2SFlorian Fainelli default:
919ae7a5affSFlorian Fainelli ret = -EINVAL;
920ba0696c2SFlorian Fainelli break;
92133061458SFlorian Fainelli }
92233061458SFlorian Fainelli
923ce24b08aSFlorian Fainelli return ret;
924ce24b08aSFlorian Fainelli }
925ce24b08aSFlorian Fainelli
bcm_sf2_cfp_rule_set(struct dsa_switch * ds,int port,struct ethtool_rx_flow_spec * fs)926ce24b08aSFlorian Fainelli static int bcm_sf2_cfp_rule_set(struct dsa_switch *ds, int port,
927ce24b08aSFlorian Fainelli struct ethtool_rx_flow_spec *fs)
928ce24b08aSFlorian Fainelli {
929ce24b08aSFlorian Fainelli struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
930ce24b08aSFlorian Fainelli struct cfp_rule *rule = NULL;
931ce24b08aSFlorian Fainelli int ret = -EINVAL;
932ce24b08aSFlorian Fainelli
933ce24b08aSFlorian Fainelli /* Check for unsupported extensions */
9348b3abe30SFlorian Fainelli if (fs->flow_type & FLOW_MAC_EXT)
935ce24b08aSFlorian Fainelli return -EINVAL;
936ce24b08aSFlorian Fainelli
937d0802dc4SFlorian Fainelli if (fs->location != RX_CLS_LOC_ANY &&
938d0802dc4SFlorian Fainelli fs->location > bcm_sf2_cfp_rule_size(priv))
939f949a12fSDan Carpenter return -EINVAL;
940f949a12fSDan Carpenter
9418b3abe30SFlorian Fainelli if ((fs->flow_type & FLOW_EXT) &&
9421958d581SVladimir Oltean !(ds->ops->port_vlan_add || ds->ops->port_vlan_del))
9438b3abe30SFlorian Fainelli return -EOPNOTSUPP;
9448b3abe30SFlorian Fainelli
945ce24b08aSFlorian Fainelli if (fs->location != RX_CLS_LOC_ANY &&
946ce24b08aSFlorian Fainelli test_bit(fs->location, priv->cfp.used))
947ce24b08aSFlorian Fainelli return -EBUSY;
948ce24b08aSFlorian Fainelli
949ce24b08aSFlorian Fainelli ret = bcm_sf2_cfp_rule_cmp(priv, port, fs);
950ce24b08aSFlorian Fainelli if (ret == 0)
951ce24b08aSFlorian Fainelli return -EEXIST;
952ce24b08aSFlorian Fainelli
953ce24b08aSFlorian Fainelli rule = kzalloc(sizeof(*rule), GFP_KERNEL);
954ce24b08aSFlorian Fainelli if (!rule)
955ce24b08aSFlorian Fainelli return -ENOMEM;
956ce24b08aSFlorian Fainelli
957ce24b08aSFlorian Fainelli ret = bcm_sf2_cfp_rule_insert(ds, port, fs);
958ae7a5affSFlorian Fainelli if (ret) {
959ae7a5affSFlorian Fainelli kfree(rule);
960ae7a5affSFlorian Fainelli return ret;
961ae7a5affSFlorian Fainelli }
962ae7a5affSFlorian Fainelli
963ae7a5affSFlorian Fainelli rule->port = port;
964ae7a5affSFlorian Fainelli memcpy(&rule->fs, fs, sizeof(*fs));
965ae7a5affSFlorian Fainelli list_add_tail(&rule->next, &priv->cfp.rules_list);
966ae7a5affSFlorian Fainelli
967ba0696c2SFlorian Fainelli return ret;
968ba0696c2SFlorian Fainelli }
969ba0696c2SFlorian Fainelli
bcm_sf2_cfp_rule_del_one(struct bcm_sf2_priv * priv,int port,u32 loc,u32 * next_loc)970ba0696c2SFlorian Fainelli static int bcm_sf2_cfp_rule_del_one(struct bcm_sf2_priv *priv, int port,
971ba0696c2SFlorian Fainelli u32 loc, u32 *next_loc)
9727318166cSFlorian Fainelli {
9737318166cSFlorian Fainelli int ret;
9747318166cSFlorian Fainelli u32 reg;
9757318166cSFlorian Fainelli
9767318166cSFlorian Fainelli /* Indicate which rule we want to read */
9777318166cSFlorian Fainelli bcm_sf2_cfp_rule_addr_set(priv, loc);
9787318166cSFlorian Fainelli
9797318166cSFlorian Fainelli ret = bcm_sf2_cfp_op(priv, OP_SEL_READ | TCAM_SEL);
9807318166cSFlorian Fainelli if (ret)
9817318166cSFlorian Fainelli return ret;
9827318166cSFlorian Fainelli
983ba0696c2SFlorian Fainelli /* Check if this is possibly an IPv6 rule that would
984ba0696c2SFlorian Fainelli * indicate we need to delete its companion rule
985ba0696c2SFlorian Fainelli * as well
986ba0696c2SFlorian Fainelli */
987ba0696c2SFlorian Fainelli reg = core_readl(priv, CORE_CFP_DATA_PORT(6));
988ba0696c2SFlorian Fainelli if (next_loc)
989ba0696c2SFlorian Fainelli *next_loc = (reg >> 24) & CHAIN_ID_MASK;
990ba0696c2SFlorian Fainelli
9917318166cSFlorian Fainelli /* Clear its valid bits */
9927318166cSFlorian Fainelli reg = core_readl(priv, CORE_CFP_DATA_PORT(0));
9937318166cSFlorian Fainelli reg &= ~SLICE_VALID;
9947318166cSFlorian Fainelli core_writel(priv, reg, CORE_CFP_DATA_PORT(0));
9957318166cSFlorian Fainelli
9967318166cSFlorian Fainelli /* Write back this entry into the TCAM now */
9977318166cSFlorian Fainelli ret = bcm_sf2_cfp_op(priv, OP_SEL_WRITE | TCAM_SEL);
9987318166cSFlorian Fainelli if (ret)
9997318166cSFlorian Fainelli return ret;
10007318166cSFlorian Fainelli
10017318166cSFlorian Fainelli clear_bit(loc, priv->cfp.used);
1002ba0696c2SFlorian Fainelli clear_bit(loc, priv->cfp.unique);
10037318166cSFlorian Fainelli
10047318166cSFlorian Fainelli return 0;
10057318166cSFlorian Fainelli }
10067318166cSFlorian Fainelli
bcm_sf2_cfp_rule_remove(struct bcm_sf2_priv * priv,int port,u32 loc)1007ce24b08aSFlorian Fainelli static int bcm_sf2_cfp_rule_remove(struct bcm_sf2_priv *priv, int port,
1008ba0696c2SFlorian Fainelli u32 loc)
1009ba0696c2SFlorian Fainelli {
1010ba0696c2SFlorian Fainelli u32 next_loc = 0;
1011ba0696c2SFlorian Fainelli int ret;
1012ba0696c2SFlorian Fainelli
1013ce24b08aSFlorian Fainelli ret = bcm_sf2_cfp_rule_del_one(priv, port, loc, &next_loc);
1014ce24b08aSFlorian Fainelli if (ret)
1015ce24b08aSFlorian Fainelli return ret;
1016ce24b08aSFlorian Fainelli
1017ce24b08aSFlorian Fainelli /* If this was an IPv6 rule, delete is companion rule too */
1018ce24b08aSFlorian Fainelli if (next_loc)
1019ce24b08aSFlorian Fainelli ret = bcm_sf2_cfp_rule_del_one(priv, port, next_loc, NULL);
1020ce24b08aSFlorian Fainelli
1021ce24b08aSFlorian Fainelli return ret;
1022ce24b08aSFlorian Fainelli }
1023ce24b08aSFlorian Fainelli
bcm_sf2_cfp_rule_del(struct bcm_sf2_priv * priv,int port,u32 loc)1024ce24b08aSFlorian Fainelli static int bcm_sf2_cfp_rule_del(struct bcm_sf2_priv *priv, int port, u32 loc)
1025ce24b08aSFlorian Fainelli {
1026ce24b08aSFlorian Fainelli struct cfp_rule *rule;
1027ce24b08aSFlorian Fainelli int ret;
1028ce24b08aSFlorian Fainelli
1029d0802dc4SFlorian Fainelli if (loc > bcm_sf2_cfp_rule_size(priv))
1030f949a12fSDan Carpenter return -EINVAL;
1031f949a12fSDan Carpenter
10321942adf6SFlorian Fainelli /* Refuse deleting unused rules, and those that are not unique since
10331942adf6SFlorian Fainelli * that could leave IPv6 rules with one of the chained rule in the
10341942adf6SFlorian Fainelli * table.
10351942adf6SFlorian Fainelli */
10361942adf6SFlorian Fainelli if (!test_bit(loc, priv->cfp.unique) || loc == 0)
10371942adf6SFlorian Fainelli return -EINVAL;
10381942adf6SFlorian Fainelli
1039ae7a5affSFlorian Fainelli rule = bcm_sf2_cfp_rule_find(priv, port, loc);
1040ae7a5affSFlorian Fainelli if (!rule)
1041ae7a5affSFlorian Fainelli return -EINVAL;
1042ae7a5affSFlorian Fainelli
1043ce24b08aSFlorian Fainelli ret = bcm_sf2_cfp_rule_remove(priv, port, loc);
1044ba0696c2SFlorian Fainelli
1045ae7a5affSFlorian Fainelli list_del(&rule->next);
1046ae7a5affSFlorian Fainelli kfree(rule);
1047ae7a5affSFlorian Fainelli
1048ba0696c2SFlorian Fainelli return ret;
1049ba0696c2SFlorian Fainelli }
1050ba0696c2SFlorian Fainelli
bcm_sf2_invert_masks(struct ethtool_rx_flow_spec * flow)10517318166cSFlorian Fainelli static void bcm_sf2_invert_masks(struct ethtool_rx_flow_spec *flow)
10527318166cSFlorian Fainelli {
10537318166cSFlorian Fainelli unsigned int i;
10547318166cSFlorian Fainelli
10557318166cSFlorian Fainelli for (i = 0; i < sizeof(flow->m_u); i++)
10567318166cSFlorian Fainelli flow->m_u.hdata[i] ^= 0xff;
10577318166cSFlorian Fainelli
10587318166cSFlorian Fainelli flow->m_ext.vlan_etype ^= cpu_to_be16(~0);
10597318166cSFlorian Fainelli flow->m_ext.vlan_tci ^= cpu_to_be16(~0);
10607318166cSFlorian Fainelli flow->m_ext.data[0] ^= cpu_to_be32(~0);
10617318166cSFlorian Fainelli flow->m_ext.data[1] ^= cpu_to_be32(~0);
10627318166cSFlorian Fainelli }
10637318166cSFlorian Fainelli
bcm_sf2_cfp_rule_get(struct bcm_sf2_priv * priv,int port,struct ethtool_rxnfc * nfc)1064ae7a5affSFlorian Fainelli static int bcm_sf2_cfp_rule_get(struct bcm_sf2_priv *priv, int port,
1065ae7a5affSFlorian Fainelli struct ethtool_rxnfc *nfc)
1066ae7a5affSFlorian Fainelli {
1067ae7a5affSFlorian Fainelli struct cfp_rule *rule;
1068ae7a5affSFlorian Fainelli
1069ae7a5affSFlorian Fainelli rule = bcm_sf2_cfp_rule_find(priv, port, nfc->fs.location);
1070ae7a5affSFlorian Fainelli if (!rule)
1071ae7a5affSFlorian Fainelli return -EINVAL;
1072ae7a5affSFlorian Fainelli
1073ae7a5affSFlorian Fainelli memcpy(&nfc->fs, &rule->fs, sizeof(rule->fs));
1074ae7a5affSFlorian Fainelli
1075ae7a5affSFlorian Fainelli bcm_sf2_invert_masks(&nfc->fs);
1076ae7a5affSFlorian Fainelli
1077ae7a5affSFlorian Fainelli /* Put the TCAM size here */
1078ae7a5affSFlorian Fainelli nfc->data = bcm_sf2_cfp_rule_size(priv);
1079ae7a5affSFlorian Fainelli
1080ae7a5affSFlorian Fainelli return 0;
1081ae7a5affSFlorian Fainelli }
1082ae7a5affSFlorian Fainelli
10837318166cSFlorian Fainelli /* We implement the search doing a TCAM search operation */
bcm_sf2_cfp_rule_get_all(struct bcm_sf2_priv * priv,int port,struct ethtool_rxnfc * nfc,u32 * rule_locs)10847318166cSFlorian Fainelli static int bcm_sf2_cfp_rule_get_all(struct bcm_sf2_priv *priv,
10857318166cSFlorian Fainelli int port, struct ethtool_rxnfc *nfc,
10867318166cSFlorian Fainelli u32 *rule_locs)
10877318166cSFlorian Fainelli {
10887318166cSFlorian Fainelli unsigned int index = 1, rules_cnt = 0;
10897318166cSFlorian Fainelli
1090ba0696c2SFlorian Fainelli for_each_set_bit_from(index, priv->cfp.unique, priv->num_cfp_rules) {
10917318166cSFlorian Fainelli rule_locs[rules_cnt] = index;
10927318166cSFlorian Fainelli rules_cnt++;
10937318166cSFlorian Fainelli }
10947318166cSFlorian Fainelli
10957318166cSFlorian Fainelli /* Put the TCAM size here */
10967318166cSFlorian Fainelli nfc->data = bcm_sf2_cfp_rule_size(priv);
10977318166cSFlorian Fainelli nfc->rule_cnt = rules_cnt;
10987318166cSFlorian Fainelli
10997318166cSFlorian Fainelli return 0;
11007318166cSFlorian Fainelli }
11017318166cSFlorian Fainelli
bcm_sf2_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * nfc,u32 * rule_locs)11027318166cSFlorian Fainelli int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
11037318166cSFlorian Fainelli struct ethtool_rxnfc *nfc, u32 *rule_locs)
11047318166cSFlorian Fainelli {
1105*8f6a19c0SVladimir Oltean struct net_device *p = dsa_port_to_master(dsa_to_port(ds, port));
11067318166cSFlorian Fainelli struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
11077318166cSFlorian Fainelli int ret = 0;
11087318166cSFlorian Fainelli
11097318166cSFlorian Fainelli mutex_lock(&priv->cfp.lock);
11107318166cSFlorian Fainelli
11117318166cSFlorian Fainelli switch (nfc->cmd) {
11127318166cSFlorian Fainelli case ETHTOOL_GRXCLSRLCNT:
11137318166cSFlorian Fainelli /* Subtract the default, unusable rule */
1114ba0696c2SFlorian Fainelli nfc->rule_cnt = bitmap_weight(priv->cfp.unique,
1115df191632SFlorian Fainelli priv->num_cfp_rules) - 1;
11167318166cSFlorian Fainelli /* We support specifying rule locations */
11177318166cSFlorian Fainelli nfc->data |= RX_CLS_LOC_SPECIAL;
11187318166cSFlorian Fainelli break;
11197318166cSFlorian Fainelli case ETHTOOL_GRXCLSRULE:
11204daa70cfSFlorian Fainelli ret = bcm_sf2_cfp_rule_get(priv, port, nfc);
11217318166cSFlorian Fainelli break;
11227318166cSFlorian Fainelli case ETHTOOL_GRXCLSRLALL:
11237318166cSFlorian Fainelli ret = bcm_sf2_cfp_rule_get_all(priv, port, nfc, rule_locs);
11247318166cSFlorian Fainelli break;
11257318166cSFlorian Fainelli default:
11267318166cSFlorian Fainelli ret = -EOPNOTSUPP;
11277318166cSFlorian Fainelli break;
11287318166cSFlorian Fainelli }
11297318166cSFlorian Fainelli
11307318166cSFlorian Fainelli mutex_unlock(&priv->cfp.lock);
11317318166cSFlorian Fainelli
11328a75f4f2SFlorian Fainelli if (ret)
11338a75f4f2SFlorian Fainelli return ret;
11348a75f4f2SFlorian Fainelli
11358a75f4f2SFlorian Fainelli /* Pass up the commands to the attached master network device */
11368a75f4f2SFlorian Fainelli if (p->ethtool_ops->get_rxnfc) {
11378a75f4f2SFlorian Fainelli ret = p->ethtool_ops->get_rxnfc(p, nfc, rule_locs);
11388a75f4f2SFlorian Fainelli if (ret == -EOPNOTSUPP)
11398a75f4f2SFlorian Fainelli ret = 0;
11408a75f4f2SFlorian Fainelli }
11418a75f4f2SFlorian Fainelli
11427318166cSFlorian Fainelli return ret;
11437318166cSFlorian Fainelli }
11447318166cSFlorian Fainelli
bcm_sf2_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * nfc)11457318166cSFlorian Fainelli int bcm_sf2_set_rxnfc(struct dsa_switch *ds, int port,
11467318166cSFlorian Fainelli struct ethtool_rxnfc *nfc)
11477318166cSFlorian Fainelli {
1148*8f6a19c0SVladimir Oltean struct net_device *p = dsa_port_to_master(dsa_to_port(ds, port));
11497318166cSFlorian Fainelli struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
11507318166cSFlorian Fainelli int ret = 0;
11517318166cSFlorian Fainelli
11527318166cSFlorian Fainelli mutex_lock(&priv->cfp.lock);
11537318166cSFlorian Fainelli
11547318166cSFlorian Fainelli switch (nfc->cmd) {
11557318166cSFlorian Fainelli case ETHTOOL_SRXCLSRLINS:
11567318166cSFlorian Fainelli ret = bcm_sf2_cfp_rule_set(ds, port, &nfc->fs);
11577318166cSFlorian Fainelli break;
11587318166cSFlorian Fainelli
11597318166cSFlorian Fainelli case ETHTOOL_SRXCLSRLDEL:
11607318166cSFlorian Fainelli ret = bcm_sf2_cfp_rule_del(priv, port, nfc->fs.location);
11617318166cSFlorian Fainelli break;
11627318166cSFlorian Fainelli default:
11637318166cSFlorian Fainelli ret = -EOPNOTSUPP;
11647318166cSFlorian Fainelli break;
11657318166cSFlorian Fainelli }
11667318166cSFlorian Fainelli
11677318166cSFlorian Fainelli mutex_unlock(&priv->cfp.lock);
11687318166cSFlorian Fainelli
11698a75f4f2SFlorian Fainelli if (ret)
11708a75f4f2SFlorian Fainelli return ret;
11718a75f4f2SFlorian Fainelli
11728a75f4f2SFlorian Fainelli /* Pass up the commands to the attached master network device.
11738a75f4f2SFlorian Fainelli * This can fail, so rollback the operation if we need to.
11748a75f4f2SFlorian Fainelli */
11758a75f4f2SFlorian Fainelli if (p->ethtool_ops->set_rxnfc) {
11768a75f4f2SFlorian Fainelli ret = p->ethtool_ops->set_rxnfc(p, nfc);
11778a75f4f2SFlorian Fainelli if (ret && ret != -EOPNOTSUPP) {
11788a75f4f2SFlorian Fainelli mutex_lock(&priv->cfp.lock);
11798a75f4f2SFlorian Fainelli bcm_sf2_cfp_rule_del(priv, port, nfc->fs.location);
11808a75f4f2SFlorian Fainelli mutex_unlock(&priv->cfp.lock);
11818a75f4f2SFlorian Fainelli } else {
11828a75f4f2SFlorian Fainelli ret = 0;
11838a75f4f2SFlorian Fainelli }
11848a75f4f2SFlorian Fainelli }
11858a75f4f2SFlorian Fainelli
11867318166cSFlorian Fainelli return ret;
11877318166cSFlorian Fainelli }
11887318166cSFlorian Fainelli
bcm_sf2_cfp_rst(struct bcm_sf2_priv * priv)11897318166cSFlorian Fainelli int bcm_sf2_cfp_rst(struct bcm_sf2_priv *priv)
11907318166cSFlorian Fainelli {
11917318166cSFlorian Fainelli unsigned int timeout = 1000;
11927318166cSFlorian Fainelli u32 reg;
11937318166cSFlorian Fainelli
11947318166cSFlorian Fainelli reg = core_readl(priv, CORE_CFP_ACC);
11957318166cSFlorian Fainelli reg |= TCAM_RESET;
11967318166cSFlorian Fainelli core_writel(priv, reg, CORE_CFP_ACC);
11977318166cSFlorian Fainelli
11987318166cSFlorian Fainelli do {
11997318166cSFlorian Fainelli reg = core_readl(priv, CORE_CFP_ACC);
12007318166cSFlorian Fainelli if (!(reg & TCAM_RESET))
12017318166cSFlorian Fainelli break;
12027318166cSFlorian Fainelli
12037318166cSFlorian Fainelli cpu_relax();
12047318166cSFlorian Fainelli } while (timeout--);
12057318166cSFlorian Fainelli
12067318166cSFlorian Fainelli if (!timeout)
12077318166cSFlorian Fainelli return -ETIMEDOUT;
12087318166cSFlorian Fainelli
12097318166cSFlorian Fainelli return 0;
12107318166cSFlorian Fainelli }
1211ae7a5affSFlorian Fainelli
bcm_sf2_cfp_exit(struct dsa_switch * ds)1212ae7a5affSFlorian Fainelli void bcm_sf2_cfp_exit(struct dsa_switch *ds)
1213ae7a5affSFlorian Fainelli {
1214ae7a5affSFlorian Fainelli struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1215ae7a5affSFlorian Fainelli struct cfp_rule *rule, *n;
1216ae7a5affSFlorian Fainelli
1217ae7a5affSFlorian Fainelli if (list_empty(&priv->cfp.rules_list))
1218ae7a5affSFlorian Fainelli return;
1219ae7a5affSFlorian Fainelli
1220ae7a5affSFlorian Fainelli list_for_each_entry_safe_reverse(rule, n, &priv->cfp.rules_list, next)
1221ae7a5affSFlorian Fainelli bcm_sf2_cfp_rule_del(priv, rule->port, rule->fs.location);
1222ae7a5affSFlorian Fainelli }
12231c0130f0SFlorian Fainelli
bcm_sf2_cfp_resume(struct dsa_switch * ds)12241c0130f0SFlorian Fainelli int bcm_sf2_cfp_resume(struct dsa_switch *ds)
12251c0130f0SFlorian Fainelli {
12261c0130f0SFlorian Fainelli struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
12271c0130f0SFlorian Fainelli struct cfp_rule *rule;
12281c0130f0SFlorian Fainelli int ret = 0;
12291c0130f0SFlorian Fainelli u32 reg;
12301c0130f0SFlorian Fainelli
12311c0130f0SFlorian Fainelli if (list_empty(&priv->cfp.rules_list))
12321c0130f0SFlorian Fainelli return ret;
12331c0130f0SFlorian Fainelli
12341c0130f0SFlorian Fainelli reg = core_readl(priv, CORE_CFP_CTL_REG);
12351c0130f0SFlorian Fainelli reg &= ~CFP_EN_MAP_MASK;
12361c0130f0SFlorian Fainelli core_writel(priv, reg, CORE_CFP_CTL_REG);
12371c0130f0SFlorian Fainelli
12381c0130f0SFlorian Fainelli ret = bcm_sf2_cfp_rst(priv);
12391c0130f0SFlorian Fainelli if (ret)
12401c0130f0SFlorian Fainelli return ret;
12411c0130f0SFlorian Fainelli
12421c0130f0SFlorian Fainelli list_for_each_entry(rule, &priv->cfp.rules_list, next) {
12431c0130f0SFlorian Fainelli ret = bcm_sf2_cfp_rule_remove(priv, rule->port,
12441c0130f0SFlorian Fainelli rule->fs.location);
12451c0130f0SFlorian Fainelli if (ret) {
12461c0130f0SFlorian Fainelli dev_err(ds->dev, "failed to remove rule\n");
12471c0130f0SFlorian Fainelli return ret;
12481c0130f0SFlorian Fainelli }
12491c0130f0SFlorian Fainelli
12501c0130f0SFlorian Fainelli ret = bcm_sf2_cfp_rule_insert(ds, rule->port, &rule->fs);
12511c0130f0SFlorian Fainelli if (ret) {
12521c0130f0SFlorian Fainelli dev_err(ds->dev, "failed to restore rule\n");
12531c0130f0SFlorian Fainelli return ret;
12541c0130f0SFlorian Fainelli }
1255f9086200Skbuild test robot }
12561c0130f0SFlorian Fainelli
12571c0130f0SFlorian Fainelli return ret;
12581c0130f0SFlorian Fainelli }
1259f4ae9c08SFlorian Fainelli
1260f4ae9c08SFlorian Fainelli static const struct bcm_sf2_cfp_stat {
1261f4ae9c08SFlorian Fainelli unsigned int offset;
1262f4ae9c08SFlorian Fainelli unsigned int ram_loc;
1263f4ae9c08SFlorian Fainelli const char *name;
1264f4ae9c08SFlorian Fainelli } bcm_sf2_cfp_stats[] = {
1265f4ae9c08SFlorian Fainelli {
1266f4ae9c08SFlorian Fainelli .offset = CORE_STAT_GREEN_CNTR,
1267f4ae9c08SFlorian Fainelli .ram_loc = GREEN_STAT_RAM,
1268f4ae9c08SFlorian Fainelli .name = "Green"
1269f4ae9c08SFlorian Fainelli },
1270f4ae9c08SFlorian Fainelli {
1271f4ae9c08SFlorian Fainelli .offset = CORE_STAT_YELLOW_CNTR,
1272f4ae9c08SFlorian Fainelli .ram_loc = YELLOW_STAT_RAM,
1273f4ae9c08SFlorian Fainelli .name = "Yellow"
1274f4ae9c08SFlorian Fainelli },
1275f4ae9c08SFlorian Fainelli {
1276f4ae9c08SFlorian Fainelli .offset = CORE_STAT_RED_CNTR,
1277f4ae9c08SFlorian Fainelli .ram_loc = RED_STAT_RAM,
1278f4ae9c08SFlorian Fainelli .name = "Red"
1279f4ae9c08SFlorian Fainelli },
1280f4ae9c08SFlorian Fainelli };
1281f4ae9c08SFlorian Fainelli
bcm_sf2_cfp_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1282f4ae9c08SFlorian Fainelli void bcm_sf2_cfp_get_strings(struct dsa_switch *ds, int port,
1283f4ae9c08SFlorian Fainelli u32 stringset, uint8_t *data)
1284f4ae9c08SFlorian Fainelli {
1285f4ae9c08SFlorian Fainelli struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1286f4ae9c08SFlorian Fainelli unsigned int s = ARRAY_SIZE(bcm_sf2_cfp_stats);
1287f4ae9c08SFlorian Fainelli char buf[ETH_GSTRING_LEN];
1288f4ae9c08SFlorian Fainelli unsigned int i, j, iter;
1289f4ae9c08SFlorian Fainelli
1290f4ae9c08SFlorian Fainelli if (stringset != ETH_SS_STATS)
1291f4ae9c08SFlorian Fainelli return;
1292f4ae9c08SFlorian Fainelli
1293f4ae9c08SFlorian Fainelli for (i = 1; i < priv->num_cfp_rules; i++) {
1294f4ae9c08SFlorian Fainelli for (j = 0; j < s; j++) {
1295f4ae9c08SFlorian Fainelli snprintf(buf, sizeof(buf),
1296f4ae9c08SFlorian Fainelli "CFP%03d_%sCntr",
1297f4ae9c08SFlorian Fainelli i, bcm_sf2_cfp_stats[j].name);
1298f4ae9c08SFlorian Fainelli iter = (i - 1) * s + j;
1299fb3ceec1SWolfram Sang strscpy(data + iter * ETH_GSTRING_LEN,
1300f4ae9c08SFlorian Fainelli buf, ETH_GSTRING_LEN);
1301f4ae9c08SFlorian Fainelli }
1302f4ae9c08SFlorian Fainelli }
1303f4ae9c08SFlorian Fainelli }
1304f4ae9c08SFlorian Fainelli
bcm_sf2_cfp_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1305f4ae9c08SFlorian Fainelli void bcm_sf2_cfp_get_ethtool_stats(struct dsa_switch *ds, int port,
1306f4ae9c08SFlorian Fainelli uint64_t *data)
1307f4ae9c08SFlorian Fainelli {
1308f4ae9c08SFlorian Fainelli struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1309f4ae9c08SFlorian Fainelli unsigned int s = ARRAY_SIZE(bcm_sf2_cfp_stats);
1310f4ae9c08SFlorian Fainelli const struct bcm_sf2_cfp_stat *stat;
1311f4ae9c08SFlorian Fainelli unsigned int i, j, iter;
1312f4ae9c08SFlorian Fainelli struct cfp_rule *rule;
1313f4ae9c08SFlorian Fainelli int ret;
1314f4ae9c08SFlorian Fainelli
1315f4ae9c08SFlorian Fainelli mutex_lock(&priv->cfp.lock);
1316f4ae9c08SFlorian Fainelli for (i = 1; i < priv->num_cfp_rules; i++) {
1317f4ae9c08SFlorian Fainelli rule = bcm_sf2_cfp_rule_find(priv, port, i);
1318f4ae9c08SFlorian Fainelli if (!rule)
1319f4ae9c08SFlorian Fainelli continue;
1320f4ae9c08SFlorian Fainelli
1321f4ae9c08SFlorian Fainelli for (j = 0; j < s; j++) {
1322f4ae9c08SFlorian Fainelli stat = &bcm_sf2_cfp_stats[j];
1323f4ae9c08SFlorian Fainelli
1324f4ae9c08SFlorian Fainelli bcm_sf2_cfp_rule_addr_set(priv, i);
1325f4ae9c08SFlorian Fainelli ret = bcm_sf2_cfp_op(priv, stat->ram_loc | OP_SEL_READ);
1326f4ae9c08SFlorian Fainelli if (ret)
1327f4ae9c08SFlorian Fainelli continue;
1328f4ae9c08SFlorian Fainelli
1329f4ae9c08SFlorian Fainelli iter = (i - 1) * s + j;
1330f4ae9c08SFlorian Fainelli data[iter] = core_readl(priv, stat->offset);
1331f4ae9c08SFlorian Fainelli }
1332f4ae9c08SFlorian Fainelli
1333f4ae9c08SFlorian Fainelli }
1334f4ae9c08SFlorian Fainelli mutex_unlock(&priv->cfp.lock);
1335f4ae9c08SFlorian Fainelli }
1336f4ae9c08SFlorian Fainelli
bcm_sf2_cfp_get_sset_count(struct dsa_switch * ds,int port,int sset)1337f4ae9c08SFlorian Fainelli int bcm_sf2_cfp_get_sset_count(struct dsa_switch *ds, int port, int sset)
1338f4ae9c08SFlorian Fainelli {
1339f4ae9c08SFlorian Fainelli struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1340f4ae9c08SFlorian Fainelli
1341f4ae9c08SFlorian Fainelli if (sset != ETH_SS_STATS)
1342f4ae9c08SFlorian Fainelli return 0;
1343f4ae9c08SFlorian Fainelli
1344f4ae9c08SFlorian Fainelli /* 3 counters per CFP rules */
1345f4ae9c08SFlorian Fainelli return (priv->num_cfp_rules - 1) * ARRAY_SIZE(bcm_sf2_cfp_stats);
1346f4ae9c08SFlorian Fainelli }
1347