1 /* 2 * Broadcom Starfighter2 private context 3 * 4 * Copyright (C) 2014, Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef __BCM_SF2_H 13 #define __BCM_SF2_H 14 15 #include <linux/platform_device.h> 16 #include <linux/kernel.h> 17 #include <linux/io.h> 18 #include <linux/spinlock.h> 19 #include <linux/mutex.h> 20 #include <linux/mii.h> 21 #include <linux/ethtool.h> 22 #include <linux/types.h> 23 #include <linux/bitops.h> 24 #include <linux/if_vlan.h> 25 26 #include <net/dsa.h> 27 28 #include "bcm_sf2_regs.h" 29 #include "b53/b53_priv.h" 30 31 struct bcm_sf2_hw_params { 32 u16 top_rev; 33 u16 core_rev; 34 u16 gphy_rev; 35 u32 num_gphy; 36 u8 num_acb_queue; 37 u8 num_rgmii; 38 u8 num_ports; 39 u8 fcb_pause_override:1; 40 u8 acb_packets_inflight:1; 41 }; 42 43 #define BCM_SF2_REGS_NAME {\ 44 "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \ 45 } 46 47 #define BCM_SF2_REGS_NUM 6 48 49 struct bcm_sf2_port_status { 50 unsigned int link; 51 }; 52 53 struct bcm_sf2_cfp_priv { 54 /* Mutex protecting concurrent accesses to the CFP registers */ 55 struct mutex lock; 56 DECLARE_BITMAP(used, CFP_NUM_RULES); 57 unsigned int rules_cnt; 58 }; 59 60 struct bcm_sf2_priv { 61 /* Base registers, keep those in order with BCM_SF2_REGS_NAME */ 62 void __iomem *core; 63 void __iomem *reg; 64 void __iomem *intrl2_0; 65 void __iomem *intrl2_1; 66 void __iomem *fcb; 67 void __iomem *acb; 68 69 /* Register offsets indirection tables */ 70 u32 type; 71 const u16 *reg_offsets; 72 unsigned int core_reg_align; 73 unsigned int num_cfp_rules; 74 75 /* spinlock protecting access to the indirect registers */ 76 spinlock_t indir_lock; 77 78 int irq0; 79 int irq1; 80 u32 irq0_stat; 81 u32 irq0_mask; 82 u32 irq1_stat; 83 u32 irq1_mask; 84 85 /* Backing b53_device */ 86 struct b53_device *dev; 87 88 /* Mutex protecting access to the MIB counters */ 89 struct mutex stats_mutex; 90 91 struct bcm_sf2_hw_params hw_params; 92 93 struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS]; 94 95 /* Mask of ports enabled for Wake-on-LAN */ 96 u32 wol_ports_mask; 97 98 /* MoCA port location */ 99 int moca_port; 100 101 /* Bitmask of ports having an integrated PHY */ 102 unsigned int int_phy_mask; 103 104 /* Master and slave MDIO bus controller */ 105 unsigned int indir_phy_mask; 106 struct device_node *master_mii_dn; 107 struct mii_bus *slave_mii_bus; 108 struct mii_bus *master_mii_bus; 109 110 /* Bitmask of ports needing BRCM tags */ 111 unsigned int brcm_tag_mask; 112 113 /* CFP rules context */ 114 struct bcm_sf2_cfp_priv cfp; 115 }; 116 117 static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds) 118 { 119 struct b53_device *dev = ds->priv; 120 121 return dev->priv; 122 } 123 124 static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off) 125 { 126 return off << priv->core_reg_align; 127 } 128 129 #define SF2_IO_MACRO(name) \ 130 static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \ 131 { \ 132 return readl_relaxed(priv->name + off); \ 133 } \ 134 static inline void name##_writel(struct bcm_sf2_priv *priv, \ 135 u32 val, u32 off) \ 136 { \ 137 writel_relaxed(val, priv->name + off); \ 138 } \ 139 140 /* Accesses to 64-bits register requires us to latch the hi/lo pairs 141 * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock' 142 * spinlock is automatically grabbed and released to provide relative 143 * atomiticy with latched reads/writes. 144 */ 145 #define SF2_IO64_MACRO(name) \ 146 static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \ 147 { \ 148 u32 indir, dir; \ 149 spin_lock(&priv->indir_lock); \ 150 dir = name##_readl(priv, off); \ 151 indir = reg_readl(priv, REG_DIR_DATA_READ); \ 152 spin_unlock(&priv->indir_lock); \ 153 return (u64)indir << 32 | dir; \ 154 } \ 155 static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val, \ 156 u32 off) \ 157 { \ 158 spin_lock(&priv->indir_lock); \ 159 reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \ 160 name##_writel(priv, lower_32_bits(val), off); \ 161 spin_unlock(&priv->indir_lock); \ 162 } 163 164 #define SWITCH_INTR_L2(which) \ 165 static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \ 166 u32 mask) \ 167 { \ 168 priv->irq##which##_mask &= ~(mask); \ 169 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ 170 } \ 171 static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \ 172 u32 mask) \ 173 { \ 174 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ 175 priv->irq##which##_mask |= (mask); \ 176 } \ 177 178 static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off) 179 { 180 u32 tmp = bcm_sf2_mangle_addr(priv, off); 181 return readl_relaxed(priv->core + tmp); 182 } 183 184 static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) 185 { 186 u32 tmp = bcm_sf2_mangle_addr(priv, off); 187 writel_relaxed(val, priv->core + tmp); 188 } 189 190 static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off) 191 { 192 return readl_relaxed(priv->reg + priv->reg_offsets[off]); 193 } 194 195 static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off) 196 { 197 writel_relaxed(val, priv->reg + priv->reg_offsets[off]); 198 } 199 200 SF2_IO64_MACRO(core); 201 SF2_IO_MACRO(intrl2_0); 202 SF2_IO_MACRO(intrl2_1); 203 SF2_IO_MACRO(fcb); 204 SF2_IO_MACRO(acb); 205 206 SWITCH_INTR_L2(0); 207 SWITCH_INTR_L2(1); 208 209 /* RXNFC */ 210 int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port, 211 struct ethtool_rxnfc *nfc, u32 *rule_locs); 212 int bcm_sf2_set_rxnfc(struct dsa_switch *ds, int port, 213 struct ethtool_rxnfc *nfc); 214 int bcm_sf2_cfp_rst(struct bcm_sf2_priv *priv); 215 216 #endif /* __BCM_SF2_H */ 217