1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <net/dsa.h> 24 #include <linux/ethtool.h> 25 #include <linux/if_bridge.h> 26 #include <linux/brcmphy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/platform_data/b53.h> 29 30 #include "bcm_sf2.h" 31 #include "bcm_sf2_regs.h" 32 #include "b53/b53_priv.h" 33 #include "b53/b53_regs.h" 34 35 static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port) 36 { 37 switch (priv->type) { 38 case BCM4908_DEVICE_ID: 39 switch (port) { 40 case 7: 41 return REG_RGMII_11_CNTRL; 42 default: 43 break; 44 } 45 break; 46 default: 47 switch (port) { 48 case 0: 49 return REG_RGMII_0_CNTRL; 50 case 1: 51 return REG_RGMII_1_CNTRL; 52 case 2: 53 return REG_RGMII_2_CNTRL; 54 default: 55 break; 56 } 57 } 58 59 WARN_ONCE(1, "Unsupported port %d\n", port); 60 61 /* RO fallback reg */ 62 return REG_SWITCH_STATUS; 63 } 64 65 static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port) 66 { 67 switch (port) { 68 case 0: 69 return REG_LED_0_CNTRL; 70 case 1: 71 return REG_LED_1_CNTRL; 72 case 2: 73 return REG_LED_2_CNTRL; 74 } 75 76 switch (priv->type) { 77 case BCM4908_DEVICE_ID: 78 switch (port) { 79 case 3: 80 return REG_LED_3_CNTRL; 81 case 7: 82 return REG_LED_4_CNTRL; 83 default: 84 break; 85 } 86 break; 87 default: 88 break; 89 } 90 91 WARN_ONCE(1, "Unsupported port %d\n", port); 92 93 /* RO fallback reg */ 94 return REG_SWITCH_STATUS; 95 } 96 97 static u32 bcm_sf2_port_override_offset(struct bcm_sf2_priv *priv, int port) 98 { 99 switch (priv->type) { 100 case BCM4908_DEVICE_ID: 101 case BCM7445_DEVICE_ID: 102 return port == 8 ? CORE_STS_OVERRIDE_IMP : 103 CORE_STS_OVERRIDE_GMIIP_PORT(port); 104 case BCM7278_DEVICE_ID: 105 return port == 8 ? CORE_STS_OVERRIDE_IMP2 : 106 CORE_STS_OVERRIDE_GMIIP2_PORT(port); 107 default: 108 WARN_ONCE(1, "Unsupported device: %d\n", priv->type); 109 } 110 111 /* RO fallback register */ 112 return REG_SWITCH_STATUS; 113 } 114 115 /* Return the number of active ports, not counting the IMP (CPU) port */ 116 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds) 117 { 118 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 119 unsigned int port, count = 0; 120 121 for (port = 0; port < ds->num_ports; port++) { 122 if (dsa_is_cpu_port(ds, port)) 123 continue; 124 if (priv->port_sts[port].enabled) 125 count++; 126 } 127 128 return count; 129 } 130 131 static void bcm_sf2_recalc_clock(struct dsa_switch *ds) 132 { 133 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 134 unsigned long new_rate; 135 unsigned int ports_active; 136 /* Frequenty in Mhz */ 137 static const unsigned long rate_table[] = { 138 59220000, 139 60820000, 140 62500000, 141 62500000, 142 }; 143 144 ports_active = bcm_sf2_num_active_ports(ds); 145 if (ports_active == 0 || !priv->clk_mdiv) 146 return; 147 148 /* If we overflow our table, just use the recommended operational 149 * frequency 150 */ 151 if (ports_active > ARRAY_SIZE(rate_table)) 152 new_rate = 90000000; 153 else 154 new_rate = rate_table[ports_active - 1]; 155 clk_set_rate(priv->clk_mdiv, new_rate); 156 } 157 158 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 159 { 160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 161 unsigned int i; 162 u32 reg; 163 164 /* Enable the port memories */ 165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 166 reg &= ~P_TXQ_PSM_VDD(port); 167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 168 169 /* Enable forwarding */ 170 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 171 172 /* Enable IMP port in dumb mode */ 173 reg = core_readl(priv, CORE_SWITCH_CTRL); 174 reg |= MII_DUMB_FWDG_EN; 175 core_writel(priv, reg, CORE_SWITCH_CTRL); 176 177 /* Configure Traffic Class to QoS mapping, allow each priority to map 178 * to a different queue number 179 */ 180 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 181 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 182 reg |= i << (PRT_TO_QID_SHIFT * i); 183 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 184 185 b53_brcm_hdr_setup(ds, port); 186 187 if (port == 8) { 188 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 189 reg = core_readl(priv, CORE_IMP_CTL); 190 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 191 reg &= ~(RX_DIS | TX_DIS); 192 core_writel(priv, reg, CORE_IMP_CTL); 193 } else { 194 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 195 reg &= ~(RX_DIS | TX_DIS); 196 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 197 } 198 199 priv->port_sts[port].enabled = true; 200 } 201 202 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 203 { 204 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 205 u32 reg; 206 207 reg = reg_readl(priv, REG_SPHY_CNTRL); 208 if (enable) { 209 reg |= PHY_RESET; 210 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 211 reg_writel(priv, reg, REG_SPHY_CNTRL); 212 udelay(21); 213 reg = reg_readl(priv, REG_SPHY_CNTRL); 214 reg &= ~PHY_RESET; 215 } else { 216 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 217 reg_writel(priv, reg, REG_SPHY_CNTRL); 218 mdelay(1); 219 reg |= CK25_DIS; 220 } 221 reg_writel(priv, reg, REG_SPHY_CNTRL); 222 223 /* Use PHY-driven LED signaling */ 224 if (!enable) { 225 u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0); 226 227 if (priv->type == BCM7278_DEVICE_ID || 228 priv->type == BCM7445_DEVICE_ID) { 229 reg = reg_led_readl(priv, led_ctrl, 0); 230 reg |= LED_CNTRL_SPDLNK_SRC_SEL; 231 reg_led_writel(priv, reg, led_ctrl, 0); 232 } 233 } 234 } 235 236 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 237 int port) 238 { 239 unsigned int off; 240 241 switch (port) { 242 case 7: 243 off = P7_IRQ_OFF; 244 break; 245 case 0: 246 /* Port 0 interrupts are located on the first bank */ 247 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 248 return; 249 default: 250 off = P_IRQ_OFF(port); 251 break; 252 } 253 254 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 255 } 256 257 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 258 int port) 259 { 260 unsigned int off; 261 262 switch (port) { 263 case 7: 264 off = P7_IRQ_OFF; 265 break; 266 case 0: 267 /* Port 0 interrupts are located on the first bank */ 268 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 269 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 270 return; 271 default: 272 off = P_IRQ_OFF(port); 273 break; 274 } 275 276 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 277 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 278 } 279 280 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 281 struct phy_device *phy) 282 { 283 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 284 unsigned int i; 285 u32 reg; 286 287 if (!dsa_is_user_port(ds, port)) 288 return 0; 289 290 priv->port_sts[port].enabled = true; 291 292 bcm_sf2_recalc_clock(ds); 293 294 /* Clear the memory power down */ 295 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 296 reg &= ~P_TXQ_PSM_VDD(port); 297 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 298 299 /* Enable Broadcom tags for that port if requested */ 300 if (priv->brcm_tag_mask & BIT(port)) 301 b53_brcm_hdr_setup(ds, port); 302 303 /* Configure Traffic Class to QoS mapping, allow each priority to map 304 * to a different queue number 305 */ 306 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 307 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 308 reg |= i << (PRT_TO_QID_SHIFT * i); 309 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 310 311 /* Re-enable the GPHY and re-apply workarounds */ 312 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 313 bcm_sf2_gphy_enable_set(ds, true); 314 if (phy) { 315 /* if phy_stop() has been called before, phy 316 * will be in halted state, and phy_start() 317 * will call resume. 318 * 319 * the resume path does not configure back 320 * autoneg settings, and since we hard reset 321 * the phy manually here, we need to reset the 322 * state machine also. 323 */ 324 phy->state = PHY_READY; 325 phy_init_hw(phy); 326 } 327 } 328 329 /* Enable MoCA port interrupts to get notified */ 330 if (port == priv->moca_port) 331 bcm_sf2_port_intr_enable(priv, port); 332 333 /* Set per-queue pause threshold to 32 */ 334 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 335 336 /* Set ACB threshold to 24 */ 337 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 338 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 339 SF2_NUM_EGRESS_QUEUES + i)); 340 reg &= ~XOFF_THRESHOLD_MASK; 341 reg |= 24; 342 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 343 SF2_NUM_EGRESS_QUEUES + i)); 344 } 345 346 return b53_enable_port(ds, port, phy); 347 } 348 349 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 350 { 351 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 352 u32 reg; 353 354 /* Disable learning while in WoL mode */ 355 if (priv->wol_ports_mask & (1 << port)) { 356 reg = core_readl(priv, CORE_DIS_LEARN); 357 reg |= BIT(port); 358 core_writel(priv, reg, CORE_DIS_LEARN); 359 return; 360 } 361 362 if (port == priv->moca_port) 363 bcm_sf2_port_intr_disable(priv, port); 364 365 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 366 bcm_sf2_gphy_enable_set(ds, false); 367 368 b53_disable_port(ds, port); 369 370 /* Power down the port memory */ 371 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 372 reg |= P_TXQ_PSM_VDD(port); 373 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 374 375 priv->port_sts[port].enabled = false; 376 377 bcm_sf2_recalc_clock(ds); 378 } 379 380 381 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 382 int regnum, u16 val) 383 { 384 int ret = 0; 385 u32 reg; 386 387 reg = reg_readl(priv, REG_SWITCH_CNTRL); 388 reg |= MDIO_MASTER_SEL; 389 reg_writel(priv, reg, REG_SWITCH_CNTRL); 390 391 /* Page << 8 | offset */ 392 reg = 0x70; 393 reg <<= 2; 394 core_writel(priv, addr, reg); 395 396 /* Page << 8 | offset */ 397 reg = 0x80 << 8 | regnum << 1; 398 reg <<= 2; 399 400 if (op) 401 ret = core_readl(priv, reg); 402 else 403 core_writel(priv, val, reg); 404 405 reg = reg_readl(priv, REG_SWITCH_CNTRL); 406 reg &= ~MDIO_MASTER_SEL; 407 reg_writel(priv, reg, REG_SWITCH_CNTRL); 408 409 return ret & 0xffff; 410 } 411 412 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 413 { 414 struct bcm_sf2_priv *priv = bus->priv; 415 416 /* Intercept reads from Broadcom pseudo-PHY address, else, send 417 * them to our master MDIO bus controller 418 */ 419 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 420 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 421 else 422 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 423 } 424 425 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 426 u16 val) 427 { 428 struct bcm_sf2_priv *priv = bus->priv; 429 430 /* Intercept writes to the Broadcom pseudo-PHY address, else, 431 * send them to our master MDIO bus controller 432 */ 433 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 434 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 435 else 436 return mdiobus_write_nested(priv->master_mii_bus, addr, 437 regnum, val); 438 } 439 440 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 441 { 442 struct dsa_switch *ds = dev_id; 443 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 444 445 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 446 ~priv->irq0_mask; 447 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 448 449 return IRQ_HANDLED; 450 } 451 452 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 453 { 454 struct dsa_switch *ds = dev_id; 455 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 456 457 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 458 ~priv->irq1_mask; 459 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 460 461 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 462 priv->port_sts[7].link = true; 463 dsa_port_phylink_mac_change(ds, 7, true); 464 } 465 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 466 priv->port_sts[7].link = false; 467 dsa_port_phylink_mac_change(ds, 7, false); 468 } 469 470 return IRQ_HANDLED; 471 } 472 473 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 474 { 475 unsigned int timeout = 1000; 476 u32 reg; 477 int ret; 478 479 /* The watchdog reset does not work on 7278, we need to hit the 480 * "external" reset line through the reset controller. 481 */ 482 if (priv->type == BCM7278_DEVICE_ID) { 483 ret = reset_control_assert(priv->rcdev); 484 if (ret) 485 return ret; 486 487 return reset_control_deassert(priv->rcdev); 488 } 489 490 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 491 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 492 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 493 494 do { 495 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 496 if (!(reg & SOFTWARE_RESET)) 497 break; 498 499 usleep_range(1000, 2000); 500 } while (timeout-- > 0); 501 502 if (timeout == 0) 503 return -ETIMEDOUT; 504 505 return 0; 506 } 507 508 static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv) 509 { 510 struct device *dev = priv->dev->ds->dev; 511 int shift; 512 u32 mask; 513 u32 reg; 514 int i; 515 516 mask = BIT(priv->num_crossbar_int_ports) - 1; 517 518 reg = reg_readl(priv, REG_CROSSBAR); 519 switch (priv->type) { 520 case BCM4908_DEVICE_ID: 521 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports; 522 reg &= ~(mask << shift); 523 if (0) /* FIXME */ 524 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift; 525 else if (priv->int_phy_mask & BIT(7)) 526 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift; 527 else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode)) 528 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift; 529 else if (WARN(1, "Invalid port mode\n")) 530 return; 531 break; 532 default: 533 return; 534 } 535 reg_writel(priv, reg, REG_CROSSBAR); 536 537 reg = reg_readl(priv, REG_CROSSBAR); 538 for (i = 0; i < priv->num_crossbar_int_ports; i++) { 539 shift = i * priv->num_crossbar_int_ports; 540 541 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i, 542 (reg >> shift) & mask); 543 } 544 } 545 546 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 547 { 548 intrl2_0_mask_set(priv, 0xffffffff); 549 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 550 intrl2_1_mask_set(priv, 0xffffffff); 551 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 552 } 553 554 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 555 struct device_node *dn) 556 { 557 struct device *dev = priv->dev->ds->dev; 558 struct bcm_sf2_port_status *port_st; 559 struct device_node *port; 560 unsigned int port_num; 561 struct property *prop; 562 int err; 563 564 priv->moca_port = -1; 565 566 for_each_available_child_of_node(dn, port) { 567 if (of_property_read_u32(port, "reg", &port_num)) 568 continue; 569 570 if (port_num >= DSA_MAX_PORTS) { 571 dev_err(dev, "Invalid port number %d\n", port_num); 572 continue; 573 } 574 575 port_st = &priv->port_sts[port_num]; 576 577 /* Internal PHYs get assigned a specific 'phy-mode' property 578 * value: "internal" to help flag them before MDIO probing 579 * has completed, since they might be turned off at that 580 * time 581 */ 582 err = of_get_phy_mode(port, &port_st->mode); 583 if (err) 584 continue; 585 586 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL) 587 priv->int_phy_mask |= 1 << port_num; 588 589 if (port_st->mode == PHY_INTERFACE_MODE_MOCA) 590 priv->moca_port = port_num; 591 592 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 593 priv->brcm_tag_mask |= 1 << port_num; 594 595 /* Ensure that port 5 is not picked up as a DSA CPU port 596 * flavour but a regular port instead. We should be using 597 * devlink to be able to set the port flavour. 598 */ 599 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) { 600 prop = of_find_property(port, "ethernet", NULL); 601 if (prop) 602 of_remove_property(port, prop); 603 } 604 } 605 } 606 607 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 608 { 609 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 610 struct device_node *dn, *child; 611 struct phy_device *phydev; 612 struct property *prop; 613 static int index; 614 int err, reg; 615 616 /* Find our integrated MDIO bus node */ 617 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 618 priv->master_mii_bus = of_mdio_find_bus(dn); 619 if (!priv->master_mii_bus) { 620 of_node_put(dn); 621 return -EPROBE_DEFER; 622 } 623 624 get_device(&priv->master_mii_bus->dev); 625 priv->master_mii_dn = dn; 626 627 priv->slave_mii_bus = mdiobus_alloc(); 628 if (!priv->slave_mii_bus) { 629 of_node_put(dn); 630 return -ENOMEM; 631 } 632 633 priv->slave_mii_bus->priv = priv; 634 priv->slave_mii_bus->name = "sf2 slave mii"; 635 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 636 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 637 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 638 index++); 639 priv->slave_mii_bus->dev.of_node = dn; 640 641 /* Include the pseudo-PHY address to divert reads towards our 642 * workaround. This is only required for 7445D0, since 7445E0 643 * disconnects the internal switch pseudo-PHY such that we can use the 644 * regular SWITCH_MDIO master controller instead. 645 * 646 * Here we flag the pseudo PHY as needing special treatment and would 647 * otherwise make all other PHY read/writes go to the master MDIO bus 648 * controller that comes with this switch backed by the "mdio-unimac" 649 * driver. 650 */ 651 if (of_machine_is_compatible("brcm,bcm7445d0")) 652 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0); 653 else 654 priv->indir_phy_mask = 0; 655 656 ds->phys_mii_mask = priv->indir_phy_mask; 657 ds->slave_mii_bus = priv->slave_mii_bus; 658 priv->slave_mii_bus->parent = ds->dev->parent; 659 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 660 661 /* We need to make sure that of_phy_connect() will not work by 662 * removing the 'phandle' and 'linux,phandle' properties and 663 * unregister the existing PHY device that was already registered. 664 */ 665 for_each_available_child_of_node(dn, child) { 666 if (of_property_read_u32(child, "reg", ®) || 667 reg >= PHY_MAX_ADDR) 668 continue; 669 670 if (!(priv->indir_phy_mask & BIT(reg))) 671 continue; 672 673 prop = of_find_property(child, "phandle", NULL); 674 if (prop) 675 of_remove_property(child, prop); 676 677 prop = of_find_property(child, "linux,phandle", NULL); 678 if (prop) 679 of_remove_property(child, prop); 680 681 phydev = of_phy_find_device(child); 682 if (phydev) 683 phy_device_remove(phydev); 684 } 685 686 err = mdiobus_register(priv->slave_mii_bus); 687 if (err && dn) { 688 mdiobus_free(priv->slave_mii_bus); 689 of_node_put(dn); 690 } 691 692 return err; 693 } 694 695 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 696 { 697 mdiobus_unregister(priv->slave_mii_bus); 698 mdiobus_free(priv->slave_mii_bus); 699 of_node_put(priv->master_mii_dn); 700 } 701 702 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 703 { 704 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 705 706 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 707 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 708 * the REG_PHY_REVISION register layout is. 709 */ 710 if (priv->int_phy_mask & BIT(port)) 711 return priv->hw_params.gphy_rev; 712 else 713 return PHY_BRCM_AUTO_PWRDWN_ENABLE | 714 PHY_BRCM_DIS_TXCRXC_NOENRGY | 715 PHY_BRCM_IDDQ_SUSPEND; 716 } 717 718 static void bcm_sf2_sw_get_caps(struct dsa_switch *ds, int port, 719 struct phylink_config *config) 720 { 721 unsigned long *interfaces = config->supported_interfaces; 722 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 723 724 if (priv->int_phy_mask & BIT(port)) { 725 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces); 726 } else if (priv->moca_port == port) { 727 __set_bit(PHY_INTERFACE_MODE_MOCA, interfaces); 728 } else { 729 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 730 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 731 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 732 phy_interface_set_rgmii(interfaces); 733 } 734 735 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 736 MAC_10 | MAC_100 | MAC_1000; 737 } 738 739 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 740 unsigned int mode, 741 const struct phylink_link_state *state) 742 { 743 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 744 u32 id_mode_dis = 0, port_mode; 745 u32 reg_rgmii_ctrl; 746 u32 reg; 747 748 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 749 return; 750 751 switch (state->interface) { 752 case PHY_INTERFACE_MODE_RGMII: 753 id_mode_dis = 1; 754 fallthrough; 755 case PHY_INTERFACE_MODE_RGMII_TXID: 756 port_mode = EXT_GPHY; 757 break; 758 case PHY_INTERFACE_MODE_MII: 759 port_mode = EXT_EPHY; 760 break; 761 case PHY_INTERFACE_MODE_REVMII: 762 port_mode = EXT_REVMII; 763 break; 764 default: 765 /* Nothing required for all other PHYs: internal and MoCA */ 766 return; 767 } 768 769 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 770 771 /* Clear id_mode_dis bit, and the existing port mode, let 772 * RGMII_MODE_EN bet set by mac_link_{up,down} 773 */ 774 reg = reg_readl(priv, reg_rgmii_ctrl); 775 reg &= ~ID_MODE_DIS; 776 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 777 778 reg |= port_mode; 779 if (id_mode_dis) 780 reg |= ID_MODE_DIS; 781 782 reg_writel(priv, reg, reg_rgmii_ctrl); 783 } 784 785 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 786 phy_interface_t interface, bool link) 787 { 788 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 789 u32 reg_rgmii_ctrl; 790 u32 reg; 791 792 if (!phy_interface_mode_is_rgmii(interface) && 793 interface != PHY_INTERFACE_MODE_MII && 794 interface != PHY_INTERFACE_MODE_REVMII) 795 return; 796 797 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 798 799 /* If the link is down, just disable the interface to conserve power */ 800 reg = reg_readl(priv, reg_rgmii_ctrl); 801 if (link) 802 reg |= RGMII_MODE_EN; 803 else 804 reg &= ~RGMII_MODE_EN; 805 reg_writel(priv, reg, reg_rgmii_ctrl); 806 } 807 808 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 809 unsigned int mode, 810 phy_interface_t interface) 811 { 812 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 813 u32 reg, offset; 814 815 if (priv->wol_ports_mask & BIT(port)) 816 return; 817 818 offset = bcm_sf2_port_override_offset(priv, port); 819 reg = core_readl(priv, offset); 820 reg &= ~LINK_STS; 821 core_writel(priv, reg, offset); 822 823 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 824 } 825 826 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 827 unsigned int mode, 828 phy_interface_t interface, 829 struct phy_device *phydev, 830 int speed, int duplex, 831 bool tx_pause, bool rx_pause) 832 { 833 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 834 struct ethtool_eee *p = &priv->dev->ports[port].eee; 835 u32 reg_rgmii_ctrl = 0; 836 u32 reg, offset; 837 838 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 839 840 offset = bcm_sf2_port_override_offset(priv, port); 841 842 if (phy_interface_mode_is_rgmii(interface) || 843 interface == PHY_INTERFACE_MODE_MII || 844 interface == PHY_INTERFACE_MODE_REVMII) { 845 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 846 reg = reg_readl(priv, reg_rgmii_ctrl); 847 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 848 849 if (tx_pause) 850 reg |= TX_PAUSE_EN; 851 if (rx_pause) 852 reg |= RX_PAUSE_EN; 853 854 reg_writel(priv, reg, reg_rgmii_ctrl); 855 } 856 857 reg = LINK_STS; 858 if (port == 8) { 859 if (priv->type == BCM4908_DEVICE_ID) 860 reg |= GMII_SPEED_UP_2G; 861 reg |= MII_SW_OR; 862 } else { 863 reg |= SW_OVERRIDE; 864 } 865 866 switch (speed) { 867 case SPEED_1000: 868 reg |= SPDSTS_1000 << SPEED_SHIFT; 869 break; 870 case SPEED_100: 871 reg |= SPDSTS_100 << SPEED_SHIFT; 872 break; 873 } 874 875 if (duplex == DUPLEX_FULL) 876 reg |= DUPLX_MODE; 877 878 if (tx_pause) 879 reg |= TXFLOW_CNTL; 880 if (rx_pause) 881 reg |= RXFLOW_CNTL; 882 883 core_writel(priv, reg, offset); 884 885 if (mode == MLO_AN_PHY && phydev) 886 p->eee_enabled = b53_eee_init(ds, port, phydev); 887 } 888 889 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 890 struct phylink_link_state *status) 891 { 892 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 893 894 status->link = false; 895 896 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 897 * which means that we need to force the link at the port override 898 * level to get the data to flow. We do use what the interrupt handler 899 * did determine before. 900 * 901 * For the other ports, we just force the link status, since this is 902 * a fixed PHY device. 903 */ 904 if (port == priv->moca_port) { 905 status->link = priv->port_sts[port].link; 906 /* For MoCA interfaces, also force a link down notification 907 * since some version of the user-space daemon (mocad) use 908 * cmd->autoneg to force the link, which messes up the PHY 909 * state machine and make it go in PHY_FORCING state instead. 910 */ 911 if (!status->link) 912 netif_carrier_off(dsa_to_port(ds, port)->slave); 913 status->duplex = DUPLEX_FULL; 914 } else { 915 status->link = true; 916 } 917 } 918 919 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 920 { 921 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 922 u32 reg; 923 924 /* Enable ACB globally */ 925 reg = acb_readl(priv, ACB_CONTROL); 926 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 927 acb_writel(priv, reg, ACB_CONTROL); 928 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 929 reg |= ACB_EN | ACB_ALGORITHM; 930 acb_writel(priv, reg, ACB_CONTROL); 931 } 932 933 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 934 { 935 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 936 unsigned int port; 937 938 bcm_sf2_intr_disable(priv); 939 940 /* Disable all ports physically present including the IMP 941 * port, the other ones have already been disabled during 942 * bcm_sf2_sw_setup 943 */ 944 for (port = 0; port < ds->num_ports; port++) { 945 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 946 bcm_sf2_port_disable(ds, port); 947 } 948 949 if (!priv->wol_ports_mask) 950 clk_disable_unprepare(priv->clk); 951 952 return 0; 953 } 954 955 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 956 { 957 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 958 int ret; 959 960 if (!priv->wol_ports_mask) 961 clk_prepare_enable(priv->clk); 962 963 ret = bcm_sf2_sw_rst(priv); 964 if (ret) { 965 pr_err("%s: failed to software reset switch\n", __func__); 966 return ret; 967 } 968 969 bcm_sf2_crossbar_setup(priv); 970 971 ret = bcm_sf2_cfp_resume(ds); 972 if (ret) 973 return ret; 974 975 if (priv->hw_params.num_gphy == 1) 976 bcm_sf2_gphy_enable_set(ds, true); 977 978 ds->ops->setup(ds); 979 980 return 0; 981 } 982 983 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 984 struct ethtool_wolinfo *wol) 985 { 986 struct net_device *p = dsa_port_to_master(dsa_to_port(ds, port)); 987 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 988 struct ethtool_wolinfo pwol = { }; 989 990 /* Get the parent device WoL settings */ 991 if (p->ethtool_ops->get_wol) 992 p->ethtool_ops->get_wol(p, &pwol); 993 994 /* Advertise the parent device supported settings */ 995 wol->supported = pwol.supported; 996 memset(&wol->sopass, 0, sizeof(wol->sopass)); 997 998 if (pwol.wolopts & WAKE_MAGICSECURE) 999 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 1000 1001 if (priv->wol_ports_mask & (1 << port)) 1002 wol->wolopts = pwol.wolopts; 1003 else 1004 wol->wolopts = 0; 1005 } 1006 1007 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 1008 struct ethtool_wolinfo *wol) 1009 { 1010 struct net_device *p = dsa_port_to_master(dsa_to_port(ds, port)); 1011 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 1012 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1013 struct ethtool_wolinfo pwol = { }; 1014 1015 if (p->ethtool_ops->get_wol) 1016 p->ethtool_ops->get_wol(p, &pwol); 1017 if (wol->wolopts & ~pwol.supported) 1018 return -EINVAL; 1019 1020 if (wol->wolopts) 1021 priv->wol_ports_mask |= (1 << port); 1022 else 1023 priv->wol_ports_mask &= ~(1 << port); 1024 1025 /* If we have at least one port enabled, make sure the CPU port 1026 * is also enabled. If the CPU port is the last one enabled, we disable 1027 * it since this configuration does not make sense. 1028 */ 1029 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 1030 priv->wol_ports_mask |= (1 << cpu_port); 1031 else 1032 priv->wol_ports_mask &= ~(1 << cpu_port); 1033 1034 return p->ethtool_ops->set_wol(p, wol); 1035 } 1036 1037 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 1038 { 1039 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 1040 unsigned int port; 1041 1042 /* Enable all valid ports and disable those unused */ 1043 for (port = 0; port < priv->hw_params.num_ports; port++) { 1044 /* IMP port receives special treatment */ 1045 if (dsa_is_user_port(ds, port)) 1046 bcm_sf2_port_setup(ds, port, NULL); 1047 else if (dsa_is_cpu_port(ds, port)) 1048 bcm_sf2_imp_setup(ds, port); 1049 else 1050 bcm_sf2_port_disable(ds, port); 1051 } 1052 1053 b53_configure_vlan(ds); 1054 bcm_sf2_enable_acb(ds); 1055 1056 return b53_setup_devlink_resources(ds); 1057 } 1058 1059 static void bcm_sf2_sw_teardown(struct dsa_switch *ds) 1060 { 1061 dsa_devlink_resources_unregister(ds); 1062 } 1063 1064 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 1065 * register basis so we need to translate that into an address that the 1066 * bus-glue understands. 1067 */ 1068 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 1069 1070 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 1071 u8 *val) 1072 { 1073 struct bcm_sf2_priv *priv = dev->priv; 1074 1075 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1076 1077 return 0; 1078 } 1079 1080 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 1081 u16 *val) 1082 { 1083 struct bcm_sf2_priv *priv = dev->priv; 1084 1085 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1086 1087 return 0; 1088 } 1089 1090 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 1091 u32 *val) 1092 { 1093 struct bcm_sf2_priv *priv = dev->priv; 1094 1095 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1096 1097 return 0; 1098 } 1099 1100 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 1101 u64 *val) 1102 { 1103 struct bcm_sf2_priv *priv = dev->priv; 1104 1105 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1106 1107 return 0; 1108 } 1109 1110 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 1111 u8 value) 1112 { 1113 struct bcm_sf2_priv *priv = dev->priv; 1114 1115 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1116 1117 return 0; 1118 } 1119 1120 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 1121 u16 value) 1122 { 1123 struct bcm_sf2_priv *priv = dev->priv; 1124 1125 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1126 1127 return 0; 1128 } 1129 1130 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 1131 u32 value) 1132 { 1133 struct bcm_sf2_priv *priv = dev->priv; 1134 1135 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1136 1137 return 0; 1138 } 1139 1140 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 1141 u64 value) 1142 { 1143 struct bcm_sf2_priv *priv = dev->priv; 1144 1145 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1146 1147 return 0; 1148 } 1149 1150 static const struct b53_io_ops bcm_sf2_io_ops = { 1151 .read8 = bcm_sf2_core_read8, 1152 .read16 = bcm_sf2_core_read16, 1153 .read32 = bcm_sf2_core_read32, 1154 .read48 = bcm_sf2_core_read64, 1155 .read64 = bcm_sf2_core_read64, 1156 .write8 = bcm_sf2_core_write8, 1157 .write16 = bcm_sf2_core_write16, 1158 .write32 = bcm_sf2_core_write32, 1159 .write48 = bcm_sf2_core_write64, 1160 .write64 = bcm_sf2_core_write64, 1161 }; 1162 1163 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 1164 u32 stringset, uint8_t *data) 1165 { 1166 int cnt = b53_get_sset_count(ds, port, stringset); 1167 1168 b53_get_strings(ds, port, stringset, data); 1169 bcm_sf2_cfp_get_strings(ds, port, stringset, 1170 data + cnt * ETH_GSTRING_LEN); 1171 } 1172 1173 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 1174 uint64_t *data) 1175 { 1176 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 1177 1178 b53_get_ethtool_stats(ds, port, data); 1179 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 1180 } 1181 1182 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 1183 int sset) 1184 { 1185 int cnt = b53_get_sset_count(ds, port, sset); 1186 1187 if (cnt < 0) 1188 return cnt; 1189 1190 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 1191 1192 return cnt; 1193 } 1194 1195 static const struct dsa_switch_ops bcm_sf2_ops = { 1196 .get_tag_protocol = b53_get_tag_protocol, 1197 .setup = bcm_sf2_sw_setup, 1198 .teardown = bcm_sf2_sw_teardown, 1199 .get_strings = bcm_sf2_sw_get_strings, 1200 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 1201 .get_sset_count = bcm_sf2_sw_get_sset_count, 1202 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1203 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 1204 .phylink_get_caps = bcm_sf2_sw_get_caps, 1205 .phylink_mac_config = bcm_sf2_sw_mac_config, 1206 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 1207 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 1208 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 1209 .suspend = bcm_sf2_sw_suspend, 1210 .resume = bcm_sf2_sw_resume, 1211 .get_wol = bcm_sf2_sw_get_wol, 1212 .set_wol = bcm_sf2_sw_set_wol, 1213 .port_enable = bcm_sf2_port_setup, 1214 .port_disable = bcm_sf2_port_disable, 1215 .get_mac_eee = b53_get_mac_eee, 1216 .set_mac_eee = b53_set_mac_eee, 1217 .port_bridge_join = b53_br_join, 1218 .port_bridge_leave = b53_br_leave, 1219 .port_pre_bridge_flags = b53_br_flags_pre, 1220 .port_bridge_flags = b53_br_flags, 1221 .port_stp_state_set = b53_br_set_stp_state, 1222 .port_fast_age = b53_br_fast_age, 1223 .port_vlan_filtering = b53_vlan_filtering, 1224 .port_vlan_add = b53_vlan_add, 1225 .port_vlan_del = b53_vlan_del, 1226 .port_fdb_dump = b53_fdb_dump, 1227 .port_fdb_add = b53_fdb_add, 1228 .port_fdb_del = b53_fdb_del, 1229 .get_rxnfc = bcm_sf2_get_rxnfc, 1230 .set_rxnfc = bcm_sf2_set_rxnfc, 1231 .port_mirror_add = b53_mirror_add, 1232 .port_mirror_del = b53_mirror_del, 1233 .port_mdb_add = b53_mdb_add, 1234 .port_mdb_del = b53_mdb_del, 1235 }; 1236 1237 struct bcm_sf2_of_data { 1238 u32 type; 1239 const u16 *reg_offsets; 1240 unsigned int core_reg_align; 1241 unsigned int num_cfp_rules; 1242 unsigned int num_crossbar_int_ports; 1243 }; 1244 1245 static const u16 bcm_sf2_4908_reg_offsets[] = { 1246 [REG_SWITCH_CNTRL] = 0x00, 1247 [REG_SWITCH_STATUS] = 0x04, 1248 [REG_DIR_DATA_WRITE] = 0x08, 1249 [REG_DIR_DATA_READ] = 0x0c, 1250 [REG_SWITCH_REVISION] = 0x10, 1251 [REG_PHY_REVISION] = 0x14, 1252 [REG_SPHY_CNTRL] = 0x24, 1253 [REG_CROSSBAR] = 0xc8, 1254 [REG_RGMII_11_CNTRL] = 0x014c, 1255 [REG_LED_0_CNTRL] = 0x40, 1256 [REG_LED_1_CNTRL] = 0x4c, 1257 [REG_LED_2_CNTRL] = 0x58, 1258 [REG_LED_3_CNTRL] = 0x64, 1259 [REG_LED_4_CNTRL] = 0x88, 1260 [REG_LED_5_CNTRL] = 0xa0, 1261 [REG_LED_AGGREGATE_CTRL] = 0xb8, 1262 1263 }; 1264 1265 static const struct bcm_sf2_of_data bcm_sf2_4908_data = { 1266 .type = BCM4908_DEVICE_ID, 1267 .core_reg_align = 0, 1268 .reg_offsets = bcm_sf2_4908_reg_offsets, 1269 .num_cfp_rules = 256, 1270 .num_crossbar_int_ports = 2, 1271 }; 1272 1273 /* Register offsets for the SWITCH_REG_* block */ 1274 static const u16 bcm_sf2_7445_reg_offsets[] = { 1275 [REG_SWITCH_CNTRL] = 0x00, 1276 [REG_SWITCH_STATUS] = 0x04, 1277 [REG_DIR_DATA_WRITE] = 0x08, 1278 [REG_DIR_DATA_READ] = 0x0C, 1279 [REG_SWITCH_REVISION] = 0x18, 1280 [REG_PHY_REVISION] = 0x1C, 1281 [REG_SPHY_CNTRL] = 0x2C, 1282 [REG_RGMII_0_CNTRL] = 0x34, 1283 [REG_RGMII_1_CNTRL] = 0x40, 1284 [REG_RGMII_2_CNTRL] = 0x4c, 1285 [REG_LED_0_CNTRL] = 0x90, 1286 [REG_LED_1_CNTRL] = 0x94, 1287 [REG_LED_2_CNTRL] = 0x98, 1288 }; 1289 1290 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1291 .type = BCM7445_DEVICE_ID, 1292 .core_reg_align = 0, 1293 .reg_offsets = bcm_sf2_7445_reg_offsets, 1294 .num_cfp_rules = 256, 1295 }; 1296 1297 static const u16 bcm_sf2_7278_reg_offsets[] = { 1298 [REG_SWITCH_CNTRL] = 0x00, 1299 [REG_SWITCH_STATUS] = 0x04, 1300 [REG_DIR_DATA_WRITE] = 0x08, 1301 [REG_DIR_DATA_READ] = 0x0c, 1302 [REG_SWITCH_REVISION] = 0x10, 1303 [REG_PHY_REVISION] = 0x14, 1304 [REG_SPHY_CNTRL] = 0x24, 1305 [REG_RGMII_0_CNTRL] = 0xe0, 1306 [REG_RGMII_1_CNTRL] = 0xec, 1307 [REG_RGMII_2_CNTRL] = 0xf8, 1308 [REG_LED_0_CNTRL] = 0x40, 1309 [REG_LED_1_CNTRL] = 0x4c, 1310 [REG_LED_2_CNTRL] = 0x58, 1311 }; 1312 1313 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1314 .type = BCM7278_DEVICE_ID, 1315 .core_reg_align = 1, 1316 .reg_offsets = bcm_sf2_7278_reg_offsets, 1317 .num_cfp_rules = 128, 1318 }; 1319 1320 static const struct of_device_id bcm_sf2_of_match[] = { 1321 { .compatible = "brcm,bcm4908-switch", 1322 .data = &bcm_sf2_4908_data 1323 }, 1324 { .compatible = "brcm,bcm7445-switch-v4.0", 1325 .data = &bcm_sf2_7445_data 1326 }, 1327 { .compatible = "brcm,bcm7278-switch-v4.0", 1328 .data = &bcm_sf2_7278_data 1329 }, 1330 { .compatible = "brcm,bcm7278-switch-v4.8", 1331 .data = &bcm_sf2_7278_data 1332 }, 1333 { /* sentinel */ }, 1334 }; 1335 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1336 1337 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1338 { 1339 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1340 struct device_node *dn = pdev->dev.of_node; 1341 const struct of_device_id *of_id = NULL; 1342 const struct bcm_sf2_of_data *data; 1343 struct b53_platform_data *pdata; 1344 struct dsa_switch_ops *ops; 1345 struct device_node *ports; 1346 struct bcm_sf2_priv *priv; 1347 struct b53_device *dev; 1348 struct dsa_switch *ds; 1349 void __iomem **base; 1350 unsigned int i; 1351 u32 reg, rev; 1352 int ret; 1353 1354 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1355 if (!priv) 1356 return -ENOMEM; 1357 1358 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1359 if (!ops) 1360 return -ENOMEM; 1361 1362 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1363 if (!dev) 1364 return -ENOMEM; 1365 1366 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1367 if (!pdata) 1368 return -ENOMEM; 1369 1370 of_id = of_match_node(bcm_sf2_of_match, dn); 1371 if (!of_id || !of_id->data) 1372 return -EINVAL; 1373 1374 data = of_id->data; 1375 1376 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1377 priv->type = data->type; 1378 priv->reg_offsets = data->reg_offsets; 1379 priv->core_reg_align = data->core_reg_align; 1380 priv->num_cfp_rules = data->num_cfp_rules; 1381 priv->num_crossbar_int_ports = data->num_crossbar_int_ports; 1382 1383 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1384 "switch"); 1385 if (IS_ERR(priv->rcdev)) 1386 return PTR_ERR(priv->rcdev); 1387 1388 /* Auto-detection using standard registers will not work, so 1389 * provide an indication of what kind of device we are for 1390 * b53_common to work with 1391 */ 1392 pdata->chip_id = priv->type; 1393 dev->pdata = pdata; 1394 1395 priv->dev = dev; 1396 ds = dev->ds; 1397 ds->ops = &bcm_sf2_ops; 1398 1399 /* Advertise the 8 egress queues */ 1400 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1401 1402 dev_set_drvdata(&pdev->dev, priv); 1403 1404 spin_lock_init(&priv->indir_lock); 1405 mutex_init(&priv->cfp.lock); 1406 INIT_LIST_HEAD(&priv->cfp.rules_list); 1407 1408 /* CFP rule #0 cannot be used for specific classifications, flag it as 1409 * permanently used 1410 */ 1411 set_bit(0, priv->cfp.used); 1412 set_bit(0, priv->cfp.unique); 1413 1414 /* Balance of_node_put() done by of_find_node_by_name() */ 1415 of_node_get(dn); 1416 ports = of_find_node_by_name(dn, "ports"); 1417 if (ports) { 1418 bcm_sf2_identify_ports(priv, ports); 1419 of_node_put(ports); 1420 } 1421 1422 priv->irq0 = irq_of_parse_and_map(dn, 0); 1423 priv->irq1 = irq_of_parse_and_map(dn, 1); 1424 1425 base = &priv->core; 1426 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1427 *base = devm_platform_ioremap_resource(pdev, i); 1428 if (IS_ERR(*base)) { 1429 pr_err("unable to find register: %s\n", reg_names[i]); 1430 return PTR_ERR(*base); 1431 } 1432 base++; 1433 } 1434 1435 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch"); 1436 if (IS_ERR(priv->clk)) 1437 return PTR_ERR(priv->clk); 1438 1439 clk_prepare_enable(priv->clk); 1440 1441 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv"); 1442 if (IS_ERR(priv->clk_mdiv)) { 1443 ret = PTR_ERR(priv->clk_mdiv); 1444 goto out_clk; 1445 } 1446 1447 clk_prepare_enable(priv->clk_mdiv); 1448 1449 ret = bcm_sf2_sw_rst(priv); 1450 if (ret) { 1451 pr_err("unable to software reset switch: %d\n", ret); 1452 goto out_clk_mdiv; 1453 } 1454 1455 bcm_sf2_crossbar_setup(priv); 1456 1457 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1458 1459 ret = bcm_sf2_mdio_register(ds); 1460 if (ret) { 1461 pr_err("failed to register MDIO bus\n"); 1462 goto out_clk_mdiv; 1463 } 1464 1465 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1466 1467 ret = bcm_sf2_cfp_rst(priv); 1468 if (ret) { 1469 pr_err("failed to reset CFP\n"); 1470 goto out_mdio; 1471 } 1472 1473 /* Disable all interrupts and request them */ 1474 bcm_sf2_intr_disable(priv); 1475 1476 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1477 "switch_0", ds); 1478 if (ret < 0) { 1479 pr_err("failed to request switch_0 IRQ\n"); 1480 goto out_mdio; 1481 } 1482 1483 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1484 "switch_1", ds); 1485 if (ret < 0) { 1486 pr_err("failed to request switch_1 IRQ\n"); 1487 goto out_mdio; 1488 } 1489 1490 /* Reset the MIB counters */ 1491 reg = core_readl(priv, CORE_GMNCFGCFG); 1492 reg |= RST_MIB_CNT; 1493 core_writel(priv, reg, CORE_GMNCFGCFG); 1494 reg &= ~RST_MIB_CNT; 1495 core_writel(priv, reg, CORE_GMNCFGCFG); 1496 1497 /* Get the maximum number of ports for this switch */ 1498 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1499 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1500 priv->hw_params.num_ports = DSA_MAX_PORTS; 1501 1502 /* Assume a single GPHY setup if we can't read that property */ 1503 if (of_property_read_u32(dn, "brcm,num-gphy", 1504 &priv->hw_params.num_gphy)) 1505 priv->hw_params.num_gphy = 1; 1506 1507 rev = reg_readl(priv, REG_SWITCH_REVISION); 1508 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1509 SWITCH_TOP_REV_MASK; 1510 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1511 1512 rev = reg_readl(priv, REG_PHY_REVISION); 1513 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1514 1515 ret = b53_switch_register(dev); 1516 if (ret) 1517 goto out_mdio; 1518 1519 dev_info(&pdev->dev, 1520 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1521 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1522 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1523 priv->irq0, priv->irq1); 1524 1525 return 0; 1526 1527 out_mdio: 1528 bcm_sf2_mdio_unregister(priv); 1529 out_clk_mdiv: 1530 clk_disable_unprepare(priv->clk_mdiv); 1531 out_clk: 1532 clk_disable_unprepare(priv->clk); 1533 return ret; 1534 } 1535 1536 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1537 { 1538 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1539 1540 if (!priv) 1541 return 0; 1542 1543 priv->wol_ports_mask = 0; 1544 /* Disable interrupts */ 1545 bcm_sf2_intr_disable(priv); 1546 dsa_unregister_switch(priv->dev->ds); 1547 bcm_sf2_cfp_exit(priv->dev->ds); 1548 bcm_sf2_mdio_unregister(priv); 1549 clk_disable_unprepare(priv->clk_mdiv); 1550 clk_disable_unprepare(priv->clk); 1551 if (priv->type == BCM7278_DEVICE_ID) 1552 reset_control_assert(priv->rcdev); 1553 1554 return 0; 1555 } 1556 1557 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1558 { 1559 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1560 1561 if (!priv) 1562 return; 1563 1564 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1565 * successful MDIO bus scan to occur. If we did turn off the GPHY 1566 * before (e.g: port_disable), this will also power it back on. 1567 * 1568 * Do not rely on kexec_in_progress, just power the PHY on. 1569 */ 1570 if (priv->hw_params.num_gphy == 1) 1571 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1572 1573 dsa_switch_shutdown(priv->dev->ds); 1574 1575 platform_set_drvdata(pdev, NULL); 1576 } 1577 1578 #ifdef CONFIG_PM_SLEEP 1579 static int bcm_sf2_suspend(struct device *dev) 1580 { 1581 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1582 1583 return dsa_switch_suspend(priv->dev->ds); 1584 } 1585 1586 static int bcm_sf2_resume(struct device *dev) 1587 { 1588 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1589 1590 return dsa_switch_resume(priv->dev->ds); 1591 } 1592 #endif /* CONFIG_PM_SLEEP */ 1593 1594 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1595 bcm_sf2_suspend, bcm_sf2_resume); 1596 1597 1598 static struct platform_driver bcm_sf2_driver = { 1599 .probe = bcm_sf2_sw_probe, 1600 .remove = bcm_sf2_sw_remove, 1601 .shutdown = bcm_sf2_sw_shutdown, 1602 .driver = { 1603 .name = "brcm-sf2", 1604 .of_match_table = bcm_sf2_of_match, 1605 .pm = &bcm_sf2_pm_ops, 1606 }, 1607 }; 1608 module_platform_driver(bcm_sf2_driver); 1609 1610 MODULE_AUTHOR("Broadcom Corporation"); 1611 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1612 MODULE_LICENSE("GPL"); 1613 MODULE_ALIAS("platform:brcm-sf2"); 1614