1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/of.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_address.h> 20 #include <linux/of_net.h> 21 #include <linux/of_mdio.h> 22 #include <net/dsa.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_bridge.h> 25 #include <linux/brcmphy.h> 26 #include <linux/etherdevice.h> 27 #include <linux/platform_data/b53.h> 28 29 #include "bcm_sf2.h" 30 #include "bcm_sf2_regs.h" 31 #include "b53/b53_priv.h" 32 #include "b53/b53_regs.h" 33 34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 35 { 36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 37 unsigned int i; 38 u32 reg, offset; 39 40 /* Enable the port memories */ 41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 42 reg &= ~P_TXQ_PSM_VDD(port); 43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 44 45 /* Enable forwarding */ 46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 47 48 /* Enable IMP port in dumb mode */ 49 reg = core_readl(priv, CORE_SWITCH_CTRL); 50 reg |= MII_DUMB_FWDG_EN; 51 core_writel(priv, reg, CORE_SWITCH_CTRL); 52 53 /* Configure Traffic Class to QoS mapping, allow each priority to map 54 * to a different queue number 55 */ 56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 58 reg |= i << (PRT_TO_QID_SHIFT * i); 59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 60 61 b53_brcm_hdr_setup(ds, port); 62 63 if (port == 8) { 64 if (priv->type == BCM7445_DEVICE_ID) 65 offset = CORE_STS_OVERRIDE_IMP; 66 else 67 offset = CORE_STS_OVERRIDE_IMP2; 68 69 /* Force link status for IMP port */ 70 reg = core_readl(priv, offset); 71 reg |= (MII_SW_OR | LINK_STS); 72 reg &= ~GMII_SPEED_UP_2G; 73 core_writel(priv, reg, offset); 74 75 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 76 reg = core_readl(priv, CORE_IMP_CTL); 77 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 78 reg &= ~(RX_DIS | TX_DIS); 79 core_writel(priv, reg, CORE_IMP_CTL); 80 } else { 81 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 82 reg &= ~(RX_DIS | TX_DIS); 83 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 84 } 85 } 86 87 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 88 { 89 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 90 u32 reg; 91 92 reg = reg_readl(priv, REG_SPHY_CNTRL); 93 if (enable) { 94 reg |= PHY_RESET; 95 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 96 reg_writel(priv, reg, REG_SPHY_CNTRL); 97 udelay(21); 98 reg = reg_readl(priv, REG_SPHY_CNTRL); 99 reg &= ~PHY_RESET; 100 } else { 101 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 102 reg_writel(priv, reg, REG_SPHY_CNTRL); 103 mdelay(1); 104 reg |= CK25_DIS; 105 } 106 reg_writel(priv, reg, REG_SPHY_CNTRL); 107 108 /* Use PHY-driven LED signaling */ 109 if (!enable) { 110 reg = reg_readl(priv, REG_LED_CNTRL(0)); 111 reg |= SPDLNK_SRC_SEL; 112 reg_writel(priv, reg, REG_LED_CNTRL(0)); 113 } 114 } 115 116 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 117 int port) 118 { 119 unsigned int off; 120 121 switch (port) { 122 case 7: 123 off = P7_IRQ_OFF; 124 break; 125 case 0: 126 /* Port 0 interrupts are located on the first bank */ 127 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 128 return; 129 default: 130 off = P_IRQ_OFF(port); 131 break; 132 } 133 134 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 135 } 136 137 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 138 int port) 139 { 140 unsigned int off; 141 142 switch (port) { 143 case 7: 144 off = P7_IRQ_OFF; 145 break; 146 case 0: 147 /* Port 0 interrupts are located on the first bank */ 148 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 149 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 150 return; 151 default: 152 off = P_IRQ_OFF(port); 153 break; 154 } 155 156 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 157 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 158 } 159 160 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 161 struct phy_device *phy) 162 { 163 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 164 unsigned int i; 165 u32 reg; 166 167 if (!dsa_is_user_port(ds, port)) 168 return 0; 169 170 /* Clear the memory power down */ 171 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 172 reg &= ~P_TXQ_PSM_VDD(port); 173 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 174 175 /* Enable learning */ 176 reg = core_readl(priv, CORE_DIS_LEARN); 177 reg &= ~BIT(port); 178 core_writel(priv, reg, CORE_DIS_LEARN); 179 180 /* Enable Broadcom tags for that port if requested */ 181 if (priv->brcm_tag_mask & BIT(port)) { 182 b53_brcm_hdr_setup(ds, port); 183 184 /* Disable learning on ASP port */ 185 if (port == 7) { 186 reg = core_readl(priv, CORE_DIS_LEARN); 187 reg |= BIT(port); 188 core_writel(priv, reg, CORE_DIS_LEARN); 189 } 190 } 191 192 /* Configure Traffic Class to QoS mapping, allow each priority to map 193 * to a different queue number 194 */ 195 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 196 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 197 reg |= i << (PRT_TO_QID_SHIFT * i); 198 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 199 200 /* Re-enable the GPHY and re-apply workarounds */ 201 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 202 bcm_sf2_gphy_enable_set(ds, true); 203 if (phy) { 204 /* if phy_stop() has been called before, phy 205 * will be in halted state, and phy_start() 206 * will call resume. 207 * 208 * the resume path does not configure back 209 * autoneg settings, and since we hard reset 210 * the phy manually here, we need to reset the 211 * state machine also. 212 */ 213 phy->state = PHY_READY; 214 phy_init_hw(phy); 215 } 216 } 217 218 /* Enable MoCA port interrupts to get notified */ 219 if (port == priv->moca_port) 220 bcm_sf2_port_intr_enable(priv, port); 221 222 /* Set per-queue pause threshold to 32 */ 223 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 224 225 /* Set ACB threshold to 24 */ 226 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 227 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 228 SF2_NUM_EGRESS_QUEUES + i)); 229 reg &= ~XOFF_THRESHOLD_MASK; 230 reg |= 24; 231 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 232 SF2_NUM_EGRESS_QUEUES + i)); 233 } 234 235 return b53_enable_port(ds, port, phy); 236 } 237 238 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 239 { 240 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 241 u32 reg; 242 243 /* Disable learning while in WoL mode */ 244 if (priv->wol_ports_mask & (1 << port)) { 245 reg = core_readl(priv, CORE_DIS_LEARN); 246 reg |= BIT(port); 247 core_writel(priv, reg, CORE_DIS_LEARN); 248 return; 249 } 250 251 if (port == priv->moca_port) 252 bcm_sf2_port_intr_disable(priv, port); 253 254 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 255 bcm_sf2_gphy_enable_set(ds, false); 256 257 b53_disable_port(ds, port); 258 259 /* Power down the port memory */ 260 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 261 reg |= P_TXQ_PSM_VDD(port); 262 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 263 } 264 265 266 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 267 int regnum, u16 val) 268 { 269 int ret = 0; 270 u32 reg; 271 272 reg = reg_readl(priv, REG_SWITCH_CNTRL); 273 reg |= MDIO_MASTER_SEL; 274 reg_writel(priv, reg, REG_SWITCH_CNTRL); 275 276 /* Page << 8 | offset */ 277 reg = 0x70; 278 reg <<= 2; 279 core_writel(priv, addr, reg); 280 281 /* Page << 8 | offset */ 282 reg = 0x80 << 8 | regnum << 1; 283 reg <<= 2; 284 285 if (op) 286 ret = core_readl(priv, reg); 287 else 288 core_writel(priv, val, reg); 289 290 reg = reg_readl(priv, REG_SWITCH_CNTRL); 291 reg &= ~MDIO_MASTER_SEL; 292 reg_writel(priv, reg, REG_SWITCH_CNTRL); 293 294 return ret & 0xffff; 295 } 296 297 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 298 { 299 struct bcm_sf2_priv *priv = bus->priv; 300 301 /* Intercept reads from Broadcom pseudo-PHY address, else, send 302 * them to our master MDIO bus controller 303 */ 304 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 305 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 306 else 307 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 308 } 309 310 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 311 u16 val) 312 { 313 struct bcm_sf2_priv *priv = bus->priv; 314 315 /* Intercept writes to the Broadcom pseudo-PHY address, else, 316 * send them to our master MDIO bus controller 317 */ 318 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 319 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 320 else 321 return mdiobus_write_nested(priv->master_mii_bus, addr, 322 regnum, val); 323 } 324 325 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 326 { 327 struct dsa_switch *ds = dev_id; 328 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 329 330 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 331 ~priv->irq0_mask; 332 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 333 334 return IRQ_HANDLED; 335 } 336 337 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 338 { 339 struct dsa_switch *ds = dev_id; 340 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 341 342 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 343 ~priv->irq1_mask; 344 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 345 346 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 347 priv->port_sts[7].link = true; 348 dsa_port_phylink_mac_change(ds, 7, true); 349 } 350 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 351 priv->port_sts[7].link = false; 352 dsa_port_phylink_mac_change(ds, 7, false); 353 } 354 355 return IRQ_HANDLED; 356 } 357 358 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 359 { 360 unsigned int timeout = 1000; 361 u32 reg; 362 int ret; 363 364 /* The watchdog reset does not work on 7278, we need to hit the 365 * "external" reset line through the reset controller. 366 */ 367 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) { 368 ret = reset_control_assert(priv->rcdev); 369 if (ret) 370 return ret; 371 372 return reset_control_deassert(priv->rcdev); 373 } 374 375 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 376 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 377 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 378 379 do { 380 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 381 if (!(reg & SOFTWARE_RESET)) 382 break; 383 384 usleep_range(1000, 2000); 385 } while (timeout-- > 0); 386 387 if (timeout == 0) 388 return -ETIMEDOUT; 389 390 return 0; 391 } 392 393 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 394 { 395 intrl2_0_mask_set(priv, 0xffffffff); 396 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 397 intrl2_1_mask_set(priv, 0xffffffff); 398 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 399 } 400 401 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 402 struct device_node *dn) 403 { 404 struct device_node *port; 405 unsigned int port_num; 406 phy_interface_t mode; 407 int err; 408 409 priv->moca_port = -1; 410 411 for_each_available_child_of_node(dn, port) { 412 if (of_property_read_u32(port, "reg", &port_num)) 413 continue; 414 415 /* Internal PHYs get assigned a specific 'phy-mode' property 416 * value: "internal" to help flag them before MDIO probing 417 * has completed, since they might be turned off at that 418 * time 419 */ 420 err = of_get_phy_mode(port, &mode); 421 if (err) 422 continue; 423 424 if (mode == PHY_INTERFACE_MODE_INTERNAL) 425 priv->int_phy_mask |= 1 << port_num; 426 427 if (mode == PHY_INTERFACE_MODE_MOCA) 428 priv->moca_port = port_num; 429 430 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 431 priv->brcm_tag_mask |= 1 << port_num; 432 } 433 } 434 435 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 436 { 437 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 438 struct device_node *dn; 439 static int index; 440 int err; 441 442 /* Find our integrated MDIO bus node */ 443 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 444 priv->master_mii_bus = of_mdio_find_bus(dn); 445 if (!priv->master_mii_bus) 446 return -EPROBE_DEFER; 447 448 get_device(&priv->master_mii_bus->dev); 449 priv->master_mii_dn = dn; 450 451 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 452 if (!priv->slave_mii_bus) 453 return -ENOMEM; 454 455 priv->slave_mii_bus->priv = priv; 456 priv->slave_mii_bus->name = "sf2 slave mii"; 457 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 458 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 459 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 460 index++); 461 priv->slave_mii_bus->dev.of_node = dn; 462 463 /* Include the pseudo-PHY address to divert reads towards our 464 * workaround. This is only required for 7445D0, since 7445E0 465 * disconnects the internal switch pseudo-PHY such that we can use the 466 * regular SWITCH_MDIO master controller instead. 467 * 468 * Here we flag the pseudo PHY as needing special treatment and would 469 * otherwise make all other PHY read/writes go to the master MDIO bus 470 * controller that comes with this switch backed by the "mdio-unimac" 471 * driver. 472 */ 473 if (of_machine_is_compatible("brcm,bcm7445d0")) 474 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 475 else 476 priv->indir_phy_mask = 0; 477 478 ds->phys_mii_mask = priv->indir_phy_mask; 479 ds->slave_mii_bus = priv->slave_mii_bus; 480 priv->slave_mii_bus->parent = ds->dev->parent; 481 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 482 483 err = mdiobus_register(priv->slave_mii_bus); 484 if (err && dn) 485 of_node_put(dn); 486 487 return err; 488 } 489 490 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 491 { 492 mdiobus_unregister(priv->slave_mii_bus); 493 of_node_put(priv->master_mii_dn); 494 } 495 496 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 497 { 498 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 499 500 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 501 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 502 * the REG_PHY_REVISION register layout is. 503 */ 504 505 return priv->hw_params.gphy_rev; 506 } 507 508 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 509 unsigned long *supported, 510 struct phylink_link_state *state) 511 { 512 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 513 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 514 515 if (!phy_interface_mode_is_rgmii(state->interface) && 516 state->interface != PHY_INTERFACE_MODE_MII && 517 state->interface != PHY_INTERFACE_MODE_REVMII && 518 state->interface != PHY_INTERFACE_MODE_GMII && 519 state->interface != PHY_INTERFACE_MODE_INTERNAL && 520 state->interface != PHY_INTERFACE_MODE_MOCA) { 521 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 522 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 523 dev_err(ds->dev, 524 "Unsupported interface: %d for port %d\n", 525 state->interface, port); 526 return; 527 } 528 529 /* Allow all the expected bits */ 530 phylink_set(mask, Autoneg); 531 phylink_set_port_modes(mask); 532 phylink_set(mask, Pause); 533 phylink_set(mask, Asym_Pause); 534 535 /* With the exclusion of MII and Reverse MII, we support Gigabit, 536 * including Half duplex 537 */ 538 if (state->interface != PHY_INTERFACE_MODE_MII && 539 state->interface != PHY_INTERFACE_MODE_REVMII) { 540 phylink_set(mask, 1000baseT_Full); 541 phylink_set(mask, 1000baseT_Half); 542 } 543 544 phylink_set(mask, 10baseT_Half); 545 phylink_set(mask, 10baseT_Full); 546 phylink_set(mask, 100baseT_Half); 547 phylink_set(mask, 100baseT_Full); 548 549 bitmap_and(supported, supported, mask, 550 __ETHTOOL_LINK_MODE_MASK_NBITS); 551 bitmap_and(state->advertising, state->advertising, mask, 552 __ETHTOOL_LINK_MODE_MASK_NBITS); 553 } 554 555 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 556 unsigned int mode, 557 const struct phylink_link_state *state) 558 { 559 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 560 u32 id_mode_dis = 0, port_mode; 561 u32 reg; 562 563 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 564 return; 565 566 switch (state->interface) { 567 case PHY_INTERFACE_MODE_RGMII: 568 id_mode_dis = 1; 569 fallthrough; 570 case PHY_INTERFACE_MODE_RGMII_TXID: 571 port_mode = EXT_GPHY; 572 break; 573 case PHY_INTERFACE_MODE_MII: 574 port_mode = EXT_EPHY; 575 break; 576 case PHY_INTERFACE_MODE_REVMII: 577 port_mode = EXT_REVMII; 578 break; 579 default: 580 /* Nothing required for all other PHYs: internal and MoCA */ 581 return; 582 } 583 584 /* Clear id_mode_dis bit, and the existing port mode, let 585 * RGMII_MODE_EN bet set by mac_link_{up,down} 586 */ 587 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 588 reg &= ~ID_MODE_DIS; 589 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 590 591 reg |= port_mode; 592 if (id_mode_dis) 593 reg |= ID_MODE_DIS; 594 595 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 596 } 597 598 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 599 phy_interface_t interface, bool link) 600 { 601 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 602 u32 reg; 603 604 if (!phy_interface_mode_is_rgmii(interface) && 605 interface != PHY_INTERFACE_MODE_MII && 606 interface != PHY_INTERFACE_MODE_REVMII) 607 return; 608 609 /* If the link is down, just disable the interface to conserve power */ 610 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 611 if (link) 612 reg |= RGMII_MODE_EN; 613 else 614 reg &= ~RGMII_MODE_EN; 615 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 616 } 617 618 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 619 unsigned int mode, 620 phy_interface_t interface) 621 { 622 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 623 u32 reg, offset; 624 625 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 626 if (priv->type == BCM7445_DEVICE_ID) 627 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 628 else 629 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 630 631 reg = core_readl(priv, offset); 632 reg &= ~LINK_STS; 633 core_writel(priv, reg, offset); 634 } 635 636 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 637 } 638 639 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 640 unsigned int mode, 641 phy_interface_t interface, 642 struct phy_device *phydev, 643 int speed, int duplex, 644 bool tx_pause, bool rx_pause) 645 { 646 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 647 struct ethtool_eee *p = &priv->dev->ports[port].eee; 648 u32 reg, offset; 649 650 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 651 652 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 653 if (priv->type == BCM7445_DEVICE_ID) 654 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 655 else 656 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 657 658 if (interface == PHY_INTERFACE_MODE_RGMII || 659 interface == PHY_INTERFACE_MODE_RGMII_TXID || 660 interface == PHY_INTERFACE_MODE_MII || 661 interface == PHY_INTERFACE_MODE_REVMII) { 662 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 663 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 664 665 if (tx_pause) 666 reg |= TX_PAUSE_EN; 667 if (rx_pause) 668 reg |= RX_PAUSE_EN; 669 670 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 671 } 672 673 reg = SW_OVERRIDE | LINK_STS; 674 switch (speed) { 675 case SPEED_1000: 676 reg |= SPDSTS_1000 << SPEED_SHIFT; 677 break; 678 case SPEED_100: 679 reg |= SPDSTS_100 << SPEED_SHIFT; 680 break; 681 } 682 683 if (duplex == DUPLEX_FULL) 684 reg |= DUPLX_MODE; 685 686 core_writel(priv, reg, offset); 687 } 688 689 if (mode == MLO_AN_PHY && phydev) 690 p->eee_enabled = b53_eee_init(ds, port, phydev); 691 } 692 693 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 694 struct phylink_link_state *status) 695 { 696 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 697 698 status->link = false; 699 700 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 701 * which means that we need to force the link at the port override 702 * level to get the data to flow. We do use what the interrupt handler 703 * did determine before. 704 * 705 * For the other ports, we just force the link status, since this is 706 * a fixed PHY device. 707 */ 708 if (port == priv->moca_port) { 709 status->link = priv->port_sts[port].link; 710 /* For MoCA interfaces, also force a link down notification 711 * since some version of the user-space daemon (mocad) use 712 * cmd->autoneg to force the link, which messes up the PHY 713 * state machine and make it go in PHY_FORCING state instead. 714 */ 715 if (!status->link) 716 netif_carrier_off(dsa_to_port(ds, port)->slave); 717 status->duplex = DUPLEX_FULL; 718 } else { 719 status->link = true; 720 } 721 } 722 723 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 724 { 725 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 726 u32 reg; 727 728 /* Enable ACB globally */ 729 reg = acb_readl(priv, ACB_CONTROL); 730 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 731 acb_writel(priv, reg, ACB_CONTROL); 732 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 733 reg |= ACB_EN | ACB_ALGORITHM; 734 acb_writel(priv, reg, ACB_CONTROL); 735 } 736 737 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 738 { 739 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 740 unsigned int port; 741 742 bcm_sf2_intr_disable(priv); 743 744 /* Disable all ports physically present including the IMP 745 * port, the other ones have already been disabled during 746 * bcm_sf2_sw_setup 747 */ 748 for (port = 0; port < ds->num_ports; port++) { 749 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 750 bcm_sf2_port_disable(ds, port); 751 } 752 753 return 0; 754 } 755 756 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 757 { 758 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 759 int ret; 760 761 ret = bcm_sf2_sw_rst(priv); 762 if (ret) { 763 pr_err("%s: failed to software reset switch\n", __func__); 764 return ret; 765 } 766 767 ret = bcm_sf2_cfp_resume(ds); 768 if (ret) 769 return ret; 770 771 if (priv->hw_params.num_gphy == 1) 772 bcm_sf2_gphy_enable_set(ds, true); 773 774 ds->ops->setup(ds); 775 776 return 0; 777 } 778 779 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 780 struct ethtool_wolinfo *wol) 781 { 782 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 783 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 784 struct ethtool_wolinfo pwol = { }; 785 786 /* Get the parent device WoL settings */ 787 if (p->ethtool_ops->get_wol) 788 p->ethtool_ops->get_wol(p, &pwol); 789 790 /* Advertise the parent device supported settings */ 791 wol->supported = pwol.supported; 792 memset(&wol->sopass, 0, sizeof(wol->sopass)); 793 794 if (pwol.wolopts & WAKE_MAGICSECURE) 795 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 796 797 if (priv->wol_ports_mask & (1 << port)) 798 wol->wolopts = pwol.wolopts; 799 else 800 wol->wolopts = 0; 801 } 802 803 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 804 struct ethtool_wolinfo *wol) 805 { 806 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 807 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 808 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 809 struct ethtool_wolinfo pwol = { }; 810 811 if (p->ethtool_ops->get_wol) 812 p->ethtool_ops->get_wol(p, &pwol); 813 if (wol->wolopts & ~pwol.supported) 814 return -EINVAL; 815 816 if (wol->wolopts) 817 priv->wol_ports_mask |= (1 << port); 818 else 819 priv->wol_ports_mask &= ~(1 << port); 820 821 /* If we have at least one port enabled, make sure the CPU port 822 * is also enabled. If the CPU port is the last one enabled, we disable 823 * it since this configuration does not make sense. 824 */ 825 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 826 priv->wol_ports_mask |= (1 << cpu_port); 827 else 828 priv->wol_ports_mask &= ~(1 << cpu_port); 829 830 return p->ethtool_ops->set_wol(p, wol); 831 } 832 833 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 834 { 835 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 836 unsigned int port; 837 838 /* Enable all valid ports and disable those unused */ 839 for (port = 0; port < priv->hw_params.num_ports; port++) { 840 /* IMP port receives special treatment */ 841 if (dsa_is_user_port(ds, port)) 842 bcm_sf2_port_setup(ds, port, NULL); 843 else if (dsa_is_cpu_port(ds, port)) 844 bcm_sf2_imp_setup(ds, port); 845 else 846 bcm_sf2_port_disable(ds, port); 847 } 848 849 b53_configure_vlan(ds); 850 bcm_sf2_enable_acb(ds); 851 852 return 0; 853 } 854 855 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 856 * register basis so we need to translate that into an address that the 857 * bus-glue understands. 858 */ 859 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 860 861 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 862 u8 *val) 863 { 864 struct bcm_sf2_priv *priv = dev->priv; 865 866 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 867 868 return 0; 869 } 870 871 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 872 u16 *val) 873 { 874 struct bcm_sf2_priv *priv = dev->priv; 875 876 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 877 878 return 0; 879 } 880 881 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 882 u32 *val) 883 { 884 struct bcm_sf2_priv *priv = dev->priv; 885 886 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 887 888 return 0; 889 } 890 891 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 892 u64 *val) 893 { 894 struct bcm_sf2_priv *priv = dev->priv; 895 896 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 897 898 return 0; 899 } 900 901 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 902 u8 value) 903 { 904 struct bcm_sf2_priv *priv = dev->priv; 905 906 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 907 908 return 0; 909 } 910 911 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 912 u16 value) 913 { 914 struct bcm_sf2_priv *priv = dev->priv; 915 916 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 917 918 return 0; 919 } 920 921 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 922 u32 value) 923 { 924 struct bcm_sf2_priv *priv = dev->priv; 925 926 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 927 928 return 0; 929 } 930 931 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 932 u64 value) 933 { 934 struct bcm_sf2_priv *priv = dev->priv; 935 936 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 937 938 return 0; 939 } 940 941 static const struct b53_io_ops bcm_sf2_io_ops = { 942 .read8 = bcm_sf2_core_read8, 943 .read16 = bcm_sf2_core_read16, 944 .read32 = bcm_sf2_core_read32, 945 .read48 = bcm_sf2_core_read64, 946 .read64 = bcm_sf2_core_read64, 947 .write8 = bcm_sf2_core_write8, 948 .write16 = bcm_sf2_core_write16, 949 .write32 = bcm_sf2_core_write32, 950 .write48 = bcm_sf2_core_write64, 951 .write64 = bcm_sf2_core_write64, 952 }; 953 954 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 955 u32 stringset, uint8_t *data) 956 { 957 int cnt = b53_get_sset_count(ds, port, stringset); 958 959 b53_get_strings(ds, port, stringset, data); 960 bcm_sf2_cfp_get_strings(ds, port, stringset, 961 data + cnt * ETH_GSTRING_LEN); 962 } 963 964 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 965 uint64_t *data) 966 { 967 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 968 969 b53_get_ethtool_stats(ds, port, data); 970 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 971 } 972 973 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 974 int sset) 975 { 976 int cnt = b53_get_sset_count(ds, port, sset); 977 978 if (cnt < 0) 979 return cnt; 980 981 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 982 983 return cnt; 984 } 985 986 static const struct dsa_switch_ops bcm_sf2_ops = { 987 .get_tag_protocol = b53_get_tag_protocol, 988 .setup = bcm_sf2_sw_setup, 989 .get_strings = bcm_sf2_sw_get_strings, 990 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 991 .get_sset_count = bcm_sf2_sw_get_sset_count, 992 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 993 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 994 .phylink_validate = bcm_sf2_sw_validate, 995 .phylink_mac_config = bcm_sf2_sw_mac_config, 996 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 997 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 998 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 999 .suspend = bcm_sf2_sw_suspend, 1000 .resume = bcm_sf2_sw_resume, 1001 .get_wol = bcm_sf2_sw_get_wol, 1002 .set_wol = bcm_sf2_sw_set_wol, 1003 .port_enable = bcm_sf2_port_setup, 1004 .port_disable = bcm_sf2_port_disable, 1005 .get_mac_eee = b53_get_mac_eee, 1006 .set_mac_eee = b53_set_mac_eee, 1007 .port_bridge_join = b53_br_join, 1008 .port_bridge_leave = b53_br_leave, 1009 .port_stp_state_set = b53_br_set_stp_state, 1010 .port_fast_age = b53_br_fast_age, 1011 .port_vlan_filtering = b53_vlan_filtering, 1012 .port_vlan_prepare = b53_vlan_prepare, 1013 .port_vlan_add = b53_vlan_add, 1014 .port_vlan_del = b53_vlan_del, 1015 .port_fdb_dump = b53_fdb_dump, 1016 .port_fdb_add = b53_fdb_add, 1017 .port_fdb_del = b53_fdb_del, 1018 .get_rxnfc = bcm_sf2_get_rxnfc, 1019 .set_rxnfc = bcm_sf2_set_rxnfc, 1020 .port_mirror_add = b53_mirror_add, 1021 .port_mirror_del = b53_mirror_del, 1022 .port_mdb_prepare = b53_mdb_prepare, 1023 .port_mdb_add = b53_mdb_add, 1024 .port_mdb_del = b53_mdb_del, 1025 }; 1026 1027 struct bcm_sf2_of_data { 1028 u32 type; 1029 const u16 *reg_offsets; 1030 unsigned int core_reg_align; 1031 unsigned int num_cfp_rules; 1032 }; 1033 1034 /* Register offsets for the SWITCH_REG_* block */ 1035 static const u16 bcm_sf2_7445_reg_offsets[] = { 1036 [REG_SWITCH_CNTRL] = 0x00, 1037 [REG_SWITCH_STATUS] = 0x04, 1038 [REG_DIR_DATA_WRITE] = 0x08, 1039 [REG_DIR_DATA_READ] = 0x0C, 1040 [REG_SWITCH_REVISION] = 0x18, 1041 [REG_PHY_REVISION] = 0x1C, 1042 [REG_SPHY_CNTRL] = 0x2C, 1043 [REG_RGMII_0_CNTRL] = 0x34, 1044 [REG_RGMII_1_CNTRL] = 0x40, 1045 [REG_RGMII_2_CNTRL] = 0x4c, 1046 [REG_LED_0_CNTRL] = 0x90, 1047 [REG_LED_1_CNTRL] = 0x94, 1048 [REG_LED_2_CNTRL] = 0x98, 1049 }; 1050 1051 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1052 .type = BCM7445_DEVICE_ID, 1053 .core_reg_align = 0, 1054 .reg_offsets = bcm_sf2_7445_reg_offsets, 1055 .num_cfp_rules = 256, 1056 }; 1057 1058 static const u16 bcm_sf2_7278_reg_offsets[] = { 1059 [REG_SWITCH_CNTRL] = 0x00, 1060 [REG_SWITCH_STATUS] = 0x04, 1061 [REG_DIR_DATA_WRITE] = 0x08, 1062 [REG_DIR_DATA_READ] = 0x0c, 1063 [REG_SWITCH_REVISION] = 0x10, 1064 [REG_PHY_REVISION] = 0x14, 1065 [REG_SPHY_CNTRL] = 0x24, 1066 [REG_RGMII_0_CNTRL] = 0xe0, 1067 [REG_RGMII_1_CNTRL] = 0xec, 1068 [REG_RGMII_2_CNTRL] = 0xf8, 1069 [REG_LED_0_CNTRL] = 0x40, 1070 [REG_LED_1_CNTRL] = 0x4c, 1071 [REG_LED_2_CNTRL] = 0x58, 1072 }; 1073 1074 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1075 .type = BCM7278_DEVICE_ID, 1076 .core_reg_align = 1, 1077 .reg_offsets = bcm_sf2_7278_reg_offsets, 1078 .num_cfp_rules = 128, 1079 }; 1080 1081 static const struct of_device_id bcm_sf2_of_match[] = { 1082 { .compatible = "brcm,bcm7445-switch-v4.0", 1083 .data = &bcm_sf2_7445_data 1084 }, 1085 { .compatible = "brcm,bcm7278-switch-v4.0", 1086 .data = &bcm_sf2_7278_data 1087 }, 1088 { .compatible = "brcm,bcm7278-switch-v4.8", 1089 .data = &bcm_sf2_7278_data 1090 }, 1091 { /* sentinel */ }, 1092 }; 1093 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1094 1095 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1096 { 1097 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1098 struct device_node *dn = pdev->dev.of_node; 1099 const struct of_device_id *of_id = NULL; 1100 const struct bcm_sf2_of_data *data; 1101 struct b53_platform_data *pdata; 1102 struct dsa_switch_ops *ops; 1103 struct device_node *ports; 1104 struct bcm_sf2_priv *priv; 1105 struct b53_device *dev; 1106 struct dsa_switch *ds; 1107 void __iomem **base; 1108 unsigned int i; 1109 u32 reg, rev; 1110 int ret; 1111 1112 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1113 if (!priv) 1114 return -ENOMEM; 1115 1116 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1117 if (!ops) 1118 return -ENOMEM; 1119 1120 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1121 if (!dev) 1122 return -ENOMEM; 1123 1124 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1125 if (!pdata) 1126 return -ENOMEM; 1127 1128 of_id = of_match_node(bcm_sf2_of_match, dn); 1129 if (!of_id || !of_id->data) 1130 return -EINVAL; 1131 1132 data = of_id->data; 1133 1134 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1135 priv->type = data->type; 1136 priv->reg_offsets = data->reg_offsets; 1137 priv->core_reg_align = data->core_reg_align; 1138 priv->num_cfp_rules = data->num_cfp_rules; 1139 1140 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1141 "switch"); 1142 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER) 1143 return PTR_ERR(priv->rcdev); 1144 1145 /* Auto-detection using standard registers will not work, so 1146 * provide an indication of what kind of device we are for 1147 * b53_common to work with 1148 */ 1149 pdata->chip_id = priv->type; 1150 dev->pdata = pdata; 1151 1152 priv->dev = dev; 1153 ds = dev->ds; 1154 ds->ops = &bcm_sf2_ops; 1155 1156 /* Advertise the 8 egress queues */ 1157 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1158 1159 dev_set_drvdata(&pdev->dev, priv); 1160 1161 spin_lock_init(&priv->indir_lock); 1162 mutex_init(&priv->cfp.lock); 1163 INIT_LIST_HEAD(&priv->cfp.rules_list); 1164 1165 /* CFP rule #0 cannot be used for specific classifications, flag it as 1166 * permanently used 1167 */ 1168 set_bit(0, priv->cfp.used); 1169 set_bit(0, priv->cfp.unique); 1170 1171 /* Balance of_node_put() done by of_find_node_by_name() */ 1172 of_node_get(dn); 1173 ports = of_find_node_by_name(dn, "ports"); 1174 if (ports) { 1175 bcm_sf2_identify_ports(priv, ports); 1176 of_node_put(ports); 1177 } 1178 1179 priv->irq0 = irq_of_parse_and_map(dn, 0); 1180 priv->irq1 = irq_of_parse_and_map(dn, 1); 1181 1182 base = &priv->core; 1183 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1184 *base = devm_platform_ioremap_resource(pdev, i); 1185 if (IS_ERR(*base)) { 1186 pr_err("unable to find register: %s\n", reg_names[i]); 1187 return PTR_ERR(*base); 1188 } 1189 base++; 1190 } 1191 1192 ret = bcm_sf2_sw_rst(priv); 1193 if (ret) { 1194 pr_err("unable to software reset switch: %d\n", ret); 1195 return ret; 1196 } 1197 1198 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1199 1200 ret = bcm_sf2_mdio_register(ds); 1201 if (ret) { 1202 pr_err("failed to register MDIO bus\n"); 1203 return ret; 1204 } 1205 1206 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1207 1208 ret = bcm_sf2_cfp_rst(priv); 1209 if (ret) { 1210 pr_err("failed to reset CFP\n"); 1211 goto out_mdio; 1212 } 1213 1214 /* Disable all interrupts and request them */ 1215 bcm_sf2_intr_disable(priv); 1216 1217 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1218 "switch_0", ds); 1219 if (ret < 0) { 1220 pr_err("failed to request switch_0 IRQ\n"); 1221 goto out_mdio; 1222 } 1223 1224 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1225 "switch_1", ds); 1226 if (ret < 0) { 1227 pr_err("failed to request switch_1 IRQ\n"); 1228 goto out_mdio; 1229 } 1230 1231 /* Reset the MIB counters */ 1232 reg = core_readl(priv, CORE_GMNCFGCFG); 1233 reg |= RST_MIB_CNT; 1234 core_writel(priv, reg, CORE_GMNCFGCFG); 1235 reg &= ~RST_MIB_CNT; 1236 core_writel(priv, reg, CORE_GMNCFGCFG); 1237 1238 /* Get the maximum number of ports for this switch */ 1239 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1240 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1241 priv->hw_params.num_ports = DSA_MAX_PORTS; 1242 1243 /* Assume a single GPHY setup if we can't read that property */ 1244 if (of_property_read_u32(dn, "brcm,num-gphy", 1245 &priv->hw_params.num_gphy)) 1246 priv->hw_params.num_gphy = 1; 1247 1248 rev = reg_readl(priv, REG_SWITCH_REVISION); 1249 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1250 SWITCH_TOP_REV_MASK; 1251 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1252 1253 rev = reg_readl(priv, REG_PHY_REVISION); 1254 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1255 1256 ret = b53_switch_register(dev); 1257 if (ret) 1258 goto out_mdio; 1259 1260 dev_info(&pdev->dev, 1261 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1262 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1263 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1264 priv->irq0, priv->irq1); 1265 1266 return 0; 1267 1268 out_mdio: 1269 bcm_sf2_mdio_unregister(priv); 1270 return ret; 1271 } 1272 1273 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1274 { 1275 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1276 1277 priv->wol_ports_mask = 0; 1278 /* Disable interrupts */ 1279 bcm_sf2_intr_disable(priv); 1280 dsa_unregister_switch(priv->dev->ds); 1281 bcm_sf2_cfp_exit(priv->dev->ds); 1282 bcm_sf2_mdio_unregister(priv); 1283 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) 1284 reset_control_assert(priv->rcdev); 1285 1286 return 0; 1287 } 1288 1289 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1290 { 1291 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1292 1293 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1294 * successful MDIO bus scan to occur. If we did turn off the GPHY 1295 * before (e.g: port_disable), this will also power it back on. 1296 * 1297 * Do not rely on kexec_in_progress, just power the PHY on. 1298 */ 1299 if (priv->hw_params.num_gphy == 1) 1300 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1301 } 1302 1303 #ifdef CONFIG_PM_SLEEP 1304 static int bcm_sf2_suspend(struct device *dev) 1305 { 1306 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1307 1308 return dsa_switch_suspend(priv->dev->ds); 1309 } 1310 1311 static int bcm_sf2_resume(struct device *dev) 1312 { 1313 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1314 1315 return dsa_switch_resume(priv->dev->ds); 1316 } 1317 #endif /* CONFIG_PM_SLEEP */ 1318 1319 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1320 bcm_sf2_suspend, bcm_sf2_resume); 1321 1322 1323 static struct platform_driver bcm_sf2_driver = { 1324 .probe = bcm_sf2_sw_probe, 1325 .remove = bcm_sf2_sw_remove, 1326 .shutdown = bcm_sf2_sw_shutdown, 1327 .driver = { 1328 .name = "brcm-sf2", 1329 .of_match_table = bcm_sf2_of_match, 1330 .pm = &bcm_sf2_pm_ops, 1331 }, 1332 }; 1333 module_platform_driver(bcm_sf2_driver); 1334 1335 MODULE_AUTHOR("Broadcom Corporation"); 1336 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1337 MODULE_LICENSE("GPL"); 1338 MODULE_ALIAS("platform:brcm-sf2"); 1339