1 /* 2 * Broadcom Starfighter 2 DSA switch driver 3 * 4 * Copyright (C) 2014, Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/list.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/phylink.h> 20 #include <linux/mii.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_address.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <net/dsa.h> 27 #include <linux/ethtool.h> 28 #include <linux/if_bridge.h> 29 #include <linux/brcmphy.h> 30 #include <linux/etherdevice.h> 31 #include <linux/platform_data/b53.h> 32 33 #include "bcm_sf2.h" 34 #include "bcm_sf2_regs.h" 35 #include "b53/b53_priv.h" 36 #include "b53/b53_regs.h" 37 38 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 39 { 40 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 41 unsigned int i; 42 u32 reg, offset; 43 44 if (priv->type == BCM7445_DEVICE_ID) 45 offset = CORE_STS_OVERRIDE_IMP; 46 else 47 offset = CORE_STS_OVERRIDE_IMP2; 48 49 /* Enable the port memories */ 50 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 51 reg &= ~P_TXQ_PSM_VDD(port); 52 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 53 54 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 55 reg = core_readl(priv, CORE_IMP_CTL); 56 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 57 reg &= ~(RX_DIS | TX_DIS); 58 core_writel(priv, reg, CORE_IMP_CTL); 59 60 /* Enable forwarding */ 61 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 62 63 /* Enable IMP port in dumb mode */ 64 reg = core_readl(priv, CORE_SWITCH_CTRL); 65 reg |= MII_DUMB_FWDG_EN; 66 core_writel(priv, reg, CORE_SWITCH_CTRL); 67 68 /* Configure Traffic Class to QoS mapping, allow each priority to map 69 * to a different queue number 70 */ 71 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 72 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 73 reg |= i << (PRT_TO_QID_SHIFT * i); 74 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 75 76 b53_brcm_hdr_setup(ds, port); 77 78 /* Force link status for IMP port */ 79 reg = core_readl(priv, offset); 80 reg |= (MII_SW_OR | LINK_STS); 81 core_writel(priv, reg, offset); 82 } 83 84 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 85 { 86 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 87 u32 reg; 88 89 reg = reg_readl(priv, REG_SPHY_CNTRL); 90 if (enable) { 91 reg |= PHY_RESET; 92 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 93 reg_writel(priv, reg, REG_SPHY_CNTRL); 94 udelay(21); 95 reg = reg_readl(priv, REG_SPHY_CNTRL); 96 reg &= ~PHY_RESET; 97 } else { 98 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 99 reg_writel(priv, reg, REG_SPHY_CNTRL); 100 mdelay(1); 101 reg |= CK25_DIS; 102 } 103 reg_writel(priv, reg, REG_SPHY_CNTRL); 104 105 /* Use PHY-driven LED signaling */ 106 if (!enable) { 107 reg = reg_readl(priv, REG_LED_CNTRL(0)); 108 reg |= SPDLNK_SRC_SEL; 109 reg_writel(priv, reg, REG_LED_CNTRL(0)); 110 } 111 } 112 113 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 114 int port) 115 { 116 unsigned int off; 117 118 switch (port) { 119 case 7: 120 off = P7_IRQ_OFF; 121 break; 122 case 0: 123 /* Port 0 interrupts are located on the first bank */ 124 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 125 return; 126 default: 127 off = P_IRQ_OFF(port); 128 break; 129 } 130 131 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 132 } 133 134 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 135 int port) 136 { 137 unsigned int off; 138 139 switch (port) { 140 case 7: 141 off = P7_IRQ_OFF; 142 break; 143 case 0: 144 /* Port 0 interrupts are located on the first bank */ 145 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 146 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 147 return; 148 default: 149 off = P_IRQ_OFF(port); 150 break; 151 } 152 153 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 154 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 155 } 156 157 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 158 struct phy_device *phy) 159 { 160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 161 unsigned int i; 162 u32 reg; 163 164 /* Clear the memory power down */ 165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 166 reg &= ~P_TXQ_PSM_VDD(port); 167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 168 169 /* Enable learning */ 170 reg = core_readl(priv, CORE_DIS_LEARN); 171 reg &= ~BIT(port); 172 core_writel(priv, reg, CORE_DIS_LEARN); 173 174 /* Enable Broadcom tags for that port if requested */ 175 if (priv->brcm_tag_mask & BIT(port)) 176 b53_brcm_hdr_setup(ds, port); 177 178 /* Configure Traffic Class to QoS mapping, allow each priority to map 179 * to a different queue number 180 */ 181 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 182 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 183 reg |= i << (PRT_TO_QID_SHIFT * i); 184 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 185 186 /* Re-enable the GPHY and re-apply workarounds */ 187 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 188 bcm_sf2_gphy_enable_set(ds, true); 189 if (phy) { 190 /* if phy_stop() has been called before, phy 191 * will be in halted state, and phy_start() 192 * will call resume. 193 * 194 * the resume path does not configure back 195 * autoneg settings, and since we hard reset 196 * the phy manually here, we need to reset the 197 * state machine also. 198 */ 199 phy->state = PHY_READY; 200 phy_init_hw(phy); 201 } 202 } 203 204 /* Enable MoCA port interrupts to get notified */ 205 if (port == priv->moca_port) 206 bcm_sf2_port_intr_enable(priv, port); 207 208 /* Set per-queue pause threshold to 32 */ 209 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 210 211 /* Set ACB threshold to 24 */ 212 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 213 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 214 SF2_NUM_EGRESS_QUEUES + i)); 215 reg &= ~XOFF_THRESHOLD_MASK; 216 reg |= 24; 217 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 218 SF2_NUM_EGRESS_QUEUES + i)); 219 } 220 221 return b53_enable_port(ds, port, phy); 222 } 223 224 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 225 { 226 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 227 u32 reg; 228 229 /* Disable learning while in WoL mode */ 230 if (priv->wol_ports_mask & (1 << port)) { 231 reg = core_readl(priv, CORE_DIS_LEARN); 232 reg |= BIT(port); 233 core_writel(priv, reg, CORE_DIS_LEARN); 234 return; 235 } 236 237 if (port == priv->moca_port) 238 bcm_sf2_port_intr_disable(priv, port); 239 240 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 241 bcm_sf2_gphy_enable_set(ds, false); 242 243 b53_disable_port(ds, port); 244 245 /* Power down the port memory */ 246 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 247 reg |= P_TXQ_PSM_VDD(port); 248 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 249 } 250 251 252 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 253 int regnum, u16 val) 254 { 255 int ret = 0; 256 u32 reg; 257 258 reg = reg_readl(priv, REG_SWITCH_CNTRL); 259 reg |= MDIO_MASTER_SEL; 260 reg_writel(priv, reg, REG_SWITCH_CNTRL); 261 262 /* Page << 8 | offset */ 263 reg = 0x70; 264 reg <<= 2; 265 core_writel(priv, addr, reg); 266 267 /* Page << 8 | offset */ 268 reg = 0x80 << 8 | regnum << 1; 269 reg <<= 2; 270 271 if (op) 272 ret = core_readl(priv, reg); 273 else 274 core_writel(priv, val, reg); 275 276 reg = reg_readl(priv, REG_SWITCH_CNTRL); 277 reg &= ~MDIO_MASTER_SEL; 278 reg_writel(priv, reg, REG_SWITCH_CNTRL); 279 280 return ret & 0xffff; 281 } 282 283 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 284 { 285 struct bcm_sf2_priv *priv = bus->priv; 286 287 /* Intercept reads from Broadcom pseudo-PHY address, else, send 288 * them to our master MDIO bus controller 289 */ 290 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 291 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 292 else 293 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 294 } 295 296 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 297 u16 val) 298 { 299 struct bcm_sf2_priv *priv = bus->priv; 300 301 /* Intercept writes to the Broadcom pseudo-PHY address, else, 302 * send them to our master MDIO bus controller 303 */ 304 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 305 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 306 else 307 return mdiobus_write_nested(priv->master_mii_bus, addr, 308 regnum, val); 309 } 310 311 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 312 { 313 struct dsa_switch *ds = dev_id; 314 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 315 316 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 317 ~priv->irq0_mask; 318 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 319 320 return IRQ_HANDLED; 321 } 322 323 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 324 { 325 struct dsa_switch *ds = dev_id; 326 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 327 328 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 329 ~priv->irq1_mask; 330 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 331 332 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 333 priv->port_sts[7].link = true; 334 dsa_port_phylink_mac_change(ds, 7, true); 335 } 336 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 337 priv->port_sts[7].link = false; 338 dsa_port_phylink_mac_change(ds, 7, false); 339 } 340 341 return IRQ_HANDLED; 342 } 343 344 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 345 { 346 unsigned int timeout = 1000; 347 u32 reg; 348 349 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 350 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 351 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 352 353 do { 354 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 355 if (!(reg & SOFTWARE_RESET)) 356 break; 357 358 usleep_range(1000, 2000); 359 } while (timeout-- > 0); 360 361 if (timeout == 0) 362 return -ETIMEDOUT; 363 364 return 0; 365 } 366 367 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 368 { 369 intrl2_0_mask_set(priv, 0xffffffff); 370 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 371 intrl2_1_mask_set(priv, 0xffffffff); 372 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 373 } 374 375 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 376 struct device_node *dn) 377 { 378 struct device_node *port; 379 int mode; 380 unsigned int port_num; 381 382 priv->moca_port = -1; 383 384 for_each_available_child_of_node(dn, port) { 385 if (of_property_read_u32(port, "reg", &port_num)) 386 continue; 387 388 /* Internal PHYs get assigned a specific 'phy-mode' property 389 * value: "internal" to help flag them before MDIO probing 390 * has completed, since they might be turned off at that 391 * time 392 */ 393 mode = of_get_phy_mode(port); 394 if (mode < 0) 395 continue; 396 397 if (mode == PHY_INTERFACE_MODE_INTERNAL) 398 priv->int_phy_mask |= 1 << port_num; 399 400 if (mode == PHY_INTERFACE_MODE_MOCA) 401 priv->moca_port = port_num; 402 403 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 404 priv->brcm_tag_mask |= 1 << port_num; 405 } 406 } 407 408 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 409 { 410 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 411 struct device_node *dn; 412 static int index; 413 int err; 414 415 /* Find our integrated MDIO bus node */ 416 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 417 priv->master_mii_bus = of_mdio_find_bus(dn); 418 if (!priv->master_mii_bus) 419 return -EPROBE_DEFER; 420 421 get_device(&priv->master_mii_bus->dev); 422 priv->master_mii_dn = dn; 423 424 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 425 if (!priv->slave_mii_bus) 426 return -ENOMEM; 427 428 priv->slave_mii_bus->priv = priv; 429 priv->slave_mii_bus->name = "sf2 slave mii"; 430 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 431 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 432 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 433 index++); 434 priv->slave_mii_bus->dev.of_node = dn; 435 436 /* Include the pseudo-PHY address to divert reads towards our 437 * workaround. This is only required for 7445D0, since 7445E0 438 * disconnects the internal switch pseudo-PHY such that we can use the 439 * regular SWITCH_MDIO master controller instead. 440 * 441 * Here we flag the pseudo PHY as needing special treatment and would 442 * otherwise make all other PHY read/writes go to the master MDIO bus 443 * controller that comes with this switch backed by the "mdio-unimac" 444 * driver. 445 */ 446 if (of_machine_is_compatible("brcm,bcm7445d0")) 447 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 448 else 449 priv->indir_phy_mask = 0; 450 451 ds->phys_mii_mask = priv->indir_phy_mask; 452 ds->slave_mii_bus = priv->slave_mii_bus; 453 priv->slave_mii_bus->parent = ds->dev->parent; 454 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 455 456 err = of_mdiobus_register(priv->slave_mii_bus, dn); 457 if (err && dn) 458 of_node_put(dn); 459 460 return err; 461 } 462 463 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 464 { 465 mdiobus_unregister(priv->slave_mii_bus); 466 of_node_put(priv->master_mii_dn); 467 } 468 469 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 470 { 471 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 472 473 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 474 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 475 * the REG_PHY_REVISION register layout is. 476 */ 477 478 return priv->hw_params.gphy_rev; 479 } 480 481 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 482 unsigned long *supported, 483 struct phylink_link_state *state) 484 { 485 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 486 487 if (!phy_interface_mode_is_rgmii(state->interface) && 488 state->interface != PHY_INTERFACE_MODE_MII && 489 state->interface != PHY_INTERFACE_MODE_REVMII && 490 state->interface != PHY_INTERFACE_MODE_GMII && 491 state->interface != PHY_INTERFACE_MODE_INTERNAL && 492 state->interface != PHY_INTERFACE_MODE_MOCA) { 493 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 494 dev_err(ds->dev, 495 "Unsupported interface: %d\n", state->interface); 496 return; 497 } 498 499 /* Allow all the expected bits */ 500 phylink_set(mask, Autoneg); 501 phylink_set_port_modes(mask); 502 phylink_set(mask, Pause); 503 phylink_set(mask, Asym_Pause); 504 505 /* With the exclusion of MII and Reverse MII, we support Gigabit, 506 * including Half duplex 507 */ 508 if (state->interface != PHY_INTERFACE_MODE_MII && 509 state->interface != PHY_INTERFACE_MODE_REVMII) { 510 phylink_set(mask, 1000baseT_Full); 511 phylink_set(mask, 1000baseT_Half); 512 } 513 514 phylink_set(mask, 10baseT_Half); 515 phylink_set(mask, 10baseT_Full); 516 phylink_set(mask, 100baseT_Half); 517 phylink_set(mask, 100baseT_Full); 518 519 bitmap_and(supported, supported, mask, 520 __ETHTOOL_LINK_MODE_MASK_NBITS); 521 bitmap_and(state->advertising, state->advertising, mask, 522 __ETHTOOL_LINK_MODE_MASK_NBITS); 523 } 524 525 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 526 unsigned int mode, 527 const struct phylink_link_state *state) 528 { 529 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 530 u32 id_mode_dis = 0, port_mode; 531 u32 reg, offset; 532 533 if (priv->type == BCM7445_DEVICE_ID) 534 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 535 else 536 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 537 538 switch (state->interface) { 539 case PHY_INTERFACE_MODE_RGMII: 540 id_mode_dis = 1; 541 /* fallthrough */ 542 case PHY_INTERFACE_MODE_RGMII_TXID: 543 port_mode = EXT_GPHY; 544 break; 545 case PHY_INTERFACE_MODE_MII: 546 port_mode = EXT_EPHY; 547 break; 548 case PHY_INTERFACE_MODE_REVMII: 549 port_mode = EXT_REVMII; 550 break; 551 default: 552 /* all other PHYs: internal and MoCA */ 553 goto force_link; 554 } 555 556 /* Clear id_mode_dis bit, and the existing port mode, let 557 * RGMII_MODE_EN bet set by mac_link_{up,down} 558 */ 559 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 560 reg &= ~ID_MODE_DIS; 561 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 562 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 563 564 reg |= port_mode; 565 if (id_mode_dis) 566 reg |= ID_MODE_DIS; 567 568 if (state->pause & MLO_PAUSE_TXRX_MASK) { 569 if (state->pause & MLO_PAUSE_TX) 570 reg |= TX_PAUSE_EN; 571 reg |= RX_PAUSE_EN; 572 } 573 574 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 575 576 force_link: 577 /* Force link settings detected from the PHY */ 578 reg = SW_OVERRIDE; 579 switch (state->speed) { 580 case SPEED_1000: 581 reg |= SPDSTS_1000 << SPEED_SHIFT; 582 break; 583 case SPEED_100: 584 reg |= SPDSTS_100 << SPEED_SHIFT; 585 break; 586 } 587 588 if (state->link) 589 reg |= LINK_STS; 590 if (state->duplex == DUPLEX_FULL) 591 reg |= DUPLX_MODE; 592 593 core_writel(priv, reg, offset); 594 } 595 596 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 597 phy_interface_t interface, bool link) 598 { 599 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 600 u32 reg; 601 602 if (!phy_interface_mode_is_rgmii(interface) && 603 interface != PHY_INTERFACE_MODE_MII && 604 interface != PHY_INTERFACE_MODE_REVMII) 605 return; 606 607 /* If the link is down, just disable the interface to conserve power */ 608 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 609 if (link) 610 reg |= RGMII_MODE_EN; 611 else 612 reg &= ~RGMII_MODE_EN; 613 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 614 } 615 616 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 617 unsigned int mode, 618 phy_interface_t interface) 619 { 620 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 621 } 622 623 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 624 unsigned int mode, 625 phy_interface_t interface, 626 struct phy_device *phydev) 627 { 628 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 629 struct ethtool_eee *p = &priv->dev->ports[port].eee; 630 631 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 632 633 if (mode == MLO_AN_PHY && phydev) 634 p->eee_enabled = b53_eee_init(ds, port, phydev); 635 } 636 637 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 638 struct phylink_link_state *status) 639 { 640 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 641 642 status->link = false; 643 644 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 645 * which means that we need to force the link at the port override 646 * level to get the data to flow. We do use what the interrupt handler 647 * did determine before. 648 * 649 * For the other ports, we just force the link status, since this is 650 * a fixed PHY device. 651 */ 652 if (port == priv->moca_port) { 653 status->link = priv->port_sts[port].link; 654 /* For MoCA interfaces, also force a link down notification 655 * since some version of the user-space daemon (mocad) use 656 * cmd->autoneg to force the link, which messes up the PHY 657 * state machine and make it go in PHY_FORCING state instead. 658 */ 659 if (!status->link) 660 netif_carrier_off(ds->ports[port].slave); 661 status->duplex = DUPLEX_FULL; 662 } else { 663 status->link = true; 664 } 665 } 666 667 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 668 { 669 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 670 u32 reg; 671 672 /* Enable ACB globally */ 673 reg = acb_readl(priv, ACB_CONTROL); 674 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 675 acb_writel(priv, reg, ACB_CONTROL); 676 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 677 reg |= ACB_EN | ACB_ALGORITHM; 678 acb_writel(priv, reg, ACB_CONTROL); 679 } 680 681 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 682 { 683 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 684 unsigned int port; 685 686 bcm_sf2_intr_disable(priv); 687 688 /* Disable all ports physically present including the IMP 689 * port, the other ones have already been disabled during 690 * bcm_sf2_sw_setup 691 */ 692 for (port = 0; port < ds->num_ports; port++) { 693 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 694 bcm_sf2_port_disable(ds, port); 695 } 696 697 return 0; 698 } 699 700 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 701 { 702 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 703 int ret; 704 705 ret = bcm_sf2_sw_rst(priv); 706 if (ret) { 707 pr_err("%s: failed to software reset switch\n", __func__); 708 return ret; 709 } 710 711 ret = bcm_sf2_cfp_resume(ds); 712 if (ret) 713 return ret; 714 715 if (priv->hw_params.num_gphy == 1) 716 bcm_sf2_gphy_enable_set(ds, true); 717 718 ds->ops->setup(ds); 719 720 return 0; 721 } 722 723 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 724 struct ethtool_wolinfo *wol) 725 { 726 struct net_device *p = ds->ports[port].cpu_dp->master; 727 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 728 struct ethtool_wolinfo pwol = { }; 729 730 /* Get the parent device WoL settings */ 731 if (p->ethtool_ops->get_wol) 732 p->ethtool_ops->get_wol(p, &pwol); 733 734 /* Advertise the parent device supported settings */ 735 wol->supported = pwol.supported; 736 memset(&wol->sopass, 0, sizeof(wol->sopass)); 737 738 if (pwol.wolopts & WAKE_MAGICSECURE) 739 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 740 741 if (priv->wol_ports_mask & (1 << port)) 742 wol->wolopts = pwol.wolopts; 743 else 744 wol->wolopts = 0; 745 } 746 747 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 748 struct ethtool_wolinfo *wol) 749 { 750 struct net_device *p = ds->ports[port].cpu_dp->master; 751 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 752 s8 cpu_port = ds->ports[port].cpu_dp->index; 753 struct ethtool_wolinfo pwol = { }; 754 755 if (p->ethtool_ops->get_wol) 756 p->ethtool_ops->get_wol(p, &pwol); 757 if (wol->wolopts & ~pwol.supported) 758 return -EINVAL; 759 760 if (wol->wolopts) 761 priv->wol_ports_mask |= (1 << port); 762 else 763 priv->wol_ports_mask &= ~(1 << port); 764 765 /* If we have at least one port enabled, make sure the CPU port 766 * is also enabled. If the CPU port is the last one enabled, we disable 767 * it since this configuration does not make sense. 768 */ 769 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 770 priv->wol_ports_mask |= (1 << cpu_port); 771 else 772 priv->wol_ports_mask &= ~(1 << cpu_port); 773 774 return p->ethtool_ops->set_wol(p, wol); 775 } 776 777 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 778 { 779 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 780 unsigned int port; 781 782 /* Enable all valid ports and disable those unused */ 783 for (port = 0; port < priv->hw_params.num_ports; port++) { 784 /* IMP port receives special treatment */ 785 if (dsa_is_user_port(ds, port)) 786 bcm_sf2_port_setup(ds, port, NULL); 787 else if (dsa_is_cpu_port(ds, port)) 788 bcm_sf2_imp_setup(ds, port); 789 else 790 bcm_sf2_port_disable(ds, port); 791 } 792 793 b53_configure_vlan(ds); 794 bcm_sf2_enable_acb(ds); 795 796 return 0; 797 } 798 799 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 800 * register basis so we need to translate that into an address that the 801 * bus-glue understands. 802 */ 803 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 804 805 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 806 u8 *val) 807 { 808 struct bcm_sf2_priv *priv = dev->priv; 809 810 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 811 812 return 0; 813 } 814 815 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 816 u16 *val) 817 { 818 struct bcm_sf2_priv *priv = dev->priv; 819 820 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 821 822 return 0; 823 } 824 825 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 826 u32 *val) 827 { 828 struct bcm_sf2_priv *priv = dev->priv; 829 830 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 831 832 return 0; 833 } 834 835 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 836 u64 *val) 837 { 838 struct bcm_sf2_priv *priv = dev->priv; 839 840 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 841 842 return 0; 843 } 844 845 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 846 u8 value) 847 { 848 struct bcm_sf2_priv *priv = dev->priv; 849 850 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 851 852 return 0; 853 } 854 855 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 856 u16 value) 857 { 858 struct bcm_sf2_priv *priv = dev->priv; 859 860 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 861 862 return 0; 863 } 864 865 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 866 u32 value) 867 { 868 struct bcm_sf2_priv *priv = dev->priv; 869 870 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 871 872 return 0; 873 } 874 875 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 876 u64 value) 877 { 878 struct bcm_sf2_priv *priv = dev->priv; 879 880 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 881 882 return 0; 883 } 884 885 static const struct b53_io_ops bcm_sf2_io_ops = { 886 .read8 = bcm_sf2_core_read8, 887 .read16 = bcm_sf2_core_read16, 888 .read32 = bcm_sf2_core_read32, 889 .read48 = bcm_sf2_core_read64, 890 .read64 = bcm_sf2_core_read64, 891 .write8 = bcm_sf2_core_write8, 892 .write16 = bcm_sf2_core_write16, 893 .write32 = bcm_sf2_core_write32, 894 .write48 = bcm_sf2_core_write64, 895 .write64 = bcm_sf2_core_write64, 896 }; 897 898 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 899 u32 stringset, uint8_t *data) 900 { 901 int cnt = b53_get_sset_count(ds, port, stringset); 902 903 b53_get_strings(ds, port, stringset, data); 904 bcm_sf2_cfp_get_strings(ds, port, stringset, 905 data + cnt * ETH_GSTRING_LEN); 906 } 907 908 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 909 uint64_t *data) 910 { 911 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 912 913 b53_get_ethtool_stats(ds, port, data); 914 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 915 } 916 917 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 918 int sset) 919 { 920 int cnt = b53_get_sset_count(ds, port, sset); 921 922 if (cnt < 0) 923 return cnt; 924 925 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 926 927 return cnt; 928 } 929 930 static const struct dsa_switch_ops bcm_sf2_ops = { 931 .get_tag_protocol = b53_get_tag_protocol, 932 .setup = bcm_sf2_sw_setup, 933 .get_strings = bcm_sf2_sw_get_strings, 934 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 935 .get_sset_count = bcm_sf2_sw_get_sset_count, 936 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 937 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 938 .phylink_validate = bcm_sf2_sw_validate, 939 .phylink_mac_config = bcm_sf2_sw_mac_config, 940 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 941 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 942 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 943 .suspend = bcm_sf2_sw_suspend, 944 .resume = bcm_sf2_sw_resume, 945 .get_wol = bcm_sf2_sw_get_wol, 946 .set_wol = bcm_sf2_sw_set_wol, 947 .port_enable = bcm_sf2_port_setup, 948 .port_disable = bcm_sf2_port_disable, 949 .get_mac_eee = b53_get_mac_eee, 950 .set_mac_eee = b53_set_mac_eee, 951 .port_bridge_join = b53_br_join, 952 .port_bridge_leave = b53_br_leave, 953 .port_stp_state_set = b53_br_set_stp_state, 954 .port_fast_age = b53_br_fast_age, 955 .port_vlan_filtering = b53_vlan_filtering, 956 .port_vlan_prepare = b53_vlan_prepare, 957 .port_vlan_add = b53_vlan_add, 958 .port_vlan_del = b53_vlan_del, 959 .port_fdb_dump = b53_fdb_dump, 960 .port_fdb_add = b53_fdb_add, 961 .port_fdb_del = b53_fdb_del, 962 .get_rxnfc = bcm_sf2_get_rxnfc, 963 .set_rxnfc = bcm_sf2_set_rxnfc, 964 .port_mirror_add = b53_mirror_add, 965 .port_mirror_del = b53_mirror_del, 966 }; 967 968 struct bcm_sf2_of_data { 969 u32 type; 970 const u16 *reg_offsets; 971 unsigned int core_reg_align; 972 unsigned int num_cfp_rules; 973 }; 974 975 /* Register offsets for the SWITCH_REG_* block */ 976 static const u16 bcm_sf2_7445_reg_offsets[] = { 977 [REG_SWITCH_CNTRL] = 0x00, 978 [REG_SWITCH_STATUS] = 0x04, 979 [REG_DIR_DATA_WRITE] = 0x08, 980 [REG_DIR_DATA_READ] = 0x0C, 981 [REG_SWITCH_REVISION] = 0x18, 982 [REG_PHY_REVISION] = 0x1C, 983 [REG_SPHY_CNTRL] = 0x2C, 984 [REG_RGMII_0_CNTRL] = 0x34, 985 [REG_RGMII_1_CNTRL] = 0x40, 986 [REG_RGMII_2_CNTRL] = 0x4c, 987 [REG_LED_0_CNTRL] = 0x90, 988 [REG_LED_1_CNTRL] = 0x94, 989 [REG_LED_2_CNTRL] = 0x98, 990 }; 991 992 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 993 .type = BCM7445_DEVICE_ID, 994 .core_reg_align = 0, 995 .reg_offsets = bcm_sf2_7445_reg_offsets, 996 .num_cfp_rules = 256, 997 }; 998 999 static const u16 bcm_sf2_7278_reg_offsets[] = { 1000 [REG_SWITCH_CNTRL] = 0x00, 1001 [REG_SWITCH_STATUS] = 0x04, 1002 [REG_DIR_DATA_WRITE] = 0x08, 1003 [REG_DIR_DATA_READ] = 0x0c, 1004 [REG_SWITCH_REVISION] = 0x10, 1005 [REG_PHY_REVISION] = 0x14, 1006 [REG_SPHY_CNTRL] = 0x24, 1007 [REG_RGMII_0_CNTRL] = 0xe0, 1008 [REG_RGMII_1_CNTRL] = 0xec, 1009 [REG_RGMII_2_CNTRL] = 0xf8, 1010 [REG_LED_0_CNTRL] = 0x40, 1011 [REG_LED_1_CNTRL] = 0x4c, 1012 [REG_LED_2_CNTRL] = 0x58, 1013 }; 1014 1015 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1016 .type = BCM7278_DEVICE_ID, 1017 .core_reg_align = 1, 1018 .reg_offsets = bcm_sf2_7278_reg_offsets, 1019 .num_cfp_rules = 128, 1020 }; 1021 1022 static const struct of_device_id bcm_sf2_of_match[] = { 1023 { .compatible = "brcm,bcm7445-switch-v4.0", 1024 .data = &bcm_sf2_7445_data 1025 }, 1026 { .compatible = "brcm,bcm7278-switch-v4.0", 1027 .data = &bcm_sf2_7278_data 1028 }, 1029 { .compatible = "brcm,bcm7278-switch-v4.8", 1030 .data = &bcm_sf2_7278_data 1031 }, 1032 { /* sentinel */ }, 1033 }; 1034 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1035 1036 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1037 { 1038 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1039 struct device_node *dn = pdev->dev.of_node; 1040 const struct of_device_id *of_id = NULL; 1041 const struct bcm_sf2_of_data *data; 1042 struct b53_platform_data *pdata; 1043 struct dsa_switch_ops *ops; 1044 struct bcm_sf2_priv *priv; 1045 struct b53_device *dev; 1046 struct dsa_switch *ds; 1047 void __iomem **base; 1048 struct resource *r; 1049 unsigned int i; 1050 u32 reg, rev; 1051 int ret; 1052 1053 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1054 if (!priv) 1055 return -ENOMEM; 1056 1057 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1058 if (!ops) 1059 return -ENOMEM; 1060 1061 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1062 if (!dev) 1063 return -ENOMEM; 1064 1065 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1066 if (!pdata) 1067 return -ENOMEM; 1068 1069 of_id = of_match_node(bcm_sf2_of_match, dn); 1070 if (!of_id || !of_id->data) 1071 return -EINVAL; 1072 1073 data = of_id->data; 1074 1075 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1076 priv->type = data->type; 1077 priv->reg_offsets = data->reg_offsets; 1078 priv->core_reg_align = data->core_reg_align; 1079 priv->num_cfp_rules = data->num_cfp_rules; 1080 1081 /* Auto-detection using standard registers will not work, so 1082 * provide an indication of what kind of device we are for 1083 * b53_common to work with 1084 */ 1085 pdata->chip_id = priv->type; 1086 dev->pdata = pdata; 1087 1088 priv->dev = dev; 1089 ds = dev->ds; 1090 ds->ops = &bcm_sf2_ops; 1091 1092 /* Advertise the 8 egress queues */ 1093 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1094 1095 dev_set_drvdata(&pdev->dev, priv); 1096 1097 spin_lock_init(&priv->indir_lock); 1098 mutex_init(&priv->cfp.lock); 1099 INIT_LIST_HEAD(&priv->cfp.rules_list); 1100 1101 /* CFP rule #0 cannot be used for specific classifications, flag it as 1102 * permanently used 1103 */ 1104 set_bit(0, priv->cfp.used); 1105 set_bit(0, priv->cfp.unique); 1106 1107 bcm_sf2_identify_ports(priv, dn->child); 1108 1109 priv->irq0 = irq_of_parse_and_map(dn, 0); 1110 priv->irq1 = irq_of_parse_and_map(dn, 1); 1111 1112 base = &priv->core; 1113 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1114 r = platform_get_resource(pdev, IORESOURCE_MEM, i); 1115 *base = devm_ioremap_resource(&pdev->dev, r); 1116 if (IS_ERR(*base)) { 1117 pr_err("unable to find register: %s\n", reg_names[i]); 1118 return PTR_ERR(*base); 1119 } 1120 base++; 1121 } 1122 1123 ret = bcm_sf2_sw_rst(priv); 1124 if (ret) { 1125 pr_err("unable to software reset switch: %d\n", ret); 1126 return ret; 1127 } 1128 1129 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1130 1131 ret = bcm_sf2_mdio_register(ds); 1132 if (ret) { 1133 pr_err("failed to register MDIO bus\n"); 1134 return ret; 1135 } 1136 1137 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1138 1139 ret = bcm_sf2_cfp_rst(priv); 1140 if (ret) { 1141 pr_err("failed to reset CFP\n"); 1142 goto out_mdio; 1143 } 1144 1145 /* Disable all interrupts and request them */ 1146 bcm_sf2_intr_disable(priv); 1147 1148 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1149 "switch_0", ds); 1150 if (ret < 0) { 1151 pr_err("failed to request switch_0 IRQ\n"); 1152 goto out_mdio; 1153 } 1154 1155 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1156 "switch_1", ds); 1157 if (ret < 0) { 1158 pr_err("failed to request switch_1 IRQ\n"); 1159 goto out_mdio; 1160 } 1161 1162 /* Reset the MIB counters */ 1163 reg = core_readl(priv, CORE_GMNCFGCFG); 1164 reg |= RST_MIB_CNT; 1165 core_writel(priv, reg, CORE_GMNCFGCFG); 1166 reg &= ~RST_MIB_CNT; 1167 core_writel(priv, reg, CORE_GMNCFGCFG); 1168 1169 /* Get the maximum number of ports for this switch */ 1170 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1171 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1172 priv->hw_params.num_ports = DSA_MAX_PORTS; 1173 1174 /* Assume a single GPHY setup if we can't read that property */ 1175 if (of_property_read_u32(dn, "brcm,num-gphy", 1176 &priv->hw_params.num_gphy)) 1177 priv->hw_params.num_gphy = 1; 1178 1179 rev = reg_readl(priv, REG_SWITCH_REVISION); 1180 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1181 SWITCH_TOP_REV_MASK; 1182 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1183 1184 rev = reg_readl(priv, REG_PHY_REVISION); 1185 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1186 1187 ret = b53_switch_register(dev); 1188 if (ret) 1189 goto out_mdio; 1190 1191 dev_info(&pdev->dev, 1192 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1193 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1194 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1195 priv->irq0, priv->irq1); 1196 1197 return 0; 1198 1199 out_mdio: 1200 bcm_sf2_mdio_unregister(priv); 1201 return ret; 1202 } 1203 1204 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1205 { 1206 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1207 1208 priv->wol_ports_mask = 0; 1209 dsa_unregister_switch(priv->dev->ds); 1210 bcm_sf2_cfp_exit(priv->dev->ds); 1211 /* Disable all ports and interrupts */ 1212 bcm_sf2_sw_suspend(priv->dev->ds); 1213 bcm_sf2_mdio_unregister(priv); 1214 1215 return 0; 1216 } 1217 1218 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1219 { 1220 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1221 1222 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1223 * successful MDIO bus scan to occur. If we did turn off the GPHY 1224 * before (e.g: port_disable), this will also power it back on. 1225 * 1226 * Do not rely on kexec_in_progress, just power the PHY on. 1227 */ 1228 if (priv->hw_params.num_gphy == 1) 1229 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1230 } 1231 1232 #ifdef CONFIG_PM_SLEEP 1233 static int bcm_sf2_suspend(struct device *dev) 1234 { 1235 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1236 1237 return dsa_switch_suspend(priv->dev->ds); 1238 } 1239 1240 static int bcm_sf2_resume(struct device *dev) 1241 { 1242 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1243 1244 return dsa_switch_resume(priv->dev->ds); 1245 } 1246 #endif /* CONFIG_PM_SLEEP */ 1247 1248 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1249 bcm_sf2_suspend, bcm_sf2_resume); 1250 1251 1252 static struct platform_driver bcm_sf2_driver = { 1253 .probe = bcm_sf2_sw_probe, 1254 .remove = bcm_sf2_sw_remove, 1255 .shutdown = bcm_sf2_sw_shutdown, 1256 .driver = { 1257 .name = "brcm-sf2", 1258 .of_match_table = bcm_sf2_of_match, 1259 .pm = &bcm_sf2_pm_ops, 1260 }, 1261 }; 1262 module_platform_driver(bcm_sf2_driver); 1263 1264 MODULE_AUTHOR("Broadcom Corporation"); 1265 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1266 MODULE_LICENSE("GPL"); 1267 MODULE_ALIAS("platform:brcm-sf2"); 1268