1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <net/dsa.h> 24 #include <linux/ethtool.h> 25 #include <linux/if_bridge.h> 26 #include <linux/brcmphy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/platform_data/b53.h> 29 30 #include "bcm_sf2.h" 31 #include "bcm_sf2_regs.h" 32 #include "b53/b53_priv.h" 33 #include "b53/b53_regs.h" 34 35 /* Return the number of active ports, not counting the IMP (CPU) port */ 36 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds) 37 { 38 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 39 unsigned int port, count = 0; 40 41 for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) { 42 if (dsa_is_cpu_port(ds, port)) 43 continue; 44 if (priv->port_sts[port].enabled) 45 count++; 46 } 47 48 return count; 49 } 50 51 static void bcm_sf2_recalc_clock(struct dsa_switch *ds) 52 { 53 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 54 unsigned long new_rate; 55 unsigned int ports_active; 56 /* Frequenty in Mhz */ 57 static const unsigned long rate_table[] = { 58 59220000, 59 60820000, 60 62500000, 61 62500000, 62 }; 63 64 ports_active = bcm_sf2_num_active_ports(ds); 65 if (ports_active == 0 || !priv->clk_mdiv) 66 return; 67 68 /* If we overflow our table, just use the recommended operational 69 * frequency 70 */ 71 if (ports_active > ARRAY_SIZE(rate_table)) 72 new_rate = 90000000; 73 else 74 new_rate = rate_table[ports_active - 1]; 75 clk_set_rate(priv->clk_mdiv, new_rate); 76 } 77 78 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 79 { 80 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 81 unsigned int i; 82 u32 reg, offset; 83 84 /* Enable the port memories */ 85 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 86 reg &= ~P_TXQ_PSM_VDD(port); 87 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 88 89 /* Enable forwarding */ 90 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 91 92 /* Enable IMP port in dumb mode */ 93 reg = core_readl(priv, CORE_SWITCH_CTRL); 94 reg |= MII_DUMB_FWDG_EN; 95 core_writel(priv, reg, CORE_SWITCH_CTRL); 96 97 /* Configure Traffic Class to QoS mapping, allow each priority to map 98 * to a different queue number 99 */ 100 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 101 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 102 reg |= i << (PRT_TO_QID_SHIFT * i); 103 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 104 105 b53_brcm_hdr_setup(ds, port); 106 107 if (port == 8) { 108 if (priv->type == BCM4908_DEVICE_ID || 109 priv->type == BCM7445_DEVICE_ID) 110 offset = CORE_STS_OVERRIDE_IMP; 111 else 112 offset = CORE_STS_OVERRIDE_IMP2; 113 114 /* Force link status for IMP port */ 115 reg = core_readl(priv, offset); 116 reg |= (MII_SW_OR | LINK_STS); 117 reg &= ~GMII_SPEED_UP_2G; 118 core_writel(priv, reg, offset); 119 120 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 121 reg = core_readl(priv, CORE_IMP_CTL); 122 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 123 reg &= ~(RX_DIS | TX_DIS); 124 core_writel(priv, reg, CORE_IMP_CTL); 125 } else { 126 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 127 reg &= ~(RX_DIS | TX_DIS); 128 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 129 } 130 131 priv->port_sts[port].enabled = true; 132 } 133 134 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 135 { 136 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 137 u32 reg; 138 139 reg = reg_readl(priv, REG_SPHY_CNTRL); 140 if (enable) { 141 reg |= PHY_RESET; 142 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 143 reg_writel(priv, reg, REG_SPHY_CNTRL); 144 udelay(21); 145 reg = reg_readl(priv, REG_SPHY_CNTRL); 146 reg &= ~PHY_RESET; 147 } else { 148 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 149 reg_writel(priv, reg, REG_SPHY_CNTRL); 150 mdelay(1); 151 reg |= CK25_DIS; 152 } 153 reg_writel(priv, reg, REG_SPHY_CNTRL); 154 155 /* Use PHY-driven LED signaling */ 156 if (!enable) { 157 reg = reg_readl(priv, REG_LED_CNTRL(0)); 158 reg |= SPDLNK_SRC_SEL; 159 reg_writel(priv, reg, REG_LED_CNTRL(0)); 160 } 161 } 162 163 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 164 int port) 165 { 166 unsigned int off; 167 168 switch (port) { 169 case 7: 170 off = P7_IRQ_OFF; 171 break; 172 case 0: 173 /* Port 0 interrupts are located on the first bank */ 174 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 175 return; 176 default: 177 off = P_IRQ_OFF(port); 178 break; 179 } 180 181 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 182 } 183 184 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 185 int port) 186 { 187 unsigned int off; 188 189 switch (port) { 190 case 7: 191 off = P7_IRQ_OFF; 192 break; 193 case 0: 194 /* Port 0 interrupts are located on the first bank */ 195 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 196 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 197 return; 198 default: 199 off = P_IRQ_OFF(port); 200 break; 201 } 202 203 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 204 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 205 } 206 207 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 208 struct phy_device *phy) 209 { 210 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 211 unsigned int i; 212 u32 reg; 213 214 if (!dsa_is_user_port(ds, port)) 215 return 0; 216 217 priv->port_sts[port].enabled = true; 218 219 bcm_sf2_recalc_clock(ds); 220 221 /* Clear the memory power down */ 222 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 223 reg &= ~P_TXQ_PSM_VDD(port); 224 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 225 226 /* Enable Broadcom tags for that port if requested */ 227 if (priv->brcm_tag_mask & BIT(port)) 228 b53_brcm_hdr_setup(ds, port); 229 230 /* Configure Traffic Class to QoS mapping, allow each priority to map 231 * to a different queue number 232 */ 233 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 234 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 235 reg |= i << (PRT_TO_QID_SHIFT * i); 236 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 237 238 /* Re-enable the GPHY and re-apply workarounds */ 239 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 240 bcm_sf2_gphy_enable_set(ds, true); 241 if (phy) { 242 /* if phy_stop() has been called before, phy 243 * will be in halted state, and phy_start() 244 * will call resume. 245 * 246 * the resume path does not configure back 247 * autoneg settings, and since we hard reset 248 * the phy manually here, we need to reset the 249 * state machine also. 250 */ 251 phy->state = PHY_READY; 252 phy_init_hw(phy); 253 } 254 } 255 256 /* Enable MoCA port interrupts to get notified */ 257 if (port == priv->moca_port) 258 bcm_sf2_port_intr_enable(priv, port); 259 260 /* Set per-queue pause threshold to 32 */ 261 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 262 263 /* Set ACB threshold to 24 */ 264 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 265 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 266 SF2_NUM_EGRESS_QUEUES + i)); 267 reg &= ~XOFF_THRESHOLD_MASK; 268 reg |= 24; 269 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 270 SF2_NUM_EGRESS_QUEUES + i)); 271 } 272 273 return b53_enable_port(ds, port, phy); 274 } 275 276 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 277 { 278 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 279 u32 reg; 280 281 /* Disable learning while in WoL mode */ 282 if (priv->wol_ports_mask & (1 << port)) { 283 reg = core_readl(priv, CORE_DIS_LEARN); 284 reg |= BIT(port); 285 core_writel(priv, reg, CORE_DIS_LEARN); 286 return; 287 } 288 289 if (port == priv->moca_port) 290 bcm_sf2_port_intr_disable(priv, port); 291 292 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 293 bcm_sf2_gphy_enable_set(ds, false); 294 295 b53_disable_port(ds, port); 296 297 /* Power down the port memory */ 298 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 299 reg |= P_TXQ_PSM_VDD(port); 300 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 301 302 priv->port_sts[port].enabled = false; 303 304 bcm_sf2_recalc_clock(ds); 305 } 306 307 308 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 309 int regnum, u16 val) 310 { 311 int ret = 0; 312 u32 reg; 313 314 reg = reg_readl(priv, REG_SWITCH_CNTRL); 315 reg |= MDIO_MASTER_SEL; 316 reg_writel(priv, reg, REG_SWITCH_CNTRL); 317 318 /* Page << 8 | offset */ 319 reg = 0x70; 320 reg <<= 2; 321 core_writel(priv, addr, reg); 322 323 /* Page << 8 | offset */ 324 reg = 0x80 << 8 | regnum << 1; 325 reg <<= 2; 326 327 if (op) 328 ret = core_readl(priv, reg); 329 else 330 core_writel(priv, val, reg); 331 332 reg = reg_readl(priv, REG_SWITCH_CNTRL); 333 reg &= ~MDIO_MASTER_SEL; 334 reg_writel(priv, reg, REG_SWITCH_CNTRL); 335 336 return ret & 0xffff; 337 } 338 339 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 340 { 341 struct bcm_sf2_priv *priv = bus->priv; 342 343 /* Intercept reads from Broadcom pseudo-PHY address, else, send 344 * them to our master MDIO bus controller 345 */ 346 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 347 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 348 else 349 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 350 } 351 352 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 353 u16 val) 354 { 355 struct bcm_sf2_priv *priv = bus->priv; 356 357 /* Intercept writes to the Broadcom pseudo-PHY address, else, 358 * send them to our master MDIO bus controller 359 */ 360 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 361 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 362 else 363 return mdiobus_write_nested(priv->master_mii_bus, addr, 364 regnum, val); 365 } 366 367 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 368 { 369 struct dsa_switch *ds = dev_id; 370 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 371 372 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 373 ~priv->irq0_mask; 374 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 375 376 return IRQ_HANDLED; 377 } 378 379 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 380 { 381 struct dsa_switch *ds = dev_id; 382 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 383 384 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 385 ~priv->irq1_mask; 386 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 387 388 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 389 priv->port_sts[7].link = true; 390 dsa_port_phylink_mac_change(ds, 7, true); 391 } 392 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 393 priv->port_sts[7].link = false; 394 dsa_port_phylink_mac_change(ds, 7, false); 395 } 396 397 return IRQ_HANDLED; 398 } 399 400 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 401 { 402 unsigned int timeout = 1000; 403 u32 reg; 404 int ret; 405 406 /* The watchdog reset does not work on 7278, we need to hit the 407 * "external" reset line through the reset controller. 408 */ 409 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) { 410 ret = reset_control_assert(priv->rcdev); 411 if (ret) 412 return ret; 413 414 return reset_control_deassert(priv->rcdev); 415 } 416 417 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 418 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 419 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 420 421 do { 422 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 423 if (!(reg & SOFTWARE_RESET)) 424 break; 425 426 usleep_range(1000, 2000); 427 } while (timeout-- > 0); 428 429 if (timeout == 0) 430 return -ETIMEDOUT; 431 432 return 0; 433 } 434 435 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 436 { 437 intrl2_0_mask_set(priv, 0xffffffff); 438 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 439 intrl2_1_mask_set(priv, 0xffffffff); 440 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 441 } 442 443 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 444 struct device_node *dn) 445 { 446 struct device_node *port; 447 unsigned int port_num; 448 struct property *prop; 449 phy_interface_t mode; 450 int err; 451 452 priv->moca_port = -1; 453 454 for_each_available_child_of_node(dn, port) { 455 if (of_property_read_u32(port, "reg", &port_num)) 456 continue; 457 458 /* Internal PHYs get assigned a specific 'phy-mode' property 459 * value: "internal" to help flag them before MDIO probing 460 * has completed, since they might be turned off at that 461 * time 462 */ 463 err = of_get_phy_mode(port, &mode); 464 if (err) 465 continue; 466 467 if (mode == PHY_INTERFACE_MODE_INTERNAL) 468 priv->int_phy_mask |= 1 << port_num; 469 470 if (mode == PHY_INTERFACE_MODE_MOCA) 471 priv->moca_port = port_num; 472 473 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 474 priv->brcm_tag_mask |= 1 << port_num; 475 476 /* Ensure that port 5 is not picked up as a DSA CPU port 477 * flavour but a regular port instead. We should be using 478 * devlink to be able to set the port flavour. 479 */ 480 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) { 481 prop = of_find_property(port, "ethernet", NULL); 482 if (prop) 483 of_remove_property(port, prop); 484 } 485 } 486 } 487 488 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 489 { 490 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 491 struct device_node *dn, *child; 492 struct phy_device *phydev; 493 struct property *prop; 494 static int index; 495 int err, reg; 496 497 /* Find our integrated MDIO bus node */ 498 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 499 priv->master_mii_bus = of_mdio_find_bus(dn); 500 if (!priv->master_mii_bus) { 501 of_node_put(dn); 502 return -EPROBE_DEFER; 503 } 504 505 get_device(&priv->master_mii_bus->dev); 506 priv->master_mii_dn = dn; 507 508 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 509 if (!priv->slave_mii_bus) { 510 of_node_put(dn); 511 return -ENOMEM; 512 } 513 514 priv->slave_mii_bus->priv = priv; 515 priv->slave_mii_bus->name = "sf2 slave mii"; 516 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 517 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 518 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 519 index++); 520 priv->slave_mii_bus->dev.of_node = dn; 521 522 /* Include the pseudo-PHY address to divert reads towards our 523 * workaround. This is only required for 7445D0, since 7445E0 524 * disconnects the internal switch pseudo-PHY such that we can use the 525 * regular SWITCH_MDIO master controller instead. 526 * 527 * Here we flag the pseudo PHY as needing special treatment and would 528 * otherwise make all other PHY read/writes go to the master MDIO bus 529 * controller that comes with this switch backed by the "mdio-unimac" 530 * driver. 531 */ 532 if (of_machine_is_compatible("brcm,bcm7445d0")) 533 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0); 534 else 535 priv->indir_phy_mask = 0; 536 537 ds->phys_mii_mask = priv->indir_phy_mask; 538 ds->slave_mii_bus = priv->slave_mii_bus; 539 priv->slave_mii_bus->parent = ds->dev->parent; 540 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 541 542 /* We need to make sure that of_phy_connect() will not work by 543 * removing the 'phandle' and 'linux,phandle' properties and 544 * unregister the existing PHY device that was already registered. 545 */ 546 for_each_available_child_of_node(dn, child) { 547 if (of_property_read_u32(child, "reg", ®) || 548 reg >= PHY_MAX_ADDR) 549 continue; 550 551 if (!(priv->indir_phy_mask & BIT(reg))) 552 continue; 553 554 prop = of_find_property(child, "phandle", NULL); 555 if (prop) 556 of_remove_property(child, prop); 557 558 prop = of_find_property(child, "linux,phandle", NULL); 559 if (prop) 560 of_remove_property(child, prop); 561 562 phydev = of_phy_find_device(child); 563 if (phydev) 564 phy_device_remove(phydev); 565 } 566 567 err = mdiobus_register(priv->slave_mii_bus); 568 if (err && dn) 569 of_node_put(dn); 570 571 return err; 572 } 573 574 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 575 { 576 mdiobus_unregister(priv->slave_mii_bus); 577 of_node_put(priv->master_mii_dn); 578 } 579 580 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 581 { 582 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 583 584 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 585 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 586 * the REG_PHY_REVISION register layout is. 587 */ 588 589 return priv->hw_params.gphy_rev; 590 } 591 592 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 593 unsigned long *supported, 594 struct phylink_link_state *state) 595 { 596 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 597 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 598 599 if (!phy_interface_mode_is_rgmii(state->interface) && 600 state->interface != PHY_INTERFACE_MODE_MII && 601 state->interface != PHY_INTERFACE_MODE_REVMII && 602 state->interface != PHY_INTERFACE_MODE_GMII && 603 state->interface != PHY_INTERFACE_MODE_INTERNAL && 604 state->interface != PHY_INTERFACE_MODE_MOCA) { 605 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 606 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 607 dev_err(ds->dev, 608 "Unsupported interface: %d for port %d\n", 609 state->interface, port); 610 return; 611 } 612 613 /* Allow all the expected bits */ 614 phylink_set(mask, Autoneg); 615 phylink_set_port_modes(mask); 616 phylink_set(mask, Pause); 617 phylink_set(mask, Asym_Pause); 618 619 /* With the exclusion of MII and Reverse MII, we support Gigabit, 620 * including Half duplex 621 */ 622 if (state->interface != PHY_INTERFACE_MODE_MII && 623 state->interface != PHY_INTERFACE_MODE_REVMII) { 624 phylink_set(mask, 1000baseT_Full); 625 phylink_set(mask, 1000baseT_Half); 626 } 627 628 phylink_set(mask, 10baseT_Half); 629 phylink_set(mask, 10baseT_Full); 630 phylink_set(mask, 100baseT_Half); 631 phylink_set(mask, 100baseT_Full); 632 633 bitmap_and(supported, supported, mask, 634 __ETHTOOL_LINK_MODE_MASK_NBITS); 635 bitmap_and(state->advertising, state->advertising, mask, 636 __ETHTOOL_LINK_MODE_MASK_NBITS); 637 } 638 639 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 640 unsigned int mode, 641 const struct phylink_link_state *state) 642 { 643 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 644 u32 id_mode_dis = 0, port_mode; 645 u32 reg; 646 647 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 648 return; 649 650 switch (state->interface) { 651 case PHY_INTERFACE_MODE_RGMII: 652 id_mode_dis = 1; 653 fallthrough; 654 case PHY_INTERFACE_MODE_RGMII_TXID: 655 port_mode = EXT_GPHY; 656 break; 657 case PHY_INTERFACE_MODE_MII: 658 port_mode = EXT_EPHY; 659 break; 660 case PHY_INTERFACE_MODE_REVMII: 661 port_mode = EXT_REVMII; 662 break; 663 default: 664 /* Nothing required for all other PHYs: internal and MoCA */ 665 return; 666 } 667 668 /* Clear id_mode_dis bit, and the existing port mode, let 669 * RGMII_MODE_EN bet set by mac_link_{up,down} 670 */ 671 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 672 reg &= ~ID_MODE_DIS; 673 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 674 675 reg |= port_mode; 676 if (id_mode_dis) 677 reg |= ID_MODE_DIS; 678 679 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 680 } 681 682 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 683 phy_interface_t interface, bool link) 684 { 685 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 686 u32 reg; 687 688 if (!phy_interface_mode_is_rgmii(interface) && 689 interface != PHY_INTERFACE_MODE_MII && 690 interface != PHY_INTERFACE_MODE_REVMII) 691 return; 692 693 /* If the link is down, just disable the interface to conserve power */ 694 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 695 if (link) 696 reg |= RGMII_MODE_EN; 697 else 698 reg &= ~RGMII_MODE_EN; 699 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 700 } 701 702 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 703 unsigned int mode, 704 phy_interface_t interface) 705 { 706 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 707 u32 reg, offset; 708 709 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 710 if (priv->type == BCM4908_DEVICE_ID || 711 priv->type == BCM7445_DEVICE_ID) 712 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 713 else 714 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 715 716 reg = core_readl(priv, offset); 717 reg &= ~LINK_STS; 718 core_writel(priv, reg, offset); 719 } 720 721 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 722 } 723 724 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 725 unsigned int mode, 726 phy_interface_t interface, 727 struct phy_device *phydev, 728 int speed, int duplex, 729 bool tx_pause, bool rx_pause) 730 { 731 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 732 struct ethtool_eee *p = &priv->dev->ports[port].eee; 733 u32 reg, offset; 734 735 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 736 737 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 738 if (priv->type == BCM4908_DEVICE_ID || 739 priv->type == BCM7445_DEVICE_ID) 740 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 741 else 742 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 743 744 if (interface == PHY_INTERFACE_MODE_RGMII || 745 interface == PHY_INTERFACE_MODE_RGMII_TXID || 746 interface == PHY_INTERFACE_MODE_MII || 747 interface == PHY_INTERFACE_MODE_REVMII) { 748 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 749 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 750 751 if (tx_pause) 752 reg |= TX_PAUSE_EN; 753 if (rx_pause) 754 reg |= RX_PAUSE_EN; 755 756 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 757 } 758 759 reg = SW_OVERRIDE | LINK_STS; 760 switch (speed) { 761 case SPEED_1000: 762 reg |= SPDSTS_1000 << SPEED_SHIFT; 763 break; 764 case SPEED_100: 765 reg |= SPDSTS_100 << SPEED_SHIFT; 766 break; 767 } 768 769 if (duplex == DUPLEX_FULL) 770 reg |= DUPLX_MODE; 771 772 core_writel(priv, reg, offset); 773 } 774 775 if (mode == MLO_AN_PHY && phydev) 776 p->eee_enabled = b53_eee_init(ds, port, phydev); 777 } 778 779 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 780 struct phylink_link_state *status) 781 { 782 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 783 784 status->link = false; 785 786 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 787 * which means that we need to force the link at the port override 788 * level to get the data to flow. We do use what the interrupt handler 789 * did determine before. 790 * 791 * For the other ports, we just force the link status, since this is 792 * a fixed PHY device. 793 */ 794 if (port == priv->moca_port) { 795 status->link = priv->port_sts[port].link; 796 /* For MoCA interfaces, also force a link down notification 797 * since some version of the user-space daemon (mocad) use 798 * cmd->autoneg to force the link, which messes up the PHY 799 * state machine and make it go in PHY_FORCING state instead. 800 */ 801 if (!status->link) 802 netif_carrier_off(dsa_to_port(ds, port)->slave); 803 status->duplex = DUPLEX_FULL; 804 } else { 805 status->link = true; 806 } 807 } 808 809 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 810 { 811 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 812 u32 reg; 813 814 /* Enable ACB globally */ 815 reg = acb_readl(priv, ACB_CONTROL); 816 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 817 acb_writel(priv, reg, ACB_CONTROL); 818 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 819 reg |= ACB_EN | ACB_ALGORITHM; 820 acb_writel(priv, reg, ACB_CONTROL); 821 } 822 823 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 824 { 825 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 826 unsigned int port; 827 828 bcm_sf2_intr_disable(priv); 829 830 /* Disable all ports physically present including the IMP 831 * port, the other ones have already been disabled during 832 * bcm_sf2_sw_setup 833 */ 834 for (port = 0; port < ds->num_ports; port++) { 835 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 836 bcm_sf2_port_disable(ds, port); 837 } 838 839 if (!priv->wol_ports_mask) 840 clk_disable_unprepare(priv->clk); 841 842 return 0; 843 } 844 845 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 846 { 847 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 848 int ret; 849 850 if (!priv->wol_ports_mask) 851 clk_prepare_enable(priv->clk); 852 853 ret = bcm_sf2_sw_rst(priv); 854 if (ret) { 855 pr_err("%s: failed to software reset switch\n", __func__); 856 return ret; 857 } 858 859 ret = bcm_sf2_cfp_resume(ds); 860 if (ret) 861 return ret; 862 863 if (priv->hw_params.num_gphy == 1) 864 bcm_sf2_gphy_enable_set(ds, true); 865 866 ds->ops->setup(ds); 867 868 return 0; 869 } 870 871 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 872 struct ethtool_wolinfo *wol) 873 { 874 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 875 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 876 struct ethtool_wolinfo pwol = { }; 877 878 /* Get the parent device WoL settings */ 879 if (p->ethtool_ops->get_wol) 880 p->ethtool_ops->get_wol(p, &pwol); 881 882 /* Advertise the parent device supported settings */ 883 wol->supported = pwol.supported; 884 memset(&wol->sopass, 0, sizeof(wol->sopass)); 885 886 if (pwol.wolopts & WAKE_MAGICSECURE) 887 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 888 889 if (priv->wol_ports_mask & (1 << port)) 890 wol->wolopts = pwol.wolopts; 891 else 892 wol->wolopts = 0; 893 } 894 895 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 896 struct ethtool_wolinfo *wol) 897 { 898 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 899 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 900 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 901 struct ethtool_wolinfo pwol = { }; 902 903 if (p->ethtool_ops->get_wol) 904 p->ethtool_ops->get_wol(p, &pwol); 905 if (wol->wolopts & ~pwol.supported) 906 return -EINVAL; 907 908 if (wol->wolopts) 909 priv->wol_ports_mask |= (1 << port); 910 else 911 priv->wol_ports_mask &= ~(1 << port); 912 913 /* If we have at least one port enabled, make sure the CPU port 914 * is also enabled. If the CPU port is the last one enabled, we disable 915 * it since this configuration does not make sense. 916 */ 917 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 918 priv->wol_ports_mask |= (1 << cpu_port); 919 else 920 priv->wol_ports_mask &= ~(1 << cpu_port); 921 922 return p->ethtool_ops->set_wol(p, wol); 923 } 924 925 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 926 { 927 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 928 unsigned int port; 929 930 /* Enable all valid ports and disable those unused */ 931 for (port = 0; port < priv->hw_params.num_ports; port++) { 932 /* IMP port receives special treatment */ 933 if (dsa_is_user_port(ds, port)) 934 bcm_sf2_port_setup(ds, port, NULL); 935 else if (dsa_is_cpu_port(ds, port)) 936 bcm_sf2_imp_setup(ds, port); 937 else 938 bcm_sf2_port_disable(ds, port); 939 } 940 941 b53_configure_vlan(ds); 942 bcm_sf2_enable_acb(ds); 943 944 return b53_setup_devlink_resources(ds); 945 } 946 947 static void bcm_sf2_sw_teardown(struct dsa_switch *ds) 948 { 949 dsa_devlink_resources_unregister(ds); 950 } 951 952 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 953 * register basis so we need to translate that into an address that the 954 * bus-glue understands. 955 */ 956 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 957 958 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 959 u8 *val) 960 { 961 struct bcm_sf2_priv *priv = dev->priv; 962 963 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 964 965 return 0; 966 } 967 968 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 969 u16 *val) 970 { 971 struct bcm_sf2_priv *priv = dev->priv; 972 973 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 974 975 return 0; 976 } 977 978 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 979 u32 *val) 980 { 981 struct bcm_sf2_priv *priv = dev->priv; 982 983 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 984 985 return 0; 986 } 987 988 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 989 u64 *val) 990 { 991 struct bcm_sf2_priv *priv = dev->priv; 992 993 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 994 995 return 0; 996 } 997 998 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 999 u8 value) 1000 { 1001 struct bcm_sf2_priv *priv = dev->priv; 1002 1003 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1004 1005 return 0; 1006 } 1007 1008 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 1009 u16 value) 1010 { 1011 struct bcm_sf2_priv *priv = dev->priv; 1012 1013 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1014 1015 return 0; 1016 } 1017 1018 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 1019 u32 value) 1020 { 1021 struct bcm_sf2_priv *priv = dev->priv; 1022 1023 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1024 1025 return 0; 1026 } 1027 1028 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 1029 u64 value) 1030 { 1031 struct bcm_sf2_priv *priv = dev->priv; 1032 1033 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1034 1035 return 0; 1036 } 1037 1038 static const struct b53_io_ops bcm_sf2_io_ops = { 1039 .read8 = bcm_sf2_core_read8, 1040 .read16 = bcm_sf2_core_read16, 1041 .read32 = bcm_sf2_core_read32, 1042 .read48 = bcm_sf2_core_read64, 1043 .read64 = bcm_sf2_core_read64, 1044 .write8 = bcm_sf2_core_write8, 1045 .write16 = bcm_sf2_core_write16, 1046 .write32 = bcm_sf2_core_write32, 1047 .write48 = bcm_sf2_core_write64, 1048 .write64 = bcm_sf2_core_write64, 1049 }; 1050 1051 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 1052 u32 stringset, uint8_t *data) 1053 { 1054 int cnt = b53_get_sset_count(ds, port, stringset); 1055 1056 b53_get_strings(ds, port, stringset, data); 1057 bcm_sf2_cfp_get_strings(ds, port, stringset, 1058 data + cnt * ETH_GSTRING_LEN); 1059 } 1060 1061 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 1062 uint64_t *data) 1063 { 1064 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 1065 1066 b53_get_ethtool_stats(ds, port, data); 1067 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 1068 } 1069 1070 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 1071 int sset) 1072 { 1073 int cnt = b53_get_sset_count(ds, port, sset); 1074 1075 if (cnt < 0) 1076 return cnt; 1077 1078 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 1079 1080 return cnt; 1081 } 1082 1083 static const struct dsa_switch_ops bcm_sf2_ops = { 1084 .get_tag_protocol = b53_get_tag_protocol, 1085 .setup = bcm_sf2_sw_setup, 1086 .teardown = bcm_sf2_sw_teardown, 1087 .get_strings = bcm_sf2_sw_get_strings, 1088 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 1089 .get_sset_count = bcm_sf2_sw_get_sset_count, 1090 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1091 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 1092 .phylink_validate = bcm_sf2_sw_validate, 1093 .phylink_mac_config = bcm_sf2_sw_mac_config, 1094 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 1095 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 1096 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 1097 .suspend = bcm_sf2_sw_suspend, 1098 .resume = bcm_sf2_sw_resume, 1099 .get_wol = bcm_sf2_sw_get_wol, 1100 .set_wol = bcm_sf2_sw_set_wol, 1101 .port_enable = bcm_sf2_port_setup, 1102 .port_disable = bcm_sf2_port_disable, 1103 .get_mac_eee = b53_get_mac_eee, 1104 .set_mac_eee = b53_set_mac_eee, 1105 .port_bridge_join = b53_br_join, 1106 .port_bridge_leave = b53_br_leave, 1107 .port_pre_bridge_flags = b53_br_flags_pre, 1108 .port_bridge_flags = b53_br_flags, 1109 .port_stp_state_set = b53_br_set_stp_state, 1110 .port_set_mrouter = b53_set_mrouter, 1111 .port_fast_age = b53_br_fast_age, 1112 .port_vlan_filtering = b53_vlan_filtering, 1113 .port_vlan_add = b53_vlan_add, 1114 .port_vlan_del = b53_vlan_del, 1115 .port_fdb_dump = b53_fdb_dump, 1116 .port_fdb_add = b53_fdb_add, 1117 .port_fdb_del = b53_fdb_del, 1118 .get_rxnfc = bcm_sf2_get_rxnfc, 1119 .set_rxnfc = bcm_sf2_set_rxnfc, 1120 .port_mirror_add = b53_mirror_add, 1121 .port_mirror_del = b53_mirror_del, 1122 .port_mdb_add = b53_mdb_add, 1123 .port_mdb_del = b53_mdb_del, 1124 }; 1125 1126 struct bcm_sf2_of_data { 1127 u32 type; 1128 const u16 *reg_offsets; 1129 unsigned int core_reg_align; 1130 unsigned int num_cfp_rules; 1131 }; 1132 1133 static const u16 bcm_sf2_4908_reg_offsets[] = { 1134 [REG_SWITCH_CNTRL] = 0x00, 1135 [REG_SWITCH_STATUS] = 0x04, 1136 [REG_DIR_DATA_WRITE] = 0x08, 1137 [REG_DIR_DATA_READ] = 0x0c, 1138 [REG_SWITCH_REVISION] = 0x10, 1139 [REG_PHY_REVISION] = 0x14, 1140 [REG_SPHY_CNTRL] = 0x24, 1141 [REG_CROSSBAR] = 0xc8, 1142 [REG_RGMII_0_CNTRL] = 0xe0, 1143 [REG_RGMII_1_CNTRL] = 0xec, 1144 [REG_RGMII_2_CNTRL] = 0xf8, 1145 [REG_LED_0_CNTRL] = 0x40, 1146 [REG_LED_1_CNTRL] = 0x4c, 1147 [REG_LED_2_CNTRL] = 0x58, 1148 }; 1149 1150 static const struct bcm_sf2_of_data bcm_sf2_4908_data = { 1151 .type = BCM4908_DEVICE_ID, 1152 .core_reg_align = 0, 1153 .reg_offsets = bcm_sf2_4908_reg_offsets, 1154 .num_cfp_rules = 0, /* FIXME */ 1155 }; 1156 1157 /* Register offsets for the SWITCH_REG_* block */ 1158 static const u16 bcm_sf2_7445_reg_offsets[] = { 1159 [REG_SWITCH_CNTRL] = 0x00, 1160 [REG_SWITCH_STATUS] = 0x04, 1161 [REG_DIR_DATA_WRITE] = 0x08, 1162 [REG_DIR_DATA_READ] = 0x0C, 1163 [REG_SWITCH_REVISION] = 0x18, 1164 [REG_PHY_REVISION] = 0x1C, 1165 [REG_SPHY_CNTRL] = 0x2C, 1166 [REG_RGMII_0_CNTRL] = 0x34, 1167 [REG_RGMII_1_CNTRL] = 0x40, 1168 [REG_RGMII_2_CNTRL] = 0x4c, 1169 [REG_LED_0_CNTRL] = 0x90, 1170 [REG_LED_1_CNTRL] = 0x94, 1171 [REG_LED_2_CNTRL] = 0x98, 1172 }; 1173 1174 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1175 .type = BCM7445_DEVICE_ID, 1176 .core_reg_align = 0, 1177 .reg_offsets = bcm_sf2_7445_reg_offsets, 1178 .num_cfp_rules = 256, 1179 }; 1180 1181 static const u16 bcm_sf2_7278_reg_offsets[] = { 1182 [REG_SWITCH_CNTRL] = 0x00, 1183 [REG_SWITCH_STATUS] = 0x04, 1184 [REG_DIR_DATA_WRITE] = 0x08, 1185 [REG_DIR_DATA_READ] = 0x0c, 1186 [REG_SWITCH_REVISION] = 0x10, 1187 [REG_PHY_REVISION] = 0x14, 1188 [REG_SPHY_CNTRL] = 0x24, 1189 [REG_RGMII_0_CNTRL] = 0xe0, 1190 [REG_RGMII_1_CNTRL] = 0xec, 1191 [REG_RGMII_2_CNTRL] = 0xf8, 1192 [REG_LED_0_CNTRL] = 0x40, 1193 [REG_LED_1_CNTRL] = 0x4c, 1194 [REG_LED_2_CNTRL] = 0x58, 1195 }; 1196 1197 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1198 .type = BCM7278_DEVICE_ID, 1199 .core_reg_align = 1, 1200 .reg_offsets = bcm_sf2_7278_reg_offsets, 1201 .num_cfp_rules = 128, 1202 }; 1203 1204 static const struct of_device_id bcm_sf2_of_match[] = { 1205 { .compatible = "brcm,bcm4908-switch", 1206 .data = &bcm_sf2_4908_data 1207 }, 1208 { .compatible = "brcm,bcm7445-switch-v4.0", 1209 .data = &bcm_sf2_7445_data 1210 }, 1211 { .compatible = "brcm,bcm7278-switch-v4.0", 1212 .data = &bcm_sf2_7278_data 1213 }, 1214 { .compatible = "brcm,bcm7278-switch-v4.8", 1215 .data = &bcm_sf2_7278_data 1216 }, 1217 { /* sentinel */ }, 1218 }; 1219 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1220 1221 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1222 { 1223 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1224 struct device_node *dn = pdev->dev.of_node; 1225 const struct of_device_id *of_id = NULL; 1226 const struct bcm_sf2_of_data *data; 1227 struct b53_platform_data *pdata; 1228 struct dsa_switch_ops *ops; 1229 struct device_node *ports; 1230 struct bcm_sf2_priv *priv; 1231 struct b53_device *dev; 1232 struct dsa_switch *ds; 1233 void __iomem **base; 1234 unsigned int i; 1235 u32 reg, rev; 1236 int ret; 1237 1238 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1239 if (!priv) 1240 return -ENOMEM; 1241 1242 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1243 if (!ops) 1244 return -ENOMEM; 1245 1246 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1247 if (!dev) 1248 return -ENOMEM; 1249 1250 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1251 if (!pdata) 1252 return -ENOMEM; 1253 1254 of_id = of_match_node(bcm_sf2_of_match, dn); 1255 if (!of_id || !of_id->data) 1256 return -EINVAL; 1257 1258 data = of_id->data; 1259 1260 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1261 priv->type = data->type; 1262 priv->reg_offsets = data->reg_offsets; 1263 priv->core_reg_align = data->core_reg_align; 1264 priv->num_cfp_rules = data->num_cfp_rules; 1265 1266 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1267 "switch"); 1268 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER) 1269 return PTR_ERR(priv->rcdev); 1270 1271 /* Auto-detection using standard registers will not work, so 1272 * provide an indication of what kind of device we are for 1273 * b53_common to work with 1274 */ 1275 pdata->chip_id = priv->type; 1276 dev->pdata = pdata; 1277 1278 priv->dev = dev; 1279 ds = dev->ds; 1280 ds->ops = &bcm_sf2_ops; 1281 1282 /* Advertise the 8 egress queues */ 1283 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1284 1285 dev_set_drvdata(&pdev->dev, priv); 1286 1287 spin_lock_init(&priv->indir_lock); 1288 mutex_init(&priv->cfp.lock); 1289 INIT_LIST_HEAD(&priv->cfp.rules_list); 1290 1291 /* CFP rule #0 cannot be used for specific classifications, flag it as 1292 * permanently used 1293 */ 1294 set_bit(0, priv->cfp.used); 1295 set_bit(0, priv->cfp.unique); 1296 1297 /* Balance of_node_put() done by of_find_node_by_name() */ 1298 of_node_get(dn); 1299 ports = of_find_node_by_name(dn, "ports"); 1300 if (ports) { 1301 bcm_sf2_identify_ports(priv, ports); 1302 of_node_put(ports); 1303 } 1304 1305 priv->irq0 = irq_of_parse_and_map(dn, 0); 1306 priv->irq1 = irq_of_parse_and_map(dn, 1); 1307 1308 base = &priv->core; 1309 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1310 *base = devm_platform_ioremap_resource(pdev, i); 1311 if (IS_ERR(*base)) { 1312 pr_err("unable to find register: %s\n", reg_names[i]); 1313 return PTR_ERR(*base); 1314 } 1315 base++; 1316 } 1317 1318 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch"); 1319 if (IS_ERR(priv->clk)) 1320 return PTR_ERR(priv->clk); 1321 1322 clk_prepare_enable(priv->clk); 1323 1324 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv"); 1325 if (IS_ERR(priv->clk_mdiv)) { 1326 ret = PTR_ERR(priv->clk_mdiv); 1327 goto out_clk; 1328 } 1329 1330 clk_prepare_enable(priv->clk_mdiv); 1331 1332 ret = bcm_sf2_sw_rst(priv); 1333 if (ret) { 1334 pr_err("unable to software reset switch: %d\n", ret); 1335 goto out_clk_mdiv; 1336 } 1337 1338 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1339 1340 ret = bcm_sf2_mdio_register(ds); 1341 if (ret) { 1342 pr_err("failed to register MDIO bus\n"); 1343 goto out_clk_mdiv; 1344 } 1345 1346 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1347 1348 ret = bcm_sf2_cfp_rst(priv); 1349 if (ret) { 1350 pr_err("failed to reset CFP\n"); 1351 goto out_mdio; 1352 } 1353 1354 /* Disable all interrupts and request them */ 1355 bcm_sf2_intr_disable(priv); 1356 1357 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1358 "switch_0", ds); 1359 if (ret < 0) { 1360 pr_err("failed to request switch_0 IRQ\n"); 1361 goto out_mdio; 1362 } 1363 1364 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1365 "switch_1", ds); 1366 if (ret < 0) { 1367 pr_err("failed to request switch_1 IRQ\n"); 1368 goto out_mdio; 1369 } 1370 1371 /* Reset the MIB counters */ 1372 reg = core_readl(priv, CORE_GMNCFGCFG); 1373 reg |= RST_MIB_CNT; 1374 core_writel(priv, reg, CORE_GMNCFGCFG); 1375 reg &= ~RST_MIB_CNT; 1376 core_writel(priv, reg, CORE_GMNCFGCFG); 1377 1378 /* Get the maximum number of ports for this switch */ 1379 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1380 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1381 priv->hw_params.num_ports = DSA_MAX_PORTS; 1382 1383 /* Assume a single GPHY setup if we can't read that property */ 1384 if (of_property_read_u32(dn, "brcm,num-gphy", 1385 &priv->hw_params.num_gphy)) 1386 priv->hw_params.num_gphy = 1; 1387 1388 rev = reg_readl(priv, REG_SWITCH_REVISION); 1389 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1390 SWITCH_TOP_REV_MASK; 1391 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1392 1393 rev = reg_readl(priv, REG_PHY_REVISION); 1394 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1395 1396 ret = b53_switch_register(dev); 1397 if (ret) 1398 goto out_mdio; 1399 1400 dev_info(&pdev->dev, 1401 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1402 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1403 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1404 priv->irq0, priv->irq1); 1405 1406 return 0; 1407 1408 out_mdio: 1409 bcm_sf2_mdio_unregister(priv); 1410 out_clk_mdiv: 1411 clk_disable_unprepare(priv->clk_mdiv); 1412 out_clk: 1413 clk_disable_unprepare(priv->clk); 1414 return ret; 1415 } 1416 1417 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1418 { 1419 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1420 1421 priv->wol_ports_mask = 0; 1422 /* Disable interrupts */ 1423 bcm_sf2_intr_disable(priv); 1424 dsa_unregister_switch(priv->dev->ds); 1425 bcm_sf2_cfp_exit(priv->dev->ds); 1426 bcm_sf2_mdio_unregister(priv); 1427 clk_disable_unprepare(priv->clk_mdiv); 1428 clk_disable_unprepare(priv->clk); 1429 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) 1430 reset_control_assert(priv->rcdev); 1431 1432 return 0; 1433 } 1434 1435 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1436 { 1437 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1438 1439 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1440 * successful MDIO bus scan to occur. If we did turn off the GPHY 1441 * before (e.g: port_disable), this will also power it back on. 1442 * 1443 * Do not rely on kexec_in_progress, just power the PHY on. 1444 */ 1445 if (priv->hw_params.num_gphy == 1) 1446 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1447 } 1448 1449 #ifdef CONFIG_PM_SLEEP 1450 static int bcm_sf2_suspend(struct device *dev) 1451 { 1452 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1453 1454 return dsa_switch_suspend(priv->dev->ds); 1455 } 1456 1457 static int bcm_sf2_resume(struct device *dev) 1458 { 1459 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1460 1461 return dsa_switch_resume(priv->dev->ds); 1462 } 1463 #endif /* CONFIG_PM_SLEEP */ 1464 1465 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1466 bcm_sf2_suspend, bcm_sf2_resume); 1467 1468 1469 static struct platform_driver bcm_sf2_driver = { 1470 .probe = bcm_sf2_sw_probe, 1471 .remove = bcm_sf2_sw_remove, 1472 .shutdown = bcm_sf2_sw_shutdown, 1473 .driver = { 1474 .name = "brcm-sf2", 1475 .of_match_table = bcm_sf2_of_match, 1476 .pm = &bcm_sf2_pm_ops, 1477 }, 1478 }; 1479 module_platform_driver(bcm_sf2_driver); 1480 1481 MODULE_AUTHOR("Broadcom Corporation"); 1482 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1483 MODULE_LICENSE("GPL"); 1484 MODULE_ALIAS("platform:brcm-sf2"); 1485