1 /* 2 * Broadcom Starfighter 2 DSA switch driver 3 * 4 * Copyright (C) 2014, Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/list.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/phylink.h> 20 #include <linux/mii.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_address.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <net/dsa.h> 27 #include <linux/ethtool.h> 28 #include <linux/if_bridge.h> 29 #include <linux/brcmphy.h> 30 #include <linux/etherdevice.h> 31 #include <linux/platform_data/b53.h> 32 33 #include "bcm_sf2.h" 34 #include "bcm_sf2_regs.h" 35 #include "b53/b53_priv.h" 36 #include "b53/b53_regs.h" 37 38 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 39 { 40 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 41 unsigned int i; 42 u32 reg, offset; 43 44 if (priv->type == BCM7445_DEVICE_ID) 45 offset = CORE_STS_OVERRIDE_IMP; 46 else 47 offset = CORE_STS_OVERRIDE_IMP2; 48 49 /* Enable the port memories */ 50 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 51 reg &= ~P_TXQ_PSM_VDD(port); 52 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 53 54 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 55 reg = core_readl(priv, CORE_IMP_CTL); 56 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 57 reg &= ~(RX_DIS | TX_DIS); 58 core_writel(priv, reg, CORE_IMP_CTL); 59 60 /* Enable forwarding */ 61 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 62 63 /* Enable IMP port in dumb mode */ 64 reg = core_readl(priv, CORE_SWITCH_CTRL); 65 reg |= MII_DUMB_FWDG_EN; 66 core_writel(priv, reg, CORE_SWITCH_CTRL); 67 68 /* Configure Traffic Class to QoS mapping, allow each priority to map 69 * to a different queue number 70 */ 71 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 72 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 73 reg |= i << (PRT_TO_QID_SHIFT * i); 74 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 75 76 b53_brcm_hdr_setup(ds, port); 77 78 /* Force link status for IMP port */ 79 reg = core_readl(priv, offset); 80 reg |= (MII_SW_OR | LINK_STS); 81 core_writel(priv, reg, offset); 82 } 83 84 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 85 { 86 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 87 u32 reg; 88 89 reg = reg_readl(priv, REG_SPHY_CNTRL); 90 if (enable) { 91 reg |= PHY_RESET; 92 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 93 reg_writel(priv, reg, REG_SPHY_CNTRL); 94 udelay(21); 95 reg = reg_readl(priv, REG_SPHY_CNTRL); 96 reg &= ~PHY_RESET; 97 } else { 98 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 99 reg_writel(priv, reg, REG_SPHY_CNTRL); 100 mdelay(1); 101 reg |= CK25_DIS; 102 } 103 reg_writel(priv, reg, REG_SPHY_CNTRL); 104 105 /* Use PHY-driven LED signaling */ 106 if (!enable) { 107 reg = reg_readl(priv, REG_LED_CNTRL(0)); 108 reg |= SPDLNK_SRC_SEL; 109 reg_writel(priv, reg, REG_LED_CNTRL(0)); 110 } 111 } 112 113 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 114 int port) 115 { 116 unsigned int off; 117 118 switch (port) { 119 case 7: 120 off = P7_IRQ_OFF; 121 break; 122 case 0: 123 /* Port 0 interrupts are located on the first bank */ 124 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 125 return; 126 default: 127 off = P_IRQ_OFF(port); 128 break; 129 } 130 131 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 132 } 133 134 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 135 int port) 136 { 137 unsigned int off; 138 139 switch (port) { 140 case 7: 141 off = P7_IRQ_OFF; 142 break; 143 case 0: 144 /* Port 0 interrupts are located on the first bank */ 145 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 146 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 147 return; 148 default: 149 off = P_IRQ_OFF(port); 150 break; 151 } 152 153 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 154 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 155 } 156 157 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 158 struct phy_device *phy) 159 { 160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 161 unsigned int i; 162 u32 reg; 163 164 /* Clear the memory power down */ 165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 166 reg &= ~P_TXQ_PSM_VDD(port); 167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 168 169 /* Enable Broadcom tags for that port if requested */ 170 if (priv->brcm_tag_mask & BIT(port)) 171 b53_brcm_hdr_setup(ds, port); 172 173 /* Configure Traffic Class to QoS mapping, allow each priority to map 174 * to a different queue number 175 */ 176 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 177 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 178 reg |= i << (PRT_TO_QID_SHIFT * i); 179 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 180 181 /* Re-enable the GPHY and re-apply workarounds */ 182 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 183 bcm_sf2_gphy_enable_set(ds, true); 184 if (phy) { 185 /* if phy_stop() has been called before, phy 186 * will be in halted state, and phy_start() 187 * will call resume. 188 * 189 * the resume path does not configure back 190 * autoneg settings, and since we hard reset 191 * the phy manually here, we need to reset the 192 * state machine also. 193 */ 194 phy->state = PHY_READY; 195 phy_init_hw(phy); 196 } 197 } 198 199 /* Enable MoCA port interrupts to get notified */ 200 if (port == priv->moca_port) 201 bcm_sf2_port_intr_enable(priv, port); 202 203 /* Set per-queue pause threshold to 32 */ 204 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 205 206 /* Set ACB threshold to 24 */ 207 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 208 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 209 SF2_NUM_EGRESS_QUEUES + i)); 210 reg &= ~XOFF_THRESHOLD_MASK; 211 reg |= 24; 212 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 213 SF2_NUM_EGRESS_QUEUES + i)); 214 } 215 216 return b53_enable_port(ds, port, phy); 217 } 218 219 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port, 220 struct phy_device *phy) 221 { 222 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 223 u32 reg; 224 225 if (priv->wol_ports_mask & (1 << port)) 226 return; 227 228 if (port == priv->moca_port) 229 bcm_sf2_port_intr_disable(priv, port); 230 231 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 232 bcm_sf2_gphy_enable_set(ds, false); 233 234 b53_disable_port(ds, port, phy); 235 236 /* Power down the port memory */ 237 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 238 reg |= P_TXQ_PSM_VDD(port); 239 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 240 } 241 242 243 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 244 int regnum, u16 val) 245 { 246 int ret = 0; 247 u32 reg; 248 249 reg = reg_readl(priv, REG_SWITCH_CNTRL); 250 reg |= MDIO_MASTER_SEL; 251 reg_writel(priv, reg, REG_SWITCH_CNTRL); 252 253 /* Page << 8 | offset */ 254 reg = 0x70; 255 reg <<= 2; 256 core_writel(priv, addr, reg); 257 258 /* Page << 8 | offset */ 259 reg = 0x80 << 8 | regnum << 1; 260 reg <<= 2; 261 262 if (op) 263 ret = core_readl(priv, reg); 264 else 265 core_writel(priv, val, reg); 266 267 reg = reg_readl(priv, REG_SWITCH_CNTRL); 268 reg &= ~MDIO_MASTER_SEL; 269 reg_writel(priv, reg, REG_SWITCH_CNTRL); 270 271 return ret & 0xffff; 272 } 273 274 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 275 { 276 struct bcm_sf2_priv *priv = bus->priv; 277 278 /* Intercept reads from Broadcom pseudo-PHY address, else, send 279 * them to our master MDIO bus controller 280 */ 281 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 282 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 283 else 284 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 285 } 286 287 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 288 u16 val) 289 { 290 struct bcm_sf2_priv *priv = bus->priv; 291 292 /* Intercept writes to the Broadcom pseudo-PHY address, else, 293 * send them to our master MDIO bus controller 294 */ 295 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 296 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 297 else 298 mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val); 299 300 return 0; 301 } 302 303 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 304 { 305 struct dsa_switch *ds = dev_id; 306 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 307 308 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 309 ~priv->irq0_mask; 310 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 311 312 return IRQ_HANDLED; 313 } 314 315 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 316 { 317 struct dsa_switch *ds = dev_id; 318 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 319 320 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 321 ~priv->irq1_mask; 322 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 323 324 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 325 priv->port_sts[7].link = true; 326 dsa_port_phylink_mac_change(ds, 7, true); 327 } 328 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 329 priv->port_sts[7].link = false; 330 dsa_port_phylink_mac_change(ds, 7, false); 331 } 332 333 return IRQ_HANDLED; 334 } 335 336 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 337 { 338 unsigned int timeout = 1000; 339 u32 reg; 340 341 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 342 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 343 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 344 345 do { 346 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 347 if (!(reg & SOFTWARE_RESET)) 348 break; 349 350 usleep_range(1000, 2000); 351 } while (timeout-- > 0); 352 353 if (timeout == 0) 354 return -ETIMEDOUT; 355 356 return 0; 357 } 358 359 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 360 { 361 intrl2_0_mask_set(priv, 0xffffffff); 362 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 363 intrl2_1_mask_set(priv, 0xffffffff); 364 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 365 } 366 367 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 368 struct device_node *dn) 369 { 370 struct device_node *port; 371 int mode; 372 unsigned int port_num; 373 374 priv->moca_port = -1; 375 376 for_each_available_child_of_node(dn, port) { 377 if (of_property_read_u32(port, "reg", &port_num)) 378 continue; 379 380 /* Internal PHYs get assigned a specific 'phy-mode' property 381 * value: "internal" to help flag them before MDIO probing 382 * has completed, since they might be turned off at that 383 * time 384 */ 385 mode = of_get_phy_mode(port); 386 if (mode < 0) 387 continue; 388 389 if (mode == PHY_INTERFACE_MODE_INTERNAL) 390 priv->int_phy_mask |= 1 << port_num; 391 392 if (mode == PHY_INTERFACE_MODE_MOCA) 393 priv->moca_port = port_num; 394 395 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 396 priv->brcm_tag_mask |= 1 << port_num; 397 } 398 } 399 400 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 401 { 402 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 403 struct device_node *dn; 404 static int index; 405 int err; 406 407 /* Find our integrated MDIO bus node */ 408 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 409 priv->master_mii_bus = of_mdio_find_bus(dn); 410 if (!priv->master_mii_bus) 411 return -EPROBE_DEFER; 412 413 get_device(&priv->master_mii_bus->dev); 414 priv->master_mii_dn = dn; 415 416 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 417 if (!priv->slave_mii_bus) 418 return -ENOMEM; 419 420 priv->slave_mii_bus->priv = priv; 421 priv->slave_mii_bus->name = "sf2 slave mii"; 422 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 423 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 424 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 425 index++); 426 priv->slave_mii_bus->dev.of_node = dn; 427 428 /* Include the pseudo-PHY address to divert reads towards our 429 * workaround. This is only required for 7445D0, since 7445E0 430 * disconnects the internal switch pseudo-PHY such that we can use the 431 * regular SWITCH_MDIO master controller instead. 432 * 433 * Here we flag the pseudo PHY as needing special treatment and would 434 * otherwise make all other PHY read/writes go to the master MDIO bus 435 * controller that comes with this switch backed by the "mdio-unimac" 436 * driver. 437 */ 438 if (of_machine_is_compatible("brcm,bcm7445d0")) 439 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 440 else 441 priv->indir_phy_mask = 0; 442 443 ds->phys_mii_mask = priv->indir_phy_mask; 444 ds->slave_mii_bus = priv->slave_mii_bus; 445 priv->slave_mii_bus->parent = ds->dev->parent; 446 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 447 448 err = of_mdiobus_register(priv->slave_mii_bus, dn); 449 if (err && dn) 450 of_node_put(dn); 451 452 return err; 453 } 454 455 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 456 { 457 mdiobus_unregister(priv->slave_mii_bus); 458 if (priv->master_mii_dn) 459 of_node_put(priv->master_mii_dn); 460 } 461 462 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 463 { 464 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 465 466 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 467 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 468 * the REG_PHY_REVISION register layout is. 469 */ 470 471 return priv->hw_params.gphy_rev; 472 } 473 474 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 475 unsigned long *supported, 476 struct phylink_link_state *state) 477 { 478 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 479 480 if (!phy_interface_mode_is_rgmii(state->interface) && 481 state->interface != PHY_INTERFACE_MODE_MII && 482 state->interface != PHY_INTERFACE_MODE_REVMII && 483 state->interface != PHY_INTERFACE_MODE_GMII && 484 state->interface != PHY_INTERFACE_MODE_INTERNAL && 485 state->interface != PHY_INTERFACE_MODE_MOCA) { 486 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 487 dev_err(ds->dev, 488 "Unsupported interface: %d\n", state->interface); 489 return; 490 } 491 492 /* Allow all the expected bits */ 493 phylink_set(mask, Autoneg); 494 phylink_set_port_modes(mask); 495 phylink_set(mask, Pause); 496 phylink_set(mask, Asym_Pause); 497 498 /* With the exclusion of MII and Reverse MII, we support Gigabit, 499 * including Half duplex 500 */ 501 if (state->interface != PHY_INTERFACE_MODE_MII && 502 state->interface != PHY_INTERFACE_MODE_REVMII) { 503 phylink_set(mask, 1000baseT_Full); 504 phylink_set(mask, 1000baseT_Half); 505 } 506 507 phylink_set(mask, 10baseT_Half); 508 phylink_set(mask, 10baseT_Full); 509 phylink_set(mask, 100baseT_Half); 510 phylink_set(mask, 100baseT_Full); 511 512 bitmap_and(supported, supported, mask, 513 __ETHTOOL_LINK_MODE_MASK_NBITS); 514 bitmap_and(state->advertising, state->advertising, mask, 515 __ETHTOOL_LINK_MODE_MASK_NBITS); 516 } 517 518 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 519 unsigned int mode, 520 const struct phylink_link_state *state) 521 { 522 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 523 u32 id_mode_dis = 0, port_mode; 524 u32 reg, offset; 525 526 if (priv->type == BCM7445_DEVICE_ID) 527 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 528 else 529 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 530 531 switch (state->interface) { 532 case PHY_INTERFACE_MODE_RGMII: 533 id_mode_dis = 1; 534 /* fallthrough */ 535 case PHY_INTERFACE_MODE_RGMII_TXID: 536 port_mode = EXT_GPHY; 537 break; 538 case PHY_INTERFACE_MODE_MII: 539 port_mode = EXT_EPHY; 540 break; 541 case PHY_INTERFACE_MODE_REVMII: 542 port_mode = EXT_REVMII; 543 break; 544 default: 545 /* all other PHYs: internal and MoCA */ 546 goto force_link; 547 } 548 549 /* Clear id_mode_dis bit, and the existing port mode, let 550 * RGMII_MODE_EN bet set by mac_link_{up,down} 551 */ 552 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 553 reg &= ~ID_MODE_DIS; 554 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 555 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 556 557 reg |= port_mode; 558 if (id_mode_dis) 559 reg |= ID_MODE_DIS; 560 561 if (state->pause & MLO_PAUSE_TXRX_MASK) { 562 if (state->pause & MLO_PAUSE_TX) 563 reg |= TX_PAUSE_EN; 564 reg |= RX_PAUSE_EN; 565 } 566 567 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 568 569 force_link: 570 /* Force link settings detected from the PHY */ 571 reg = SW_OVERRIDE; 572 switch (state->speed) { 573 case SPEED_1000: 574 reg |= SPDSTS_1000 << SPEED_SHIFT; 575 break; 576 case SPEED_100: 577 reg |= SPDSTS_100 << SPEED_SHIFT; 578 break; 579 } 580 581 if (state->link) 582 reg |= LINK_STS; 583 if (state->duplex == DUPLEX_FULL) 584 reg |= DUPLX_MODE; 585 586 core_writel(priv, reg, offset); 587 } 588 589 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 590 phy_interface_t interface, bool link) 591 { 592 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 593 u32 reg; 594 595 if (!phy_interface_mode_is_rgmii(interface) && 596 interface != PHY_INTERFACE_MODE_MII && 597 interface != PHY_INTERFACE_MODE_REVMII) 598 return; 599 600 /* If the link is down, just disable the interface to conserve power */ 601 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 602 if (link) 603 reg |= RGMII_MODE_EN; 604 else 605 reg &= ~RGMII_MODE_EN; 606 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 607 } 608 609 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 610 unsigned int mode, 611 phy_interface_t interface) 612 { 613 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 614 } 615 616 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 617 unsigned int mode, 618 phy_interface_t interface, 619 struct phy_device *phydev) 620 { 621 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 622 struct ethtool_eee *p = &priv->dev->ports[port].eee; 623 624 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 625 626 if (mode == MLO_AN_PHY && phydev) 627 p->eee_enabled = b53_eee_init(ds, port, phydev); 628 } 629 630 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 631 struct phylink_link_state *status) 632 { 633 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 634 635 status->link = false; 636 637 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 638 * which means that we need to force the link at the port override 639 * level to get the data to flow. We do use what the interrupt handler 640 * did determine before. 641 * 642 * For the other ports, we just force the link status, since this is 643 * a fixed PHY device. 644 */ 645 if (port == priv->moca_port) { 646 status->link = priv->port_sts[port].link; 647 /* For MoCA interfaces, also force a link down notification 648 * since some version of the user-space daemon (mocad) use 649 * cmd->autoneg to force the link, which messes up the PHY 650 * state machine and make it go in PHY_FORCING state instead. 651 */ 652 if (!status->link) 653 netif_carrier_off(ds->ports[port].slave); 654 status->duplex = DUPLEX_FULL; 655 } else { 656 status->link = true; 657 } 658 } 659 660 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 661 { 662 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 663 u32 reg; 664 665 /* Enable ACB globally */ 666 reg = acb_readl(priv, ACB_CONTROL); 667 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 668 acb_writel(priv, reg, ACB_CONTROL); 669 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 670 reg |= ACB_EN | ACB_ALGORITHM; 671 acb_writel(priv, reg, ACB_CONTROL); 672 } 673 674 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 675 { 676 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 677 unsigned int port; 678 679 bcm_sf2_intr_disable(priv); 680 681 /* Disable all ports physically present including the IMP 682 * port, the other ones have already been disabled during 683 * bcm_sf2_sw_setup 684 */ 685 for (port = 0; port < DSA_MAX_PORTS; port++) { 686 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 687 bcm_sf2_port_disable(ds, port, NULL); 688 } 689 690 return 0; 691 } 692 693 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 694 { 695 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 696 unsigned int port; 697 int ret; 698 699 ret = bcm_sf2_sw_rst(priv); 700 if (ret) { 701 pr_err("%s: failed to software reset switch\n", __func__); 702 return ret; 703 } 704 705 if (priv->hw_params.num_gphy == 1) 706 bcm_sf2_gphy_enable_set(ds, true); 707 708 for (port = 0; port < DSA_MAX_PORTS; port++) { 709 if (dsa_is_user_port(ds, port)) 710 bcm_sf2_port_setup(ds, port, NULL); 711 else if (dsa_is_cpu_port(ds, port)) 712 bcm_sf2_imp_setup(ds, port); 713 } 714 715 bcm_sf2_enable_acb(ds); 716 717 return 0; 718 } 719 720 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 721 struct ethtool_wolinfo *wol) 722 { 723 struct net_device *p = ds->ports[port].cpu_dp->master; 724 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 725 struct ethtool_wolinfo pwol; 726 727 /* Get the parent device WoL settings */ 728 p->ethtool_ops->get_wol(p, &pwol); 729 730 /* Advertise the parent device supported settings */ 731 wol->supported = pwol.supported; 732 memset(&wol->sopass, 0, sizeof(wol->sopass)); 733 734 if (pwol.wolopts & WAKE_MAGICSECURE) 735 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 736 737 if (priv->wol_ports_mask & (1 << port)) 738 wol->wolopts = pwol.wolopts; 739 else 740 wol->wolopts = 0; 741 } 742 743 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 744 struct ethtool_wolinfo *wol) 745 { 746 struct net_device *p = ds->ports[port].cpu_dp->master; 747 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 748 s8 cpu_port = ds->ports[port].cpu_dp->index; 749 struct ethtool_wolinfo pwol; 750 751 p->ethtool_ops->get_wol(p, &pwol); 752 if (wol->wolopts & ~pwol.supported) 753 return -EINVAL; 754 755 if (wol->wolopts) 756 priv->wol_ports_mask |= (1 << port); 757 else 758 priv->wol_ports_mask &= ~(1 << port); 759 760 /* If we have at least one port enabled, make sure the CPU port 761 * is also enabled. If the CPU port is the last one enabled, we disable 762 * it since this configuration does not make sense. 763 */ 764 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 765 priv->wol_ports_mask |= (1 << cpu_port); 766 else 767 priv->wol_ports_mask &= ~(1 << cpu_port); 768 769 return p->ethtool_ops->set_wol(p, wol); 770 } 771 772 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 773 { 774 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 775 unsigned int port; 776 777 /* Enable all valid ports and disable those unused */ 778 for (port = 0; port < priv->hw_params.num_ports; port++) { 779 /* IMP port receives special treatment */ 780 if (dsa_is_user_port(ds, port)) 781 bcm_sf2_port_setup(ds, port, NULL); 782 else if (dsa_is_cpu_port(ds, port)) 783 bcm_sf2_imp_setup(ds, port); 784 else 785 bcm_sf2_port_disable(ds, port, NULL); 786 } 787 788 b53_configure_vlan(ds); 789 bcm_sf2_enable_acb(ds); 790 791 return 0; 792 } 793 794 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 795 * register basis so we need to translate that into an address that the 796 * bus-glue understands. 797 */ 798 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 799 800 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 801 u8 *val) 802 { 803 struct bcm_sf2_priv *priv = dev->priv; 804 805 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 806 807 return 0; 808 } 809 810 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 811 u16 *val) 812 { 813 struct bcm_sf2_priv *priv = dev->priv; 814 815 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 816 817 return 0; 818 } 819 820 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 821 u32 *val) 822 { 823 struct bcm_sf2_priv *priv = dev->priv; 824 825 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 826 827 return 0; 828 } 829 830 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 831 u64 *val) 832 { 833 struct bcm_sf2_priv *priv = dev->priv; 834 835 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 836 837 return 0; 838 } 839 840 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 841 u8 value) 842 { 843 struct bcm_sf2_priv *priv = dev->priv; 844 845 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 846 847 return 0; 848 } 849 850 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 851 u16 value) 852 { 853 struct bcm_sf2_priv *priv = dev->priv; 854 855 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 856 857 return 0; 858 } 859 860 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 861 u32 value) 862 { 863 struct bcm_sf2_priv *priv = dev->priv; 864 865 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 866 867 return 0; 868 } 869 870 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 871 u64 value) 872 { 873 struct bcm_sf2_priv *priv = dev->priv; 874 875 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 876 877 return 0; 878 } 879 880 static const struct b53_io_ops bcm_sf2_io_ops = { 881 .read8 = bcm_sf2_core_read8, 882 .read16 = bcm_sf2_core_read16, 883 .read32 = bcm_sf2_core_read32, 884 .read48 = bcm_sf2_core_read64, 885 .read64 = bcm_sf2_core_read64, 886 .write8 = bcm_sf2_core_write8, 887 .write16 = bcm_sf2_core_write16, 888 .write32 = bcm_sf2_core_write32, 889 .write48 = bcm_sf2_core_write64, 890 .write64 = bcm_sf2_core_write64, 891 }; 892 893 static const struct dsa_switch_ops bcm_sf2_ops = { 894 .get_tag_protocol = b53_get_tag_protocol, 895 .setup = bcm_sf2_sw_setup, 896 .get_strings = b53_get_strings, 897 .get_ethtool_stats = b53_get_ethtool_stats, 898 .get_sset_count = b53_get_sset_count, 899 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 900 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 901 .phylink_validate = bcm_sf2_sw_validate, 902 .phylink_mac_config = bcm_sf2_sw_mac_config, 903 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 904 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 905 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 906 .suspend = bcm_sf2_sw_suspend, 907 .resume = bcm_sf2_sw_resume, 908 .get_wol = bcm_sf2_sw_get_wol, 909 .set_wol = bcm_sf2_sw_set_wol, 910 .port_enable = bcm_sf2_port_setup, 911 .port_disable = bcm_sf2_port_disable, 912 .get_mac_eee = b53_get_mac_eee, 913 .set_mac_eee = b53_set_mac_eee, 914 .port_bridge_join = b53_br_join, 915 .port_bridge_leave = b53_br_leave, 916 .port_stp_state_set = b53_br_set_stp_state, 917 .port_fast_age = b53_br_fast_age, 918 .port_vlan_filtering = b53_vlan_filtering, 919 .port_vlan_prepare = b53_vlan_prepare, 920 .port_vlan_add = b53_vlan_add, 921 .port_vlan_del = b53_vlan_del, 922 .port_fdb_dump = b53_fdb_dump, 923 .port_fdb_add = b53_fdb_add, 924 .port_fdb_del = b53_fdb_del, 925 .get_rxnfc = bcm_sf2_get_rxnfc, 926 .set_rxnfc = bcm_sf2_set_rxnfc, 927 .port_mirror_add = b53_mirror_add, 928 .port_mirror_del = b53_mirror_del, 929 }; 930 931 struct bcm_sf2_of_data { 932 u32 type; 933 const u16 *reg_offsets; 934 unsigned int core_reg_align; 935 unsigned int num_cfp_rules; 936 }; 937 938 /* Register offsets for the SWITCH_REG_* block */ 939 static const u16 bcm_sf2_7445_reg_offsets[] = { 940 [REG_SWITCH_CNTRL] = 0x00, 941 [REG_SWITCH_STATUS] = 0x04, 942 [REG_DIR_DATA_WRITE] = 0x08, 943 [REG_DIR_DATA_READ] = 0x0C, 944 [REG_SWITCH_REVISION] = 0x18, 945 [REG_PHY_REVISION] = 0x1C, 946 [REG_SPHY_CNTRL] = 0x2C, 947 [REG_RGMII_0_CNTRL] = 0x34, 948 [REG_RGMII_1_CNTRL] = 0x40, 949 [REG_RGMII_2_CNTRL] = 0x4c, 950 [REG_LED_0_CNTRL] = 0x90, 951 [REG_LED_1_CNTRL] = 0x94, 952 [REG_LED_2_CNTRL] = 0x98, 953 }; 954 955 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 956 .type = BCM7445_DEVICE_ID, 957 .core_reg_align = 0, 958 .reg_offsets = bcm_sf2_7445_reg_offsets, 959 .num_cfp_rules = 256, 960 }; 961 962 static const u16 bcm_sf2_7278_reg_offsets[] = { 963 [REG_SWITCH_CNTRL] = 0x00, 964 [REG_SWITCH_STATUS] = 0x04, 965 [REG_DIR_DATA_WRITE] = 0x08, 966 [REG_DIR_DATA_READ] = 0x0c, 967 [REG_SWITCH_REVISION] = 0x10, 968 [REG_PHY_REVISION] = 0x14, 969 [REG_SPHY_CNTRL] = 0x24, 970 [REG_RGMII_0_CNTRL] = 0xe0, 971 [REG_RGMII_1_CNTRL] = 0xec, 972 [REG_RGMII_2_CNTRL] = 0xf8, 973 [REG_LED_0_CNTRL] = 0x40, 974 [REG_LED_1_CNTRL] = 0x4c, 975 [REG_LED_2_CNTRL] = 0x58, 976 }; 977 978 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 979 .type = BCM7278_DEVICE_ID, 980 .core_reg_align = 1, 981 .reg_offsets = bcm_sf2_7278_reg_offsets, 982 .num_cfp_rules = 128, 983 }; 984 985 static const struct of_device_id bcm_sf2_of_match[] = { 986 { .compatible = "brcm,bcm7445-switch-v4.0", 987 .data = &bcm_sf2_7445_data 988 }, 989 { .compatible = "brcm,bcm7278-switch-v4.0", 990 .data = &bcm_sf2_7278_data 991 }, 992 { .compatible = "brcm,bcm7278-switch-v4.8", 993 .data = &bcm_sf2_7278_data 994 }, 995 { /* sentinel */ }, 996 }; 997 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 998 999 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1000 { 1001 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1002 struct device_node *dn = pdev->dev.of_node; 1003 const struct of_device_id *of_id = NULL; 1004 const struct bcm_sf2_of_data *data; 1005 struct b53_platform_data *pdata; 1006 struct dsa_switch_ops *ops; 1007 struct bcm_sf2_priv *priv; 1008 struct b53_device *dev; 1009 struct dsa_switch *ds; 1010 void __iomem **base; 1011 struct resource *r; 1012 unsigned int i; 1013 u32 reg, rev; 1014 int ret; 1015 1016 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1017 if (!priv) 1018 return -ENOMEM; 1019 1020 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1021 if (!ops) 1022 return -ENOMEM; 1023 1024 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1025 if (!dev) 1026 return -ENOMEM; 1027 1028 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1029 if (!pdata) 1030 return -ENOMEM; 1031 1032 of_id = of_match_node(bcm_sf2_of_match, dn); 1033 if (!of_id || !of_id->data) 1034 return -EINVAL; 1035 1036 data = of_id->data; 1037 1038 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1039 priv->type = data->type; 1040 priv->reg_offsets = data->reg_offsets; 1041 priv->core_reg_align = data->core_reg_align; 1042 priv->num_cfp_rules = data->num_cfp_rules; 1043 1044 /* Auto-detection using standard registers will not work, so 1045 * provide an indication of what kind of device we are for 1046 * b53_common to work with 1047 */ 1048 pdata->chip_id = priv->type; 1049 dev->pdata = pdata; 1050 1051 priv->dev = dev; 1052 ds = dev->ds; 1053 ds->ops = &bcm_sf2_ops; 1054 1055 /* Advertise the 8 egress queues */ 1056 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1057 1058 dev_set_drvdata(&pdev->dev, priv); 1059 1060 spin_lock_init(&priv->indir_lock); 1061 mutex_init(&priv->stats_mutex); 1062 mutex_init(&priv->cfp.lock); 1063 1064 /* CFP rule #0 cannot be used for specific classifications, flag it as 1065 * permanently used 1066 */ 1067 set_bit(0, priv->cfp.used); 1068 set_bit(0, priv->cfp.unique); 1069 1070 bcm_sf2_identify_ports(priv, dn->child); 1071 1072 priv->irq0 = irq_of_parse_and_map(dn, 0); 1073 priv->irq1 = irq_of_parse_and_map(dn, 1); 1074 1075 base = &priv->core; 1076 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1077 r = platform_get_resource(pdev, IORESOURCE_MEM, i); 1078 *base = devm_ioremap_resource(&pdev->dev, r); 1079 if (IS_ERR(*base)) { 1080 pr_err("unable to find register: %s\n", reg_names[i]); 1081 return PTR_ERR(*base); 1082 } 1083 base++; 1084 } 1085 1086 ret = bcm_sf2_sw_rst(priv); 1087 if (ret) { 1088 pr_err("unable to software reset switch: %d\n", ret); 1089 return ret; 1090 } 1091 1092 ret = bcm_sf2_mdio_register(ds); 1093 if (ret) { 1094 pr_err("failed to register MDIO bus\n"); 1095 return ret; 1096 } 1097 1098 ret = bcm_sf2_cfp_rst(priv); 1099 if (ret) { 1100 pr_err("failed to reset CFP\n"); 1101 goto out_mdio; 1102 } 1103 1104 /* Disable all interrupts and request them */ 1105 bcm_sf2_intr_disable(priv); 1106 1107 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1108 "switch_0", ds); 1109 if (ret < 0) { 1110 pr_err("failed to request switch_0 IRQ\n"); 1111 goto out_mdio; 1112 } 1113 1114 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1115 "switch_1", ds); 1116 if (ret < 0) { 1117 pr_err("failed to request switch_1 IRQ\n"); 1118 goto out_mdio; 1119 } 1120 1121 /* Reset the MIB counters */ 1122 reg = core_readl(priv, CORE_GMNCFGCFG); 1123 reg |= RST_MIB_CNT; 1124 core_writel(priv, reg, CORE_GMNCFGCFG); 1125 reg &= ~RST_MIB_CNT; 1126 core_writel(priv, reg, CORE_GMNCFGCFG); 1127 1128 /* Get the maximum number of ports for this switch */ 1129 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1130 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1131 priv->hw_params.num_ports = DSA_MAX_PORTS; 1132 1133 /* Assume a single GPHY setup if we can't read that property */ 1134 if (of_property_read_u32(dn, "brcm,num-gphy", 1135 &priv->hw_params.num_gphy)) 1136 priv->hw_params.num_gphy = 1; 1137 1138 rev = reg_readl(priv, REG_SWITCH_REVISION); 1139 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1140 SWITCH_TOP_REV_MASK; 1141 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1142 1143 rev = reg_readl(priv, REG_PHY_REVISION); 1144 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1145 1146 ret = b53_switch_register(dev); 1147 if (ret) 1148 goto out_mdio; 1149 1150 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n", 1151 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1152 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1153 priv->core, priv->irq0, priv->irq1); 1154 1155 return 0; 1156 1157 out_mdio: 1158 bcm_sf2_mdio_unregister(priv); 1159 return ret; 1160 } 1161 1162 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1163 { 1164 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1165 1166 /* Disable all ports and interrupts */ 1167 priv->wol_ports_mask = 0; 1168 bcm_sf2_sw_suspend(priv->dev->ds); 1169 dsa_unregister_switch(priv->dev->ds); 1170 bcm_sf2_mdio_unregister(priv); 1171 1172 return 0; 1173 } 1174 1175 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1176 { 1177 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1178 1179 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1180 * successful MDIO bus scan to occur. If we did turn off the GPHY 1181 * before (e.g: port_disable), this will also power it back on. 1182 * 1183 * Do not rely on kexec_in_progress, just power the PHY on. 1184 */ 1185 if (priv->hw_params.num_gphy == 1) 1186 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1187 } 1188 1189 #ifdef CONFIG_PM_SLEEP 1190 static int bcm_sf2_suspend(struct device *dev) 1191 { 1192 struct platform_device *pdev = to_platform_device(dev); 1193 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1194 1195 return dsa_switch_suspend(priv->dev->ds); 1196 } 1197 1198 static int bcm_sf2_resume(struct device *dev) 1199 { 1200 struct platform_device *pdev = to_platform_device(dev); 1201 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1202 1203 return dsa_switch_resume(priv->dev->ds); 1204 } 1205 #endif /* CONFIG_PM_SLEEP */ 1206 1207 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1208 bcm_sf2_suspend, bcm_sf2_resume); 1209 1210 1211 static struct platform_driver bcm_sf2_driver = { 1212 .probe = bcm_sf2_sw_probe, 1213 .remove = bcm_sf2_sw_remove, 1214 .shutdown = bcm_sf2_sw_shutdown, 1215 .driver = { 1216 .name = "brcm-sf2", 1217 .of_match_table = bcm_sf2_of_match, 1218 .pm = &bcm_sf2_pm_ops, 1219 }, 1220 }; 1221 module_platform_driver(bcm_sf2_driver); 1222 1223 MODULE_AUTHOR("Broadcom Corporation"); 1224 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1225 MODULE_LICENSE("GPL"); 1226 MODULE_ALIAS("platform:brcm-sf2"); 1227