1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <net/dsa.h> 24 #include <linux/ethtool.h> 25 #include <linux/if_bridge.h> 26 #include <linux/brcmphy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/platform_data/b53.h> 29 30 #include "bcm_sf2.h" 31 #include "bcm_sf2_regs.h" 32 #include "b53/b53_priv.h" 33 #include "b53/b53_regs.h" 34 35 static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port) 36 { 37 switch (priv->type) { 38 case BCM4908_DEVICE_ID: 39 switch (port) { 40 case 7: 41 return REG_RGMII_11_CNTRL; 42 default: 43 break; 44 } 45 break; 46 default: 47 switch (port) { 48 case 0: 49 return REG_RGMII_0_CNTRL; 50 case 1: 51 return REG_RGMII_1_CNTRL; 52 case 2: 53 return REG_RGMII_2_CNTRL; 54 default: 55 break; 56 } 57 } 58 59 WARN_ONCE(1, "Unsupported port %d\n", port); 60 61 /* RO fallback reg */ 62 return REG_SWITCH_STATUS; 63 } 64 65 static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port) 66 { 67 switch (port) { 68 case 0: 69 return REG_LED_0_CNTRL; 70 case 1: 71 return REG_LED_1_CNTRL; 72 case 2: 73 return REG_LED_2_CNTRL; 74 } 75 76 switch (priv->type) { 77 case BCM4908_DEVICE_ID: 78 switch (port) { 79 case 3: 80 return REG_LED_3_CNTRL; 81 case 7: 82 return REG_LED_4_CNTRL; 83 default: 84 break; 85 } 86 break; 87 default: 88 break; 89 } 90 91 WARN_ONCE(1, "Unsupported port %d\n", port); 92 93 /* RO fallback reg */ 94 return REG_SWITCH_STATUS; 95 } 96 97 /* Return the number of active ports, not counting the IMP (CPU) port */ 98 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds) 99 { 100 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 101 unsigned int port, count = 0; 102 103 for (port = 0; port < ds->num_ports; port++) { 104 if (dsa_is_cpu_port(ds, port)) 105 continue; 106 if (priv->port_sts[port].enabled) 107 count++; 108 } 109 110 return count; 111 } 112 113 static void bcm_sf2_recalc_clock(struct dsa_switch *ds) 114 { 115 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 116 unsigned long new_rate; 117 unsigned int ports_active; 118 /* Frequenty in Mhz */ 119 static const unsigned long rate_table[] = { 120 59220000, 121 60820000, 122 62500000, 123 62500000, 124 }; 125 126 ports_active = bcm_sf2_num_active_ports(ds); 127 if (ports_active == 0 || !priv->clk_mdiv) 128 return; 129 130 /* If we overflow our table, just use the recommended operational 131 * frequency 132 */ 133 if (ports_active > ARRAY_SIZE(rate_table)) 134 new_rate = 90000000; 135 else 136 new_rate = rate_table[ports_active - 1]; 137 clk_set_rate(priv->clk_mdiv, new_rate); 138 } 139 140 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 141 { 142 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 143 unsigned int i; 144 u32 reg, offset; 145 146 /* Enable the port memories */ 147 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 148 reg &= ~P_TXQ_PSM_VDD(port); 149 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 150 151 /* Enable forwarding */ 152 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 153 154 /* Enable IMP port in dumb mode */ 155 reg = core_readl(priv, CORE_SWITCH_CTRL); 156 reg |= MII_DUMB_FWDG_EN; 157 core_writel(priv, reg, CORE_SWITCH_CTRL); 158 159 /* Configure Traffic Class to QoS mapping, allow each priority to map 160 * to a different queue number 161 */ 162 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 163 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 164 reg |= i << (PRT_TO_QID_SHIFT * i); 165 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 166 167 b53_brcm_hdr_setup(ds, port); 168 169 if (port == 8) { 170 if (priv->type == BCM4908_DEVICE_ID || 171 priv->type == BCM7445_DEVICE_ID) 172 offset = CORE_STS_OVERRIDE_IMP; 173 else 174 offset = CORE_STS_OVERRIDE_IMP2; 175 176 /* Force link status for IMP port */ 177 reg = core_readl(priv, offset); 178 reg |= (MII_SW_OR | LINK_STS); 179 if (priv->type == BCM4908_DEVICE_ID) 180 reg |= GMII_SPEED_UP_2G; 181 else 182 reg &= ~GMII_SPEED_UP_2G; 183 core_writel(priv, reg, offset); 184 185 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 186 reg = core_readl(priv, CORE_IMP_CTL); 187 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 188 reg &= ~(RX_DIS | TX_DIS); 189 core_writel(priv, reg, CORE_IMP_CTL); 190 } else { 191 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 192 reg &= ~(RX_DIS | TX_DIS); 193 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 194 } 195 196 priv->port_sts[port].enabled = true; 197 } 198 199 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 200 { 201 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 202 u32 reg; 203 204 reg = reg_readl(priv, REG_SPHY_CNTRL); 205 if (enable) { 206 reg |= PHY_RESET; 207 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 208 reg_writel(priv, reg, REG_SPHY_CNTRL); 209 udelay(21); 210 reg = reg_readl(priv, REG_SPHY_CNTRL); 211 reg &= ~PHY_RESET; 212 } else { 213 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 214 reg_writel(priv, reg, REG_SPHY_CNTRL); 215 mdelay(1); 216 reg |= CK25_DIS; 217 } 218 reg_writel(priv, reg, REG_SPHY_CNTRL); 219 220 /* Use PHY-driven LED signaling */ 221 if (!enable) { 222 u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0); 223 224 if (priv->type == BCM7278_DEVICE_ID || 225 priv->type == BCM7445_DEVICE_ID) { 226 reg = reg_led_readl(priv, led_ctrl, 0); 227 reg |= LED_CNTRL_SPDLNK_SRC_SEL; 228 reg_led_writel(priv, reg, led_ctrl, 0); 229 } 230 } 231 } 232 233 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 234 int port) 235 { 236 unsigned int off; 237 238 switch (port) { 239 case 7: 240 off = P7_IRQ_OFF; 241 break; 242 case 0: 243 /* Port 0 interrupts are located on the first bank */ 244 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 245 return; 246 default: 247 off = P_IRQ_OFF(port); 248 break; 249 } 250 251 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 252 } 253 254 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 255 int port) 256 { 257 unsigned int off; 258 259 switch (port) { 260 case 7: 261 off = P7_IRQ_OFF; 262 break; 263 case 0: 264 /* Port 0 interrupts are located on the first bank */ 265 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 266 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 267 return; 268 default: 269 off = P_IRQ_OFF(port); 270 break; 271 } 272 273 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 274 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 275 } 276 277 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 278 struct phy_device *phy) 279 { 280 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 281 unsigned int i; 282 u32 reg; 283 284 if (!dsa_is_user_port(ds, port)) 285 return 0; 286 287 priv->port_sts[port].enabled = true; 288 289 bcm_sf2_recalc_clock(ds); 290 291 /* Clear the memory power down */ 292 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 293 reg &= ~P_TXQ_PSM_VDD(port); 294 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 295 296 /* Enable Broadcom tags for that port if requested */ 297 if (priv->brcm_tag_mask & BIT(port)) 298 b53_brcm_hdr_setup(ds, port); 299 300 /* Configure Traffic Class to QoS mapping, allow each priority to map 301 * to a different queue number 302 */ 303 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 304 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 305 reg |= i << (PRT_TO_QID_SHIFT * i); 306 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 307 308 /* Re-enable the GPHY and re-apply workarounds */ 309 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 310 bcm_sf2_gphy_enable_set(ds, true); 311 if (phy) { 312 /* if phy_stop() has been called before, phy 313 * will be in halted state, and phy_start() 314 * will call resume. 315 * 316 * the resume path does not configure back 317 * autoneg settings, and since we hard reset 318 * the phy manually here, we need to reset the 319 * state machine also. 320 */ 321 phy->state = PHY_READY; 322 phy_init_hw(phy); 323 } 324 } 325 326 /* Enable MoCA port interrupts to get notified */ 327 if (port == priv->moca_port) 328 bcm_sf2_port_intr_enable(priv, port); 329 330 /* Set per-queue pause threshold to 32 */ 331 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 332 333 /* Set ACB threshold to 24 */ 334 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 335 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 336 SF2_NUM_EGRESS_QUEUES + i)); 337 reg &= ~XOFF_THRESHOLD_MASK; 338 reg |= 24; 339 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 340 SF2_NUM_EGRESS_QUEUES + i)); 341 } 342 343 return b53_enable_port(ds, port, phy); 344 } 345 346 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 347 { 348 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 349 u32 reg; 350 351 /* Disable learning while in WoL mode */ 352 if (priv->wol_ports_mask & (1 << port)) { 353 reg = core_readl(priv, CORE_DIS_LEARN); 354 reg |= BIT(port); 355 core_writel(priv, reg, CORE_DIS_LEARN); 356 return; 357 } 358 359 if (port == priv->moca_port) 360 bcm_sf2_port_intr_disable(priv, port); 361 362 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 363 bcm_sf2_gphy_enable_set(ds, false); 364 365 b53_disable_port(ds, port); 366 367 /* Power down the port memory */ 368 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 369 reg |= P_TXQ_PSM_VDD(port); 370 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 371 372 priv->port_sts[port].enabled = false; 373 374 bcm_sf2_recalc_clock(ds); 375 } 376 377 378 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 379 int regnum, u16 val) 380 { 381 int ret = 0; 382 u32 reg; 383 384 reg = reg_readl(priv, REG_SWITCH_CNTRL); 385 reg |= MDIO_MASTER_SEL; 386 reg_writel(priv, reg, REG_SWITCH_CNTRL); 387 388 /* Page << 8 | offset */ 389 reg = 0x70; 390 reg <<= 2; 391 core_writel(priv, addr, reg); 392 393 /* Page << 8 | offset */ 394 reg = 0x80 << 8 | regnum << 1; 395 reg <<= 2; 396 397 if (op) 398 ret = core_readl(priv, reg); 399 else 400 core_writel(priv, val, reg); 401 402 reg = reg_readl(priv, REG_SWITCH_CNTRL); 403 reg &= ~MDIO_MASTER_SEL; 404 reg_writel(priv, reg, REG_SWITCH_CNTRL); 405 406 return ret & 0xffff; 407 } 408 409 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 410 { 411 struct bcm_sf2_priv *priv = bus->priv; 412 413 /* Intercept reads from Broadcom pseudo-PHY address, else, send 414 * them to our master MDIO bus controller 415 */ 416 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 417 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 418 else 419 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 420 } 421 422 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 423 u16 val) 424 { 425 struct bcm_sf2_priv *priv = bus->priv; 426 427 /* Intercept writes to the Broadcom pseudo-PHY address, else, 428 * send them to our master MDIO bus controller 429 */ 430 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 431 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 432 else 433 return mdiobus_write_nested(priv->master_mii_bus, addr, 434 regnum, val); 435 } 436 437 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 438 { 439 struct dsa_switch *ds = dev_id; 440 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 441 442 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 443 ~priv->irq0_mask; 444 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 445 446 return IRQ_HANDLED; 447 } 448 449 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 450 { 451 struct dsa_switch *ds = dev_id; 452 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 453 454 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 455 ~priv->irq1_mask; 456 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 457 458 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 459 priv->port_sts[7].link = true; 460 dsa_port_phylink_mac_change(ds, 7, true); 461 } 462 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 463 priv->port_sts[7].link = false; 464 dsa_port_phylink_mac_change(ds, 7, false); 465 } 466 467 return IRQ_HANDLED; 468 } 469 470 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 471 { 472 unsigned int timeout = 1000; 473 u32 reg; 474 int ret; 475 476 /* The watchdog reset does not work on 7278, we need to hit the 477 * "external" reset line through the reset controller. 478 */ 479 if (priv->type == BCM7278_DEVICE_ID) { 480 ret = reset_control_assert(priv->rcdev); 481 if (ret) 482 return ret; 483 484 return reset_control_deassert(priv->rcdev); 485 } 486 487 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 488 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 489 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 490 491 do { 492 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 493 if (!(reg & SOFTWARE_RESET)) 494 break; 495 496 usleep_range(1000, 2000); 497 } while (timeout-- > 0); 498 499 if (timeout == 0) 500 return -ETIMEDOUT; 501 502 return 0; 503 } 504 505 static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv) 506 { 507 struct device *dev = priv->dev->ds->dev; 508 int shift; 509 u32 mask; 510 u32 reg; 511 int i; 512 513 mask = BIT(priv->num_crossbar_int_ports) - 1; 514 515 reg = reg_readl(priv, REG_CROSSBAR); 516 switch (priv->type) { 517 case BCM4908_DEVICE_ID: 518 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports; 519 reg &= ~(mask << shift); 520 if (0) /* FIXME */ 521 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift; 522 else if (priv->int_phy_mask & BIT(7)) 523 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift; 524 else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode)) 525 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift; 526 else if (WARN(1, "Invalid port mode\n")) 527 return; 528 break; 529 default: 530 return; 531 } 532 reg_writel(priv, reg, REG_CROSSBAR); 533 534 reg = reg_readl(priv, REG_CROSSBAR); 535 for (i = 0; i < priv->num_crossbar_int_ports; i++) { 536 shift = i * priv->num_crossbar_int_ports; 537 538 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i, 539 (reg >> shift) & mask); 540 } 541 } 542 543 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 544 { 545 intrl2_0_mask_set(priv, 0xffffffff); 546 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 547 intrl2_1_mask_set(priv, 0xffffffff); 548 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 549 } 550 551 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 552 struct device_node *dn) 553 { 554 struct device *dev = priv->dev->ds->dev; 555 struct bcm_sf2_port_status *port_st; 556 struct device_node *port; 557 unsigned int port_num; 558 struct property *prop; 559 int err; 560 561 priv->moca_port = -1; 562 563 for_each_available_child_of_node(dn, port) { 564 if (of_property_read_u32(port, "reg", &port_num)) 565 continue; 566 567 if (port_num >= DSA_MAX_PORTS) { 568 dev_err(dev, "Invalid port number %d\n", port_num); 569 continue; 570 } 571 572 port_st = &priv->port_sts[port_num]; 573 574 /* Internal PHYs get assigned a specific 'phy-mode' property 575 * value: "internal" to help flag them before MDIO probing 576 * has completed, since they might be turned off at that 577 * time 578 */ 579 err = of_get_phy_mode(port, &port_st->mode); 580 if (err) 581 continue; 582 583 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL) 584 priv->int_phy_mask |= 1 << port_num; 585 586 if (port_st->mode == PHY_INTERFACE_MODE_MOCA) 587 priv->moca_port = port_num; 588 589 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 590 priv->brcm_tag_mask |= 1 << port_num; 591 592 /* Ensure that port 5 is not picked up as a DSA CPU port 593 * flavour but a regular port instead. We should be using 594 * devlink to be able to set the port flavour. 595 */ 596 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) { 597 prop = of_find_property(port, "ethernet", NULL); 598 if (prop) 599 of_remove_property(port, prop); 600 } 601 } 602 } 603 604 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 605 { 606 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 607 struct device_node *dn, *child; 608 struct phy_device *phydev; 609 struct property *prop; 610 static int index; 611 int err, reg; 612 613 /* Find our integrated MDIO bus node */ 614 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 615 priv->master_mii_bus = of_mdio_find_bus(dn); 616 if (!priv->master_mii_bus) { 617 of_node_put(dn); 618 return -EPROBE_DEFER; 619 } 620 621 get_device(&priv->master_mii_bus->dev); 622 priv->master_mii_dn = dn; 623 624 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 625 if (!priv->slave_mii_bus) { 626 of_node_put(dn); 627 return -ENOMEM; 628 } 629 630 priv->slave_mii_bus->priv = priv; 631 priv->slave_mii_bus->name = "sf2 slave mii"; 632 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 633 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 634 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 635 index++); 636 priv->slave_mii_bus->dev.of_node = dn; 637 638 /* Include the pseudo-PHY address to divert reads towards our 639 * workaround. This is only required for 7445D0, since 7445E0 640 * disconnects the internal switch pseudo-PHY such that we can use the 641 * regular SWITCH_MDIO master controller instead. 642 * 643 * Here we flag the pseudo PHY as needing special treatment and would 644 * otherwise make all other PHY read/writes go to the master MDIO bus 645 * controller that comes with this switch backed by the "mdio-unimac" 646 * driver. 647 */ 648 if (of_machine_is_compatible("brcm,bcm7445d0")) 649 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0); 650 else 651 priv->indir_phy_mask = 0; 652 653 ds->phys_mii_mask = priv->indir_phy_mask; 654 ds->slave_mii_bus = priv->slave_mii_bus; 655 priv->slave_mii_bus->parent = ds->dev->parent; 656 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 657 658 /* We need to make sure that of_phy_connect() will not work by 659 * removing the 'phandle' and 'linux,phandle' properties and 660 * unregister the existing PHY device that was already registered. 661 */ 662 for_each_available_child_of_node(dn, child) { 663 if (of_property_read_u32(child, "reg", ®) || 664 reg >= PHY_MAX_ADDR) 665 continue; 666 667 if (!(priv->indir_phy_mask & BIT(reg))) 668 continue; 669 670 prop = of_find_property(child, "phandle", NULL); 671 if (prop) 672 of_remove_property(child, prop); 673 674 prop = of_find_property(child, "linux,phandle", NULL); 675 if (prop) 676 of_remove_property(child, prop); 677 678 phydev = of_phy_find_device(child); 679 if (phydev) 680 phy_device_remove(phydev); 681 } 682 683 err = mdiobus_register(priv->slave_mii_bus); 684 if (err && dn) 685 of_node_put(dn); 686 687 return err; 688 } 689 690 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 691 { 692 mdiobus_unregister(priv->slave_mii_bus); 693 of_node_put(priv->master_mii_dn); 694 } 695 696 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 697 { 698 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 699 700 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 701 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 702 * the REG_PHY_REVISION register layout is. 703 */ 704 if (priv->int_phy_mask & BIT(port)) 705 return priv->hw_params.gphy_rev; 706 else 707 return PHY_BRCM_AUTO_PWRDWN_ENABLE | 708 PHY_BRCM_DIS_TXCRXC_NOENRGY | 709 PHY_BRCM_IDDQ_SUSPEND; 710 } 711 712 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 713 unsigned long *supported, 714 struct phylink_link_state *state) 715 { 716 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 717 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 718 719 if (!phy_interface_mode_is_rgmii(state->interface) && 720 state->interface != PHY_INTERFACE_MODE_MII && 721 state->interface != PHY_INTERFACE_MODE_REVMII && 722 state->interface != PHY_INTERFACE_MODE_GMII && 723 state->interface != PHY_INTERFACE_MODE_INTERNAL && 724 state->interface != PHY_INTERFACE_MODE_MOCA) { 725 linkmode_zero(supported); 726 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 727 dev_err(ds->dev, 728 "Unsupported interface: %d for port %d\n", 729 state->interface, port); 730 return; 731 } 732 733 /* Allow all the expected bits */ 734 phylink_set(mask, Autoneg); 735 phylink_set_port_modes(mask); 736 phylink_set(mask, Pause); 737 phylink_set(mask, Asym_Pause); 738 739 /* With the exclusion of MII and Reverse MII, we support Gigabit, 740 * including Half duplex 741 */ 742 if (state->interface != PHY_INTERFACE_MODE_MII && 743 state->interface != PHY_INTERFACE_MODE_REVMII) { 744 phylink_set(mask, 1000baseT_Full); 745 phylink_set(mask, 1000baseT_Half); 746 } 747 748 phylink_set(mask, 10baseT_Half); 749 phylink_set(mask, 10baseT_Full); 750 phylink_set(mask, 100baseT_Half); 751 phylink_set(mask, 100baseT_Full); 752 753 linkmode_and(supported, supported, mask); 754 linkmode_and(state->advertising, state->advertising, mask); 755 } 756 757 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 758 unsigned int mode, 759 const struct phylink_link_state *state) 760 { 761 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 762 u32 id_mode_dis = 0, port_mode; 763 u32 reg_rgmii_ctrl; 764 u32 reg; 765 766 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 767 return; 768 769 switch (state->interface) { 770 case PHY_INTERFACE_MODE_RGMII: 771 id_mode_dis = 1; 772 fallthrough; 773 case PHY_INTERFACE_MODE_RGMII_TXID: 774 port_mode = EXT_GPHY; 775 break; 776 case PHY_INTERFACE_MODE_MII: 777 port_mode = EXT_EPHY; 778 break; 779 case PHY_INTERFACE_MODE_REVMII: 780 port_mode = EXT_REVMII; 781 break; 782 default: 783 /* Nothing required for all other PHYs: internal and MoCA */ 784 return; 785 } 786 787 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 788 789 /* Clear id_mode_dis bit, and the existing port mode, let 790 * RGMII_MODE_EN bet set by mac_link_{up,down} 791 */ 792 reg = reg_readl(priv, reg_rgmii_ctrl); 793 reg &= ~ID_MODE_DIS; 794 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 795 796 reg |= port_mode; 797 if (id_mode_dis) 798 reg |= ID_MODE_DIS; 799 800 reg_writel(priv, reg, reg_rgmii_ctrl); 801 } 802 803 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 804 phy_interface_t interface, bool link) 805 { 806 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 807 u32 reg_rgmii_ctrl; 808 u32 reg; 809 810 if (!phy_interface_mode_is_rgmii(interface) && 811 interface != PHY_INTERFACE_MODE_MII && 812 interface != PHY_INTERFACE_MODE_REVMII) 813 return; 814 815 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 816 817 /* If the link is down, just disable the interface to conserve power */ 818 reg = reg_readl(priv, reg_rgmii_ctrl); 819 if (link) 820 reg |= RGMII_MODE_EN; 821 else 822 reg &= ~RGMII_MODE_EN; 823 reg_writel(priv, reg, reg_rgmii_ctrl); 824 } 825 826 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 827 unsigned int mode, 828 phy_interface_t interface) 829 { 830 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 831 u32 reg, offset; 832 833 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 834 if (priv->type == BCM4908_DEVICE_ID || 835 priv->type == BCM7445_DEVICE_ID) 836 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 837 else 838 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 839 840 reg = core_readl(priv, offset); 841 reg &= ~LINK_STS; 842 core_writel(priv, reg, offset); 843 } 844 845 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 846 } 847 848 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 849 unsigned int mode, 850 phy_interface_t interface, 851 struct phy_device *phydev, 852 int speed, int duplex, 853 bool tx_pause, bool rx_pause) 854 { 855 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 856 struct ethtool_eee *p = &priv->dev->ports[port].eee; 857 858 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 859 860 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 861 u32 reg_rgmii_ctrl = 0; 862 u32 reg, offset; 863 864 if (priv->type == BCM4908_DEVICE_ID || 865 priv->type == BCM7445_DEVICE_ID) 866 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 867 else 868 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 869 870 if (interface == PHY_INTERFACE_MODE_RGMII || 871 interface == PHY_INTERFACE_MODE_RGMII_TXID || 872 interface == PHY_INTERFACE_MODE_MII || 873 interface == PHY_INTERFACE_MODE_REVMII) { 874 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); 875 reg = reg_readl(priv, reg_rgmii_ctrl); 876 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 877 878 if (tx_pause) 879 reg |= TX_PAUSE_EN; 880 if (rx_pause) 881 reg |= RX_PAUSE_EN; 882 883 reg_writel(priv, reg, reg_rgmii_ctrl); 884 } 885 886 reg = SW_OVERRIDE | LINK_STS; 887 switch (speed) { 888 case SPEED_1000: 889 reg |= SPDSTS_1000 << SPEED_SHIFT; 890 break; 891 case SPEED_100: 892 reg |= SPDSTS_100 << SPEED_SHIFT; 893 break; 894 } 895 896 if (duplex == DUPLEX_FULL) 897 reg |= DUPLX_MODE; 898 899 core_writel(priv, reg, offset); 900 } 901 902 if (mode == MLO_AN_PHY && phydev) 903 p->eee_enabled = b53_eee_init(ds, port, phydev); 904 } 905 906 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 907 struct phylink_link_state *status) 908 { 909 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 910 911 status->link = false; 912 913 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 914 * which means that we need to force the link at the port override 915 * level to get the data to flow. We do use what the interrupt handler 916 * did determine before. 917 * 918 * For the other ports, we just force the link status, since this is 919 * a fixed PHY device. 920 */ 921 if (port == priv->moca_port) { 922 status->link = priv->port_sts[port].link; 923 /* For MoCA interfaces, also force a link down notification 924 * since some version of the user-space daemon (mocad) use 925 * cmd->autoneg to force the link, which messes up the PHY 926 * state machine and make it go in PHY_FORCING state instead. 927 */ 928 if (!status->link) 929 netif_carrier_off(dsa_to_port(ds, port)->slave); 930 status->duplex = DUPLEX_FULL; 931 } else { 932 status->link = true; 933 } 934 } 935 936 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 937 { 938 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 939 u32 reg; 940 941 /* Enable ACB globally */ 942 reg = acb_readl(priv, ACB_CONTROL); 943 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 944 acb_writel(priv, reg, ACB_CONTROL); 945 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 946 reg |= ACB_EN | ACB_ALGORITHM; 947 acb_writel(priv, reg, ACB_CONTROL); 948 } 949 950 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 951 { 952 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 953 unsigned int port; 954 955 bcm_sf2_intr_disable(priv); 956 957 /* Disable all ports physically present including the IMP 958 * port, the other ones have already been disabled during 959 * bcm_sf2_sw_setup 960 */ 961 for (port = 0; port < ds->num_ports; port++) { 962 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 963 bcm_sf2_port_disable(ds, port); 964 } 965 966 if (!priv->wol_ports_mask) 967 clk_disable_unprepare(priv->clk); 968 969 return 0; 970 } 971 972 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 973 { 974 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 975 int ret; 976 977 if (!priv->wol_ports_mask) 978 clk_prepare_enable(priv->clk); 979 980 ret = bcm_sf2_sw_rst(priv); 981 if (ret) { 982 pr_err("%s: failed to software reset switch\n", __func__); 983 return ret; 984 } 985 986 bcm_sf2_crossbar_setup(priv); 987 988 ret = bcm_sf2_cfp_resume(ds); 989 if (ret) 990 return ret; 991 992 if (priv->hw_params.num_gphy == 1) 993 bcm_sf2_gphy_enable_set(ds, true); 994 995 ds->ops->setup(ds); 996 997 return 0; 998 } 999 1000 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 1001 struct ethtool_wolinfo *wol) 1002 { 1003 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 1004 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 1005 struct ethtool_wolinfo pwol = { }; 1006 1007 /* Get the parent device WoL settings */ 1008 if (p->ethtool_ops->get_wol) 1009 p->ethtool_ops->get_wol(p, &pwol); 1010 1011 /* Advertise the parent device supported settings */ 1012 wol->supported = pwol.supported; 1013 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1014 1015 if (pwol.wolopts & WAKE_MAGICSECURE) 1016 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 1017 1018 if (priv->wol_ports_mask & (1 << port)) 1019 wol->wolopts = pwol.wolopts; 1020 else 1021 wol->wolopts = 0; 1022 } 1023 1024 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 1025 struct ethtool_wolinfo *wol) 1026 { 1027 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 1028 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 1029 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1030 struct ethtool_wolinfo pwol = { }; 1031 1032 if (p->ethtool_ops->get_wol) 1033 p->ethtool_ops->get_wol(p, &pwol); 1034 if (wol->wolopts & ~pwol.supported) 1035 return -EINVAL; 1036 1037 if (wol->wolopts) 1038 priv->wol_ports_mask |= (1 << port); 1039 else 1040 priv->wol_ports_mask &= ~(1 << port); 1041 1042 /* If we have at least one port enabled, make sure the CPU port 1043 * is also enabled. If the CPU port is the last one enabled, we disable 1044 * it since this configuration does not make sense. 1045 */ 1046 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 1047 priv->wol_ports_mask |= (1 << cpu_port); 1048 else 1049 priv->wol_ports_mask &= ~(1 << cpu_port); 1050 1051 return p->ethtool_ops->set_wol(p, wol); 1052 } 1053 1054 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 1055 { 1056 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 1057 unsigned int port; 1058 1059 /* Enable all valid ports and disable those unused */ 1060 for (port = 0; port < priv->hw_params.num_ports; port++) { 1061 /* IMP port receives special treatment */ 1062 if (dsa_is_user_port(ds, port)) 1063 bcm_sf2_port_setup(ds, port, NULL); 1064 else if (dsa_is_cpu_port(ds, port)) 1065 bcm_sf2_imp_setup(ds, port); 1066 else 1067 bcm_sf2_port_disable(ds, port); 1068 } 1069 1070 b53_configure_vlan(ds); 1071 bcm_sf2_enable_acb(ds); 1072 1073 return b53_setup_devlink_resources(ds); 1074 } 1075 1076 static void bcm_sf2_sw_teardown(struct dsa_switch *ds) 1077 { 1078 dsa_devlink_resources_unregister(ds); 1079 } 1080 1081 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 1082 * register basis so we need to translate that into an address that the 1083 * bus-glue understands. 1084 */ 1085 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 1086 1087 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 1088 u8 *val) 1089 { 1090 struct bcm_sf2_priv *priv = dev->priv; 1091 1092 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1093 1094 return 0; 1095 } 1096 1097 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 1098 u16 *val) 1099 { 1100 struct bcm_sf2_priv *priv = dev->priv; 1101 1102 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1103 1104 return 0; 1105 } 1106 1107 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 1108 u32 *val) 1109 { 1110 struct bcm_sf2_priv *priv = dev->priv; 1111 1112 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1113 1114 return 0; 1115 } 1116 1117 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 1118 u64 *val) 1119 { 1120 struct bcm_sf2_priv *priv = dev->priv; 1121 1122 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1123 1124 return 0; 1125 } 1126 1127 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 1128 u8 value) 1129 { 1130 struct bcm_sf2_priv *priv = dev->priv; 1131 1132 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1133 1134 return 0; 1135 } 1136 1137 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 1138 u16 value) 1139 { 1140 struct bcm_sf2_priv *priv = dev->priv; 1141 1142 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1143 1144 return 0; 1145 } 1146 1147 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 1148 u32 value) 1149 { 1150 struct bcm_sf2_priv *priv = dev->priv; 1151 1152 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1153 1154 return 0; 1155 } 1156 1157 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 1158 u64 value) 1159 { 1160 struct bcm_sf2_priv *priv = dev->priv; 1161 1162 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1163 1164 return 0; 1165 } 1166 1167 static const struct b53_io_ops bcm_sf2_io_ops = { 1168 .read8 = bcm_sf2_core_read8, 1169 .read16 = bcm_sf2_core_read16, 1170 .read32 = bcm_sf2_core_read32, 1171 .read48 = bcm_sf2_core_read64, 1172 .read64 = bcm_sf2_core_read64, 1173 .write8 = bcm_sf2_core_write8, 1174 .write16 = bcm_sf2_core_write16, 1175 .write32 = bcm_sf2_core_write32, 1176 .write48 = bcm_sf2_core_write64, 1177 .write64 = bcm_sf2_core_write64, 1178 }; 1179 1180 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 1181 u32 stringset, uint8_t *data) 1182 { 1183 int cnt = b53_get_sset_count(ds, port, stringset); 1184 1185 b53_get_strings(ds, port, stringset, data); 1186 bcm_sf2_cfp_get_strings(ds, port, stringset, 1187 data + cnt * ETH_GSTRING_LEN); 1188 } 1189 1190 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 1191 uint64_t *data) 1192 { 1193 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 1194 1195 b53_get_ethtool_stats(ds, port, data); 1196 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 1197 } 1198 1199 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 1200 int sset) 1201 { 1202 int cnt = b53_get_sset_count(ds, port, sset); 1203 1204 if (cnt < 0) 1205 return cnt; 1206 1207 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 1208 1209 return cnt; 1210 } 1211 1212 static const struct dsa_switch_ops bcm_sf2_ops = { 1213 .get_tag_protocol = b53_get_tag_protocol, 1214 .setup = bcm_sf2_sw_setup, 1215 .teardown = bcm_sf2_sw_teardown, 1216 .get_strings = bcm_sf2_sw_get_strings, 1217 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 1218 .get_sset_count = bcm_sf2_sw_get_sset_count, 1219 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1220 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 1221 .phylink_validate = bcm_sf2_sw_validate, 1222 .phylink_mac_config = bcm_sf2_sw_mac_config, 1223 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 1224 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 1225 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 1226 .suspend = bcm_sf2_sw_suspend, 1227 .resume = bcm_sf2_sw_resume, 1228 .get_wol = bcm_sf2_sw_get_wol, 1229 .set_wol = bcm_sf2_sw_set_wol, 1230 .port_enable = bcm_sf2_port_setup, 1231 .port_disable = bcm_sf2_port_disable, 1232 .get_mac_eee = b53_get_mac_eee, 1233 .set_mac_eee = b53_set_mac_eee, 1234 .port_bridge_join = b53_br_join, 1235 .port_bridge_leave = b53_br_leave, 1236 .port_pre_bridge_flags = b53_br_flags_pre, 1237 .port_bridge_flags = b53_br_flags, 1238 .port_stp_state_set = b53_br_set_stp_state, 1239 .port_fast_age = b53_br_fast_age, 1240 .port_vlan_filtering = b53_vlan_filtering, 1241 .port_vlan_add = b53_vlan_add, 1242 .port_vlan_del = b53_vlan_del, 1243 .port_fdb_dump = b53_fdb_dump, 1244 .port_fdb_add = b53_fdb_add, 1245 .port_fdb_del = b53_fdb_del, 1246 .get_rxnfc = bcm_sf2_get_rxnfc, 1247 .set_rxnfc = bcm_sf2_set_rxnfc, 1248 .port_mirror_add = b53_mirror_add, 1249 .port_mirror_del = b53_mirror_del, 1250 .port_mdb_add = b53_mdb_add, 1251 .port_mdb_del = b53_mdb_del, 1252 }; 1253 1254 struct bcm_sf2_of_data { 1255 u32 type; 1256 const u16 *reg_offsets; 1257 unsigned int core_reg_align; 1258 unsigned int num_cfp_rules; 1259 unsigned int num_crossbar_int_ports; 1260 }; 1261 1262 static const u16 bcm_sf2_4908_reg_offsets[] = { 1263 [REG_SWITCH_CNTRL] = 0x00, 1264 [REG_SWITCH_STATUS] = 0x04, 1265 [REG_DIR_DATA_WRITE] = 0x08, 1266 [REG_DIR_DATA_READ] = 0x0c, 1267 [REG_SWITCH_REVISION] = 0x10, 1268 [REG_PHY_REVISION] = 0x14, 1269 [REG_SPHY_CNTRL] = 0x24, 1270 [REG_CROSSBAR] = 0xc8, 1271 [REG_RGMII_11_CNTRL] = 0x014c, 1272 [REG_LED_0_CNTRL] = 0x40, 1273 [REG_LED_1_CNTRL] = 0x4c, 1274 [REG_LED_2_CNTRL] = 0x58, 1275 [REG_LED_3_CNTRL] = 0x64, 1276 [REG_LED_4_CNTRL] = 0x88, 1277 [REG_LED_5_CNTRL] = 0xa0, 1278 [REG_LED_AGGREGATE_CTRL] = 0xb8, 1279 1280 }; 1281 1282 static const struct bcm_sf2_of_data bcm_sf2_4908_data = { 1283 .type = BCM4908_DEVICE_ID, 1284 .core_reg_align = 0, 1285 .reg_offsets = bcm_sf2_4908_reg_offsets, 1286 .num_cfp_rules = 256, 1287 .num_crossbar_int_ports = 2, 1288 }; 1289 1290 /* Register offsets for the SWITCH_REG_* block */ 1291 static const u16 bcm_sf2_7445_reg_offsets[] = { 1292 [REG_SWITCH_CNTRL] = 0x00, 1293 [REG_SWITCH_STATUS] = 0x04, 1294 [REG_DIR_DATA_WRITE] = 0x08, 1295 [REG_DIR_DATA_READ] = 0x0C, 1296 [REG_SWITCH_REVISION] = 0x18, 1297 [REG_PHY_REVISION] = 0x1C, 1298 [REG_SPHY_CNTRL] = 0x2C, 1299 [REG_RGMII_0_CNTRL] = 0x34, 1300 [REG_RGMII_1_CNTRL] = 0x40, 1301 [REG_RGMII_2_CNTRL] = 0x4c, 1302 [REG_LED_0_CNTRL] = 0x90, 1303 [REG_LED_1_CNTRL] = 0x94, 1304 [REG_LED_2_CNTRL] = 0x98, 1305 }; 1306 1307 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1308 .type = BCM7445_DEVICE_ID, 1309 .core_reg_align = 0, 1310 .reg_offsets = bcm_sf2_7445_reg_offsets, 1311 .num_cfp_rules = 256, 1312 }; 1313 1314 static const u16 bcm_sf2_7278_reg_offsets[] = { 1315 [REG_SWITCH_CNTRL] = 0x00, 1316 [REG_SWITCH_STATUS] = 0x04, 1317 [REG_DIR_DATA_WRITE] = 0x08, 1318 [REG_DIR_DATA_READ] = 0x0c, 1319 [REG_SWITCH_REVISION] = 0x10, 1320 [REG_PHY_REVISION] = 0x14, 1321 [REG_SPHY_CNTRL] = 0x24, 1322 [REG_RGMII_0_CNTRL] = 0xe0, 1323 [REG_RGMII_1_CNTRL] = 0xec, 1324 [REG_RGMII_2_CNTRL] = 0xf8, 1325 [REG_LED_0_CNTRL] = 0x40, 1326 [REG_LED_1_CNTRL] = 0x4c, 1327 [REG_LED_2_CNTRL] = 0x58, 1328 }; 1329 1330 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1331 .type = BCM7278_DEVICE_ID, 1332 .core_reg_align = 1, 1333 .reg_offsets = bcm_sf2_7278_reg_offsets, 1334 .num_cfp_rules = 128, 1335 }; 1336 1337 static const struct of_device_id bcm_sf2_of_match[] = { 1338 { .compatible = "brcm,bcm4908-switch", 1339 .data = &bcm_sf2_4908_data 1340 }, 1341 { .compatible = "brcm,bcm7445-switch-v4.0", 1342 .data = &bcm_sf2_7445_data 1343 }, 1344 { .compatible = "brcm,bcm7278-switch-v4.0", 1345 .data = &bcm_sf2_7278_data 1346 }, 1347 { .compatible = "brcm,bcm7278-switch-v4.8", 1348 .data = &bcm_sf2_7278_data 1349 }, 1350 { /* sentinel */ }, 1351 }; 1352 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1353 1354 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1355 { 1356 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1357 struct device_node *dn = pdev->dev.of_node; 1358 const struct of_device_id *of_id = NULL; 1359 const struct bcm_sf2_of_data *data; 1360 struct b53_platform_data *pdata; 1361 struct dsa_switch_ops *ops; 1362 struct device_node *ports; 1363 struct bcm_sf2_priv *priv; 1364 struct b53_device *dev; 1365 struct dsa_switch *ds; 1366 void __iomem **base; 1367 unsigned int i; 1368 u32 reg, rev; 1369 int ret; 1370 1371 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1372 if (!priv) 1373 return -ENOMEM; 1374 1375 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1376 if (!ops) 1377 return -ENOMEM; 1378 1379 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1380 if (!dev) 1381 return -ENOMEM; 1382 1383 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1384 if (!pdata) 1385 return -ENOMEM; 1386 1387 of_id = of_match_node(bcm_sf2_of_match, dn); 1388 if (!of_id || !of_id->data) 1389 return -EINVAL; 1390 1391 data = of_id->data; 1392 1393 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1394 priv->type = data->type; 1395 priv->reg_offsets = data->reg_offsets; 1396 priv->core_reg_align = data->core_reg_align; 1397 priv->num_cfp_rules = data->num_cfp_rules; 1398 priv->num_crossbar_int_ports = data->num_crossbar_int_ports; 1399 1400 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1401 "switch"); 1402 if (IS_ERR(priv->rcdev)) 1403 return PTR_ERR(priv->rcdev); 1404 1405 /* Auto-detection using standard registers will not work, so 1406 * provide an indication of what kind of device we are for 1407 * b53_common to work with 1408 */ 1409 pdata->chip_id = priv->type; 1410 dev->pdata = pdata; 1411 1412 priv->dev = dev; 1413 ds = dev->ds; 1414 ds->ops = &bcm_sf2_ops; 1415 1416 /* Advertise the 8 egress queues */ 1417 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1418 1419 dev_set_drvdata(&pdev->dev, priv); 1420 1421 spin_lock_init(&priv->indir_lock); 1422 mutex_init(&priv->cfp.lock); 1423 INIT_LIST_HEAD(&priv->cfp.rules_list); 1424 1425 /* CFP rule #0 cannot be used for specific classifications, flag it as 1426 * permanently used 1427 */ 1428 set_bit(0, priv->cfp.used); 1429 set_bit(0, priv->cfp.unique); 1430 1431 /* Balance of_node_put() done by of_find_node_by_name() */ 1432 of_node_get(dn); 1433 ports = of_find_node_by_name(dn, "ports"); 1434 if (ports) { 1435 bcm_sf2_identify_ports(priv, ports); 1436 of_node_put(ports); 1437 } 1438 1439 priv->irq0 = irq_of_parse_and_map(dn, 0); 1440 priv->irq1 = irq_of_parse_and_map(dn, 1); 1441 1442 base = &priv->core; 1443 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1444 *base = devm_platform_ioremap_resource(pdev, i); 1445 if (IS_ERR(*base)) { 1446 pr_err("unable to find register: %s\n", reg_names[i]); 1447 return PTR_ERR(*base); 1448 } 1449 base++; 1450 } 1451 1452 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch"); 1453 if (IS_ERR(priv->clk)) 1454 return PTR_ERR(priv->clk); 1455 1456 clk_prepare_enable(priv->clk); 1457 1458 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv"); 1459 if (IS_ERR(priv->clk_mdiv)) { 1460 ret = PTR_ERR(priv->clk_mdiv); 1461 goto out_clk; 1462 } 1463 1464 clk_prepare_enable(priv->clk_mdiv); 1465 1466 ret = bcm_sf2_sw_rst(priv); 1467 if (ret) { 1468 pr_err("unable to software reset switch: %d\n", ret); 1469 goto out_clk_mdiv; 1470 } 1471 1472 bcm_sf2_crossbar_setup(priv); 1473 1474 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1475 1476 ret = bcm_sf2_mdio_register(ds); 1477 if (ret) { 1478 pr_err("failed to register MDIO bus\n"); 1479 goto out_clk_mdiv; 1480 } 1481 1482 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1483 1484 ret = bcm_sf2_cfp_rst(priv); 1485 if (ret) { 1486 pr_err("failed to reset CFP\n"); 1487 goto out_mdio; 1488 } 1489 1490 /* Disable all interrupts and request them */ 1491 bcm_sf2_intr_disable(priv); 1492 1493 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1494 "switch_0", ds); 1495 if (ret < 0) { 1496 pr_err("failed to request switch_0 IRQ\n"); 1497 goto out_mdio; 1498 } 1499 1500 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1501 "switch_1", ds); 1502 if (ret < 0) { 1503 pr_err("failed to request switch_1 IRQ\n"); 1504 goto out_mdio; 1505 } 1506 1507 /* Reset the MIB counters */ 1508 reg = core_readl(priv, CORE_GMNCFGCFG); 1509 reg |= RST_MIB_CNT; 1510 core_writel(priv, reg, CORE_GMNCFGCFG); 1511 reg &= ~RST_MIB_CNT; 1512 core_writel(priv, reg, CORE_GMNCFGCFG); 1513 1514 /* Get the maximum number of ports for this switch */ 1515 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1516 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1517 priv->hw_params.num_ports = DSA_MAX_PORTS; 1518 1519 /* Assume a single GPHY setup if we can't read that property */ 1520 if (of_property_read_u32(dn, "brcm,num-gphy", 1521 &priv->hw_params.num_gphy)) 1522 priv->hw_params.num_gphy = 1; 1523 1524 rev = reg_readl(priv, REG_SWITCH_REVISION); 1525 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1526 SWITCH_TOP_REV_MASK; 1527 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1528 1529 rev = reg_readl(priv, REG_PHY_REVISION); 1530 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1531 1532 ret = b53_switch_register(dev); 1533 if (ret) 1534 goto out_mdio; 1535 1536 dev_info(&pdev->dev, 1537 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1538 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1539 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1540 priv->irq0, priv->irq1); 1541 1542 return 0; 1543 1544 out_mdio: 1545 bcm_sf2_mdio_unregister(priv); 1546 out_clk_mdiv: 1547 clk_disable_unprepare(priv->clk_mdiv); 1548 out_clk: 1549 clk_disable_unprepare(priv->clk); 1550 return ret; 1551 } 1552 1553 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1554 { 1555 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1556 1557 if (!priv) 1558 return 0; 1559 1560 priv->wol_ports_mask = 0; 1561 /* Disable interrupts */ 1562 bcm_sf2_intr_disable(priv); 1563 dsa_unregister_switch(priv->dev->ds); 1564 bcm_sf2_cfp_exit(priv->dev->ds); 1565 bcm_sf2_mdio_unregister(priv); 1566 clk_disable_unprepare(priv->clk_mdiv); 1567 clk_disable_unprepare(priv->clk); 1568 if (priv->type == BCM7278_DEVICE_ID) 1569 reset_control_assert(priv->rcdev); 1570 1571 platform_set_drvdata(pdev, NULL); 1572 1573 return 0; 1574 } 1575 1576 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1577 { 1578 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1579 1580 if (!priv) 1581 return; 1582 1583 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1584 * successful MDIO bus scan to occur. If we did turn off the GPHY 1585 * before (e.g: port_disable), this will also power it back on. 1586 * 1587 * Do not rely on kexec_in_progress, just power the PHY on. 1588 */ 1589 if (priv->hw_params.num_gphy == 1) 1590 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1591 1592 dsa_switch_shutdown(priv->dev->ds); 1593 1594 platform_set_drvdata(pdev, NULL); 1595 } 1596 1597 #ifdef CONFIG_PM_SLEEP 1598 static int bcm_sf2_suspend(struct device *dev) 1599 { 1600 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1601 1602 return dsa_switch_suspend(priv->dev->ds); 1603 } 1604 1605 static int bcm_sf2_resume(struct device *dev) 1606 { 1607 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1608 1609 return dsa_switch_resume(priv->dev->ds); 1610 } 1611 #endif /* CONFIG_PM_SLEEP */ 1612 1613 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1614 bcm_sf2_suspend, bcm_sf2_resume); 1615 1616 1617 static struct platform_driver bcm_sf2_driver = { 1618 .probe = bcm_sf2_sw_probe, 1619 .remove = bcm_sf2_sw_remove, 1620 .shutdown = bcm_sf2_sw_shutdown, 1621 .driver = { 1622 .name = "brcm-sf2", 1623 .of_match_table = bcm_sf2_of_match, 1624 .pm = &bcm_sf2_pm_ops, 1625 }, 1626 }; 1627 module_platform_driver(bcm_sf2_driver); 1628 1629 MODULE_AUTHOR("Broadcom Corporation"); 1630 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1631 MODULE_LICENSE("GPL"); 1632 MODULE_ALIAS("platform:brcm-sf2"); 1633