1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/of.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_address.h> 20 #include <linux/of_net.h> 21 #include <linux/of_mdio.h> 22 #include <net/dsa.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_bridge.h> 25 #include <linux/brcmphy.h> 26 #include <linux/etherdevice.h> 27 #include <linux/platform_data/b53.h> 28 29 #include "bcm_sf2.h" 30 #include "bcm_sf2_regs.h" 31 #include "b53/b53_priv.h" 32 #include "b53/b53_regs.h" 33 34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 35 { 36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 37 unsigned int i; 38 u32 reg, offset; 39 40 if (priv->type == BCM7445_DEVICE_ID) 41 offset = CORE_STS_OVERRIDE_IMP; 42 else 43 offset = CORE_STS_OVERRIDE_IMP2; 44 45 /* Enable the port memories */ 46 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 47 reg &= ~P_TXQ_PSM_VDD(port); 48 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 49 50 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 51 reg = core_readl(priv, CORE_IMP_CTL); 52 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 53 reg &= ~(RX_DIS | TX_DIS); 54 core_writel(priv, reg, CORE_IMP_CTL); 55 56 /* Enable forwarding */ 57 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 58 59 /* Enable IMP port in dumb mode */ 60 reg = core_readl(priv, CORE_SWITCH_CTRL); 61 reg |= MII_DUMB_FWDG_EN; 62 core_writel(priv, reg, CORE_SWITCH_CTRL); 63 64 /* Configure Traffic Class to QoS mapping, allow each priority to map 65 * to a different queue number 66 */ 67 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 68 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 69 reg |= i << (PRT_TO_QID_SHIFT * i); 70 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 71 72 b53_brcm_hdr_setup(ds, port); 73 74 /* Force link status for IMP port */ 75 reg = core_readl(priv, offset); 76 reg |= (MII_SW_OR | LINK_STS); 77 core_writel(priv, reg, offset); 78 } 79 80 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 81 { 82 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 83 u32 reg; 84 85 reg = reg_readl(priv, REG_SPHY_CNTRL); 86 if (enable) { 87 reg |= PHY_RESET; 88 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 89 reg_writel(priv, reg, REG_SPHY_CNTRL); 90 udelay(21); 91 reg = reg_readl(priv, REG_SPHY_CNTRL); 92 reg &= ~PHY_RESET; 93 } else { 94 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 95 reg_writel(priv, reg, REG_SPHY_CNTRL); 96 mdelay(1); 97 reg |= CK25_DIS; 98 } 99 reg_writel(priv, reg, REG_SPHY_CNTRL); 100 101 /* Use PHY-driven LED signaling */ 102 if (!enable) { 103 reg = reg_readl(priv, REG_LED_CNTRL(0)); 104 reg |= SPDLNK_SRC_SEL; 105 reg_writel(priv, reg, REG_LED_CNTRL(0)); 106 } 107 } 108 109 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 110 int port) 111 { 112 unsigned int off; 113 114 switch (port) { 115 case 7: 116 off = P7_IRQ_OFF; 117 break; 118 case 0: 119 /* Port 0 interrupts are located on the first bank */ 120 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 121 return; 122 default: 123 off = P_IRQ_OFF(port); 124 break; 125 } 126 127 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 128 } 129 130 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 131 int port) 132 { 133 unsigned int off; 134 135 switch (port) { 136 case 7: 137 off = P7_IRQ_OFF; 138 break; 139 case 0: 140 /* Port 0 interrupts are located on the first bank */ 141 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 142 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 143 return; 144 default: 145 off = P_IRQ_OFF(port); 146 break; 147 } 148 149 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 150 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 151 } 152 153 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 154 struct phy_device *phy) 155 { 156 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 157 unsigned int i; 158 u32 reg; 159 160 if (!dsa_is_user_port(ds, port)) 161 return 0; 162 163 /* Clear the memory power down */ 164 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 165 reg &= ~P_TXQ_PSM_VDD(port); 166 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 167 168 /* Enable learning */ 169 reg = core_readl(priv, CORE_DIS_LEARN); 170 reg &= ~BIT(port); 171 core_writel(priv, reg, CORE_DIS_LEARN); 172 173 /* Enable Broadcom tags for that port if requested */ 174 if (priv->brcm_tag_mask & BIT(port)) 175 b53_brcm_hdr_setup(ds, port); 176 177 /* Configure Traffic Class to QoS mapping, allow each priority to map 178 * to a different queue number 179 */ 180 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 181 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 182 reg |= i << (PRT_TO_QID_SHIFT * i); 183 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 184 185 /* Re-enable the GPHY and re-apply workarounds */ 186 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 187 bcm_sf2_gphy_enable_set(ds, true); 188 if (phy) { 189 /* if phy_stop() has been called before, phy 190 * will be in halted state, and phy_start() 191 * will call resume. 192 * 193 * the resume path does not configure back 194 * autoneg settings, and since we hard reset 195 * the phy manually here, we need to reset the 196 * state machine also. 197 */ 198 phy->state = PHY_READY; 199 phy_init_hw(phy); 200 } 201 } 202 203 /* Enable MoCA port interrupts to get notified */ 204 if (port == priv->moca_port) 205 bcm_sf2_port_intr_enable(priv, port); 206 207 /* Set per-queue pause threshold to 32 */ 208 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 209 210 /* Set ACB threshold to 24 */ 211 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 212 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 213 SF2_NUM_EGRESS_QUEUES + i)); 214 reg &= ~XOFF_THRESHOLD_MASK; 215 reg |= 24; 216 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 217 SF2_NUM_EGRESS_QUEUES + i)); 218 } 219 220 return b53_enable_port(ds, port, phy); 221 } 222 223 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 224 { 225 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 226 u32 reg; 227 228 /* Disable learning while in WoL mode */ 229 if (priv->wol_ports_mask & (1 << port)) { 230 reg = core_readl(priv, CORE_DIS_LEARN); 231 reg |= BIT(port); 232 core_writel(priv, reg, CORE_DIS_LEARN); 233 return; 234 } 235 236 if (port == priv->moca_port) 237 bcm_sf2_port_intr_disable(priv, port); 238 239 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 240 bcm_sf2_gphy_enable_set(ds, false); 241 242 b53_disable_port(ds, port); 243 244 /* Power down the port memory */ 245 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 246 reg |= P_TXQ_PSM_VDD(port); 247 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 248 } 249 250 251 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 252 int regnum, u16 val) 253 { 254 int ret = 0; 255 u32 reg; 256 257 reg = reg_readl(priv, REG_SWITCH_CNTRL); 258 reg |= MDIO_MASTER_SEL; 259 reg_writel(priv, reg, REG_SWITCH_CNTRL); 260 261 /* Page << 8 | offset */ 262 reg = 0x70; 263 reg <<= 2; 264 core_writel(priv, addr, reg); 265 266 /* Page << 8 | offset */ 267 reg = 0x80 << 8 | regnum << 1; 268 reg <<= 2; 269 270 if (op) 271 ret = core_readl(priv, reg); 272 else 273 core_writel(priv, val, reg); 274 275 reg = reg_readl(priv, REG_SWITCH_CNTRL); 276 reg &= ~MDIO_MASTER_SEL; 277 reg_writel(priv, reg, REG_SWITCH_CNTRL); 278 279 return ret & 0xffff; 280 } 281 282 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 283 { 284 struct bcm_sf2_priv *priv = bus->priv; 285 286 /* Intercept reads from Broadcom pseudo-PHY address, else, send 287 * them to our master MDIO bus controller 288 */ 289 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 290 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 291 else 292 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 293 } 294 295 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 296 u16 val) 297 { 298 struct bcm_sf2_priv *priv = bus->priv; 299 300 /* Intercept writes to the Broadcom pseudo-PHY address, else, 301 * send them to our master MDIO bus controller 302 */ 303 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 304 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 305 else 306 return mdiobus_write_nested(priv->master_mii_bus, addr, 307 regnum, val); 308 } 309 310 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 311 { 312 struct dsa_switch *ds = dev_id; 313 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 314 315 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 316 ~priv->irq0_mask; 317 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 318 319 return IRQ_HANDLED; 320 } 321 322 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 323 { 324 struct dsa_switch *ds = dev_id; 325 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 326 327 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 328 ~priv->irq1_mask; 329 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 330 331 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 332 priv->port_sts[7].link = true; 333 dsa_port_phylink_mac_change(ds, 7, true); 334 } 335 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 336 priv->port_sts[7].link = false; 337 dsa_port_phylink_mac_change(ds, 7, false); 338 } 339 340 return IRQ_HANDLED; 341 } 342 343 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 344 { 345 unsigned int timeout = 1000; 346 u32 reg; 347 348 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 349 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 350 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 351 352 do { 353 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 354 if (!(reg & SOFTWARE_RESET)) 355 break; 356 357 usleep_range(1000, 2000); 358 } while (timeout-- > 0); 359 360 if (timeout == 0) 361 return -ETIMEDOUT; 362 363 return 0; 364 } 365 366 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 367 { 368 intrl2_0_mask_set(priv, 0xffffffff); 369 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 370 intrl2_1_mask_set(priv, 0xffffffff); 371 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 372 } 373 374 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 375 struct device_node *dn) 376 { 377 struct device_node *port; 378 int mode; 379 unsigned int port_num; 380 381 priv->moca_port = -1; 382 383 for_each_available_child_of_node(dn, port) { 384 if (of_property_read_u32(port, "reg", &port_num)) 385 continue; 386 387 /* Internal PHYs get assigned a specific 'phy-mode' property 388 * value: "internal" to help flag them before MDIO probing 389 * has completed, since they might be turned off at that 390 * time 391 */ 392 mode = of_get_phy_mode(port); 393 if (mode < 0) 394 continue; 395 396 if (mode == PHY_INTERFACE_MODE_INTERNAL) 397 priv->int_phy_mask |= 1 << port_num; 398 399 if (mode == PHY_INTERFACE_MODE_MOCA) 400 priv->moca_port = port_num; 401 402 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 403 priv->brcm_tag_mask |= 1 << port_num; 404 } 405 } 406 407 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 408 { 409 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 410 struct device_node *dn; 411 static int index; 412 int err; 413 414 /* Find our integrated MDIO bus node */ 415 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 416 priv->master_mii_bus = of_mdio_find_bus(dn); 417 if (!priv->master_mii_bus) 418 return -EPROBE_DEFER; 419 420 get_device(&priv->master_mii_bus->dev); 421 priv->master_mii_dn = dn; 422 423 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 424 if (!priv->slave_mii_bus) 425 return -ENOMEM; 426 427 priv->slave_mii_bus->priv = priv; 428 priv->slave_mii_bus->name = "sf2 slave mii"; 429 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 430 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 431 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 432 index++); 433 priv->slave_mii_bus->dev.of_node = dn; 434 435 /* Include the pseudo-PHY address to divert reads towards our 436 * workaround. This is only required for 7445D0, since 7445E0 437 * disconnects the internal switch pseudo-PHY such that we can use the 438 * regular SWITCH_MDIO master controller instead. 439 * 440 * Here we flag the pseudo PHY as needing special treatment and would 441 * otherwise make all other PHY read/writes go to the master MDIO bus 442 * controller that comes with this switch backed by the "mdio-unimac" 443 * driver. 444 */ 445 if (of_machine_is_compatible("brcm,bcm7445d0")) 446 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 447 else 448 priv->indir_phy_mask = 0; 449 450 ds->phys_mii_mask = priv->indir_phy_mask; 451 ds->slave_mii_bus = priv->slave_mii_bus; 452 priv->slave_mii_bus->parent = ds->dev->parent; 453 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 454 455 err = of_mdiobus_register(priv->slave_mii_bus, dn); 456 if (err && dn) 457 of_node_put(dn); 458 459 return err; 460 } 461 462 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 463 { 464 mdiobus_unregister(priv->slave_mii_bus); 465 of_node_put(priv->master_mii_dn); 466 } 467 468 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 469 { 470 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 471 472 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 473 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 474 * the REG_PHY_REVISION register layout is. 475 */ 476 477 return priv->hw_params.gphy_rev; 478 } 479 480 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 481 unsigned long *supported, 482 struct phylink_link_state *state) 483 { 484 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 485 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 486 487 if (!phy_interface_mode_is_rgmii(state->interface) && 488 state->interface != PHY_INTERFACE_MODE_MII && 489 state->interface != PHY_INTERFACE_MODE_REVMII && 490 state->interface != PHY_INTERFACE_MODE_GMII && 491 state->interface != PHY_INTERFACE_MODE_INTERNAL && 492 state->interface != PHY_INTERFACE_MODE_MOCA) { 493 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 494 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 495 dev_err(ds->dev, 496 "Unsupported interface: %d for port %d\n", 497 state->interface, port); 498 return; 499 } 500 501 /* Allow all the expected bits */ 502 phylink_set(mask, Autoneg); 503 phylink_set_port_modes(mask); 504 phylink_set(mask, Pause); 505 phylink_set(mask, Asym_Pause); 506 507 /* With the exclusion of MII and Reverse MII, we support Gigabit, 508 * including Half duplex 509 */ 510 if (state->interface != PHY_INTERFACE_MODE_MII && 511 state->interface != PHY_INTERFACE_MODE_REVMII) { 512 phylink_set(mask, 1000baseT_Full); 513 phylink_set(mask, 1000baseT_Half); 514 } 515 516 phylink_set(mask, 10baseT_Half); 517 phylink_set(mask, 10baseT_Full); 518 phylink_set(mask, 100baseT_Half); 519 phylink_set(mask, 100baseT_Full); 520 521 bitmap_and(supported, supported, mask, 522 __ETHTOOL_LINK_MODE_MASK_NBITS); 523 bitmap_and(state->advertising, state->advertising, mask, 524 __ETHTOOL_LINK_MODE_MASK_NBITS); 525 } 526 527 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 528 unsigned int mode, 529 const struct phylink_link_state *state) 530 { 531 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 532 u32 id_mode_dis = 0, port_mode; 533 u32 reg, offset; 534 535 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 536 return; 537 538 if (priv->type == BCM7445_DEVICE_ID) 539 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 540 else 541 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 542 543 switch (state->interface) { 544 case PHY_INTERFACE_MODE_RGMII: 545 id_mode_dis = 1; 546 /* fallthrough */ 547 case PHY_INTERFACE_MODE_RGMII_TXID: 548 port_mode = EXT_GPHY; 549 break; 550 case PHY_INTERFACE_MODE_MII: 551 port_mode = EXT_EPHY; 552 break; 553 case PHY_INTERFACE_MODE_REVMII: 554 port_mode = EXT_REVMII; 555 break; 556 default: 557 /* all other PHYs: internal and MoCA */ 558 goto force_link; 559 } 560 561 /* Clear id_mode_dis bit, and the existing port mode, let 562 * RGMII_MODE_EN bet set by mac_link_{up,down} 563 */ 564 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 565 reg &= ~ID_MODE_DIS; 566 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 567 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 568 569 reg |= port_mode; 570 if (id_mode_dis) 571 reg |= ID_MODE_DIS; 572 573 if (state->pause & MLO_PAUSE_TXRX_MASK) { 574 if (state->pause & MLO_PAUSE_TX) 575 reg |= TX_PAUSE_EN; 576 reg |= RX_PAUSE_EN; 577 } 578 579 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 580 581 force_link: 582 /* Force link settings detected from the PHY */ 583 reg = SW_OVERRIDE; 584 switch (state->speed) { 585 case SPEED_1000: 586 reg |= SPDSTS_1000 << SPEED_SHIFT; 587 break; 588 case SPEED_100: 589 reg |= SPDSTS_100 << SPEED_SHIFT; 590 break; 591 } 592 593 if (state->link) 594 reg |= LINK_STS; 595 if (state->duplex == DUPLEX_FULL) 596 reg |= DUPLX_MODE; 597 598 core_writel(priv, reg, offset); 599 } 600 601 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 602 phy_interface_t interface, bool link) 603 { 604 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 605 u32 reg; 606 607 if (!phy_interface_mode_is_rgmii(interface) && 608 interface != PHY_INTERFACE_MODE_MII && 609 interface != PHY_INTERFACE_MODE_REVMII) 610 return; 611 612 /* If the link is down, just disable the interface to conserve power */ 613 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 614 if (link) 615 reg |= RGMII_MODE_EN; 616 else 617 reg &= ~RGMII_MODE_EN; 618 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 619 } 620 621 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 622 unsigned int mode, 623 phy_interface_t interface) 624 { 625 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 626 } 627 628 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 629 unsigned int mode, 630 phy_interface_t interface, 631 struct phy_device *phydev) 632 { 633 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 634 struct ethtool_eee *p = &priv->dev->ports[port].eee; 635 636 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 637 638 if (mode == MLO_AN_PHY && phydev) 639 p->eee_enabled = b53_eee_init(ds, port, phydev); 640 } 641 642 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 643 struct phylink_link_state *status) 644 { 645 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 646 647 status->link = false; 648 649 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 650 * which means that we need to force the link at the port override 651 * level to get the data to flow. We do use what the interrupt handler 652 * did determine before. 653 * 654 * For the other ports, we just force the link status, since this is 655 * a fixed PHY device. 656 */ 657 if (port == priv->moca_port) { 658 status->link = priv->port_sts[port].link; 659 /* For MoCA interfaces, also force a link down notification 660 * since some version of the user-space daemon (mocad) use 661 * cmd->autoneg to force the link, which messes up the PHY 662 * state machine and make it go in PHY_FORCING state instead. 663 */ 664 if (!status->link) 665 netif_carrier_off(ds->ports[port].slave); 666 status->duplex = DUPLEX_FULL; 667 } else { 668 status->link = true; 669 } 670 } 671 672 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 673 { 674 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 675 u32 reg; 676 677 /* Enable ACB globally */ 678 reg = acb_readl(priv, ACB_CONTROL); 679 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 680 acb_writel(priv, reg, ACB_CONTROL); 681 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 682 reg |= ACB_EN | ACB_ALGORITHM; 683 acb_writel(priv, reg, ACB_CONTROL); 684 } 685 686 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 687 { 688 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 689 unsigned int port; 690 691 bcm_sf2_intr_disable(priv); 692 693 /* Disable all ports physically present including the IMP 694 * port, the other ones have already been disabled during 695 * bcm_sf2_sw_setup 696 */ 697 for (port = 0; port < ds->num_ports; port++) { 698 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 699 bcm_sf2_port_disable(ds, port); 700 } 701 702 return 0; 703 } 704 705 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 706 { 707 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 708 int ret; 709 710 ret = bcm_sf2_sw_rst(priv); 711 if (ret) { 712 pr_err("%s: failed to software reset switch\n", __func__); 713 return ret; 714 } 715 716 ret = bcm_sf2_cfp_resume(ds); 717 if (ret) 718 return ret; 719 720 if (priv->hw_params.num_gphy == 1) 721 bcm_sf2_gphy_enable_set(ds, true); 722 723 ds->ops->setup(ds); 724 725 return 0; 726 } 727 728 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 729 struct ethtool_wolinfo *wol) 730 { 731 struct net_device *p = ds->ports[port].cpu_dp->master; 732 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 733 struct ethtool_wolinfo pwol = { }; 734 735 /* Get the parent device WoL settings */ 736 if (p->ethtool_ops->get_wol) 737 p->ethtool_ops->get_wol(p, &pwol); 738 739 /* Advertise the parent device supported settings */ 740 wol->supported = pwol.supported; 741 memset(&wol->sopass, 0, sizeof(wol->sopass)); 742 743 if (pwol.wolopts & WAKE_MAGICSECURE) 744 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 745 746 if (priv->wol_ports_mask & (1 << port)) 747 wol->wolopts = pwol.wolopts; 748 else 749 wol->wolopts = 0; 750 } 751 752 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 753 struct ethtool_wolinfo *wol) 754 { 755 struct net_device *p = ds->ports[port].cpu_dp->master; 756 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 757 s8 cpu_port = ds->ports[port].cpu_dp->index; 758 struct ethtool_wolinfo pwol = { }; 759 760 if (p->ethtool_ops->get_wol) 761 p->ethtool_ops->get_wol(p, &pwol); 762 if (wol->wolopts & ~pwol.supported) 763 return -EINVAL; 764 765 if (wol->wolopts) 766 priv->wol_ports_mask |= (1 << port); 767 else 768 priv->wol_ports_mask &= ~(1 << port); 769 770 /* If we have at least one port enabled, make sure the CPU port 771 * is also enabled. If the CPU port is the last one enabled, we disable 772 * it since this configuration does not make sense. 773 */ 774 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 775 priv->wol_ports_mask |= (1 << cpu_port); 776 else 777 priv->wol_ports_mask &= ~(1 << cpu_port); 778 779 return p->ethtool_ops->set_wol(p, wol); 780 } 781 782 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 783 { 784 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 785 unsigned int port; 786 787 /* Enable all valid ports and disable those unused */ 788 for (port = 0; port < priv->hw_params.num_ports; port++) { 789 /* IMP port receives special treatment */ 790 if (dsa_is_user_port(ds, port)) 791 bcm_sf2_port_setup(ds, port, NULL); 792 else if (dsa_is_cpu_port(ds, port)) 793 bcm_sf2_imp_setup(ds, port); 794 else 795 bcm_sf2_port_disable(ds, port); 796 } 797 798 b53_configure_vlan(ds); 799 bcm_sf2_enable_acb(ds); 800 801 return 0; 802 } 803 804 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 805 * register basis so we need to translate that into an address that the 806 * bus-glue understands. 807 */ 808 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 809 810 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 811 u8 *val) 812 { 813 struct bcm_sf2_priv *priv = dev->priv; 814 815 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 816 817 return 0; 818 } 819 820 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 821 u16 *val) 822 { 823 struct bcm_sf2_priv *priv = dev->priv; 824 825 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 826 827 return 0; 828 } 829 830 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 831 u32 *val) 832 { 833 struct bcm_sf2_priv *priv = dev->priv; 834 835 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 836 837 return 0; 838 } 839 840 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 841 u64 *val) 842 { 843 struct bcm_sf2_priv *priv = dev->priv; 844 845 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 846 847 return 0; 848 } 849 850 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 851 u8 value) 852 { 853 struct bcm_sf2_priv *priv = dev->priv; 854 855 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 856 857 return 0; 858 } 859 860 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 861 u16 value) 862 { 863 struct bcm_sf2_priv *priv = dev->priv; 864 865 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 866 867 return 0; 868 } 869 870 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 871 u32 value) 872 { 873 struct bcm_sf2_priv *priv = dev->priv; 874 875 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 876 877 return 0; 878 } 879 880 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 881 u64 value) 882 { 883 struct bcm_sf2_priv *priv = dev->priv; 884 885 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 886 887 return 0; 888 } 889 890 static const struct b53_io_ops bcm_sf2_io_ops = { 891 .read8 = bcm_sf2_core_read8, 892 .read16 = bcm_sf2_core_read16, 893 .read32 = bcm_sf2_core_read32, 894 .read48 = bcm_sf2_core_read64, 895 .read64 = bcm_sf2_core_read64, 896 .write8 = bcm_sf2_core_write8, 897 .write16 = bcm_sf2_core_write16, 898 .write32 = bcm_sf2_core_write32, 899 .write48 = bcm_sf2_core_write64, 900 .write64 = bcm_sf2_core_write64, 901 }; 902 903 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 904 u32 stringset, uint8_t *data) 905 { 906 int cnt = b53_get_sset_count(ds, port, stringset); 907 908 b53_get_strings(ds, port, stringset, data); 909 bcm_sf2_cfp_get_strings(ds, port, stringset, 910 data + cnt * ETH_GSTRING_LEN); 911 } 912 913 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 914 uint64_t *data) 915 { 916 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 917 918 b53_get_ethtool_stats(ds, port, data); 919 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 920 } 921 922 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 923 int sset) 924 { 925 int cnt = b53_get_sset_count(ds, port, sset); 926 927 if (cnt < 0) 928 return cnt; 929 930 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 931 932 return cnt; 933 } 934 935 static const struct dsa_switch_ops bcm_sf2_ops = { 936 .get_tag_protocol = b53_get_tag_protocol, 937 .setup = bcm_sf2_sw_setup, 938 .get_strings = bcm_sf2_sw_get_strings, 939 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 940 .get_sset_count = bcm_sf2_sw_get_sset_count, 941 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 942 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 943 .phylink_validate = bcm_sf2_sw_validate, 944 .phylink_mac_config = bcm_sf2_sw_mac_config, 945 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 946 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 947 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 948 .suspend = bcm_sf2_sw_suspend, 949 .resume = bcm_sf2_sw_resume, 950 .get_wol = bcm_sf2_sw_get_wol, 951 .set_wol = bcm_sf2_sw_set_wol, 952 .port_enable = bcm_sf2_port_setup, 953 .port_disable = bcm_sf2_port_disable, 954 .get_mac_eee = b53_get_mac_eee, 955 .set_mac_eee = b53_set_mac_eee, 956 .port_bridge_join = b53_br_join, 957 .port_bridge_leave = b53_br_leave, 958 .port_stp_state_set = b53_br_set_stp_state, 959 .port_fast_age = b53_br_fast_age, 960 .port_vlan_filtering = b53_vlan_filtering, 961 .port_vlan_prepare = b53_vlan_prepare, 962 .port_vlan_add = b53_vlan_add, 963 .port_vlan_del = b53_vlan_del, 964 .port_fdb_dump = b53_fdb_dump, 965 .port_fdb_add = b53_fdb_add, 966 .port_fdb_del = b53_fdb_del, 967 .get_rxnfc = bcm_sf2_get_rxnfc, 968 .set_rxnfc = bcm_sf2_set_rxnfc, 969 .port_mirror_add = b53_mirror_add, 970 .port_mirror_del = b53_mirror_del, 971 }; 972 973 struct bcm_sf2_of_data { 974 u32 type; 975 const u16 *reg_offsets; 976 unsigned int core_reg_align; 977 unsigned int num_cfp_rules; 978 }; 979 980 /* Register offsets for the SWITCH_REG_* block */ 981 static const u16 bcm_sf2_7445_reg_offsets[] = { 982 [REG_SWITCH_CNTRL] = 0x00, 983 [REG_SWITCH_STATUS] = 0x04, 984 [REG_DIR_DATA_WRITE] = 0x08, 985 [REG_DIR_DATA_READ] = 0x0C, 986 [REG_SWITCH_REVISION] = 0x18, 987 [REG_PHY_REVISION] = 0x1C, 988 [REG_SPHY_CNTRL] = 0x2C, 989 [REG_RGMII_0_CNTRL] = 0x34, 990 [REG_RGMII_1_CNTRL] = 0x40, 991 [REG_RGMII_2_CNTRL] = 0x4c, 992 [REG_LED_0_CNTRL] = 0x90, 993 [REG_LED_1_CNTRL] = 0x94, 994 [REG_LED_2_CNTRL] = 0x98, 995 }; 996 997 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 998 .type = BCM7445_DEVICE_ID, 999 .core_reg_align = 0, 1000 .reg_offsets = bcm_sf2_7445_reg_offsets, 1001 .num_cfp_rules = 256, 1002 }; 1003 1004 static const u16 bcm_sf2_7278_reg_offsets[] = { 1005 [REG_SWITCH_CNTRL] = 0x00, 1006 [REG_SWITCH_STATUS] = 0x04, 1007 [REG_DIR_DATA_WRITE] = 0x08, 1008 [REG_DIR_DATA_READ] = 0x0c, 1009 [REG_SWITCH_REVISION] = 0x10, 1010 [REG_PHY_REVISION] = 0x14, 1011 [REG_SPHY_CNTRL] = 0x24, 1012 [REG_RGMII_0_CNTRL] = 0xe0, 1013 [REG_RGMII_1_CNTRL] = 0xec, 1014 [REG_RGMII_2_CNTRL] = 0xf8, 1015 [REG_LED_0_CNTRL] = 0x40, 1016 [REG_LED_1_CNTRL] = 0x4c, 1017 [REG_LED_2_CNTRL] = 0x58, 1018 }; 1019 1020 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1021 .type = BCM7278_DEVICE_ID, 1022 .core_reg_align = 1, 1023 .reg_offsets = bcm_sf2_7278_reg_offsets, 1024 .num_cfp_rules = 128, 1025 }; 1026 1027 static const struct of_device_id bcm_sf2_of_match[] = { 1028 { .compatible = "brcm,bcm7445-switch-v4.0", 1029 .data = &bcm_sf2_7445_data 1030 }, 1031 { .compatible = "brcm,bcm7278-switch-v4.0", 1032 .data = &bcm_sf2_7278_data 1033 }, 1034 { .compatible = "brcm,bcm7278-switch-v4.8", 1035 .data = &bcm_sf2_7278_data 1036 }, 1037 { /* sentinel */ }, 1038 }; 1039 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1040 1041 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1042 { 1043 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1044 struct device_node *dn = pdev->dev.of_node; 1045 const struct of_device_id *of_id = NULL; 1046 const struct bcm_sf2_of_data *data; 1047 struct b53_platform_data *pdata; 1048 struct dsa_switch_ops *ops; 1049 struct bcm_sf2_priv *priv; 1050 struct b53_device *dev; 1051 struct dsa_switch *ds; 1052 void __iomem **base; 1053 unsigned int i; 1054 u32 reg, rev; 1055 int ret; 1056 1057 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1058 if (!priv) 1059 return -ENOMEM; 1060 1061 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1062 if (!ops) 1063 return -ENOMEM; 1064 1065 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1066 if (!dev) 1067 return -ENOMEM; 1068 1069 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1070 if (!pdata) 1071 return -ENOMEM; 1072 1073 of_id = of_match_node(bcm_sf2_of_match, dn); 1074 if (!of_id || !of_id->data) 1075 return -EINVAL; 1076 1077 data = of_id->data; 1078 1079 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1080 priv->type = data->type; 1081 priv->reg_offsets = data->reg_offsets; 1082 priv->core_reg_align = data->core_reg_align; 1083 priv->num_cfp_rules = data->num_cfp_rules; 1084 1085 /* Auto-detection using standard registers will not work, so 1086 * provide an indication of what kind of device we are for 1087 * b53_common to work with 1088 */ 1089 pdata->chip_id = priv->type; 1090 dev->pdata = pdata; 1091 1092 priv->dev = dev; 1093 ds = dev->ds; 1094 ds->ops = &bcm_sf2_ops; 1095 1096 /* Advertise the 8 egress queues */ 1097 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1098 1099 dev_set_drvdata(&pdev->dev, priv); 1100 1101 spin_lock_init(&priv->indir_lock); 1102 mutex_init(&priv->cfp.lock); 1103 INIT_LIST_HEAD(&priv->cfp.rules_list); 1104 1105 /* CFP rule #0 cannot be used for specific classifications, flag it as 1106 * permanently used 1107 */ 1108 set_bit(0, priv->cfp.used); 1109 set_bit(0, priv->cfp.unique); 1110 1111 bcm_sf2_identify_ports(priv, dn->child); 1112 1113 priv->irq0 = irq_of_parse_and_map(dn, 0); 1114 priv->irq1 = irq_of_parse_and_map(dn, 1); 1115 1116 base = &priv->core; 1117 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1118 *base = devm_platform_ioremap_resource(pdev, i); 1119 if (IS_ERR(*base)) { 1120 pr_err("unable to find register: %s\n", reg_names[i]); 1121 return PTR_ERR(*base); 1122 } 1123 base++; 1124 } 1125 1126 ret = bcm_sf2_sw_rst(priv); 1127 if (ret) { 1128 pr_err("unable to software reset switch: %d\n", ret); 1129 return ret; 1130 } 1131 1132 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1133 1134 ret = bcm_sf2_mdio_register(ds); 1135 if (ret) { 1136 pr_err("failed to register MDIO bus\n"); 1137 return ret; 1138 } 1139 1140 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1141 1142 ret = bcm_sf2_cfp_rst(priv); 1143 if (ret) { 1144 pr_err("failed to reset CFP\n"); 1145 goto out_mdio; 1146 } 1147 1148 /* Disable all interrupts and request them */ 1149 bcm_sf2_intr_disable(priv); 1150 1151 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1152 "switch_0", ds); 1153 if (ret < 0) { 1154 pr_err("failed to request switch_0 IRQ\n"); 1155 goto out_mdio; 1156 } 1157 1158 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1159 "switch_1", ds); 1160 if (ret < 0) { 1161 pr_err("failed to request switch_1 IRQ\n"); 1162 goto out_mdio; 1163 } 1164 1165 /* Reset the MIB counters */ 1166 reg = core_readl(priv, CORE_GMNCFGCFG); 1167 reg |= RST_MIB_CNT; 1168 core_writel(priv, reg, CORE_GMNCFGCFG); 1169 reg &= ~RST_MIB_CNT; 1170 core_writel(priv, reg, CORE_GMNCFGCFG); 1171 1172 /* Get the maximum number of ports for this switch */ 1173 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1174 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1175 priv->hw_params.num_ports = DSA_MAX_PORTS; 1176 1177 /* Assume a single GPHY setup if we can't read that property */ 1178 if (of_property_read_u32(dn, "brcm,num-gphy", 1179 &priv->hw_params.num_gphy)) 1180 priv->hw_params.num_gphy = 1; 1181 1182 rev = reg_readl(priv, REG_SWITCH_REVISION); 1183 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1184 SWITCH_TOP_REV_MASK; 1185 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1186 1187 rev = reg_readl(priv, REG_PHY_REVISION); 1188 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1189 1190 ret = b53_switch_register(dev); 1191 if (ret) 1192 goto out_mdio; 1193 1194 dev_info(&pdev->dev, 1195 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1196 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1197 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1198 priv->irq0, priv->irq1); 1199 1200 return 0; 1201 1202 out_mdio: 1203 bcm_sf2_mdio_unregister(priv); 1204 return ret; 1205 } 1206 1207 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1208 { 1209 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1210 1211 priv->wol_ports_mask = 0; 1212 dsa_unregister_switch(priv->dev->ds); 1213 bcm_sf2_cfp_exit(priv->dev->ds); 1214 /* Disable all ports and interrupts */ 1215 bcm_sf2_sw_suspend(priv->dev->ds); 1216 bcm_sf2_mdio_unregister(priv); 1217 1218 return 0; 1219 } 1220 1221 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1222 { 1223 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1224 1225 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1226 * successful MDIO bus scan to occur. If we did turn off the GPHY 1227 * before (e.g: port_disable), this will also power it back on. 1228 * 1229 * Do not rely on kexec_in_progress, just power the PHY on. 1230 */ 1231 if (priv->hw_params.num_gphy == 1) 1232 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1233 } 1234 1235 #ifdef CONFIG_PM_SLEEP 1236 static int bcm_sf2_suspend(struct device *dev) 1237 { 1238 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1239 1240 return dsa_switch_suspend(priv->dev->ds); 1241 } 1242 1243 static int bcm_sf2_resume(struct device *dev) 1244 { 1245 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1246 1247 return dsa_switch_resume(priv->dev->ds); 1248 } 1249 #endif /* CONFIG_PM_SLEEP */ 1250 1251 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1252 bcm_sf2_suspend, bcm_sf2_resume); 1253 1254 1255 static struct platform_driver bcm_sf2_driver = { 1256 .probe = bcm_sf2_sw_probe, 1257 .remove = bcm_sf2_sw_remove, 1258 .shutdown = bcm_sf2_sw_shutdown, 1259 .driver = { 1260 .name = "brcm-sf2", 1261 .of_match_table = bcm_sf2_of_match, 1262 .pm = &bcm_sf2_pm_ops, 1263 }, 1264 }; 1265 module_platform_driver(bcm_sf2_driver); 1266 1267 MODULE_AUTHOR("Broadcom Corporation"); 1268 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1269 MODULE_LICENSE("GPL"); 1270 MODULE_ALIAS("platform:brcm-sf2"); 1271