1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <net/dsa.h> 24 #include <linux/ethtool.h> 25 #include <linux/if_bridge.h> 26 #include <linux/brcmphy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/platform_data/b53.h> 29 30 #include "bcm_sf2.h" 31 #include "bcm_sf2_regs.h" 32 #include "b53/b53_priv.h" 33 #include "b53/b53_regs.h" 34 35 /* Return the number of active ports, not counting the IMP (CPU) port */ 36 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds) 37 { 38 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 39 unsigned int port, count = 0; 40 41 for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) { 42 if (dsa_is_cpu_port(ds, port)) 43 continue; 44 if (priv->port_sts[port].enabled) 45 count++; 46 } 47 48 return count; 49 } 50 51 static void bcm_sf2_recalc_clock(struct dsa_switch *ds) 52 { 53 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 54 unsigned long new_rate; 55 unsigned int ports_active; 56 /* Frequenty in Mhz */ 57 static const unsigned long rate_table[] = { 58 59220000, 59 60820000, 60 62500000, 61 62500000, 62 }; 63 64 ports_active = bcm_sf2_num_active_ports(ds); 65 if (ports_active == 0 || !priv->clk_mdiv) 66 return; 67 68 /* If we overflow our table, just use the recommended operational 69 * frequency 70 */ 71 if (ports_active > ARRAY_SIZE(rate_table)) 72 new_rate = 90000000; 73 else 74 new_rate = rate_table[ports_active - 1]; 75 clk_set_rate(priv->clk_mdiv, new_rate); 76 } 77 78 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 79 { 80 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 81 unsigned int i; 82 u32 reg, offset; 83 84 /* Enable the port memories */ 85 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 86 reg &= ~P_TXQ_PSM_VDD(port); 87 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 88 89 /* Enable forwarding */ 90 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 91 92 /* Enable IMP port in dumb mode */ 93 reg = core_readl(priv, CORE_SWITCH_CTRL); 94 reg |= MII_DUMB_FWDG_EN; 95 core_writel(priv, reg, CORE_SWITCH_CTRL); 96 97 /* Configure Traffic Class to QoS mapping, allow each priority to map 98 * to a different queue number 99 */ 100 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 101 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 102 reg |= i << (PRT_TO_QID_SHIFT * i); 103 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 104 105 b53_brcm_hdr_setup(ds, port); 106 107 if (port == 8) { 108 if (priv->type == BCM4908_DEVICE_ID || 109 priv->type == BCM7445_DEVICE_ID) 110 offset = CORE_STS_OVERRIDE_IMP; 111 else 112 offset = CORE_STS_OVERRIDE_IMP2; 113 114 /* Force link status for IMP port */ 115 reg = core_readl(priv, offset); 116 reg |= (MII_SW_OR | LINK_STS); 117 reg &= ~GMII_SPEED_UP_2G; 118 core_writel(priv, reg, offset); 119 120 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 121 reg = core_readl(priv, CORE_IMP_CTL); 122 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 123 reg &= ~(RX_DIS | TX_DIS); 124 core_writel(priv, reg, CORE_IMP_CTL); 125 } else { 126 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 127 reg &= ~(RX_DIS | TX_DIS); 128 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 129 } 130 131 priv->port_sts[port].enabled = true; 132 } 133 134 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 135 { 136 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 137 u32 reg; 138 139 reg = reg_readl(priv, REG_SPHY_CNTRL); 140 if (enable) { 141 reg |= PHY_RESET; 142 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 143 reg_writel(priv, reg, REG_SPHY_CNTRL); 144 udelay(21); 145 reg = reg_readl(priv, REG_SPHY_CNTRL); 146 reg &= ~PHY_RESET; 147 } else { 148 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 149 reg_writel(priv, reg, REG_SPHY_CNTRL); 150 mdelay(1); 151 reg |= CK25_DIS; 152 } 153 reg_writel(priv, reg, REG_SPHY_CNTRL); 154 155 /* Use PHY-driven LED signaling */ 156 if (!enable) { 157 reg = reg_readl(priv, REG_LED_CNTRL(0)); 158 reg |= SPDLNK_SRC_SEL; 159 reg_writel(priv, reg, REG_LED_CNTRL(0)); 160 } 161 } 162 163 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 164 int port) 165 { 166 unsigned int off; 167 168 switch (port) { 169 case 7: 170 off = P7_IRQ_OFF; 171 break; 172 case 0: 173 /* Port 0 interrupts are located on the first bank */ 174 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 175 return; 176 default: 177 off = P_IRQ_OFF(port); 178 break; 179 } 180 181 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 182 } 183 184 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 185 int port) 186 { 187 unsigned int off; 188 189 switch (port) { 190 case 7: 191 off = P7_IRQ_OFF; 192 break; 193 case 0: 194 /* Port 0 interrupts are located on the first bank */ 195 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 196 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 197 return; 198 default: 199 off = P_IRQ_OFF(port); 200 break; 201 } 202 203 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 204 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 205 } 206 207 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 208 struct phy_device *phy) 209 { 210 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 211 unsigned int i; 212 u32 reg; 213 214 if (!dsa_is_user_port(ds, port)) 215 return 0; 216 217 priv->port_sts[port].enabled = true; 218 219 bcm_sf2_recalc_clock(ds); 220 221 /* Clear the memory power down */ 222 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 223 reg &= ~P_TXQ_PSM_VDD(port); 224 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 225 226 /* Enable Broadcom tags for that port if requested */ 227 if (priv->brcm_tag_mask & BIT(port)) 228 b53_brcm_hdr_setup(ds, port); 229 230 /* Configure Traffic Class to QoS mapping, allow each priority to map 231 * to a different queue number 232 */ 233 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 234 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 235 reg |= i << (PRT_TO_QID_SHIFT * i); 236 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 237 238 /* Re-enable the GPHY and re-apply workarounds */ 239 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 240 bcm_sf2_gphy_enable_set(ds, true); 241 if (phy) { 242 /* if phy_stop() has been called before, phy 243 * will be in halted state, and phy_start() 244 * will call resume. 245 * 246 * the resume path does not configure back 247 * autoneg settings, and since we hard reset 248 * the phy manually here, we need to reset the 249 * state machine also. 250 */ 251 phy->state = PHY_READY; 252 phy_init_hw(phy); 253 } 254 } 255 256 /* Enable MoCA port interrupts to get notified */ 257 if (port == priv->moca_port) 258 bcm_sf2_port_intr_enable(priv, port); 259 260 /* Set per-queue pause threshold to 32 */ 261 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 262 263 /* Set ACB threshold to 24 */ 264 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 265 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 266 SF2_NUM_EGRESS_QUEUES + i)); 267 reg &= ~XOFF_THRESHOLD_MASK; 268 reg |= 24; 269 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 270 SF2_NUM_EGRESS_QUEUES + i)); 271 } 272 273 return b53_enable_port(ds, port, phy); 274 } 275 276 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 277 { 278 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 279 u32 reg; 280 281 /* Disable learning while in WoL mode */ 282 if (priv->wol_ports_mask & (1 << port)) { 283 reg = core_readl(priv, CORE_DIS_LEARN); 284 reg |= BIT(port); 285 core_writel(priv, reg, CORE_DIS_LEARN); 286 return; 287 } 288 289 if (port == priv->moca_port) 290 bcm_sf2_port_intr_disable(priv, port); 291 292 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 293 bcm_sf2_gphy_enable_set(ds, false); 294 295 b53_disable_port(ds, port); 296 297 /* Power down the port memory */ 298 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 299 reg |= P_TXQ_PSM_VDD(port); 300 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 301 302 priv->port_sts[port].enabled = false; 303 304 bcm_sf2_recalc_clock(ds); 305 } 306 307 308 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 309 int regnum, u16 val) 310 { 311 int ret = 0; 312 u32 reg; 313 314 reg = reg_readl(priv, REG_SWITCH_CNTRL); 315 reg |= MDIO_MASTER_SEL; 316 reg_writel(priv, reg, REG_SWITCH_CNTRL); 317 318 /* Page << 8 | offset */ 319 reg = 0x70; 320 reg <<= 2; 321 core_writel(priv, addr, reg); 322 323 /* Page << 8 | offset */ 324 reg = 0x80 << 8 | regnum << 1; 325 reg <<= 2; 326 327 if (op) 328 ret = core_readl(priv, reg); 329 else 330 core_writel(priv, val, reg); 331 332 reg = reg_readl(priv, REG_SWITCH_CNTRL); 333 reg &= ~MDIO_MASTER_SEL; 334 reg_writel(priv, reg, REG_SWITCH_CNTRL); 335 336 return ret & 0xffff; 337 } 338 339 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 340 { 341 struct bcm_sf2_priv *priv = bus->priv; 342 343 /* Intercept reads from Broadcom pseudo-PHY address, else, send 344 * them to our master MDIO bus controller 345 */ 346 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 347 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 348 else 349 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 350 } 351 352 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 353 u16 val) 354 { 355 struct bcm_sf2_priv *priv = bus->priv; 356 357 /* Intercept writes to the Broadcom pseudo-PHY address, else, 358 * send them to our master MDIO bus controller 359 */ 360 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 361 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 362 else 363 return mdiobus_write_nested(priv->master_mii_bus, addr, 364 regnum, val); 365 } 366 367 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 368 { 369 struct dsa_switch *ds = dev_id; 370 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 371 372 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 373 ~priv->irq0_mask; 374 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 375 376 return IRQ_HANDLED; 377 } 378 379 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 380 { 381 struct dsa_switch *ds = dev_id; 382 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 383 384 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 385 ~priv->irq1_mask; 386 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 387 388 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 389 priv->port_sts[7].link = true; 390 dsa_port_phylink_mac_change(ds, 7, true); 391 } 392 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 393 priv->port_sts[7].link = false; 394 dsa_port_phylink_mac_change(ds, 7, false); 395 } 396 397 return IRQ_HANDLED; 398 } 399 400 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 401 { 402 unsigned int timeout = 1000; 403 u32 reg; 404 int ret; 405 406 /* The watchdog reset does not work on 7278, we need to hit the 407 * "external" reset line through the reset controller. 408 */ 409 if (priv->type == BCM7278_DEVICE_ID) { 410 ret = reset_control_assert(priv->rcdev); 411 if (ret) 412 return ret; 413 414 return reset_control_deassert(priv->rcdev); 415 } 416 417 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 418 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 419 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 420 421 do { 422 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 423 if (!(reg & SOFTWARE_RESET)) 424 break; 425 426 usleep_range(1000, 2000); 427 } while (timeout-- > 0); 428 429 if (timeout == 0) 430 return -ETIMEDOUT; 431 432 return 0; 433 } 434 435 static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv) 436 { 437 struct device *dev = priv->dev->ds->dev; 438 int shift; 439 u32 mask; 440 u32 reg; 441 int i; 442 443 mask = BIT(priv->num_crossbar_int_ports) - 1; 444 445 reg = reg_readl(priv, REG_CROSSBAR); 446 switch (priv->type) { 447 case BCM4908_DEVICE_ID: 448 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports; 449 reg &= ~(mask << shift); 450 if (0) /* FIXME */ 451 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift; 452 else if (priv->int_phy_mask & BIT(7)) 453 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift; 454 else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode)) 455 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift; 456 else if (WARN(1, "Invalid port mode\n")) 457 return; 458 break; 459 default: 460 return; 461 } 462 reg_writel(priv, reg, REG_CROSSBAR); 463 464 reg = reg_readl(priv, REG_CROSSBAR); 465 for (i = 0; i < priv->num_crossbar_int_ports; i++) { 466 shift = i * priv->num_crossbar_int_ports; 467 468 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i, 469 (reg >> shift) & mask); 470 } 471 } 472 473 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 474 { 475 intrl2_0_mask_set(priv, 0xffffffff); 476 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 477 intrl2_1_mask_set(priv, 0xffffffff); 478 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 479 } 480 481 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 482 struct device_node *dn) 483 { 484 struct device *dev = priv->dev->ds->dev; 485 struct bcm_sf2_port_status *port_st; 486 struct device_node *port; 487 unsigned int port_num; 488 struct property *prop; 489 int err; 490 491 priv->moca_port = -1; 492 493 for_each_available_child_of_node(dn, port) { 494 if (of_property_read_u32(port, "reg", &port_num)) 495 continue; 496 497 if (port_num >= DSA_MAX_PORTS) { 498 dev_err(dev, "Invalid port number %d\n", port_num); 499 continue; 500 } 501 502 port_st = &priv->port_sts[port_num]; 503 504 /* Internal PHYs get assigned a specific 'phy-mode' property 505 * value: "internal" to help flag them before MDIO probing 506 * has completed, since they might be turned off at that 507 * time 508 */ 509 err = of_get_phy_mode(port, &port_st->mode); 510 if (err) 511 continue; 512 513 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL) 514 priv->int_phy_mask |= 1 << port_num; 515 516 if (port_st->mode == PHY_INTERFACE_MODE_MOCA) 517 priv->moca_port = port_num; 518 519 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 520 priv->brcm_tag_mask |= 1 << port_num; 521 522 /* Ensure that port 5 is not picked up as a DSA CPU port 523 * flavour but a regular port instead. We should be using 524 * devlink to be able to set the port flavour. 525 */ 526 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) { 527 prop = of_find_property(port, "ethernet", NULL); 528 if (prop) 529 of_remove_property(port, prop); 530 } 531 } 532 } 533 534 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 535 { 536 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 537 struct device_node *dn, *child; 538 struct phy_device *phydev; 539 struct property *prop; 540 static int index; 541 int err, reg; 542 543 /* Find our integrated MDIO bus node */ 544 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 545 priv->master_mii_bus = of_mdio_find_bus(dn); 546 if (!priv->master_mii_bus) { 547 of_node_put(dn); 548 return -EPROBE_DEFER; 549 } 550 551 get_device(&priv->master_mii_bus->dev); 552 priv->master_mii_dn = dn; 553 554 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 555 if (!priv->slave_mii_bus) { 556 of_node_put(dn); 557 return -ENOMEM; 558 } 559 560 priv->slave_mii_bus->priv = priv; 561 priv->slave_mii_bus->name = "sf2 slave mii"; 562 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 563 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 564 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 565 index++); 566 priv->slave_mii_bus->dev.of_node = dn; 567 568 /* Include the pseudo-PHY address to divert reads towards our 569 * workaround. This is only required for 7445D0, since 7445E0 570 * disconnects the internal switch pseudo-PHY such that we can use the 571 * regular SWITCH_MDIO master controller instead. 572 * 573 * Here we flag the pseudo PHY as needing special treatment and would 574 * otherwise make all other PHY read/writes go to the master MDIO bus 575 * controller that comes with this switch backed by the "mdio-unimac" 576 * driver. 577 */ 578 if (of_machine_is_compatible("brcm,bcm7445d0")) 579 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0); 580 else 581 priv->indir_phy_mask = 0; 582 583 ds->phys_mii_mask = priv->indir_phy_mask; 584 ds->slave_mii_bus = priv->slave_mii_bus; 585 priv->slave_mii_bus->parent = ds->dev->parent; 586 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 587 588 /* We need to make sure that of_phy_connect() will not work by 589 * removing the 'phandle' and 'linux,phandle' properties and 590 * unregister the existing PHY device that was already registered. 591 */ 592 for_each_available_child_of_node(dn, child) { 593 if (of_property_read_u32(child, "reg", ®) || 594 reg >= PHY_MAX_ADDR) 595 continue; 596 597 if (!(priv->indir_phy_mask & BIT(reg))) 598 continue; 599 600 prop = of_find_property(child, "phandle", NULL); 601 if (prop) 602 of_remove_property(child, prop); 603 604 prop = of_find_property(child, "linux,phandle", NULL); 605 if (prop) 606 of_remove_property(child, prop); 607 608 phydev = of_phy_find_device(child); 609 if (phydev) 610 phy_device_remove(phydev); 611 } 612 613 err = mdiobus_register(priv->slave_mii_bus); 614 if (err && dn) 615 of_node_put(dn); 616 617 return err; 618 } 619 620 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 621 { 622 mdiobus_unregister(priv->slave_mii_bus); 623 of_node_put(priv->master_mii_dn); 624 } 625 626 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 627 { 628 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 629 630 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 631 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 632 * the REG_PHY_REVISION register layout is. 633 */ 634 635 return priv->hw_params.gphy_rev; 636 } 637 638 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 639 unsigned long *supported, 640 struct phylink_link_state *state) 641 { 642 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 643 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 644 645 if (!phy_interface_mode_is_rgmii(state->interface) && 646 state->interface != PHY_INTERFACE_MODE_MII && 647 state->interface != PHY_INTERFACE_MODE_REVMII && 648 state->interface != PHY_INTERFACE_MODE_GMII && 649 state->interface != PHY_INTERFACE_MODE_INTERNAL && 650 state->interface != PHY_INTERFACE_MODE_MOCA) { 651 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 652 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 653 dev_err(ds->dev, 654 "Unsupported interface: %d for port %d\n", 655 state->interface, port); 656 return; 657 } 658 659 /* Allow all the expected bits */ 660 phylink_set(mask, Autoneg); 661 phylink_set_port_modes(mask); 662 phylink_set(mask, Pause); 663 phylink_set(mask, Asym_Pause); 664 665 /* With the exclusion of MII and Reverse MII, we support Gigabit, 666 * including Half duplex 667 */ 668 if (state->interface != PHY_INTERFACE_MODE_MII && 669 state->interface != PHY_INTERFACE_MODE_REVMII) { 670 phylink_set(mask, 1000baseT_Full); 671 phylink_set(mask, 1000baseT_Half); 672 } 673 674 phylink_set(mask, 10baseT_Half); 675 phylink_set(mask, 10baseT_Full); 676 phylink_set(mask, 100baseT_Half); 677 phylink_set(mask, 100baseT_Full); 678 679 bitmap_and(supported, supported, mask, 680 __ETHTOOL_LINK_MODE_MASK_NBITS); 681 bitmap_and(state->advertising, state->advertising, mask, 682 __ETHTOOL_LINK_MODE_MASK_NBITS); 683 } 684 685 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 686 unsigned int mode, 687 const struct phylink_link_state *state) 688 { 689 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 690 u32 id_mode_dis = 0, port_mode; 691 u32 reg; 692 693 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 694 return; 695 696 switch (state->interface) { 697 case PHY_INTERFACE_MODE_RGMII: 698 id_mode_dis = 1; 699 fallthrough; 700 case PHY_INTERFACE_MODE_RGMII_TXID: 701 port_mode = EXT_GPHY; 702 break; 703 case PHY_INTERFACE_MODE_MII: 704 port_mode = EXT_EPHY; 705 break; 706 case PHY_INTERFACE_MODE_REVMII: 707 port_mode = EXT_REVMII; 708 break; 709 default: 710 /* Nothing required for all other PHYs: internal and MoCA */ 711 return; 712 } 713 714 /* Clear id_mode_dis bit, and the existing port mode, let 715 * RGMII_MODE_EN bet set by mac_link_{up,down} 716 */ 717 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 718 reg &= ~ID_MODE_DIS; 719 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 720 721 reg |= port_mode; 722 if (id_mode_dis) 723 reg |= ID_MODE_DIS; 724 725 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 726 } 727 728 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 729 phy_interface_t interface, bool link) 730 { 731 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 732 u32 reg; 733 734 if (!phy_interface_mode_is_rgmii(interface) && 735 interface != PHY_INTERFACE_MODE_MII && 736 interface != PHY_INTERFACE_MODE_REVMII) 737 return; 738 739 /* If the link is down, just disable the interface to conserve power */ 740 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 741 if (link) 742 reg |= RGMII_MODE_EN; 743 else 744 reg &= ~RGMII_MODE_EN; 745 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 746 } 747 748 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 749 unsigned int mode, 750 phy_interface_t interface) 751 { 752 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 753 u32 reg, offset; 754 755 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 756 if (priv->type == BCM4908_DEVICE_ID || 757 priv->type == BCM7445_DEVICE_ID) 758 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 759 else 760 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 761 762 reg = core_readl(priv, offset); 763 reg &= ~LINK_STS; 764 core_writel(priv, reg, offset); 765 } 766 767 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 768 } 769 770 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 771 unsigned int mode, 772 phy_interface_t interface, 773 struct phy_device *phydev, 774 int speed, int duplex, 775 bool tx_pause, bool rx_pause) 776 { 777 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 778 struct ethtool_eee *p = &priv->dev->ports[port].eee; 779 u32 reg, offset; 780 781 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 782 783 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 784 if (priv->type == BCM4908_DEVICE_ID || 785 priv->type == BCM7445_DEVICE_ID) 786 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 787 else 788 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 789 790 if (interface == PHY_INTERFACE_MODE_RGMII || 791 interface == PHY_INTERFACE_MODE_RGMII_TXID || 792 interface == PHY_INTERFACE_MODE_MII || 793 interface == PHY_INTERFACE_MODE_REVMII) { 794 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 795 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 796 797 if (tx_pause) 798 reg |= TX_PAUSE_EN; 799 if (rx_pause) 800 reg |= RX_PAUSE_EN; 801 802 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 803 } 804 805 reg = SW_OVERRIDE | LINK_STS; 806 switch (speed) { 807 case SPEED_1000: 808 reg |= SPDSTS_1000 << SPEED_SHIFT; 809 break; 810 case SPEED_100: 811 reg |= SPDSTS_100 << SPEED_SHIFT; 812 break; 813 } 814 815 if (duplex == DUPLEX_FULL) 816 reg |= DUPLX_MODE; 817 818 core_writel(priv, reg, offset); 819 } 820 821 if (mode == MLO_AN_PHY && phydev) 822 p->eee_enabled = b53_eee_init(ds, port, phydev); 823 } 824 825 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 826 struct phylink_link_state *status) 827 { 828 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 829 830 status->link = false; 831 832 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 833 * which means that we need to force the link at the port override 834 * level to get the data to flow. We do use what the interrupt handler 835 * did determine before. 836 * 837 * For the other ports, we just force the link status, since this is 838 * a fixed PHY device. 839 */ 840 if (port == priv->moca_port) { 841 status->link = priv->port_sts[port].link; 842 /* For MoCA interfaces, also force a link down notification 843 * since some version of the user-space daemon (mocad) use 844 * cmd->autoneg to force the link, which messes up the PHY 845 * state machine and make it go in PHY_FORCING state instead. 846 */ 847 if (!status->link) 848 netif_carrier_off(dsa_to_port(ds, port)->slave); 849 status->duplex = DUPLEX_FULL; 850 } else { 851 status->link = true; 852 } 853 } 854 855 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 856 { 857 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 858 u32 reg; 859 860 /* Enable ACB globally */ 861 reg = acb_readl(priv, ACB_CONTROL); 862 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 863 acb_writel(priv, reg, ACB_CONTROL); 864 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 865 reg |= ACB_EN | ACB_ALGORITHM; 866 acb_writel(priv, reg, ACB_CONTROL); 867 } 868 869 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 870 { 871 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 872 unsigned int port; 873 874 bcm_sf2_intr_disable(priv); 875 876 /* Disable all ports physically present including the IMP 877 * port, the other ones have already been disabled during 878 * bcm_sf2_sw_setup 879 */ 880 for (port = 0; port < ds->num_ports; port++) { 881 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 882 bcm_sf2_port_disable(ds, port); 883 } 884 885 if (!priv->wol_ports_mask) 886 clk_disable_unprepare(priv->clk); 887 888 return 0; 889 } 890 891 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 892 { 893 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 894 int ret; 895 896 if (!priv->wol_ports_mask) 897 clk_prepare_enable(priv->clk); 898 899 ret = bcm_sf2_sw_rst(priv); 900 if (ret) { 901 pr_err("%s: failed to software reset switch\n", __func__); 902 return ret; 903 } 904 905 bcm_sf2_crossbar_setup(priv); 906 907 ret = bcm_sf2_cfp_resume(ds); 908 if (ret) 909 return ret; 910 911 if (priv->hw_params.num_gphy == 1) 912 bcm_sf2_gphy_enable_set(ds, true); 913 914 ds->ops->setup(ds); 915 916 return 0; 917 } 918 919 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 920 struct ethtool_wolinfo *wol) 921 { 922 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 923 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 924 struct ethtool_wolinfo pwol = { }; 925 926 /* Get the parent device WoL settings */ 927 if (p->ethtool_ops->get_wol) 928 p->ethtool_ops->get_wol(p, &pwol); 929 930 /* Advertise the parent device supported settings */ 931 wol->supported = pwol.supported; 932 memset(&wol->sopass, 0, sizeof(wol->sopass)); 933 934 if (pwol.wolopts & WAKE_MAGICSECURE) 935 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 936 937 if (priv->wol_ports_mask & (1 << port)) 938 wol->wolopts = pwol.wolopts; 939 else 940 wol->wolopts = 0; 941 } 942 943 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 944 struct ethtool_wolinfo *wol) 945 { 946 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 947 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 948 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 949 struct ethtool_wolinfo pwol = { }; 950 951 if (p->ethtool_ops->get_wol) 952 p->ethtool_ops->get_wol(p, &pwol); 953 if (wol->wolopts & ~pwol.supported) 954 return -EINVAL; 955 956 if (wol->wolopts) 957 priv->wol_ports_mask |= (1 << port); 958 else 959 priv->wol_ports_mask &= ~(1 << port); 960 961 /* If we have at least one port enabled, make sure the CPU port 962 * is also enabled. If the CPU port is the last one enabled, we disable 963 * it since this configuration does not make sense. 964 */ 965 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 966 priv->wol_ports_mask |= (1 << cpu_port); 967 else 968 priv->wol_ports_mask &= ~(1 << cpu_port); 969 970 return p->ethtool_ops->set_wol(p, wol); 971 } 972 973 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 974 { 975 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 976 unsigned int port; 977 978 /* Enable all valid ports and disable those unused */ 979 for (port = 0; port < priv->hw_params.num_ports; port++) { 980 /* IMP port receives special treatment */ 981 if (dsa_is_user_port(ds, port)) 982 bcm_sf2_port_setup(ds, port, NULL); 983 else if (dsa_is_cpu_port(ds, port)) 984 bcm_sf2_imp_setup(ds, port); 985 else 986 bcm_sf2_port_disable(ds, port); 987 } 988 989 b53_configure_vlan(ds); 990 bcm_sf2_enable_acb(ds); 991 992 return b53_setup_devlink_resources(ds); 993 } 994 995 static void bcm_sf2_sw_teardown(struct dsa_switch *ds) 996 { 997 dsa_devlink_resources_unregister(ds); 998 } 999 1000 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 1001 * register basis so we need to translate that into an address that the 1002 * bus-glue understands. 1003 */ 1004 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 1005 1006 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 1007 u8 *val) 1008 { 1009 struct bcm_sf2_priv *priv = dev->priv; 1010 1011 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1012 1013 return 0; 1014 } 1015 1016 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 1017 u16 *val) 1018 { 1019 struct bcm_sf2_priv *priv = dev->priv; 1020 1021 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1022 1023 return 0; 1024 } 1025 1026 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 1027 u32 *val) 1028 { 1029 struct bcm_sf2_priv *priv = dev->priv; 1030 1031 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1032 1033 return 0; 1034 } 1035 1036 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 1037 u64 *val) 1038 { 1039 struct bcm_sf2_priv *priv = dev->priv; 1040 1041 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 1042 1043 return 0; 1044 } 1045 1046 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 1047 u8 value) 1048 { 1049 struct bcm_sf2_priv *priv = dev->priv; 1050 1051 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1052 1053 return 0; 1054 } 1055 1056 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 1057 u16 value) 1058 { 1059 struct bcm_sf2_priv *priv = dev->priv; 1060 1061 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1062 1063 return 0; 1064 } 1065 1066 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 1067 u32 value) 1068 { 1069 struct bcm_sf2_priv *priv = dev->priv; 1070 1071 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1072 1073 return 0; 1074 } 1075 1076 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 1077 u64 value) 1078 { 1079 struct bcm_sf2_priv *priv = dev->priv; 1080 1081 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1082 1083 return 0; 1084 } 1085 1086 static const struct b53_io_ops bcm_sf2_io_ops = { 1087 .read8 = bcm_sf2_core_read8, 1088 .read16 = bcm_sf2_core_read16, 1089 .read32 = bcm_sf2_core_read32, 1090 .read48 = bcm_sf2_core_read64, 1091 .read64 = bcm_sf2_core_read64, 1092 .write8 = bcm_sf2_core_write8, 1093 .write16 = bcm_sf2_core_write16, 1094 .write32 = bcm_sf2_core_write32, 1095 .write48 = bcm_sf2_core_write64, 1096 .write64 = bcm_sf2_core_write64, 1097 }; 1098 1099 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 1100 u32 stringset, uint8_t *data) 1101 { 1102 int cnt = b53_get_sset_count(ds, port, stringset); 1103 1104 b53_get_strings(ds, port, stringset, data); 1105 bcm_sf2_cfp_get_strings(ds, port, stringset, 1106 data + cnt * ETH_GSTRING_LEN); 1107 } 1108 1109 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 1110 uint64_t *data) 1111 { 1112 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 1113 1114 b53_get_ethtool_stats(ds, port, data); 1115 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 1116 } 1117 1118 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 1119 int sset) 1120 { 1121 int cnt = b53_get_sset_count(ds, port, sset); 1122 1123 if (cnt < 0) 1124 return cnt; 1125 1126 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 1127 1128 return cnt; 1129 } 1130 1131 static const struct dsa_switch_ops bcm_sf2_ops = { 1132 .get_tag_protocol = b53_get_tag_protocol, 1133 .setup = bcm_sf2_sw_setup, 1134 .teardown = bcm_sf2_sw_teardown, 1135 .get_strings = bcm_sf2_sw_get_strings, 1136 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 1137 .get_sset_count = bcm_sf2_sw_get_sset_count, 1138 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1139 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 1140 .phylink_validate = bcm_sf2_sw_validate, 1141 .phylink_mac_config = bcm_sf2_sw_mac_config, 1142 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 1143 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 1144 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 1145 .suspend = bcm_sf2_sw_suspend, 1146 .resume = bcm_sf2_sw_resume, 1147 .get_wol = bcm_sf2_sw_get_wol, 1148 .set_wol = bcm_sf2_sw_set_wol, 1149 .port_enable = bcm_sf2_port_setup, 1150 .port_disable = bcm_sf2_port_disable, 1151 .get_mac_eee = b53_get_mac_eee, 1152 .set_mac_eee = b53_set_mac_eee, 1153 .port_bridge_join = b53_br_join, 1154 .port_bridge_leave = b53_br_leave, 1155 .port_pre_bridge_flags = b53_br_flags_pre, 1156 .port_bridge_flags = b53_br_flags, 1157 .port_stp_state_set = b53_br_set_stp_state, 1158 .port_set_mrouter = b53_set_mrouter, 1159 .port_fast_age = b53_br_fast_age, 1160 .port_vlan_filtering = b53_vlan_filtering, 1161 .port_vlan_add = b53_vlan_add, 1162 .port_vlan_del = b53_vlan_del, 1163 .port_fdb_dump = b53_fdb_dump, 1164 .port_fdb_add = b53_fdb_add, 1165 .port_fdb_del = b53_fdb_del, 1166 .get_rxnfc = bcm_sf2_get_rxnfc, 1167 .set_rxnfc = bcm_sf2_set_rxnfc, 1168 .port_mirror_add = b53_mirror_add, 1169 .port_mirror_del = b53_mirror_del, 1170 .port_mdb_add = b53_mdb_add, 1171 .port_mdb_del = b53_mdb_del, 1172 }; 1173 1174 struct bcm_sf2_of_data { 1175 u32 type; 1176 const u16 *reg_offsets; 1177 unsigned int core_reg_align; 1178 unsigned int num_cfp_rules; 1179 unsigned int num_crossbar_int_ports; 1180 }; 1181 1182 static const u16 bcm_sf2_4908_reg_offsets[] = { 1183 [REG_SWITCH_CNTRL] = 0x00, 1184 [REG_SWITCH_STATUS] = 0x04, 1185 [REG_DIR_DATA_WRITE] = 0x08, 1186 [REG_DIR_DATA_READ] = 0x0c, 1187 [REG_SWITCH_REVISION] = 0x10, 1188 [REG_PHY_REVISION] = 0x14, 1189 [REG_SPHY_CNTRL] = 0x24, 1190 [REG_CROSSBAR] = 0xc8, 1191 [REG_RGMII_0_CNTRL] = 0xe0, 1192 [REG_RGMII_1_CNTRL] = 0xec, 1193 [REG_RGMII_2_CNTRL] = 0xf8, 1194 [REG_LED_0_CNTRL] = 0x40, 1195 [REG_LED_1_CNTRL] = 0x4c, 1196 [REG_LED_2_CNTRL] = 0x58, 1197 }; 1198 1199 static const struct bcm_sf2_of_data bcm_sf2_4908_data = { 1200 .type = BCM4908_DEVICE_ID, 1201 .core_reg_align = 0, 1202 .reg_offsets = bcm_sf2_4908_reg_offsets, 1203 .num_cfp_rules = 256, 1204 .num_crossbar_int_ports = 2, 1205 }; 1206 1207 /* Register offsets for the SWITCH_REG_* block */ 1208 static const u16 bcm_sf2_7445_reg_offsets[] = { 1209 [REG_SWITCH_CNTRL] = 0x00, 1210 [REG_SWITCH_STATUS] = 0x04, 1211 [REG_DIR_DATA_WRITE] = 0x08, 1212 [REG_DIR_DATA_READ] = 0x0C, 1213 [REG_SWITCH_REVISION] = 0x18, 1214 [REG_PHY_REVISION] = 0x1C, 1215 [REG_SPHY_CNTRL] = 0x2C, 1216 [REG_RGMII_0_CNTRL] = 0x34, 1217 [REG_RGMII_1_CNTRL] = 0x40, 1218 [REG_RGMII_2_CNTRL] = 0x4c, 1219 [REG_LED_0_CNTRL] = 0x90, 1220 [REG_LED_1_CNTRL] = 0x94, 1221 [REG_LED_2_CNTRL] = 0x98, 1222 }; 1223 1224 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1225 .type = BCM7445_DEVICE_ID, 1226 .core_reg_align = 0, 1227 .reg_offsets = bcm_sf2_7445_reg_offsets, 1228 .num_cfp_rules = 256, 1229 }; 1230 1231 static const u16 bcm_sf2_7278_reg_offsets[] = { 1232 [REG_SWITCH_CNTRL] = 0x00, 1233 [REG_SWITCH_STATUS] = 0x04, 1234 [REG_DIR_DATA_WRITE] = 0x08, 1235 [REG_DIR_DATA_READ] = 0x0c, 1236 [REG_SWITCH_REVISION] = 0x10, 1237 [REG_PHY_REVISION] = 0x14, 1238 [REG_SPHY_CNTRL] = 0x24, 1239 [REG_RGMII_0_CNTRL] = 0xe0, 1240 [REG_RGMII_1_CNTRL] = 0xec, 1241 [REG_RGMII_2_CNTRL] = 0xf8, 1242 [REG_LED_0_CNTRL] = 0x40, 1243 [REG_LED_1_CNTRL] = 0x4c, 1244 [REG_LED_2_CNTRL] = 0x58, 1245 }; 1246 1247 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1248 .type = BCM7278_DEVICE_ID, 1249 .core_reg_align = 1, 1250 .reg_offsets = bcm_sf2_7278_reg_offsets, 1251 .num_cfp_rules = 128, 1252 }; 1253 1254 static const struct of_device_id bcm_sf2_of_match[] = { 1255 { .compatible = "brcm,bcm4908-switch", 1256 .data = &bcm_sf2_4908_data 1257 }, 1258 { .compatible = "brcm,bcm7445-switch-v4.0", 1259 .data = &bcm_sf2_7445_data 1260 }, 1261 { .compatible = "brcm,bcm7278-switch-v4.0", 1262 .data = &bcm_sf2_7278_data 1263 }, 1264 { .compatible = "brcm,bcm7278-switch-v4.8", 1265 .data = &bcm_sf2_7278_data 1266 }, 1267 { /* sentinel */ }, 1268 }; 1269 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1270 1271 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1272 { 1273 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1274 struct device_node *dn = pdev->dev.of_node; 1275 const struct of_device_id *of_id = NULL; 1276 const struct bcm_sf2_of_data *data; 1277 struct b53_platform_data *pdata; 1278 struct dsa_switch_ops *ops; 1279 struct device_node *ports; 1280 struct bcm_sf2_priv *priv; 1281 struct b53_device *dev; 1282 struct dsa_switch *ds; 1283 void __iomem **base; 1284 unsigned int i; 1285 u32 reg, rev; 1286 int ret; 1287 1288 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1289 if (!priv) 1290 return -ENOMEM; 1291 1292 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1293 if (!ops) 1294 return -ENOMEM; 1295 1296 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1297 if (!dev) 1298 return -ENOMEM; 1299 1300 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1301 if (!pdata) 1302 return -ENOMEM; 1303 1304 of_id = of_match_node(bcm_sf2_of_match, dn); 1305 if (!of_id || !of_id->data) 1306 return -EINVAL; 1307 1308 data = of_id->data; 1309 1310 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1311 priv->type = data->type; 1312 priv->reg_offsets = data->reg_offsets; 1313 priv->core_reg_align = data->core_reg_align; 1314 priv->num_cfp_rules = data->num_cfp_rules; 1315 priv->num_crossbar_int_ports = data->num_crossbar_int_ports; 1316 1317 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1318 "switch"); 1319 if (IS_ERR(priv->rcdev)) 1320 return PTR_ERR(priv->rcdev); 1321 1322 /* Auto-detection using standard registers will not work, so 1323 * provide an indication of what kind of device we are for 1324 * b53_common to work with 1325 */ 1326 pdata->chip_id = priv->type; 1327 dev->pdata = pdata; 1328 1329 priv->dev = dev; 1330 ds = dev->ds; 1331 ds->ops = &bcm_sf2_ops; 1332 1333 /* Advertise the 8 egress queues */ 1334 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1335 1336 dev_set_drvdata(&pdev->dev, priv); 1337 1338 spin_lock_init(&priv->indir_lock); 1339 mutex_init(&priv->cfp.lock); 1340 INIT_LIST_HEAD(&priv->cfp.rules_list); 1341 1342 /* CFP rule #0 cannot be used for specific classifications, flag it as 1343 * permanently used 1344 */ 1345 set_bit(0, priv->cfp.used); 1346 set_bit(0, priv->cfp.unique); 1347 1348 /* Balance of_node_put() done by of_find_node_by_name() */ 1349 of_node_get(dn); 1350 ports = of_find_node_by_name(dn, "ports"); 1351 if (ports) { 1352 bcm_sf2_identify_ports(priv, ports); 1353 of_node_put(ports); 1354 } 1355 1356 priv->irq0 = irq_of_parse_and_map(dn, 0); 1357 priv->irq1 = irq_of_parse_and_map(dn, 1); 1358 1359 base = &priv->core; 1360 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1361 *base = devm_platform_ioremap_resource(pdev, i); 1362 if (IS_ERR(*base)) { 1363 pr_err("unable to find register: %s\n", reg_names[i]); 1364 return PTR_ERR(*base); 1365 } 1366 base++; 1367 } 1368 1369 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch"); 1370 if (IS_ERR(priv->clk)) 1371 return PTR_ERR(priv->clk); 1372 1373 clk_prepare_enable(priv->clk); 1374 1375 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv"); 1376 if (IS_ERR(priv->clk_mdiv)) { 1377 ret = PTR_ERR(priv->clk_mdiv); 1378 goto out_clk; 1379 } 1380 1381 clk_prepare_enable(priv->clk_mdiv); 1382 1383 ret = bcm_sf2_sw_rst(priv); 1384 if (ret) { 1385 pr_err("unable to software reset switch: %d\n", ret); 1386 goto out_clk_mdiv; 1387 } 1388 1389 bcm_sf2_crossbar_setup(priv); 1390 1391 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1392 1393 ret = bcm_sf2_mdio_register(ds); 1394 if (ret) { 1395 pr_err("failed to register MDIO bus\n"); 1396 goto out_clk_mdiv; 1397 } 1398 1399 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1400 1401 ret = bcm_sf2_cfp_rst(priv); 1402 if (ret) { 1403 pr_err("failed to reset CFP\n"); 1404 goto out_mdio; 1405 } 1406 1407 /* Disable all interrupts and request them */ 1408 bcm_sf2_intr_disable(priv); 1409 1410 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1411 "switch_0", ds); 1412 if (ret < 0) { 1413 pr_err("failed to request switch_0 IRQ\n"); 1414 goto out_mdio; 1415 } 1416 1417 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1418 "switch_1", ds); 1419 if (ret < 0) { 1420 pr_err("failed to request switch_1 IRQ\n"); 1421 goto out_mdio; 1422 } 1423 1424 /* Reset the MIB counters */ 1425 reg = core_readl(priv, CORE_GMNCFGCFG); 1426 reg |= RST_MIB_CNT; 1427 core_writel(priv, reg, CORE_GMNCFGCFG); 1428 reg &= ~RST_MIB_CNT; 1429 core_writel(priv, reg, CORE_GMNCFGCFG); 1430 1431 /* Get the maximum number of ports for this switch */ 1432 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1433 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1434 priv->hw_params.num_ports = DSA_MAX_PORTS; 1435 1436 /* Assume a single GPHY setup if we can't read that property */ 1437 if (of_property_read_u32(dn, "brcm,num-gphy", 1438 &priv->hw_params.num_gphy)) 1439 priv->hw_params.num_gphy = 1; 1440 1441 rev = reg_readl(priv, REG_SWITCH_REVISION); 1442 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1443 SWITCH_TOP_REV_MASK; 1444 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1445 1446 rev = reg_readl(priv, REG_PHY_REVISION); 1447 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1448 1449 ret = b53_switch_register(dev); 1450 if (ret) 1451 goto out_mdio; 1452 1453 dev_info(&pdev->dev, 1454 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1455 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1456 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1457 priv->irq0, priv->irq1); 1458 1459 return 0; 1460 1461 out_mdio: 1462 bcm_sf2_mdio_unregister(priv); 1463 out_clk_mdiv: 1464 clk_disable_unprepare(priv->clk_mdiv); 1465 out_clk: 1466 clk_disable_unprepare(priv->clk); 1467 return ret; 1468 } 1469 1470 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1471 { 1472 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1473 1474 priv->wol_ports_mask = 0; 1475 /* Disable interrupts */ 1476 bcm_sf2_intr_disable(priv); 1477 dsa_unregister_switch(priv->dev->ds); 1478 bcm_sf2_cfp_exit(priv->dev->ds); 1479 bcm_sf2_mdio_unregister(priv); 1480 clk_disable_unprepare(priv->clk_mdiv); 1481 clk_disable_unprepare(priv->clk); 1482 if (priv->type == BCM7278_DEVICE_ID) 1483 reset_control_assert(priv->rcdev); 1484 1485 return 0; 1486 } 1487 1488 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1489 { 1490 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1491 1492 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1493 * successful MDIO bus scan to occur. If we did turn off the GPHY 1494 * before (e.g: port_disable), this will also power it back on. 1495 * 1496 * Do not rely on kexec_in_progress, just power the PHY on. 1497 */ 1498 if (priv->hw_params.num_gphy == 1) 1499 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1500 } 1501 1502 #ifdef CONFIG_PM_SLEEP 1503 static int bcm_sf2_suspend(struct device *dev) 1504 { 1505 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1506 1507 return dsa_switch_suspend(priv->dev->ds); 1508 } 1509 1510 static int bcm_sf2_resume(struct device *dev) 1511 { 1512 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1513 1514 return dsa_switch_resume(priv->dev->ds); 1515 } 1516 #endif /* CONFIG_PM_SLEEP */ 1517 1518 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1519 bcm_sf2_suspend, bcm_sf2_resume); 1520 1521 1522 static struct platform_driver bcm_sf2_driver = { 1523 .probe = bcm_sf2_sw_probe, 1524 .remove = bcm_sf2_sw_remove, 1525 .shutdown = bcm_sf2_sw_shutdown, 1526 .driver = { 1527 .name = "brcm-sf2", 1528 .of_match_table = bcm_sf2_of_match, 1529 .pm = &bcm_sf2_pm_ops, 1530 }, 1531 }; 1532 module_platform_driver(bcm_sf2_driver); 1533 1534 MODULE_AUTHOR("Broadcom Corporation"); 1535 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1536 MODULE_LICENSE("GPL"); 1537 MODULE_ALIAS("platform:brcm-sf2"); 1538