1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/of.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_address.h> 20 #include <linux/of_net.h> 21 #include <linux/of_mdio.h> 22 #include <net/dsa.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_bridge.h> 25 #include <linux/brcmphy.h> 26 #include <linux/etherdevice.h> 27 #include <linux/platform_data/b53.h> 28 29 #include "bcm_sf2.h" 30 #include "bcm_sf2_regs.h" 31 #include "b53/b53_priv.h" 32 #include "b53/b53_regs.h" 33 34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 35 { 36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 37 unsigned int i; 38 u32 reg, offset; 39 40 /* Enable the port memories */ 41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 42 reg &= ~P_TXQ_PSM_VDD(port); 43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 44 45 /* Enable forwarding */ 46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 47 48 /* Enable IMP port in dumb mode */ 49 reg = core_readl(priv, CORE_SWITCH_CTRL); 50 reg |= MII_DUMB_FWDG_EN; 51 core_writel(priv, reg, CORE_SWITCH_CTRL); 52 53 /* Configure Traffic Class to QoS mapping, allow each priority to map 54 * to a different queue number 55 */ 56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 58 reg |= i << (PRT_TO_QID_SHIFT * i); 59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 60 61 b53_brcm_hdr_setup(ds, port); 62 63 if (port == 8) { 64 if (priv->type == BCM7445_DEVICE_ID) 65 offset = CORE_STS_OVERRIDE_IMP; 66 else 67 offset = CORE_STS_OVERRIDE_IMP2; 68 69 /* Force link status for IMP port */ 70 reg = core_readl(priv, offset); 71 reg |= (MII_SW_OR | LINK_STS); 72 reg &= ~GMII_SPEED_UP_2G; 73 core_writel(priv, reg, offset); 74 75 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 76 reg = core_readl(priv, CORE_IMP_CTL); 77 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 78 reg &= ~(RX_DIS | TX_DIS); 79 core_writel(priv, reg, CORE_IMP_CTL); 80 } else { 81 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 82 reg &= ~(RX_DIS | TX_DIS); 83 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 84 } 85 } 86 87 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 88 { 89 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 90 u32 reg; 91 92 reg = reg_readl(priv, REG_SPHY_CNTRL); 93 if (enable) { 94 reg |= PHY_RESET; 95 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 96 reg_writel(priv, reg, REG_SPHY_CNTRL); 97 udelay(21); 98 reg = reg_readl(priv, REG_SPHY_CNTRL); 99 reg &= ~PHY_RESET; 100 } else { 101 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 102 reg_writel(priv, reg, REG_SPHY_CNTRL); 103 mdelay(1); 104 reg |= CK25_DIS; 105 } 106 reg_writel(priv, reg, REG_SPHY_CNTRL); 107 108 /* Use PHY-driven LED signaling */ 109 if (!enable) { 110 reg = reg_readl(priv, REG_LED_CNTRL(0)); 111 reg |= SPDLNK_SRC_SEL; 112 reg_writel(priv, reg, REG_LED_CNTRL(0)); 113 } 114 } 115 116 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 117 int port) 118 { 119 unsigned int off; 120 121 switch (port) { 122 case 7: 123 off = P7_IRQ_OFF; 124 break; 125 case 0: 126 /* Port 0 interrupts are located on the first bank */ 127 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 128 return; 129 default: 130 off = P_IRQ_OFF(port); 131 break; 132 } 133 134 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 135 } 136 137 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 138 int port) 139 { 140 unsigned int off; 141 142 switch (port) { 143 case 7: 144 off = P7_IRQ_OFF; 145 break; 146 case 0: 147 /* Port 0 interrupts are located on the first bank */ 148 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 149 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 150 return; 151 default: 152 off = P_IRQ_OFF(port); 153 break; 154 } 155 156 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 157 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 158 } 159 160 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 161 struct phy_device *phy) 162 { 163 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 164 unsigned int i; 165 u32 reg; 166 167 if (!dsa_is_user_port(ds, port)) 168 return 0; 169 170 /* Clear the memory power down */ 171 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 172 reg &= ~P_TXQ_PSM_VDD(port); 173 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 174 175 /* Enable learning */ 176 reg = core_readl(priv, CORE_DIS_LEARN); 177 reg &= ~BIT(port); 178 core_writel(priv, reg, CORE_DIS_LEARN); 179 180 /* Enable Broadcom tags for that port if requested */ 181 if (priv->brcm_tag_mask & BIT(port)) { 182 b53_brcm_hdr_setup(ds, port); 183 184 /* Disable learning on ASP port */ 185 if (port == 7) { 186 reg = core_readl(priv, CORE_DIS_LEARN); 187 reg |= BIT(port); 188 core_writel(priv, reg, CORE_DIS_LEARN); 189 } 190 } 191 192 /* Configure Traffic Class to QoS mapping, allow each priority to map 193 * to a different queue number 194 */ 195 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 196 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 197 reg |= i << (PRT_TO_QID_SHIFT * i); 198 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 199 200 /* Re-enable the GPHY and re-apply workarounds */ 201 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 202 bcm_sf2_gphy_enable_set(ds, true); 203 if (phy) { 204 /* if phy_stop() has been called before, phy 205 * will be in halted state, and phy_start() 206 * will call resume. 207 * 208 * the resume path does not configure back 209 * autoneg settings, and since we hard reset 210 * the phy manually here, we need to reset the 211 * state machine also. 212 */ 213 phy->state = PHY_READY; 214 phy_init_hw(phy); 215 } 216 } 217 218 /* Enable MoCA port interrupts to get notified */ 219 if (port == priv->moca_port) 220 bcm_sf2_port_intr_enable(priv, port); 221 222 /* Set per-queue pause threshold to 32 */ 223 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 224 225 /* Set ACB threshold to 24 */ 226 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 227 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 228 SF2_NUM_EGRESS_QUEUES + i)); 229 reg &= ~XOFF_THRESHOLD_MASK; 230 reg |= 24; 231 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 232 SF2_NUM_EGRESS_QUEUES + i)); 233 } 234 235 return b53_enable_port(ds, port, phy); 236 } 237 238 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 239 { 240 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 241 u32 reg; 242 243 /* Disable learning while in WoL mode */ 244 if (priv->wol_ports_mask & (1 << port)) { 245 reg = core_readl(priv, CORE_DIS_LEARN); 246 reg |= BIT(port); 247 core_writel(priv, reg, CORE_DIS_LEARN); 248 return; 249 } 250 251 if (port == priv->moca_port) 252 bcm_sf2_port_intr_disable(priv, port); 253 254 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 255 bcm_sf2_gphy_enable_set(ds, false); 256 257 b53_disable_port(ds, port); 258 259 /* Power down the port memory */ 260 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 261 reg |= P_TXQ_PSM_VDD(port); 262 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 263 } 264 265 266 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 267 int regnum, u16 val) 268 { 269 int ret = 0; 270 u32 reg; 271 272 reg = reg_readl(priv, REG_SWITCH_CNTRL); 273 reg |= MDIO_MASTER_SEL; 274 reg_writel(priv, reg, REG_SWITCH_CNTRL); 275 276 /* Page << 8 | offset */ 277 reg = 0x70; 278 reg <<= 2; 279 core_writel(priv, addr, reg); 280 281 /* Page << 8 | offset */ 282 reg = 0x80 << 8 | regnum << 1; 283 reg <<= 2; 284 285 if (op) 286 ret = core_readl(priv, reg); 287 else 288 core_writel(priv, val, reg); 289 290 reg = reg_readl(priv, REG_SWITCH_CNTRL); 291 reg &= ~MDIO_MASTER_SEL; 292 reg_writel(priv, reg, REG_SWITCH_CNTRL); 293 294 return ret & 0xffff; 295 } 296 297 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 298 { 299 struct bcm_sf2_priv *priv = bus->priv; 300 301 /* Intercept reads from Broadcom pseudo-PHY address, else, send 302 * them to our master MDIO bus controller 303 */ 304 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 305 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 306 else 307 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 308 } 309 310 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 311 u16 val) 312 { 313 struct bcm_sf2_priv *priv = bus->priv; 314 315 /* Intercept writes to the Broadcom pseudo-PHY address, else, 316 * send them to our master MDIO bus controller 317 */ 318 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 319 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 320 else 321 return mdiobus_write_nested(priv->master_mii_bus, addr, 322 regnum, val); 323 } 324 325 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 326 { 327 struct dsa_switch *ds = dev_id; 328 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 329 330 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 331 ~priv->irq0_mask; 332 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 333 334 return IRQ_HANDLED; 335 } 336 337 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 338 { 339 struct dsa_switch *ds = dev_id; 340 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 341 342 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 343 ~priv->irq1_mask; 344 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 345 346 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 347 priv->port_sts[7].link = true; 348 dsa_port_phylink_mac_change(ds, 7, true); 349 } 350 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 351 priv->port_sts[7].link = false; 352 dsa_port_phylink_mac_change(ds, 7, false); 353 } 354 355 return IRQ_HANDLED; 356 } 357 358 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 359 { 360 unsigned int timeout = 1000; 361 u32 reg; 362 int ret; 363 364 /* The watchdog reset does not work on 7278, we need to hit the 365 * "external" reset line through the reset controller. 366 */ 367 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) { 368 ret = reset_control_assert(priv->rcdev); 369 if (ret) 370 return ret; 371 372 return reset_control_deassert(priv->rcdev); 373 } 374 375 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 376 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 377 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 378 379 do { 380 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 381 if (!(reg & SOFTWARE_RESET)) 382 break; 383 384 usleep_range(1000, 2000); 385 } while (timeout-- > 0); 386 387 if (timeout == 0) 388 return -ETIMEDOUT; 389 390 return 0; 391 } 392 393 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 394 { 395 intrl2_0_mask_set(priv, 0xffffffff); 396 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 397 intrl2_1_mask_set(priv, 0xffffffff); 398 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 399 } 400 401 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 402 struct device_node *dn) 403 { 404 struct device_node *port; 405 unsigned int port_num; 406 phy_interface_t mode; 407 int err; 408 409 priv->moca_port = -1; 410 411 for_each_available_child_of_node(dn, port) { 412 if (of_property_read_u32(port, "reg", &port_num)) 413 continue; 414 415 /* Internal PHYs get assigned a specific 'phy-mode' property 416 * value: "internal" to help flag them before MDIO probing 417 * has completed, since they might be turned off at that 418 * time 419 */ 420 err = of_get_phy_mode(port, &mode); 421 if (err) 422 continue; 423 424 if (mode == PHY_INTERFACE_MODE_INTERNAL) 425 priv->int_phy_mask |= 1 << port_num; 426 427 if (mode == PHY_INTERFACE_MODE_MOCA) 428 priv->moca_port = port_num; 429 430 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 431 priv->brcm_tag_mask |= 1 << port_num; 432 } 433 } 434 435 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 436 { 437 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 438 struct device_node *dn; 439 static int index; 440 int err; 441 442 /* Find our integrated MDIO bus node */ 443 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 444 priv->master_mii_bus = of_mdio_find_bus(dn); 445 if (!priv->master_mii_bus) 446 return -EPROBE_DEFER; 447 448 get_device(&priv->master_mii_bus->dev); 449 priv->master_mii_dn = dn; 450 451 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 452 if (!priv->slave_mii_bus) 453 return -ENOMEM; 454 455 priv->slave_mii_bus->priv = priv; 456 priv->slave_mii_bus->name = "sf2 slave mii"; 457 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 458 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 459 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 460 index++); 461 priv->slave_mii_bus->dev.of_node = dn; 462 463 /* Include the pseudo-PHY address to divert reads towards our 464 * workaround. This is only required for 7445D0, since 7445E0 465 * disconnects the internal switch pseudo-PHY such that we can use the 466 * regular SWITCH_MDIO master controller instead. 467 * 468 * Here we flag the pseudo PHY as needing special treatment and would 469 * otherwise make all other PHY read/writes go to the master MDIO bus 470 * controller that comes with this switch backed by the "mdio-unimac" 471 * driver. 472 */ 473 if (of_machine_is_compatible("brcm,bcm7445d0")) 474 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 475 else 476 priv->indir_phy_mask = 0; 477 478 ds->phys_mii_mask = priv->indir_phy_mask; 479 ds->slave_mii_bus = priv->slave_mii_bus; 480 priv->slave_mii_bus->parent = ds->dev->parent; 481 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 482 483 err = mdiobus_register(priv->slave_mii_bus); 484 if (err && dn) 485 of_node_put(dn); 486 487 return err; 488 } 489 490 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 491 { 492 mdiobus_unregister(priv->slave_mii_bus); 493 of_node_put(priv->master_mii_dn); 494 } 495 496 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 497 { 498 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 499 500 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 501 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 502 * the REG_PHY_REVISION register layout is. 503 */ 504 505 return priv->hw_params.gphy_rev; 506 } 507 508 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 509 unsigned long *supported, 510 struct phylink_link_state *state) 511 { 512 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 513 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 514 515 if (!phy_interface_mode_is_rgmii(state->interface) && 516 state->interface != PHY_INTERFACE_MODE_MII && 517 state->interface != PHY_INTERFACE_MODE_REVMII && 518 state->interface != PHY_INTERFACE_MODE_GMII && 519 state->interface != PHY_INTERFACE_MODE_INTERNAL && 520 state->interface != PHY_INTERFACE_MODE_MOCA) { 521 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 522 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 523 dev_err(ds->dev, 524 "Unsupported interface: %d for port %d\n", 525 state->interface, port); 526 return; 527 } 528 529 /* Allow all the expected bits */ 530 phylink_set(mask, Autoneg); 531 phylink_set_port_modes(mask); 532 phylink_set(mask, Pause); 533 phylink_set(mask, Asym_Pause); 534 535 /* With the exclusion of MII and Reverse MII, we support Gigabit, 536 * including Half duplex 537 */ 538 if (state->interface != PHY_INTERFACE_MODE_MII && 539 state->interface != PHY_INTERFACE_MODE_REVMII) { 540 phylink_set(mask, 1000baseT_Full); 541 phylink_set(mask, 1000baseT_Half); 542 } 543 544 phylink_set(mask, 10baseT_Half); 545 phylink_set(mask, 10baseT_Full); 546 phylink_set(mask, 100baseT_Half); 547 phylink_set(mask, 100baseT_Full); 548 549 bitmap_and(supported, supported, mask, 550 __ETHTOOL_LINK_MODE_MASK_NBITS); 551 bitmap_and(state->advertising, state->advertising, mask, 552 __ETHTOOL_LINK_MODE_MASK_NBITS); 553 } 554 555 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 556 unsigned int mode, 557 const struct phylink_link_state *state) 558 { 559 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 560 u32 id_mode_dis = 0, port_mode; 561 u32 reg, offset; 562 563 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 564 return; 565 566 if (priv->type == BCM7445_DEVICE_ID) 567 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 568 else 569 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 570 571 switch (state->interface) { 572 case PHY_INTERFACE_MODE_RGMII: 573 id_mode_dis = 1; 574 /* fallthrough */ 575 case PHY_INTERFACE_MODE_RGMII_TXID: 576 port_mode = EXT_GPHY; 577 break; 578 case PHY_INTERFACE_MODE_MII: 579 port_mode = EXT_EPHY; 580 break; 581 case PHY_INTERFACE_MODE_REVMII: 582 port_mode = EXT_REVMII; 583 break; 584 default: 585 /* all other PHYs: internal and MoCA */ 586 goto force_link; 587 } 588 589 /* Clear id_mode_dis bit, and the existing port mode, let 590 * RGMII_MODE_EN bet set by mac_link_{up,down} 591 */ 592 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 593 reg &= ~ID_MODE_DIS; 594 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 595 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 596 597 reg |= port_mode; 598 if (id_mode_dis) 599 reg |= ID_MODE_DIS; 600 601 if (state->pause & MLO_PAUSE_TXRX_MASK) { 602 if (state->pause & MLO_PAUSE_TX) 603 reg |= TX_PAUSE_EN; 604 reg |= RX_PAUSE_EN; 605 } 606 607 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 608 609 force_link: 610 /* Force link settings detected from the PHY */ 611 reg = SW_OVERRIDE; 612 switch (state->speed) { 613 case SPEED_1000: 614 reg |= SPDSTS_1000 << SPEED_SHIFT; 615 break; 616 case SPEED_100: 617 reg |= SPDSTS_100 << SPEED_SHIFT; 618 break; 619 } 620 621 if (state->link) 622 reg |= LINK_STS; 623 if (state->duplex == DUPLEX_FULL) 624 reg |= DUPLX_MODE; 625 626 core_writel(priv, reg, offset); 627 } 628 629 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 630 phy_interface_t interface, bool link) 631 { 632 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 633 u32 reg; 634 635 if (!phy_interface_mode_is_rgmii(interface) && 636 interface != PHY_INTERFACE_MODE_MII && 637 interface != PHY_INTERFACE_MODE_REVMII) 638 return; 639 640 /* If the link is down, just disable the interface to conserve power */ 641 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 642 if (link) 643 reg |= RGMII_MODE_EN; 644 else 645 reg &= ~RGMII_MODE_EN; 646 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 647 } 648 649 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 650 unsigned int mode, 651 phy_interface_t interface) 652 { 653 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 654 } 655 656 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 657 unsigned int mode, 658 phy_interface_t interface, 659 struct phy_device *phydev, 660 int speed, int duplex, 661 bool tx_pause, bool rx_pause) 662 { 663 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 664 struct ethtool_eee *p = &priv->dev->ports[port].eee; 665 666 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 667 668 if (mode == MLO_AN_PHY && phydev) 669 p->eee_enabled = b53_eee_init(ds, port, phydev); 670 } 671 672 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 673 struct phylink_link_state *status) 674 { 675 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 676 677 status->link = false; 678 679 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 680 * which means that we need to force the link at the port override 681 * level to get the data to flow. We do use what the interrupt handler 682 * did determine before. 683 * 684 * For the other ports, we just force the link status, since this is 685 * a fixed PHY device. 686 */ 687 if (port == priv->moca_port) { 688 status->link = priv->port_sts[port].link; 689 /* For MoCA interfaces, also force a link down notification 690 * since some version of the user-space daemon (mocad) use 691 * cmd->autoneg to force the link, which messes up the PHY 692 * state machine and make it go in PHY_FORCING state instead. 693 */ 694 if (!status->link) 695 netif_carrier_off(dsa_to_port(ds, port)->slave); 696 status->duplex = DUPLEX_FULL; 697 } else { 698 status->link = true; 699 } 700 } 701 702 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 703 { 704 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 705 u32 reg; 706 707 /* Enable ACB globally */ 708 reg = acb_readl(priv, ACB_CONTROL); 709 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 710 acb_writel(priv, reg, ACB_CONTROL); 711 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 712 reg |= ACB_EN | ACB_ALGORITHM; 713 acb_writel(priv, reg, ACB_CONTROL); 714 } 715 716 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 717 { 718 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 719 unsigned int port; 720 721 bcm_sf2_intr_disable(priv); 722 723 /* Disable all ports physically present including the IMP 724 * port, the other ones have already been disabled during 725 * bcm_sf2_sw_setup 726 */ 727 for (port = 0; port < ds->num_ports; port++) { 728 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 729 bcm_sf2_port_disable(ds, port); 730 } 731 732 return 0; 733 } 734 735 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 736 { 737 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 738 int ret; 739 740 ret = bcm_sf2_sw_rst(priv); 741 if (ret) { 742 pr_err("%s: failed to software reset switch\n", __func__); 743 return ret; 744 } 745 746 ret = bcm_sf2_cfp_resume(ds); 747 if (ret) 748 return ret; 749 750 if (priv->hw_params.num_gphy == 1) 751 bcm_sf2_gphy_enable_set(ds, true); 752 753 ds->ops->setup(ds); 754 755 return 0; 756 } 757 758 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 759 struct ethtool_wolinfo *wol) 760 { 761 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 762 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 763 struct ethtool_wolinfo pwol = { }; 764 765 /* Get the parent device WoL settings */ 766 if (p->ethtool_ops->get_wol) 767 p->ethtool_ops->get_wol(p, &pwol); 768 769 /* Advertise the parent device supported settings */ 770 wol->supported = pwol.supported; 771 memset(&wol->sopass, 0, sizeof(wol->sopass)); 772 773 if (pwol.wolopts & WAKE_MAGICSECURE) 774 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 775 776 if (priv->wol_ports_mask & (1 << port)) 777 wol->wolopts = pwol.wolopts; 778 else 779 wol->wolopts = 0; 780 } 781 782 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 783 struct ethtool_wolinfo *wol) 784 { 785 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 786 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 787 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 788 struct ethtool_wolinfo pwol = { }; 789 790 if (p->ethtool_ops->get_wol) 791 p->ethtool_ops->get_wol(p, &pwol); 792 if (wol->wolopts & ~pwol.supported) 793 return -EINVAL; 794 795 if (wol->wolopts) 796 priv->wol_ports_mask |= (1 << port); 797 else 798 priv->wol_ports_mask &= ~(1 << port); 799 800 /* If we have at least one port enabled, make sure the CPU port 801 * is also enabled. If the CPU port is the last one enabled, we disable 802 * it since this configuration does not make sense. 803 */ 804 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 805 priv->wol_ports_mask |= (1 << cpu_port); 806 else 807 priv->wol_ports_mask &= ~(1 << cpu_port); 808 809 return p->ethtool_ops->set_wol(p, wol); 810 } 811 812 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 813 { 814 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 815 unsigned int port; 816 817 /* Enable all valid ports and disable those unused */ 818 for (port = 0; port < priv->hw_params.num_ports; port++) { 819 /* IMP port receives special treatment */ 820 if (dsa_is_user_port(ds, port)) 821 bcm_sf2_port_setup(ds, port, NULL); 822 else if (dsa_is_cpu_port(ds, port)) 823 bcm_sf2_imp_setup(ds, port); 824 else 825 bcm_sf2_port_disable(ds, port); 826 } 827 828 b53_configure_vlan(ds); 829 bcm_sf2_enable_acb(ds); 830 831 return 0; 832 } 833 834 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 835 * register basis so we need to translate that into an address that the 836 * bus-glue understands. 837 */ 838 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 839 840 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 841 u8 *val) 842 { 843 struct bcm_sf2_priv *priv = dev->priv; 844 845 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 846 847 return 0; 848 } 849 850 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 851 u16 *val) 852 { 853 struct bcm_sf2_priv *priv = dev->priv; 854 855 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 856 857 return 0; 858 } 859 860 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 861 u32 *val) 862 { 863 struct bcm_sf2_priv *priv = dev->priv; 864 865 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 866 867 return 0; 868 } 869 870 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 871 u64 *val) 872 { 873 struct bcm_sf2_priv *priv = dev->priv; 874 875 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 876 877 return 0; 878 } 879 880 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 881 u8 value) 882 { 883 struct bcm_sf2_priv *priv = dev->priv; 884 885 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 886 887 return 0; 888 } 889 890 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 891 u16 value) 892 { 893 struct bcm_sf2_priv *priv = dev->priv; 894 895 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 896 897 return 0; 898 } 899 900 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 901 u32 value) 902 { 903 struct bcm_sf2_priv *priv = dev->priv; 904 905 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 906 907 return 0; 908 } 909 910 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 911 u64 value) 912 { 913 struct bcm_sf2_priv *priv = dev->priv; 914 915 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 916 917 return 0; 918 } 919 920 static const struct b53_io_ops bcm_sf2_io_ops = { 921 .read8 = bcm_sf2_core_read8, 922 .read16 = bcm_sf2_core_read16, 923 .read32 = bcm_sf2_core_read32, 924 .read48 = bcm_sf2_core_read64, 925 .read64 = bcm_sf2_core_read64, 926 .write8 = bcm_sf2_core_write8, 927 .write16 = bcm_sf2_core_write16, 928 .write32 = bcm_sf2_core_write32, 929 .write48 = bcm_sf2_core_write64, 930 .write64 = bcm_sf2_core_write64, 931 }; 932 933 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 934 u32 stringset, uint8_t *data) 935 { 936 int cnt = b53_get_sset_count(ds, port, stringset); 937 938 b53_get_strings(ds, port, stringset, data); 939 bcm_sf2_cfp_get_strings(ds, port, stringset, 940 data + cnt * ETH_GSTRING_LEN); 941 } 942 943 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 944 uint64_t *data) 945 { 946 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 947 948 b53_get_ethtool_stats(ds, port, data); 949 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 950 } 951 952 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 953 int sset) 954 { 955 int cnt = b53_get_sset_count(ds, port, sset); 956 957 if (cnt < 0) 958 return cnt; 959 960 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 961 962 return cnt; 963 } 964 965 static const struct dsa_switch_ops bcm_sf2_ops = { 966 .get_tag_protocol = b53_get_tag_protocol, 967 .setup = bcm_sf2_sw_setup, 968 .get_strings = bcm_sf2_sw_get_strings, 969 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 970 .get_sset_count = bcm_sf2_sw_get_sset_count, 971 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 972 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 973 .phylink_validate = bcm_sf2_sw_validate, 974 .phylink_mac_config = bcm_sf2_sw_mac_config, 975 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 976 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 977 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 978 .suspend = bcm_sf2_sw_suspend, 979 .resume = bcm_sf2_sw_resume, 980 .get_wol = bcm_sf2_sw_get_wol, 981 .set_wol = bcm_sf2_sw_set_wol, 982 .port_enable = bcm_sf2_port_setup, 983 .port_disable = bcm_sf2_port_disable, 984 .get_mac_eee = b53_get_mac_eee, 985 .set_mac_eee = b53_set_mac_eee, 986 .port_bridge_join = b53_br_join, 987 .port_bridge_leave = b53_br_leave, 988 .port_stp_state_set = b53_br_set_stp_state, 989 .port_fast_age = b53_br_fast_age, 990 .port_vlan_filtering = b53_vlan_filtering, 991 .port_vlan_prepare = b53_vlan_prepare, 992 .port_vlan_add = b53_vlan_add, 993 .port_vlan_del = b53_vlan_del, 994 .port_fdb_dump = b53_fdb_dump, 995 .port_fdb_add = b53_fdb_add, 996 .port_fdb_del = b53_fdb_del, 997 .get_rxnfc = bcm_sf2_get_rxnfc, 998 .set_rxnfc = bcm_sf2_set_rxnfc, 999 .port_mirror_add = b53_mirror_add, 1000 .port_mirror_del = b53_mirror_del, 1001 .port_mdb_prepare = b53_mdb_prepare, 1002 .port_mdb_add = b53_mdb_add, 1003 .port_mdb_del = b53_mdb_del, 1004 }; 1005 1006 struct bcm_sf2_of_data { 1007 u32 type; 1008 const u16 *reg_offsets; 1009 unsigned int core_reg_align; 1010 unsigned int num_cfp_rules; 1011 }; 1012 1013 /* Register offsets for the SWITCH_REG_* block */ 1014 static const u16 bcm_sf2_7445_reg_offsets[] = { 1015 [REG_SWITCH_CNTRL] = 0x00, 1016 [REG_SWITCH_STATUS] = 0x04, 1017 [REG_DIR_DATA_WRITE] = 0x08, 1018 [REG_DIR_DATA_READ] = 0x0C, 1019 [REG_SWITCH_REVISION] = 0x18, 1020 [REG_PHY_REVISION] = 0x1C, 1021 [REG_SPHY_CNTRL] = 0x2C, 1022 [REG_RGMII_0_CNTRL] = 0x34, 1023 [REG_RGMII_1_CNTRL] = 0x40, 1024 [REG_RGMII_2_CNTRL] = 0x4c, 1025 [REG_LED_0_CNTRL] = 0x90, 1026 [REG_LED_1_CNTRL] = 0x94, 1027 [REG_LED_2_CNTRL] = 0x98, 1028 }; 1029 1030 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1031 .type = BCM7445_DEVICE_ID, 1032 .core_reg_align = 0, 1033 .reg_offsets = bcm_sf2_7445_reg_offsets, 1034 .num_cfp_rules = 256, 1035 }; 1036 1037 static const u16 bcm_sf2_7278_reg_offsets[] = { 1038 [REG_SWITCH_CNTRL] = 0x00, 1039 [REG_SWITCH_STATUS] = 0x04, 1040 [REG_DIR_DATA_WRITE] = 0x08, 1041 [REG_DIR_DATA_READ] = 0x0c, 1042 [REG_SWITCH_REVISION] = 0x10, 1043 [REG_PHY_REVISION] = 0x14, 1044 [REG_SPHY_CNTRL] = 0x24, 1045 [REG_RGMII_0_CNTRL] = 0xe0, 1046 [REG_RGMII_1_CNTRL] = 0xec, 1047 [REG_RGMII_2_CNTRL] = 0xf8, 1048 [REG_LED_0_CNTRL] = 0x40, 1049 [REG_LED_1_CNTRL] = 0x4c, 1050 [REG_LED_2_CNTRL] = 0x58, 1051 }; 1052 1053 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1054 .type = BCM7278_DEVICE_ID, 1055 .core_reg_align = 1, 1056 .reg_offsets = bcm_sf2_7278_reg_offsets, 1057 .num_cfp_rules = 128, 1058 }; 1059 1060 static const struct of_device_id bcm_sf2_of_match[] = { 1061 { .compatible = "brcm,bcm7445-switch-v4.0", 1062 .data = &bcm_sf2_7445_data 1063 }, 1064 { .compatible = "brcm,bcm7278-switch-v4.0", 1065 .data = &bcm_sf2_7278_data 1066 }, 1067 { .compatible = "brcm,bcm7278-switch-v4.8", 1068 .data = &bcm_sf2_7278_data 1069 }, 1070 { /* sentinel */ }, 1071 }; 1072 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1073 1074 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1075 { 1076 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1077 struct device_node *dn = pdev->dev.of_node; 1078 const struct of_device_id *of_id = NULL; 1079 const struct bcm_sf2_of_data *data; 1080 struct b53_platform_data *pdata; 1081 struct dsa_switch_ops *ops; 1082 struct device_node *ports; 1083 struct bcm_sf2_priv *priv; 1084 struct b53_device *dev; 1085 struct dsa_switch *ds; 1086 void __iomem **base; 1087 unsigned int i; 1088 u32 reg, rev; 1089 int ret; 1090 1091 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1092 if (!priv) 1093 return -ENOMEM; 1094 1095 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1096 if (!ops) 1097 return -ENOMEM; 1098 1099 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1100 if (!dev) 1101 return -ENOMEM; 1102 1103 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1104 if (!pdata) 1105 return -ENOMEM; 1106 1107 of_id = of_match_node(bcm_sf2_of_match, dn); 1108 if (!of_id || !of_id->data) 1109 return -EINVAL; 1110 1111 data = of_id->data; 1112 1113 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1114 priv->type = data->type; 1115 priv->reg_offsets = data->reg_offsets; 1116 priv->core_reg_align = data->core_reg_align; 1117 priv->num_cfp_rules = data->num_cfp_rules; 1118 1119 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1120 "switch"); 1121 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER) 1122 return PTR_ERR(priv->rcdev); 1123 1124 /* Auto-detection using standard registers will not work, so 1125 * provide an indication of what kind of device we are for 1126 * b53_common to work with 1127 */ 1128 pdata->chip_id = priv->type; 1129 dev->pdata = pdata; 1130 1131 priv->dev = dev; 1132 ds = dev->ds; 1133 ds->ops = &bcm_sf2_ops; 1134 1135 /* Advertise the 8 egress queues */ 1136 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1137 1138 dev_set_drvdata(&pdev->dev, priv); 1139 1140 spin_lock_init(&priv->indir_lock); 1141 mutex_init(&priv->cfp.lock); 1142 INIT_LIST_HEAD(&priv->cfp.rules_list); 1143 1144 /* CFP rule #0 cannot be used for specific classifications, flag it as 1145 * permanently used 1146 */ 1147 set_bit(0, priv->cfp.used); 1148 set_bit(0, priv->cfp.unique); 1149 1150 /* Balance of_node_put() done by of_find_node_by_name() */ 1151 of_node_get(dn); 1152 ports = of_find_node_by_name(dn, "ports"); 1153 if (ports) { 1154 bcm_sf2_identify_ports(priv, ports); 1155 of_node_put(ports); 1156 } 1157 1158 priv->irq0 = irq_of_parse_and_map(dn, 0); 1159 priv->irq1 = irq_of_parse_and_map(dn, 1); 1160 1161 base = &priv->core; 1162 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1163 *base = devm_platform_ioremap_resource(pdev, i); 1164 if (IS_ERR(*base)) { 1165 pr_err("unable to find register: %s\n", reg_names[i]); 1166 return PTR_ERR(*base); 1167 } 1168 base++; 1169 } 1170 1171 ret = bcm_sf2_sw_rst(priv); 1172 if (ret) { 1173 pr_err("unable to software reset switch: %d\n", ret); 1174 return ret; 1175 } 1176 1177 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1178 1179 ret = bcm_sf2_mdio_register(ds); 1180 if (ret) { 1181 pr_err("failed to register MDIO bus\n"); 1182 return ret; 1183 } 1184 1185 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1186 1187 ret = bcm_sf2_cfp_rst(priv); 1188 if (ret) { 1189 pr_err("failed to reset CFP\n"); 1190 goto out_mdio; 1191 } 1192 1193 /* Disable all interrupts and request them */ 1194 bcm_sf2_intr_disable(priv); 1195 1196 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1197 "switch_0", ds); 1198 if (ret < 0) { 1199 pr_err("failed to request switch_0 IRQ\n"); 1200 goto out_mdio; 1201 } 1202 1203 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1204 "switch_1", ds); 1205 if (ret < 0) { 1206 pr_err("failed to request switch_1 IRQ\n"); 1207 goto out_mdio; 1208 } 1209 1210 /* Reset the MIB counters */ 1211 reg = core_readl(priv, CORE_GMNCFGCFG); 1212 reg |= RST_MIB_CNT; 1213 core_writel(priv, reg, CORE_GMNCFGCFG); 1214 reg &= ~RST_MIB_CNT; 1215 core_writel(priv, reg, CORE_GMNCFGCFG); 1216 1217 /* Get the maximum number of ports for this switch */ 1218 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1219 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1220 priv->hw_params.num_ports = DSA_MAX_PORTS; 1221 1222 /* Assume a single GPHY setup if we can't read that property */ 1223 if (of_property_read_u32(dn, "brcm,num-gphy", 1224 &priv->hw_params.num_gphy)) 1225 priv->hw_params.num_gphy = 1; 1226 1227 rev = reg_readl(priv, REG_SWITCH_REVISION); 1228 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1229 SWITCH_TOP_REV_MASK; 1230 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1231 1232 rev = reg_readl(priv, REG_PHY_REVISION); 1233 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1234 1235 ret = b53_switch_register(dev); 1236 if (ret) 1237 goto out_mdio; 1238 1239 dev_info(&pdev->dev, 1240 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1241 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1242 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1243 priv->irq0, priv->irq1); 1244 1245 return 0; 1246 1247 out_mdio: 1248 bcm_sf2_mdio_unregister(priv); 1249 return ret; 1250 } 1251 1252 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1253 { 1254 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1255 1256 priv->wol_ports_mask = 0; 1257 /* Disable interrupts */ 1258 bcm_sf2_intr_disable(priv); 1259 dsa_unregister_switch(priv->dev->ds); 1260 bcm_sf2_cfp_exit(priv->dev->ds); 1261 bcm_sf2_mdio_unregister(priv); 1262 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) 1263 reset_control_assert(priv->rcdev); 1264 1265 return 0; 1266 } 1267 1268 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1269 { 1270 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1271 1272 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1273 * successful MDIO bus scan to occur. If we did turn off the GPHY 1274 * before (e.g: port_disable), this will also power it back on. 1275 * 1276 * Do not rely on kexec_in_progress, just power the PHY on. 1277 */ 1278 if (priv->hw_params.num_gphy == 1) 1279 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1280 } 1281 1282 #ifdef CONFIG_PM_SLEEP 1283 static int bcm_sf2_suspend(struct device *dev) 1284 { 1285 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1286 1287 return dsa_switch_suspend(priv->dev->ds); 1288 } 1289 1290 static int bcm_sf2_resume(struct device *dev) 1291 { 1292 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1293 1294 return dsa_switch_resume(priv->dev->ds); 1295 } 1296 #endif /* CONFIG_PM_SLEEP */ 1297 1298 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1299 bcm_sf2_suspend, bcm_sf2_resume); 1300 1301 1302 static struct platform_driver bcm_sf2_driver = { 1303 .probe = bcm_sf2_sw_probe, 1304 .remove = bcm_sf2_sw_remove, 1305 .shutdown = bcm_sf2_sw_shutdown, 1306 .driver = { 1307 .name = "brcm-sf2", 1308 .of_match_table = bcm_sf2_of_match, 1309 .pm = &bcm_sf2_pm_ops, 1310 }, 1311 }; 1312 module_platform_driver(bcm_sf2_driver); 1313 1314 MODULE_AUTHOR("Broadcom Corporation"); 1315 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1316 MODULE_LICENSE("GPL"); 1317 MODULE_ALIAS("platform:brcm-sf2"); 1318