1 /* 2 * Broadcom Starfighter 2 DSA switch driver 3 * 4 * Copyright (C) 2014, Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/list.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/phylink.h> 20 #include <linux/mii.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_address.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <net/dsa.h> 27 #include <linux/ethtool.h> 28 #include <linux/if_bridge.h> 29 #include <linux/brcmphy.h> 30 #include <linux/etherdevice.h> 31 #include <linux/platform_data/b53.h> 32 33 #include "bcm_sf2.h" 34 #include "bcm_sf2_regs.h" 35 #include "b53/b53_priv.h" 36 #include "b53/b53_regs.h" 37 38 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 39 { 40 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 41 unsigned int i; 42 u32 reg, offset; 43 44 if (priv->type == BCM7445_DEVICE_ID) 45 offset = CORE_STS_OVERRIDE_IMP; 46 else 47 offset = CORE_STS_OVERRIDE_IMP2; 48 49 /* Enable the port memories */ 50 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 51 reg &= ~P_TXQ_PSM_VDD(port); 52 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 53 54 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 55 reg = core_readl(priv, CORE_IMP_CTL); 56 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 57 reg &= ~(RX_DIS | TX_DIS); 58 core_writel(priv, reg, CORE_IMP_CTL); 59 60 /* Enable forwarding */ 61 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 62 63 /* Enable IMP port in dumb mode */ 64 reg = core_readl(priv, CORE_SWITCH_CTRL); 65 reg |= MII_DUMB_FWDG_EN; 66 core_writel(priv, reg, CORE_SWITCH_CTRL); 67 68 /* Configure Traffic Class to QoS mapping, allow each priority to map 69 * to a different queue number 70 */ 71 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 72 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 73 reg |= i << (PRT_TO_QID_SHIFT * i); 74 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 75 76 b53_brcm_hdr_setup(ds, port); 77 78 /* Force link status for IMP port */ 79 reg = core_readl(priv, offset); 80 reg |= (MII_SW_OR | LINK_STS); 81 core_writel(priv, reg, offset); 82 } 83 84 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 85 { 86 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 87 u32 reg; 88 89 reg = reg_readl(priv, REG_SPHY_CNTRL); 90 if (enable) { 91 reg |= PHY_RESET; 92 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 93 reg_writel(priv, reg, REG_SPHY_CNTRL); 94 udelay(21); 95 reg = reg_readl(priv, REG_SPHY_CNTRL); 96 reg &= ~PHY_RESET; 97 } else { 98 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 99 reg_writel(priv, reg, REG_SPHY_CNTRL); 100 mdelay(1); 101 reg |= CK25_DIS; 102 } 103 reg_writel(priv, reg, REG_SPHY_CNTRL); 104 105 /* Use PHY-driven LED signaling */ 106 if (!enable) { 107 reg = reg_readl(priv, REG_LED_CNTRL(0)); 108 reg |= SPDLNK_SRC_SEL; 109 reg_writel(priv, reg, REG_LED_CNTRL(0)); 110 } 111 } 112 113 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 114 int port) 115 { 116 unsigned int off; 117 118 switch (port) { 119 case 7: 120 off = P7_IRQ_OFF; 121 break; 122 case 0: 123 /* Port 0 interrupts are located on the first bank */ 124 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 125 return; 126 default: 127 off = P_IRQ_OFF(port); 128 break; 129 } 130 131 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 132 } 133 134 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 135 int port) 136 { 137 unsigned int off; 138 139 switch (port) { 140 case 7: 141 off = P7_IRQ_OFF; 142 break; 143 case 0: 144 /* Port 0 interrupts are located on the first bank */ 145 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 146 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 147 return; 148 default: 149 off = P_IRQ_OFF(port); 150 break; 151 } 152 153 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 154 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 155 } 156 157 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 158 struct phy_device *phy) 159 { 160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 161 unsigned int i; 162 u32 reg; 163 164 /* Clear the memory power down */ 165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 166 reg &= ~P_TXQ_PSM_VDD(port); 167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 168 169 /* Enable learning */ 170 reg = core_readl(priv, CORE_DIS_LEARN); 171 reg &= ~BIT(port); 172 core_writel(priv, reg, CORE_DIS_LEARN); 173 174 /* Enable Broadcom tags for that port if requested */ 175 if (priv->brcm_tag_mask & BIT(port)) 176 b53_brcm_hdr_setup(ds, port); 177 178 /* Configure Traffic Class to QoS mapping, allow each priority to map 179 * to a different queue number 180 */ 181 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 182 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 183 reg |= i << (PRT_TO_QID_SHIFT * i); 184 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 185 186 /* Re-enable the GPHY and re-apply workarounds */ 187 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 188 bcm_sf2_gphy_enable_set(ds, true); 189 if (phy) { 190 /* if phy_stop() has been called before, phy 191 * will be in halted state, and phy_start() 192 * will call resume. 193 * 194 * the resume path does not configure back 195 * autoneg settings, and since we hard reset 196 * the phy manually here, we need to reset the 197 * state machine also. 198 */ 199 phy->state = PHY_READY; 200 phy_init_hw(phy); 201 } 202 } 203 204 /* Enable MoCA port interrupts to get notified */ 205 if (port == priv->moca_port) 206 bcm_sf2_port_intr_enable(priv, port); 207 208 /* Set per-queue pause threshold to 32 */ 209 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 210 211 /* Set ACB threshold to 24 */ 212 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 213 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 214 SF2_NUM_EGRESS_QUEUES + i)); 215 reg &= ~XOFF_THRESHOLD_MASK; 216 reg |= 24; 217 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 218 SF2_NUM_EGRESS_QUEUES + i)); 219 } 220 221 return b53_enable_port(ds, port, phy); 222 } 223 224 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port, 225 struct phy_device *phy) 226 { 227 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 228 u32 reg; 229 230 /* Disable learning while in WoL mode */ 231 if (priv->wol_ports_mask & (1 << port)) { 232 reg = core_readl(priv, CORE_DIS_LEARN); 233 reg |= BIT(port); 234 core_writel(priv, reg, CORE_DIS_LEARN); 235 return; 236 } 237 238 if (port == priv->moca_port) 239 bcm_sf2_port_intr_disable(priv, port); 240 241 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 242 bcm_sf2_gphy_enable_set(ds, false); 243 244 b53_disable_port(ds, port, phy); 245 246 /* Power down the port memory */ 247 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 248 reg |= P_TXQ_PSM_VDD(port); 249 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 250 } 251 252 253 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 254 int regnum, u16 val) 255 { 256 int ret = 0; 257 u32 reg; 258 259 reg = reg_readl(priv, REG_SWITCH_CNTRL); 260 reg |= MDIO_MASTER_SEL; 261 reg_writel(priv, reg, REG_SWITCH_CNTRL); 262 263 /* Page << 8 | offset */ 264 reg = 0x70; 265 reg <<= 2; 266 core_writel(priv, addr, reg); 267 268 /* Page << 8 | offset */ 269 reg = 0x80 << 8 | regnum << 1; 270 reg <<= 2; 271 272 if (op) 273 ret = core_readl(priv, reg); 274 else 275 core_writel(priv, val, reg); 276 277 reg = reg_readl(priv, REG_SWITCH_CNTRL); 278 reg &= ~MDIO_MASTER_SEL; 279 reg_writel(priv, reg, REG_SWITCH_CNTRL); 280 281 return ret & 0xffff; 282 } 283 284 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 285 { 286 struct bcm_sf2_priv *priv = bus->priv; 287 288 /* Intercept reads from Broadcom pseudo-PHY address, else, send 289 * them to our master MDIO bus controller 290 */ 291 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 292 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 293 else 294 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 295 } 296 297 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 298 u16 val) 299 { 300 struct bcm_sf2_priv *priv = bus->priv; 301 302 /* Intercept writes to the Broadcom pseudo-PHY address, else, 303 * send them to our master MDIO bus controller 304 */ 305 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 306 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 307 else 308 return mdiobus_write_nested(priv->master_mii_bus, addr, 309 regnum, val); 310 } 311 312 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 313 { 314 struct dsa_switch *ds = dev_id; 315 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 316 317 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 318 ~priv->irq0_mask; 319 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 320 321 return IRQ_HANDLED; 322 } 323 324 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 325 { 326 struct dsa_switch *ds = dev_id; 327 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 328 329 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 330 ~priv->irq1_mask; 331 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 332 333 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 334 priv->port_sts[7].link = true; 335 dsa_port_phylink_mac_change(ds, 7, true); 336 } 337 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 338 priv->port_sts[7].link = false; 339 dsa_port_phylink_mac_change(ds, 7, false); 340 } 341 342 return IRQ_HANDLED; 343 } 344 345 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 346 { 347 unsigned int timeout = 1000; 348 u32 reg; 349 350 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 351 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 352 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 353 354 do { 355 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 356 if (!(reg & SOFTWARE_RESET)) 357 break; 358 359 usleep_range(1000, 2000); 360 } while (timeout-- > 0); 361 362 if (timeout == 0) 363 return -ETIMEDOUT; 364 365 return 0; 366 } 367 368 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 369 { 370 intrl2_0_mask_set(priv, 0xffffffff); 371 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 372 intrl2_1_mask_set(priv, 0xffffffff); 373 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 374 } 375 376 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 377 struct device_node *dn) 378 { 379 struct device_node *port; 380 int mode; 381 unsigned int port_num; 382 383 priv->moca_port = -1; 384 385 for_each_available_child_of_node(dn, port) { 386 if (of_property_read_u32(port, "reg", &port_num)) 387 continue; 388 389 /* Internal PHYs get assigned a specific 'phy-mode' property 390 * value: "internal" to help flag them before MDIO probing 391 * has completed, since they might be turned off at that 392 * time 393 */ 394 mode = of_get_phy_mode(port); 395 if (mode < 0) 396 continue; 397 398 if (mode == PHY_INTERFACE_MODE_INTERNAL) 399 priv->int_phy_mask |= 1 << port_num; 400 401 if (mode == PHY_INTERFACE_MODE_MOCA) 402 priv->moca_port = port_num; 403 404 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 405 priv->brcm_tag_mask |= 1 << port_num; 406 } 407 } 408 409 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 410 { 411 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 412 struct device_node *dn; 413 static int index; 414 int err; 415 416 /* Find our integrated MDIO bus node */ 417 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 418 priv->master_mii_bus = of_mdio_find_bus(dn); 419 if (!priv->master_mii_bus) 420 return -EPROBE_DEFER; 421 422 get_device(&priv->master_mii_bus->dev); 423 priv->master_mii_dn = dn; 424 425 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 426 if (!priv->slave_mii_bus) 427 return -ENOMEM; 428 429 priv->slave_mii_bus->priv = priv; 430 priv->slave_mii_bus->name = "sf2 slave mii"; 431 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 432 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 433 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 434 index++); 435 priv->slave_mii_bus->dev.of_node = dn; 436 437 /* Include the pseudo-PHY address to divert reads towards our 438 * workaround. This is only required for 7445D0, since 7445E0 439 * disconnects the internal switch pseudo-PHY such that we can use the 440 * regular SWITCH_MDIO master controller instead. 441 * 442 * Here we flag the pseudo PHY as needing special treatment and would 443 * otherwise make all other PHY read/writes go to the master MDIO bus 444 * controller that comes with this switch backed by the "mdio-unimac" 445 * driver. 446 */ 447 if (of_machine_is_compatible("brcm,bcm7445d0")) 448 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 449 else 450 priv->indir_phy_mask = 0; 451 452 ds->phys_mii_mask = priv->indir_phy_mask; 453 ds->slave_mii_bus = priv->slave_mii_bus; 454 priv->slave_mii_bus->parent = ds->dev->parent; 455 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 456 457 err = of_mdiobus_register(priv->slave_mii_bus, dn); 458 if (err && dn) 459 of_node_put(dn); 460 461 return err; 462 } 463 464 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 465 { 466 mdiobus_unregister(priv->slave_mii_bus); 467 of_node_put(priv->master_mii_dn); 468 } 469 470 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 471 { 472 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 473 474 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 475 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 476 * the REG_PHY_REVISION register layout is. 477 */ 478 479 return priv->hw_params.gphy_rev; 480 } 481 482 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 483 unsigned long *supported, 484 struct phylink_link_state *state) 485 { 486 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 487 488 if (!phy_interface_mode_is_rgmii(state->interface) && 489 state->interface != PHY_INTERFACE_MODE_MII && 490 state->interface != PHY_INTERFACE_MODE_REVMII && 491 state->interface != PHY_INTERFACE_MODE_GMII && 492 state->interface != PHY_INTERFACE_MODE_INTERNAL && 493 state->interface != PHY_INTERFACE_MODE_MOCA) { 494 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 495 dev_err(ds->dev, 496 "Unsupported interface: %d\n", state->interface); 497 return; 498 } 499 500 /* Allow all the expected bits */ 501 phylink_set(mask, Autoneg); 502 phylink_set_port_modes(mask); 503 phylink_set(mask, Pause); 504 phylink_set(mask, Asym_Pause); 505 506 /* With the exclusion of MII and Reverse MII, we support Gigabit, 507 * including Half duplex 508 */ 509 if (state->interface != PHY_INTERFACE_MODE_MII && 510 state->interface != PHY_INTERFACE_MODE_REVMII) { 511 phylink_set(mask, 1000baseT_Full); 512 phylink_set(mask, 1000baseT_Half); 513 } 514 515 phylink_set(mask, 10baseT_Half); 516 phylink_set(mask, 10baseT_Full); 517 phylink_set(mask, 100baseT_Half); 518 phylink_set(mask, 100baseT_Full); 519 520 bitmap_and(supported, supported, mask, 521 __ETHTOOL_LINK_MODE_MASK_NBITS); 522 bitmap_and(state->advertising, state->advertising, mask, 523 __ETHTOOL_LINK_MODE_MASK_NBITS); 524 } 525 526 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 527 unsigned int mode, 528 const struct phylink_link_state *state) 529 { 530 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 531 u32 id_mode_dis = 0, port_mode; 532 u32 reg, offset; 533 534 if (priv->type == BCM7445_DEVICE_ID) 535 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 536 else 537 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 538 539 switch (state->interface) { 540 case PHY_INTERFACE_MODE_RGMII: 541 id_mode_dis = 1; 542 /* fallthrough */ 543 case PHY_INTERFACE_MODE_RGMII_TXID: 544 port_mode = EXT_GPHY; 545 break; 546 case PHY_INTERFACE_MODE_MII: 547 port_mode = EXT_EPHY; 548 break; 549 case PHY_INTERFACE_MODE_REVMII: 550 port_mode = EXT_REVMII; 551 break; 552 default: 553 /* all other PHYs: internal and MoCA */ 554 goto force_link; 555 } 556 557 /* Clear id_mode_dis bit, and the existing port mode, let 558 * RGMII_MODE_EN bet set by mac_link_{up,down} 559 */ 560 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 561 reg &= ~ID_MODE_DIS; 562 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 563 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 564 565 reg |= port_mode; 566 if (id_mode_dis) 567 reg |= ID_MODE_DIS; 568 569 if (state->pause & MLO_PAUSE_TXRX_MASK) { 570 if (state->pause & MLO_PAUSE_TX) 571 reg |= TX_PAUSE_EN; 572 reg |= RX_PAUSE_EN; 573 } 574 575 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 576 577 force_link: 578 /* Force link settings detected from the PHY */ 579 reg = SW_OVERRIDE; 580 switch (state->speed) { 581 case SPEED_1000: 582 reg |= SPDSTS_1000 << SPEED_SHIFT; 583 break; 584 case SPEED_100: 585 reg |= SPDSTS_100 << SPEED_SHIFT; 586 break; 587 } 588 589 if (state->link) 590 reg |= LINK_STS; 591 if (state->duplex == DUPLEX_FULL) 592 reg |= DUPLX_MODE; 593 594 core_writel(priv, reg, offset); 595 } 596 597 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 598 phy_interface_t interface, bool link) 599 { 600 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 601 u32 reg; 602 603 if (!phy_interface_mode_is_rgmii(interface) && 604 interface != PHY_INTERFACE_MODE_MII && 605 interface != PHY_INTERFACE_MODE_REVMII) 606 return; 607 608 /* If the link is down, just disable the interface to conserve power */ 609 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 610 if (link) 611 reg |= RGMII_MODE_EN; 612 else 613 reg &= ~RGMII_MODE_EN; 614 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 615 } 616 617 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 618 unsigned int mode, 619 phy_interface_t interface) 620 { 621 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 622 } 623 624 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 625 unsigned int mode, 626 phy_interface_t interface, 627 struct phy_device *phydev) 628 { 629 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 630 struct ethtool_eee *p = &priv->dev->ports[port].eee; 631 632 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 633 634 if (mode == MLO_AN_PHY && phydev) 635 p->eee_enabled = b53_eee_init(ds, port, phydev); 636 } 637 638 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 639 struct phylink_link_state *status) 640 { 641 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 642 643 status->link = false; 644 645 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 646 * which means that we need to force the link at the port override 647 * level to get the data to flow. We do use what the interrupt handler 648 * did determine before. 649 * 650 * For the other ports, we just force the link status, since this is 651 * a fixed PHY device. 652 */ 653 if (port == priv->moca_port) { 654 status->link = priv->port_sts[port].link; 655 /* For MoCA interfaces, also force a link down notification 656 * since some version of the user-space daemon (mocad) use 657 * cmd->autoneg to force the link, which messes up the PHY 658 * state machine and make it go in PHY_FORCING state instead. 659 */ 660 if (!status->link) 661 netif_carrier_off(ds->ports[port].slave); 662 status->duplex = DUPLEX_FULL; 663 } else { 664 status->link = true; 665 } 666 } 667 668 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 669 { 670 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 671 u32 reg; 672 673 /* Enable ACB globally */ 674 reg = acb_readl(priv, ACB_CONTROL); 675 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 676 acb_writel(priv, reg, ACB_CONTROL); 677 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 678 reg |= ACB_EN | ACB_ALGORITHM; 679 acb_writel(priv, reg, ACB_CONTROL); 680 } 681 682 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 683 { 684 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 685 unsigned int port; 686 687 bcm_sf2_intr_disable(priv); 688 689 /* Disable all ports physically present including the IMP 690 * port, the other ones have already been disabled during 691 * bcm_sf2_sw_setup 692 */ 693 for (port = 0; port < DSA_MAX_PORTS; port++) { 694 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 695 bcm_sf2_port_disable(ds, port, NULL); 696 } 697 698 return 0; 699 } 700 701 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 702 { 703 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 704 int ret; 705 706 ret = bcm_sf2_sw_rst(priv); 707 if (ret) { 708 pr_err("%s: failed to software reset switch\n", __func__); 709 return ret; 710 } 711 712 ret = bcm_sf2_cfp_resume(ds); 713 if (ret) 714 return ret; 715 716 if (priv->hw_params.num_gphy == 1) 717 bcm_sf2_gphy_enable_set(ds, true); 718 719 ds->ops->setup(ds); 720 721 return 0; 722 } 723 724 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 725 struct ethtool_wolinfo *wol) 726 { 727 struct net_device *p = ds->ports[port].cpu_dp->master; 728 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 729 struct ethtool_wolinfo pwol; 730 731 /* Get the parent device WoL settings */ 732 p->ethtool_ops->get_wol(p, &pwol); 733 734 /* Advertise the parent device supported settings */ 735 wol->supported = pwol.supported; 736 memset(&wol->sopass, 0, sizeof(wol->sopass)); 737 738 if (pwol.wolopts & WAKE_MAGICSECURE) 739 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 740 741 if (priv->wol_ports_mask & (1 << port)) 742 wol->wolopts = pwol.wolopts; 743 else 744 wol->wolopts = 0; 745 } 746 747 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 748 struct ethtool_wolinfo *wol) 749 { 750 struct net_device *p = ds->ports[port].cpu_dp->master; 751 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 752 s8 cpu_port = ds->ports[port].cpu_dp->index; 753 struct ethtool_wolinfo pwol; 754 755 p->ethtool_ops->get_wol(p, &pwol); 756 if (wol->wolopts & ~pwol.supported) 757 return -EINVAL; 758 759 if (wol->wolopts) 760 priv->wol_ports_mask |= (1 << port); 761 else 762 priv->wol_ports_mask &= ~(1 << port); 763 764 /* If we have at least one port enabled, make sure the CPU port 765 * is also enabled. If the CPU port is the last one enabled, we disable 766 * it since this configuration does not make sense. 767 */ 768 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 769 priv->wol_ports_mask |= (1 << cpu_port); 770 else 771 priv->wol_ports_mask &= ~(1 << cpu_port); 772 773 return p->ethtool_ops->set_wol(p, wol); 774 } 775 776 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 777 { 778 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 779 unsigned int port; 780 781 /* Enable all valid ports and disable those unused */ 782 for (port = 0; port < priv->hw_params.num_ports; port++) { 783 /* IMP port receives special treatment */ 784 if (dsa_is_user_port(ds, port)) 785 bcm_sf2_port_setup(ds, port, NULL); 786 else if (dsa_is_cpu_port(ds, port)) 787 bcm_sf2_imp_setup(ds, port); 788 else 789 bcm_sf2_port_disable(ds, port, NULL); 790 } 791 792 b53_configure_vlan(ds); 793 bcm_sf2_enable_acb(ds); 794 795 return 0; 796 } 797 798 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 799 * register basis so we need to translate that into an address that the 800 * bus-glue understands. 801 */ 802 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 803 804 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 805 u8 *val) 806 { 807 struct bcm_sf2_priv *priv = dev->priv; 808 809 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 810 811 return 0; 812 } 813 814 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 815 u16 *val) 816 { 817 struct bcm_sf2_priv *priv = dev->priv; 818 819 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 820 821 return 0; 822 } 823 824 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 825 u32 *val) 826 { 827 struct bcm_sf2_priv *priv = dev->priv; 828 829 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 830 831 return 0; 832 } 833 834 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 835 u64 *val) 836 { 837 struct bcm_sf2_priv *priv = dev->priv; 838 839 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 840 841 return 0; 842 } 843 844 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 845 u8 value) 846 { 847 struct bcm_sf2_priv *priv = dev->priv; 848 849 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 850 851 return 0; 852 } 853 854 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 855 u16 value) 856 { 857 struct bcm_sf2_priv *priv = dev->priv; 858 859 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 860 861 return 0; 862 } 863 864 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 865 u32 value) 866 { 867 struct bcm_sf2_priv *priv = dev->priv; 868 869 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 870 871 return 0; 872 } 873 874 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 875 u64 value) 876 { 877 struct bcm_sf2_priv *priv = dev->priv; 878 879 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 880 881 return 0; 882 } 883 884 static const struct b53_io_ops bcm_sf2_io_ops = { 885 .read8 = bcm_sf2_core_read8, 886 .read16 = bcm_sf2_core_read16, 887 .read32 = bcm_sf2_core_read32, 888 .read48 = bcm_sf2_core_read64, 889 .read64 = bcm_sf2_core_read64, 890 .write8 = bcm_sf2_core_write8, 891 .write16 = bcm_sf2_core_write16, 892 .write32 = bcm_sf2_core_write32, 893 .write48 = bcm_sf2_core_write64, 894 .write64 = bcm_sf2_core_write64, 895 }; 896 897 static const struct dsa_switch_ops bcm_sf2_ops = { 898 .get_tag_protocol = b53_get_tag_protocol, 899 .setup = bcm_sf2_sw_setup, 900 .get_strings = b53_get_strings, 901 .get_ethtool_stats = b53_get_ethtool_stats, 902 .get_sset_count = b53_get_sset_count, 903 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 904 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 905 .phylink_validate = bcm_sf2_sw_validate, 906 .phylink_mac_config = bcm_sf2_sw_mac_config, 907 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 908 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 909 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 910 .suspend = bcm_sf2_sw_suspend, 911 .resume = bcm_sf2_sw_resume, 912 .get_wol = bcm_sf2_sw_get_wol, 913 .set_wol = bcm_sf2_sw_set_wol, 914 .port_enable = bcm_sf2_port_setup, 915 .port_disable = bcm_sf2_port_disable, 916 .get_mac_eee = b53_get_mac_eee, 917 .set_mac_eee = b53_set_mac_eee, 918 .port_bridge_join = b53_br_join, 919 .port_bridge_leave = b53_br_leave, 920 .port_stp_state_set = b53_br_set_stp_state, 921 .port_fast_age = b53_br_fast_age, 922 .port_vlan_filtering = b53_vlan_filtering, 923 .port_vlan_prepare = b53_vlan_prepare, 924 .port_vlan_add = b53_vlan_add, 925 .port_vlan_del = b53_vlan_del, 926 .port_fdb_dump = b53_fdb_dump, 927 .port_fdb_add = b53_fdb_add, 928 .port_fdb_del = b53_fdb_del, 929 .get_rxnfc = bcm_sf2_get_rxnfc, 930 .set_rxnfc = bcm_sf2_set_rxnfc, 931 .port_mirror_add = b53_mirror_add, 932 .port_mirror_del = b53_mirror_del, 933 }; 934 935 struct bcm_sf2_of_data { 936 u32 type; 937 const u16 *reg_offsets; 938 unsigned int core_reg_align; 939 unsigned int num_cfp_rules; 940 }; 941 942 /* Register offsets for the SWITCH_REG_* block */ 943 static const u16 bcm_sf2_7445_reg_offsets[] = { 944 [REG_SWITCH_CNTRL] = 0x00, 945 [REG_SWITCH_STATUS] = 0x04, 946 [REG_DIR_DATA_WRITE] = 0x08, 947 [REG_DIR_DATA_READ] = 0x0C, 948 [REG_SWITCH_REVISION] = 0x18, 949 [REG_PHY_REVISION] = 0x1C, 950 [REG_SPHY_CNTRL] = 0x2C, 951 [REG_RGMII_0_CNTRL] = 0x34, 952 [REG_RGMII_1_CNTRL] = 0x40, 953 [REG_RGMII_2_CNTRL] = 0x4c, 954 [REG_LED_0_CNTRL] = 0x90, 955 [REG_LED_1_CNTRL] = 0x94, 956 [REG_LED_2_CNTRL] = 0x98, 957 }; 958 959 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 960 .type = BCM7445_DEVICE_ID, 961 .core_reg_align = 0, 962 .reg_offsets = bcm_sf2_7445_reg_offsets, 963 .num_cfp_rules = 256, 964 }; 965 966 static const u16 bcm_sf2_7278_reg_offsets[] = { 967 [REG_SWITCH_CNTRL] = 0x00, 968 [REG_SWITCH_STATUS] = 0x04, 969 [REG_DIR_DATA_WRITE] = 0x08, 970 [REG_DIR_DATA_READ] = 0x0c, 971 [REG_SWITCH_REVISION] = 0x10, 972 [REG_PHY_REVISION] = 0x14, 973 [REG_SPHY_CNTRL] = 0x24, 974 [REG_RGMII_0_CNTRL] = 0xe0, 975 [REG_RGMII_1_CNTRL] = 0xec, 976 [REG_RGMII_2_CNTRL] = 0xf8, 977 [REG_LED_0_CNTRL] = 0x40, 978 [REG_LED_1_CNTRL] = 0x4c, 979 [REG_LED_2_CNTRL] = 0x58, 980 }; 981 982 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 983 .type = BCM7278_DEVICE_ID, 984 .core_reg_align = 1, 985 .reg_offsets = bcm_sf2_7278_reg_offsets, 986 .num_cfp_rules = 128, 987 }; 988 989 static const struct of_device_id bcm_sf2_of_match[] = { 990 { .compatible = "brcm,bcm7445-switch-v4.0", 991 .data = &bcm_sf2_7445_data 992 }, 993 { .compatible = "brcm,bcm7278-switch-v4.0", 994 .data = &bcm_sf2_7278_data 995 }, 996 { .compatible = "brcm,bcm7278-switch-v4.8", 997 .data = &bcm_sf2_7278_data 998 }, 999 { /* sentinel */ }, 1000 }; 1001 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1002 1003 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1004 { 1005 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1006 struct device_node *dn = pdev->dev.of_node; 1007 const struct of_device_id *of_id = NULL; 1008 const struct bcm_sf2_of_data *data; 1009 struct b53_platform_data *pdata; 1010 struct dsa_switch_ops *ops; 1011 struct bcm_sf2_priv *priv; 1012 struct b53_device *dev; 1013 struct dsa_switch *ds; 1014 void __iomem **base; 1015 struct resource *r; 1016 unsigned int i; 1017 u32 reg, rev; 1018 int ret; 1019 1020 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1021 if (!priv) 1022 return -ENOMEM; 1023 1024 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1025 if (!ops) 1026 return -ENOMEM; 1027 1028 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1029 if (!dev) 1030 return -ENOMEM; 1031 1032 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1033 if (!pdata) 1034 return -ENOMEM; 1035 1036 of_id = of_match_node(bcm_sf2_of_match, dn); 1037 if (!of_id || !of_id->data) 1038 return -EINVAL; 1039 1040 data = of_id->data; 1041 1042 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1043 priv->type = data->type; 1044 priv->reg_offsets = data->reg_offsets; 1045 priv->core_reg_align = data->core_reg_align; 1046 priv->num_cfp_rules = data->num_cfp_rules; 1047 1048 /* Auto-detection using standard registers will not work, so 1049 * provide an indication of what kind of device we are for 1050 * b53_common to work with 1051 */ 1052 pdata->chip_id = priv->type; 1053 dev->pdata = pdata; 1054 1055 priv->dev = dev; 1056 ds = dev->ds; 1057 ds->ops = &bcm_sf2_ops; 1058 1059 /* Advertise the 8 egress queues */ 1060 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1061 1062 dev_set_drvdata(&pdev->dev, priv); 1063 1064 spin_lock_init(&priv->indir_lock); 1065 mutex_init(&priv->stats_mutex); 1066 mutex_init(&priv->cfp.lock); 1067 INIT_LIST_HEAD(&priv->cfp.rules_list); 1068 1069 /* CFP rule #0 cannot be used for specific classifications, flag it as 1070 * permanently used 1071 */ 1072 set_bit(0, priv->cfp.used); 1073 set_bit(0, priv->cfp.unique); 1074 1075 bcm_sf2_identify_ports(priv, dn->child); 1076 1077 priv->irq0 = irq_of_parse_and_map(dn, 0); 1078 priv->irq1 = irq_of_parse_and_map(dn, 1); 1079 1080 base = &priv->core; 1081 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1082 r = platform_get_resource(pdev, IORESOURCE_MEM, i); 1083 *base = devm_ioremap_resource(&pdev->dev, r); 1084 if (IS_ERR(*base)) { 1085 pr_err("unable to find register: %s\n", reg_names[i]); 1086 return PTR_ERR(*base); 1087 } 1088 base++; 1089 } 1090 1091 ret = bcm_sf2_sw_rst(priv); 1092 if (ret) { 1093 pr_err("unable to software reset switch: %d\n", ret); 1094 return ret; 1095 } 1096 1097 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1098 1099 ret = bcm_sf2_mdio_register(ds); 1100 if (ret) { 1101 pr_err("failed to register MDIO bus\n"); 1102 return ret; 1103 } 1104 1105 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1106 1107 ret = bcm_sf2_cfp_rst(priv); 1108 if (ret) { 1109 pr_err("failed to reset CFP\n"); 1110 goto out_mdio; 1111 } 1112 1113 /* Disable all interrupts and request them */ 1114 bcm_sf2_intr_disable(priv); 1115 1116 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1117 "switch_0", ds); 1118 if (ret < 0) { 1119 pr_err("failed to request switch_0 IRQ\n"); 1120 goto out_mdio; 1121 } 1122 1123 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1124 "switch_1", ds); 1125 if (ret < 0) { 1126 pr_err("failed to request switch_1 IRQ\n"); 1127 goto out_mdio; 1128 } 1129 1130 /* Reset the MIB counters */ 1131 reg = core_readl(priv, CORE_GMNCFGCFG); 1132 reg |= RST_MIB_CNT; 1133 core_writel(priv, reg, CORE_GMNCFGCFG); 1134 reg &= ~RST_MIB_CNT; 1135 core_writel(priv, reg, CORE_GMNCFGCFG); 1136 1137 /* Get the maximum number of ports for this switch */ 1138 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1139 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1140 priv->hw_params.num_ports = DSA_MAX_PORTS; 1141 1142 /* Assume a single GPHY setup if we can't read that property */ 1143 if (of_property_read_u32(dn, "brcm,num-gphy", 1144 &priv->hw_params.num_gphy)) 1145 priv->hw_params.num_gphy = 1; 1146 1147 rev = reg_readl(priv, REG_SWITCH_REVISION); 1148 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1149 SWITCH_TOP_REV_MASK; 1150 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1151 1152 rev = reg_readl(priv, REG_PHY_REVISION); 1153 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1154 1155 ret = b53_switch_register(dev); 1156 if (ret) 1157 goto out_mdio; 1158 1159 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n", 1160 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1161 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1162 priv->core, priv->irq0, priv->irq1); 1163 1164 return 0; 1165 1166 out_mdio: 1167 bcm_sf2_mdio_unregister(priv); 1168 return ret; 1169 } 1170 1171 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1172 { 1173 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1174 1175 priv->wol_ports_mask = 0; 1176 dsa_unregister_switch(priv->dev->ds); 1177 bcm_sf2_cfp_exit(priv->dev->ds); 1178 /* Disable all ports and interrupts */ 1179 bcm_sf2_sw_suspend(priv->dev->ds); 1180 bcm_sf2_mdio_unregister(priv); 1181 1182 return 0; 1183 } 1184 1185 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1186 { 1187 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1188 1189 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1190 * successful MDIO bus scan to occur. If we did turn off the GPHY 1191 * before (e.g: port_disable), this will also power it back on. 1192 * 1193 * Do not rely on kexec_in_progress, just power the PHY on. 1194 */ 1195 if (priv->hw_params.num_gphy == 1) 1196 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1197 } 1198 1199 #ifdef CONFIG_PM_SLEEP 1200 static int bcm_sf2_suspend(struct device *dev) 1201 { 1202 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1203 1204 return dsa_switch_suspend(priv->dev->ds); 1205 } 1206 1207 static int bcm_sf2_resume(struct device *dev) 1208 { 1209 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1210 1211 return dsa_switch_resume(priv->dev->ds); 1212 } 1213 #endif /* CONFIG_PM_SLEEP */ 1214 1215 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1216 bcm_sf2_suspend, bcm_sf2_resume); 1217 1218 1219 static struct platform_driver bcm_sf2_driver = { 1220 .probe = bcm_sf2_sw_probe, 1221 .remove = bcm_sf2_sw_remove, 1222 .shutdown = bcm_sf2_sw_shutdown, 1223 .driver = { 1224 .name = "brcm-sf2", 1225 .of_match_table = bcm_sf2_of_match, 1226 .pm = &bcm_sf2_pm_ops, 1227 }, 1228 }; 1229 module_platform_driver(bcm_sf2_driver); 1230 1231 MODULE_AUTHOR("Broadcom Corporation"); 1232 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1233 MODULE_LICENSE("GPL"); 1234 MODULE_ALIAS("platform:brcm-sf2"); 1235