1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <net/dsa.h> 24 #include <linux/ethtool.h> 25 #include <linux/if_bridge.h> 26 #include <linux/brcmphy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/platform_data/b53.h> 29 30 #include "bcm_sf2.h" 31 #include "bcm_sf2_regs.h" 32 #include "b53/b53_priv.h" 33 #include "b53/b53_regs.h" 34 35 /* Return the number of active ports, not counting the IMP (CPU) port */ 36 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds) 37 { 38 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 39 unsigned int port, count = 0; 40 41 for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) { 42 if (dsa_is_cpu_port(ds, port)) 43 continue; 44 if (priv->port_sts[port].enabled) 45 count++; 46 } 47 48 return count; 49 } 50 51 static void bcm_sf2_recalc_clock(struct dsa_switch *ds) 52 { 53 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 54 unsigned long new_rate; 55 unsigned int ports_active; 56 /* Frequenty in Mhz */ 57 static const unsigned long rate_table[] = { 58 59220000, 59 60820000, 60 62500000, 61 62500000, 62 }; 63 64 ports_active = bcm_sf2_num_active_ports(ds); 65 if (ports_active == 0 || !priv->clk_mdiv) 66 return; 67 68 /* If we overflow our table, just use the recommended operational 69 * frequency 70 */ 71 if (ports_active > ARRAY_SIZE(rate_table)) 72 new_rate = 90000000; 73 else 74 new_rate = rate_table[ports_active - 1]; 75 clk_set_rate(priv->clk_mdiv, new_rate); 76 } 77 78 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 79 { 80 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 81 unsigned int i; 82 u32 reg, offset; 83 84 /* Enable the port memories */ 85 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 86 reg &= ~P_TXQ_PSM_VDD(port); 87 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 88 89 /* Enable forwarding */ 90 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 91 92 /* Enable IMP port in dumb mode */ 93 reg = core_readl(priv, CORE_SWITCH_CTRL); 94 reg |= MII_DUMB_FWDG_EN; 95 core_writel(priv, reg, CORE_SWITCH_CTRL); 96 97 /* Configure Traffic Class to QoS mapping, allow each priority to map 98 * to a different queue number 99 */ 100 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 101 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 102 reg |= i << (PRT_TO_QID_SHIFT * i); 103 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 104 105 b53_brcm_hdr_setup(ds, port); 106 107 if (port == 8) { 108 if (priv->type == BCM4908_DEVICE_ID || 109 priv->type == BCM7445_DEVICE_ID) 110 offset = CORE_STS_OVERRIDE_IMP; 111 else 112 offset = CORE_STS_OVERRIDE_IMP2; 113 114 /* Force link status for IMP port */ 115 reg = core_readl(priv, offset); 116 reg |= (MII_SW_OR | LINK_STS); 117 if (priv->type == BCM4908_DEVICE_ID) 118 reg |= GMII_SPEED_UP_2G; 119 else 120 reg &= ~GMII_SPEED_UP_2G; 121 core_writel(priv, reg, offset); 122 123 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 124 reg = core_readl(priv, CORE_IMP_CTL); 125 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 126 reg &= ~(RX_DIS | TX_DIS); 127 core_writel(priv, reg, CORE_IMP_CTL); 128 } else { 129 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 130 reg &= ~(RX_DIS | TX_DIS); 131 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 132 } 133 134 priv->port_sts[port].enabled = true; 135 } 136 137 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 138 { 139 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 140 u32 reg; 141 142 reg = reg_readl(priv, REG_SPHY_CNTRL); 143 if (enable) { 144 reg |= PHY_RESET; 145 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 146 reg_writel(priv, reg, REG_SPHY_CNTRL); 147 udelay(21); 148 reg = reg_readl(priv, REG_SPHY_CNTRL); 149 reg &= ~PHY_RESET; 150 } else { 151 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 152 reg_writel(priv, reg, REG_SPHY_CNTRL); 153 mdelay(1); 154 reg |= CK25_DIS; 155 } 156 reg_writel(priv, reg, REG_SPHY_CNTRL); 157 158 /* Use PHY-driven LED signaling */ 159 if (!enable) { 160 reg = reg_readl(priv, REG_LED_CNTRL(0)); 161 reg |= SPDLNK_SRC_SEL; 162 reg_writel(priv, reg, REG_LED_CNTRL(0)); 163 } 164 } 165 166 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 167 int port) 168 { 169 unsigned int off; 170 171 switch (port) { 172 case 7: 173 off = P7_IRQ_OFF; 174 break; 175 case 0: 176 /* Port 0 interrupts are located on the first bank */ 177 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 178 return; 179 default: 180 off = P_IRQ_OFF(port); 181 break; 182 } 183 184 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 185 } 186 187 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 188 int port) 189 { 190 unsigned int off; 191 192 switch (port) { 193 case 7: 194 off = P7_IRQ_OFF; 195 break; 196 case 0: 197 /* Port 0 interrupts are located on the first bank */ 198 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 199 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 200 return; 201 default: 202 off = P_IRQ_OFF(port); 203 break; 204 } 205 206 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 207 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 208 } 209 210 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 211 struct phy_device *phy) 212 { 213 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 214 unsigned int i; 215 u32 reg; 216 217 if (!dsa_is_user_port(ds, port)) 218 return 0; 219 220 priv->port_sts[port].enabled = true; 221 222 bcm_sf2_recalc_clock(ds); 223 224 /* Clear the memory power down */ 225 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 226 reg &= ~P_TXQ_PSM_VDD(port); 227 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 228 229 /* Enable Broadcom tags for that port if requested */ 230 if (priv->brcm_tag_mask & BIT(port)) 231 b53_brcm_hdr_setup(ds, port); 232 233 /* Configure Traffic Class to QoS mapping, allow each priority to map 234 * to a different queue number 235 */ 236 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 237 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 238 reg |= i << (PRT_TO_QID_SHIFT * i); 239 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 240 241 /* Re-enable the GPHY and re-apply workarounds */ 242 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 243 bcm_sf2_gphy_enable_set(ds, true); 244 if (phy) { 245 /* if phy_stop() has been called before, phy 246 * will be in halted state, and phy_start() 247 * will call resume. 248 * 249 * the resume path does not configure back 250 * autoneg settings, and since we hard reset 251 * the phy manually here, we need to reset the 252 * state machine also. 253 */ 254 phy->state = PHY_READY; 255 phy_init_hw(phy); 256 } 257 } 258 259 /* Enable MoCA port interrupts to get notified */ 260 if (port == priv->moca_port) 261 bcm_sf2_port_intr_enable(priv, port); 262 263 /* Set per-queue pause threshold to 32 */ 264 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 265 266 /* Set ACB threshold to 24 */ 267 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 268 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 269 SF2_NUM_EGRESS_QUEUES + i)); 270 reg &= ~XOFF_THRESHOLD_MASK; 271 reg |= 24; 272 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 273 SF2_NUM_EGRESS_QUEUES + i)); 274 } 275 276 return b53_enable_port(ds, port, phy); 277 } 278 279 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 280 { 281 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 282 u32 reg; 283 284 /* Disable learning while in WoL mode */ 285 if (priv->wol_ports_mask & (1 << port)) { 286 reg = core_readl(priv, CORE_DIS_LEARN); 287 reg |= BIT(port); 288 core_writel(priv, reg, CORE_DIS_LEARN); 289 return; 290 } 291 292 if (port == priv->moca_port) 293 bcm_sf2_port_intr_disable(priv, port); 294 295 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 296 bcm_sf2_gphy_enable_set(ds, false); 297 298 b53_disable_port(ds, port); 299 300 /* Power down the port memory */ 301 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 302 reg |= P_TXQ_PSM_VDD(port); 303 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 304 305 priv->port_sts[port].enabled = false; 306 307 bcm_sf2_recalc_clock(ds); 308 } 309 310 311 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 312 int regnum, u16 val) 313 { 314 int ret = 0; 315 u32 reg; 316 317 reg = reg_readl(priv, REG_SWITCH_CNTRL); 318 reg |= MDIO_MASTER_SEL; 319 reg_writel(priv, reg, REG_SWITCH_CNTRL); 320 321 /* Page << 8 | offset */ 322 reg = 0x70; 323 reg <<= 2; 324 core_writel(priv, addr, reg); 325 326 /* Page << 8 | offset */ 327 reg = 0x80 << 8 | regnum << 1; 328 reg <<= 2; 329 330 if (op) 331 ret = core_readl(priv, reg); 332 else 333 core_writel(priv, val, reg); 334 335 reg = reg_readl(priv, REG_SWITCH_CNTRL); 336 reg &= ~MDIO_MASTER_SEL; 337 reg_writel(priv, reg, REG_SWITCH_CNTRL); 338 339 return ret & 0xffff; 340 } 341 342 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 343 { 344 struct bcm_sf2_priv *priv = bus->priv; 345 346 /* Intercept reads from Broadcom pseudo-PHY address, else, send 347 * them to our master MDIO bus controller 348 */ 349 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 350 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 351 else 352 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 353 } 354 355 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 356 u16 val) 357 { 358 struct bcm_sf2_priv *priv = bus->priv; 359 360 /* Intercept writes to the Broadcom pseudo-PHY address, else, 361 * send them to our master MDIO bus controller 362 */ 363 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 364 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 365 else 366 return mdiobus_write_nested(priv->master_mii_bus, addr, 367 regnum, val); 368 } 369 370 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 371 { 372 struct dsa_switch *ds = dev_id; 373 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 374 375 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 376 ~priv->irq0_mask; 377 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 378 379 return IRQ_HANDLED; 380 } 381 382 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 383 { 384 struct dsa_switch *ds = dev_id; 385 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 386 387 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 388 ~priv->irq1_mask; 389 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 390 391 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 392 priv->port_sts[7].link = true; 393 dsa_port_phylink_mac_change(ds, 7, true); 394 } 395 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 396 priv->port_sts[7].link = false; 397 dsa_port_phylink_mac_change(ds, 7, false); 398 } 399 400 return IRQ_HANDLED; 401 } 402 403 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 404 { 405 unsigned int timeout = 1000; 406 u32 reg; 407 int ret; 408 409 /* The watchdog reset does not work on 7278, we need to hit the 410 * "external" reset line through the reset controller. 411 */ 412 if (priv->type == BCM7278_DEVICE_ID) { 413 ret = reset_control_assert(priv->rcdev); 414 if (ret) 415 return ret; 416 417 return reset_control_deassert(priv->rcdev); 418 } 419 420 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 421 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 422 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 423 424 do { 425 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 426 if (!(reg & SOFTWARE_RESET)) 427 break; 428 429 usleep_range(1000, 2000); 430 } while (timeout-- > 0); 431 432 if (timeout == 0) 433 return -ETIMEDOUT; 434 435 return 0; 436 } 437 438 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 439 { 440 intrl2_0_mask_set(priv, 0xffffffff); 441 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 442 intrl2_1_mask_set(priv, 0xffffffff); 443 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 444 } 445 446 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 447 struct device_node *dn) 448 { 449 struct device_node *port; 450 unsigned int port_num; 451 struct property *prop; 452 phy_interface_t mode; 453 int err; 454 455 priv->moca_port = -1; 456 457 for_each_available_child_of_node(dn, port) { 458 if (of_property_read_u32(port, "reg", &port_num)) 459 continue; 460 461 /* Internal PHYs get assigned a specific 'phy-mode' property 462 * value: "internal" to help flag them before MDIO probing 463 * has completed, since they might be turned off at that 464 * time 465 */ 466 err = of_get_phy_mode(port, &mode); 467 if (err) 468 continue; 469 470 if (mode == PHY_INTERFACE_MODE_INTERNAL) 471 priv->int_phy_mask |= 1 << port_num; 472 473 if (mode == PHY_INTERFACE_MODE_MOCA) 474 priv->moca_port = port_num; 475 476 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 477 priv->brcm_tag_mask |= 1 << port_num; 478 479 /* Ensure that port 5 is not picked up as a DSA CPU port 480 * flavour but a regular port instead. We should be using 481 * devlink to be able to set the port flavour. 482 */ 483 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) { 484 prop = of_find_property(port, "ethernet", NULL); 485 if (prop) 486 of_remove_property(port, prop); 487 } 488 } 489 } 490 491 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 492 { 493 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 494 struct device_node *dn, *child; 495 struct phy_device *phydev; 496 struct property *prop; 497 static int index; 498 int err, reg; 499 500 /* Find our integrated MDIO bus node */ 501 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 502 priv->master_mii_bus = of_mdio_find_bus(dn); 503 if (!priv->master_mii_bus) { 504 of_node_put(dn); 505 return -EPROBE_DEFER; 506 } 507 508 get_device(&priv->master_mii_bus->dev); 509 priv->master_mii_dn = dn; 510 511 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 512 if (!priv->slave_mii_bus) { 513 of_node_put(dn); 514 return -ENOMEM; 515 } 516 517 priv->slave_mii_bus->priv = priv; 518 priv->slave_mii_bus->name = "sf2 slave mii"; 519 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 520 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 521 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 522 index++); 523 priv->slave_mii_bus->dev.of_node = dn; 524 525 /* Include the pseudo-PHY address to divert reads towards our 526 * workaround. This is only required for 7445D0, since 7445E0 527 * disconnects the internal switch pseudo-PHY such that we can use the 528 * regular SWITCH_MDIO master controller instead. 529 * 530 * Here we flag the pseudo PHY as needing special treatment and would 531 * otherwise make all other PHY read/writes go to the master MDIO bus 532 * controller that comes with this switch backed by the "mdio-unimac" 533 * driver. 534 */ 535 if (of_machine_is_compatible("brcm,bcm7445d0")) 536 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0); 537 else 538 priv->indir_phy_mask = 0; 539 540 ds->phys_mii_mask = priv->indir_phy_mask; 541 ds->slave_mii_bus = priv->slave_mii_bus; 542 priv->slave_mii_bus->parent = ds->dev->parent; 543 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 544 545 /* We need to make sure that of_phy_connect() will not work by 546 * removing the 'phandle' and 'linux,phandle' properties and 547 * unregister the existing PHY device that was already registered. 548 */ 549 for_each_available_child_of_node(dn, child) { 550 if (of_property_read_u32(child, "reg", ®) || 551 reg >= PHY_MAX_ADDR) 552 continue; 553 554 if (!(priv->indir_phy_mask & BIT(reg))) 555 continue; 556 557 prop = of_find_property(child, "phandle", NULL); 558 if (prop) 559 of_remove_property(child, prop); 560 561 prop = of_find_property(child, "linux,phandle", NULL); 562 if (prop) 563 of_remove_property(child, prop); 564 565 phydev = of_phy_find_device(child); 566 if (phydev) 567 phy_device_remove(phydev); 568 } 569 570 err = mdiobus_register(priv->slave_mii_bus); 571 if (err && dn) 572 of_node_put(dn); 573 574 return err; 575 } 576 577 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 578 { 579 mdiobus_unregister(priv->slave_mii_bus); 580 of_node_put(priv->master_mii_dn); 581 } 582 583 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 584 { 585 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 586 587 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 588 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 589 * the REG_PHY_REVISION register layout is. 590 */ 591 if (priv->int_phy_mask & BIT(port)) 592 return priv->hw_params.gphy_rev; 593 else 594 return 0; 595 } 596 597 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 598 unsigned long *supported, 599 struct phylink_link_state *state) 600 { 601 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 602 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 603 604 if (!phy_interface_mode_is_rgmii(state->interface) && 605 state->interface != PHY_INTERFACE_MODE_MII && 606 state->interface != PHY_INTERFACE_MODE_REVMII && 607 state->interface != PHY_INTERFACE_MODE_GMII && 608 state->interface != PHY_INTERFACE_MODE_INTERNAL && 609 state->interface != PHY_INTERFACE_MODE_MOCA) { 610 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 611 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 612 dev_err(ds->dev, 613 "Unsupported interface: %d for port %d\n", 614 state->interface, port); 615 return; 616 } 617 618 /* Allow all the expected bits */ 619 phylink_set(mask, Autoneg); 620 phylink_set_port_modes(mask); 621 phylink_set(mask, Pause); 622 phylink_set(mask, Asym_Pause); 623 624 /* With the exclusion of MII and Reverse MII, we support Gigabit, 625 * including Half duplex 626 */ 627 if (state->interface != PHY_INTERFACE_MODE_MII && 628 state->interface != PHY_INTERFACE_MODE_REVMII) { 629 phylink_set(mask, 1000baseT_Full); 630 phylink_set(mask, 1000baseT_Half); 631 } 632 633 phylink_set(mask, 10baseT_Half); 634 phylink_set(mask, 10baseT_Full); 635 phylink_set(mask, 100baseT_Half); 636 phylink_set(mask, 100baseT_Full); 637 638 bitmap_and(supported, supported, mask, 639 __ETHTOOL_LINK_MODE_MASK_NBITS); 640 bitmap_and(state->advertising, state->advertising, mask, 641 __ETHTOOL_LINK_MODE_MASK_NBITS); 642 } 643 644 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 645 unsigned int mode, 646 const struct phylink_link_state *state) 647 { 648 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 649 u32 id_mode_dis = 0, port_mode; 650 u32 reg; 651 652 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 653 return; 654 655 switch (state->interface) { 656 case PHY_INTERFACE_MODE_RGMII: 657 id_mode_dis = 1; 658 fallthrough; 659 case PHY_INTERFACE_MODE_RGMII_TXID: 660 port_mode = EXT_GPHY; 661 break; 662 case PHY_INTERFACE_MODE_MII: 663 port_mode = EXT_EPHY; 664 break; 665 case PHY_INTERFACE_MODE_REVMII: 666 port_mode = EXT_REVMII; 667 break; 668 default: 669 /* Nothing required for all other PHYs: internal and MoCA */ 670 return; 671 } 672 673 /* Clear id_mode_dis bit, and the existing port mode, let 674 * RGMII_MODE_EN bet set by mac_link_{up,down} 675 */ 676 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 677 reg &= ~ID_MODE_DIS; 678 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 679 680 reg |= port_mode; 681 if (id_mode_dis) 682 reg |= ID_MODE_DIS; 683 684 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 685 } 686 687 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 688 phy_interface_t interface, bool link) 689 { 690 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 691 u32 reg; 692 693 if (!phy_interface_mode_is_rgmii(interface) && 694 interface != PHY_INTERFACE_MODE_MII && 695 interface != PHY_INTERFACE_MODE_REVMII) 696 return; 697 698 /* If the link is down, just disable the interface to conserve power */ 699 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 700 if (link) 701 reg |= RGMII_MODE_EN; 702 else 703 reg &= ~RGMII_MODE_EN; 704 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 705 } 706 707 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 708 unsigned int mode, 709 phy_interface_t interface) 710 { 711 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 712 u32 reg, offset; 713 714 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 715 if (priv->type == BCM4908_DEVICE_ID || 716 priv->type == BCM7445_DEVICE_ID) 717 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 718 else 719 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 720 721 reg = core_readl(priv, offset); 722 reg &= ~LINK_STS; 723 core_writel(priv, reg, offset); 724 } 725 726 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 727 } 728 729 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 730 unsigned int mode, 731 phy_interface_t interface, 732 struct phy_device *phydev, 733 int speed, int duplex, 734 bool tx_pause, bool rx_pause) 735 { 736 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 737 struct ethtool_eee *p = &priv->dev->ports[port].eee; 738 u32 reg, offset; 739 740 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 741 742 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 743 if (priv->type == BCM4908_DEVICE_ID || 744 priv->type == BCM7445_DEVICE_ID) 745 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 746 else 747 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 748 749 if (interface == PHY_INTERFACE_MODE_RGMII || 750 interface == PHY_INTERFACE_MODE_RGMII_TXID || 751 interface == PHY_INTERFACE_MODE_MII || 752 interface == PHY_INTERFACE_MODE_REVMII) { 753 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 754 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 755 756 if (tx_pause) 757 reg |= TX_PAUSE_EN; 758 if (rx_pause) 759 reg |= RX_PAUSE_EN; 760 761 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 762 } 763 764 reg = SW_OVERRIDE | LINK_STS; 765 switch (speed) { 766 case SPEED_1000: 767 reg |= SPDSTS_1000 << SPEED_SHIFT; 768 break; 769 case SPEED_100: 770 reg |= SPDSTS_100 << SPEED_SHIFT; 771 break; 772 } 773 774 if (duplex == DUPLEX_FULL) 775 reg |= DUPLX_MODE; 776 777 core_writel(priv, reg, offset); 778 } 779 780 if (mode == MLO_AN_PHY && phydev) 781 p->eee_enabled = b53_eee_init(ds, port, phydev); 782 } 783 784 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 785 struct phylink_link_state *status) 786 { 787 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 788 789 status->link = false; 790 791 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 792 * which means that we need to force the link at the port override 793 * level to get the data to flow. We do use what the interrupt handler 794 * did determine before. 795 * 796 * For the other ports, we just force the link status, since this is 797 * a fixed PHY device. 798 */ 799 if (port == priv->moca_port) { 800 status->link = priv->port_sts[port].link; 801 /* For MoCA interfaces, also force a link down notification 802 * since some version of the user-space daemon (mocad) use 803 * cmd->autoneg to force the link, which messes up the PHY 804 * state machine and make it go in PHY_FORCING state instead. 805 */ 806 if (!status->link) 807 netif_carrier_off(dsa_to_port(ds, port)->slave); 808 status->duplex = DUPLEX_FULL; 809 } else { 810 status->link = true; 811 } 812 } 813 814 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 815 { 816 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 817 u32 reg; 818 819 /* Enable ACB globally */ 820 reg = acb_readl(priv, ACB_CONTROL); 821 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 822 acb_writel(priv, reg, ACB_CONTROL); 823 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 824 reg |= ACB_EN | ACB_ALGORITHM; 825 acb_writel(priv, reg, ACB_CONTROL); 826 } 827 828 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 829 { 830 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 831 unsigned int port; 832 833 bcm_sf2_intr_disable(priv); 834 835 /* Disable all ports physically present including the IMP 836 * port, the other ones have already been disabled during 837 * bcm_sf2_sw_setup 838 */ 839 for (port = 0; port < ds->num_ports; port++) { 840 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 841 bcm_sf2_port_disable(ds, port); 842 } 843 844 if (!priv->wol_ports_mask) 845 clk_disable_unprepare(priv->clk); 846 847 return 0; 848 } 849 850 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 851 { 852 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 853 int ret; 854 855 if (!priv->wol_ports_mask) 856 clk_prepare_enable(priv->clk); 857 858 ret = bcm_sf2_sw_rst(priv); 859 if (ret) { 860 pr_err("%s: failed to software reset switch\n", __func__); 861 return ret; 862 } 863 864 ret = bcm_sf2_cfp_resume(ds); 865 if (ret) 866 return ret; 867 868 if (priv->hw_params.num_gphy == 1) 869 bcm_sf2_gphy_enable_set(ds, true); 870 871 ds->ops->setup(ds); 872 873 return 0; 874 } 875 876 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 877 struct ethtool_wolinfo *wol) 878 { 879 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 880 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 881 struct ethtool_wolinfo pwol = { }; 882 883 /* Get the parent device WoL settings */ 884 if (p->ethtool_ops->get_wol) 885 p->ethtool_ops->get_wol(p, &pwol); 886 887 /* Advertise the parent device supported settings */ 888 wol->supported = pwol.supported; 889 memset(&wol->sopass, 0, sizeof(wol->sopass)); 890 891 if (pwol.wolopts & WAKE_MAGICSECURE) 892 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 893 894 if (priv->wol_ports_mask & (1 << port)) 895 wol->wolopts = pwol.wolopts; 896 else 897 wol->wolopts = 0; 898 } 899 900 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 901 struct ethtool_wolinfo *wol) 902 { 903 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 904 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 905 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 906 struct ethtool_wolinfo pwol = { }; 907 908 if (p->ethtool_ops->get_wol) 909 p->ethtool_ops->get_wol(p, &pwol); 910 if (wol->wolopts & ~pwol.supported) 911 return -EINVAL; 912 913 if (wol->wolopts) 914 priv->wol_ports_mask |= (1 << port); 915 else 916 priv->wol_ports_mask &= ~(1 << port); 917 918 /* If we have at least one port enabled, make sure the CPU port 919 * is also enabled. If the CPU port is the last one enabled, we disable 920 * it since this configuration does not make sense. 921 */ 922 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 923 priv->wol_ports_mask |= (1 << cpu_port); 924 else 925 priv->wol_ports_mask &= ~(1 << cpu_port); 926 927 return p->ethtool_ops->set_wol(p, wol); 928 } 929 930 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 931 { 932 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 933 unsigned int port; 934 935 /* Enable all valid ports and disable those unused */ 936 for (port = 0; port < priv->hw_params.num_ports; port++) { 937 /* IMP port receives special treatment */ 938 if (dsa_is_user_port(ds, port)) 939 bcm_sf2_port_setup(ds, port, NULL); 940 else if (dsa_is_cpu_port(ds, port)) 941 bcm_sf2_imp_setup(ds, port); 942 else 943 bcm_sf2_port_disable(ds, port); 944 } 945 946 b53_configure_vlan(ds); 947 bcm_sf2_enable_acb(ds); 948 949 return b53_setup_devlink_resources(ds); 950 } 951 952 static void bcm_sf2_sw_teardown(struct dsa_switch *ds) 953 { 954 dsa_devlink_resources_unregister(ds); 955 } 956 957 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 958 * register basis so we need to translate that into an address that the 959 * bus-glue understands. 960 */ 961 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 962 963 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 964 u8 *val) 965 { 966 struct bcm_sf2_priv *priv = dev->priv; 967 968 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 969 970 return 0; 971 } 972 973 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 974 u16 *val) 975 { 976 struct bcm_sf2_priv *priv = dev->priv; 977 978 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 979 980 return 0; 981 } 982 983 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 984 u32 *val) 985 { 986 struct bcm_sf2_priv *priv = dev->priv; 987 988 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 989 990 return 0; 991 } 992 993 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 994 u64 *val) 995 { 996 struct bcm_sf2_priv *priv = dev->priv; 997 998 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 999 1000 return 0; 1001 } 1002 1003 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 1004 u8 value) 1005 { 1006 struct bcm_sf2_priv *priv = dev->priv; 1007 1008 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1009 1010 return 0; 1011 } 1012 1013 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 1014 u16 value) 1015 { 1016 struct bcm_sf2_priv *priv = dev->priv; 1017 1018 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1019 1020 return 0; 1021 } 1022 1023 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 1024 u32 value) 1025 { 1026 struct bcm_sf2_priv *priv = dev->priv; 1027 1028 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1029 1030 return 0; 1031 } 1032 1033 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 1034 u64 value) 1035 { 1036 struct bcm_sf2_priv *priv = dev->priv; 1037 1038 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1039 1040 return 0; 1041 } 1042 1043 static const struct b53_io_ops bcm_sf2_io_ops = { 1044 .read8 = bcm_sf2_core_read8, 1045 .read16 = bcm_sf2_core_read16, 1046 .read32 = bcm_sf2_core_read32, 1047 .read48 = bcm_sf2_core_read64, 1048 .read64 = bcm_sf2_core_read64, 1049 .write8 = bcm_sf2_core_write8, 1050 .write16 = bcm_sf2_core_write16, 1051 .write32 = bcm_sf2_core_write32, 1052 .write48 = bcm_sf2_core_write64, 1053 .write64 = bcm_sf2_core_write64, 1054 }; 1055 1056 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 1057 u32 stringset, uint8_t *data) 1058 { 1059 int cnt = b53_get_sset_count(ds, port, stringset); 1060 1061 b53_get_strings(ds, port, stringset, data); 1062 bcm_sf2_cfp_get_strings(ds, port, stringset, 1063 data + cnt * ETH_GSTRING_LEN); 1064 } 1065 1066 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 1067 uint64_t *data) 1068 { 1069 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 1070 1071 b53_get_ethtool_stats(ds, port, data); 1072 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 1073 } 1074 1075 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 1076 int sset) 1077 { 1078 int cnt = b53_get_sset_count(ds, port, sset); 1079 1080 if (cnt < 0) 1081 return cnt; 1082 1083 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 1084 1085 return cnt; 1086 } 1087 1088 static const struct dsa_switch_ops bcm_sf2_ops = { 1089 .get_tag_protocol = b53_get_tag_protocol, 1090 .setup = bcm_sf2_sw_setup, 1091 .teardown = bcm_sf2_sw_teardown, 1092 .get_strings = bcm_sf2_sw_get_strings, 1093 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 1094 .get_sset_count = bcm_sf2_sw_get_sset_count, 1095 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1096 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 1097 .phylink_validate = bcm_sf2_sw_validate, 1098 .phylink_mac_config = bcm_sf2_sw_mac_config, 1099 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 1100 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 1101 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 1102 .suspend = bcm_sf2_sw_suspend, 1103 .resume = bcm_sf2_sw_resume, 1104 .get_wol = bcm_sf2_sw_get_wol, 1105 .set_wol = bcm_sf2_sw_set_wol, 1106 .port_enable = bcm_sf2_port_setup, 1107 .port_disable = bcm_sf2_port_disable, 1108 .get_mac_eee = b53_get_mac_eee, 1109 .set_mac_eee = b53_set_mac_eee, 1110 .port_bridge_join = b53_br_join, 1111 .port_bridge_leave = b53_br_leave, 1112 .port_pre_bridge_flags = b53_br_flags_pre, 1113 .port_bridge_flags = b53_br_flags, 1114 .port_stp_state_set = b53_br_set_stp_state, 1115 .port_set_mrouter = b53_set_mrouter, 1116 .port_fast_age = b53_br_fast_age, 1117 .port_vlan_filtering = b53_vlan_filtering, 1118 .port_vlan_add = b53_vlan_add, 1119 .port_vlan_del = b53_vlan_del, 1120 .port_fdb_dump = b53_fdb_dump, 1121 .port_fdb_add = b53_fdb_add, 1122 .port_fdb_del = b53_fdb_del, 1123 .get_rxnfc = bcm_sf2_get_rxnfc, 1124 .set_rxnfc = bcm_sf2_set_rxnfc, 1125 .port_mirror_add = b53_mirror_add, 1126 .port_mirror_del = b53_mirror_del, 1127 .port_mdb_add = b53_mdb_add, 1128 .port_mdb_del = b53_mdb_del, 1129 }; 1130 1131 struct bcm_sf2_of_data { 1132 u32 type; 1133 const u16 *reg_offsets; 1134 unsigned int core_reg_align; 1135 unsigned int num_cfp_rules; 1136 }; 1137 1138 static const u16 bcm_sf2_4908_reg_offsets[] = { 1139 [REG_SWITCH_CNTRL] = 0x00, 1140 [REG_SWITCH_STATUS] = 0x04, 1141 [REG_DIR_DATA_WRITE] = 0x08, 1142 [REG_DIR_DATA_READ] = 0x0c, 1143 [REG_SWITCH_REVISION] = 0x10, 1144 [REG_PHY_REVISION] = 0x14, 1145 [REG_SPHY_CNTRL] = 0x24, 1146 [REG_CROSSBAR] = 0xc8, 1147 [REG_RGMII_0_CNTRL] = 0xe0, 1148 [REG_RGMII_1_CNTRL] = 0xec, 1149 [REG_RGMII_2_CNTRL] = 0xf8, 1150 [REG_LED_0_CNTRL] = 0x40, 1151 [REG_LED_1_CNTRL] = 0x4c, 1152 [REG_LED_2_CNTRL] = 0x58, 1153 }; 1154 1155 static const struct bcm_sf2_of_data bcm_sf2_4908_data = { 1156 .type = BCM4908_DEVICE_ID, 1157 .core_reg_align = 0, 1158 .reg_offsets = bcm_sf2_4908_reg_offsets, 1159 .num_cfp_rules = 0, /* FIXME */ 1160 }; 1161 1162 /* Register offsets for the SWITCH_REG_* block */ 1163 static const u16 bcm_sf2_7445_reg_offsets[] = { 1164 [REG_SWITCH_CNTRL] = 0x00, 1165 [REG_SWITCH_STATUS] = 0x04, 1166 [REG_DIR_DATA_WRITE] = 0x08, 1167 [REG_DIR_DATA_READ] = 0x0C, 1168 [REG_SWITCH_REVISION] = 0x18, 1169 [REG_PHY_REVISION] = 0x1C, 1170 [REG_SPHY_CNTRL] = 0x2C, 1171 [REG_RGMII_0_CNTRL] = 0x34, 1172 [REG_RGMII_1_CNTRL] = 0x40, 1173 [REG_RGMII_2_CNTRL] = 0x4c, 1174 [REG_LED_0_CNTRL] = 0x90, 1175 [REG_LED_1_CNTRL] = 0x94, 1176 [REG_LED_2_CNTRL] = 0x98, 1177 }; 1178 1179 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1180 .type = BCM7445_DEVICE_ID, 1181 .core_reg_align = 0, 1182 .reg_offsets = bcm_sf2_7445_reg_offsets, 1183 .num_cfp_rules = 256, 1184 }; 1185 1186 static const u16 bcm_sf2_7278_reg_offsets[] = { 1187 [REG_SWITCH_CNTRL] = 0x00, 1188 [REG_SWITCH_STATUS] = 0x04, 1189 [REG_DIR_DATA_WRITE] = 0x08, 1190 [REG_DIR_DATA_READ] = 0x0c, 1191 [REG_SWITCH_REVISION] = 0x10, 1192 [REG_PHY_REVISION] = 0x14, 1193 [REG_SPHY_CNTRL] = 0x24, 1194 [REG_RGMII_0_CNTRL] = 0xe0, 1195 [REG_RGMII_1_CNTRL] = 0xec, 1196 [REG_RGMII_2_CNTRL] = 0xf8, 1197 [REG_LED_0_CNTRL] = 0x40, 1198 [REG_LED_1_CNTRL] = 0x4c, 1199 [REG_LED_2_CNTRL] = 0x58, 1200 }; 1201 1202 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1203 .type = BCM7278_DEVICE_ID, 1204 .core_reg_align = 1, 1205 .reg_offsets = bcm_sf2_7278_reg_offsets, 1206 .num_cfp_rules = 128, 1207 }; 1208 1209 static const struct of_device_id bcm_sf2_of_match[] = { 1210 { .compatible = "brcm,bcm4908-switch", 1211 .data = &bcm_sf2_4908_data 1212 }, 1213 { .compatible = "brcm,bcm7445-switch-v4.0", 1214 .data = &bcm_sf2_7445_data 1215 }, 1216 { .compatible = "brcm,bcm7278-switch-v4.0", 1217 .data = &bcm_sf2_7278_data 1218 }, 1219 { .compatible = "brcm,bcm7278-switch-v4.8", 1220 .data = &bcm_sf2_7278_data 1221 }, 1222 { /* sentinel */ }, 1223 }; 1224 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1225 1226 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1227 { 1228 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1229 struct device_node *dn = pdev->dev.of_node; 1230 const struct of_device_id *of_id = NULL; 1231 const struct bcm_sf2_of_data *data; 1232 struct b53_platform_data *pdata; 1233 struct dsa_switch_ops *ops; 1234 struct device_node *ports; 1235 struct bcm_sf2_priv *priv; 1236 struct b53_device *dev; 1237 struct dsa_switch *ds; 1238 void __iomem **base; 1239 unsigned int i; 1240 u32 reg, rev; 1241 int ret; 1242 1243 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1244 if (!priv) 1245 return -ENOMEM; 1246 1247 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1248 if (!ops) 1249 return -ENOMEM; 1250 1251 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1252 if (!dev) 1253 return -ENOMEM; 1254 1255 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1256 if (!pdata) 1257 return -ENOMEM; 1258 1259 of_id = of_match_node(bcm_sf2_of_match, dn); 1260 if (!of_id || !of_id->data) 1261 return -EINVAL; 1262 1263 data = of_id->data; 1264 1265 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1266 priv->type = data->type; 1267 priv->reg_offsets = data->reg_offsets; 1268 priv->core_reg_align = data->core_reg_align; 1269 priv->num_cfp_rules = data->num_cfp_rules; 1270 1271 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1272 "switch"); 1273 if (IS_ERR(priv->rcdev)) 1274 return PTR_ERR(priv->rcdev); 1275 1276 /* Auto-detection using standard registers will not work, so 1277 * provide an indication of what kind of device we are for 1278 * b53_common to work with 1279 */ 1280 pdata->chip_id = priv->type; 1281 dev->pdata = pdata; 1282 1283 priv->dev = dev; 1284 ds = dev->ds; 1285 ds->ops = &bcm_sf2_ops; 1286 1287 /* Advertise the 8 egress queues */ 1288 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1289 1290 dev_set_drvdata(&pdev->dev, priv); 1291 1292 spin_lock_init(&priv->indir_lock); 1293 mutex_init(&priv->cfp.lock); 1294 INIT_LIST_HEAD(&priv->cfp.rules_list); 1295 1296 /* CFP rule #0 cannot be used for specific classifications, flag it as 1297 * permanently used 1298 */ 1299 set_bit(0, priv->cfp.used); 1300 set_bit(0, priv->cfp.unique); 1301 1302 /* Balance of_node_put() done by of_find_node_by_name() */ 1303 of_node_get(dn); 1304 ports = of_find_node_by_name(dn, "ports"); 1305 if (ports) { 1306 bcm_sf2_identify_ports(priv, ports); 1307 of_node_put(ports); 1308 } 1309 1310 priv->irq0 = irq_of_parse_and_map(dn, 0); 1311 priv->irq1 = irq_of_parse_and_map(dn, 1); 1312 1313 base = &priv->core; 1314 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1315 *base = devm_platform_ioremap_resource(pdev, i); 1316 if (IS_ERR(*base)) { 1317 pr_err("unable to find register: %s\n", reg_names[i]); 1318 return PTR_ERR(*base); 1319 } 1320 base++; 1321 } 1322 1323 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch"); 1324 if (IS_ERR(priv->clk)) 1325 return PTR_ERR(priv->clk); 1326 1327 clk_prepare_enable(priv->clk); 1328 1329 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv"); 1330 if (IS_ERR(priv->clk_mdiv)) { 1331 ret = PTR_ERR(priv->clk_mdiv); 1332 goto out_clk; 1333 } 1334 1335 clk_prepare_enable(priv->clk_mdiv); 1336 1337 ret = bcm_sf2_sw_rst(priv); 1338 if (ret) { 1339 pr_err("unable to software reset switch: %d\n", ret); 1340 goto out_clk_mdiv; 1341 } 1342 1343 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1344 1345 ret = bcm_sf2_mdio_register(ds); 1346 if (ret) { 1347 pr_err("failed to register MDIO bus\n"); 1348 goto out_clk_mdiv; 1349 } 1350 1351 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1352 1353 ret = bcm_sf2_cfp_rst(priv); 1354 if (ret) { 1355 pr_err("failed to reset CFP\n"); 1356 goto out_mdio; 1357 } 1358 1359 /* Disable all interrupts and request them */ 1360 bcm_sf2_intr_disable(priv); 1361 1362 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1363 "switch_0", ds); 1364 if (ret < 0) { 1365 pr_err("failed to request switch_0 IRQ\n"); 1366 goto out_mdio; 1367 } 1368 1369 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1370 "switch_1", ds); 1371 if (ret < 0) { 1372 pr_err("failed to request switch_1 IRQ\n"); 1373 goto out_mdio; 1374 } 1375 1376 /* Reset the MIB counters */ 1377 reg = core_readl(priv, CORE_GMNCFGCFG); 1378 reg |= RST_MIB_CNT; 1379 core_writel(priv, reg, CORE_GMNCFGCFG); 1380 reg &= ~RST_MIB_CNT; 1381 core_writel(priv, reg, CORE_GMNCFGCFG); 1382 1383 /* Get the maximum number of ports for this switch */ 1384 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1385 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1386 priv->hw_params.num_ports = DSA_MAX_PORTS; 1387 1388 /* Assume a single GPHY setup if we can't read that property */ 1389 if (of_property_read_u32(dn, "brcm,num-gphy", 1390 &priv->hw_params.num_gphy)) 1391 priv->hw_params.num_gphy = 1; 1392 1393 rev = reg_readl(priv, REG_SWITCH_REVISION); 1394 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1395 SWITCH_TOP_REV_MASK; 1396 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1397 1398 rev = reg_readl(priv, REG_PHY_REVISION); 1399 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1400 1401 ret = b53_switch_register(dev); 1402 if (ret) 1403 goto out_mdio; 1404 1405 dev_info(&pdev->dev, 1406 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1407 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1408 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1409 priv->irq0, priv->irq1); 1410 1411 return 0; 1412 1413 out_mdio: 1414 bcm_sf2_mdio_unregister(priv); 1415 out_clk_mdiv: 1416 clk_disable_unprepare(priv->clk_mdiv); 1417 out_clk: 1418 clk_disable_unprepare(priv->clk); 1419 return ret; 1420 } 1421 1422 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1423 { 1424 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1425 1426 priv->wol_ports_mask = 0; 1427 /* Disable interrupts */ 1428 bcm_sf2_intr_disable(priv); 1429 dsa_unregister_switch(priv->dev->ds); 1430 bcm_sf2_cfp_exit(priv->dev->ds); 1431 bcm_sf2_mdio_unregister(priv); 1432 clk_disable_unprepare(priv->clk_mdiv); 1433 clk_disable_unprepare(priv->clk); 1434 if (priv->type == BCM7278_DEVICE_ID) 1435 reset_control_assert(priv->rcdev); 1436 1437 return 0; 1438 } 1439 1440 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1441 { 1442 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1443 1444 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1445 * successful MDIO bus scan to occur. If we did turn off the GPHY 1446 * before (e.g: port_disable), this will also power it back on. 1447 * 1448 * Do not rely on kexec_in_progress, just power the PHY on. 1449 */ 1450 if (priv->hw_params.num_gphy == 1) 1451 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1452 } 1453 1454 #ifdef CONFIG_PM_SLEEP 1455 static int bcm_sf2_suspend(struct device *dev) 1456 { 1457 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1458 1459 return dsa_switch_suspend(priv->dev->ds); 1460 } 1461 1462 static int bcm_sf2_resume(struct device *dev) 1463 { 1464 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1465 1466 return dsa_switch_resume(priv->dev->ds); 1467 } 1468 #endif /* CONFIG_PM_SLEEP */ 1469 1470 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1471 bcm_sf2_suspend, bcm_sf2_resume); 1472 1473 1474 static struct platform_driver bcm_sf2_driver = { 1475 .probe = bcm_sf2_sw_probe, 1476 .remove = bcm_sf2_sw_remove, 1477 .shutdown = bcm_sf2_sw_shutdown, 1478 .driver = { 1479 .name = "brcm-sf2", 1480 .of_match_table = bcm_sf2_of_match, 1481 .pm = &bcm_sf2_pm_ops, 1482 }, 1483 }; 1484 module_platform_driver(bcm_sf2_driver); 1485 1486 MODULE_AUTHOR("Broadcom Corporation"); 1487 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1488 MODULE_LICENSE("GPL"); 1489 MODULE_ALIAS("platform:brcm-sf2"); 1490