1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/of.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_address.h> 20 #include <linux/of_net.h> 21 #include <linux/of_mdio.h> 22 #include <net/dsa.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_bridge.h> 25 #include <linux/brcmphy.h> 26 #include <linux/etherdevice.h> 27 #include <linux/platform_data/b53.h> 28 29 #include "bcm_sf2.h" 30 #include "bcm_sf2_regs.h" 31 #include "b53/b53_priv.h" 32 #include "b53/b53_regs.h" 33 34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 35 { 36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 37 unsigned int i; 38 u32 reg, offset; 39 40 if (priv->type == BCM7445_DEVICE_ID) 41 offset = CORE_STS_OVERRIDE_IMP; 42 else 43 offset = CORE_STS_OVERRIDE_IMP2; 44 45 /* Enable the port memories */ 46 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 47 reg &= ~P_TXQ_PSM_VDD(port); 48 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 49 50 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 51 reg = core_readl(priv, CORE_IMP_CTL); 52 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 53 reg &= ~(RX_DIS | TX_DIS); 54 core_writel(priv, reg, CORE_IMP_CTL); 55 56 /* Enable forwarding */ 57 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 58 59 /* Enable IMP port in dumb mode */ 60 reg = core_readl(priv, CORE_SWITCH_CTRL); 61 reg |= MII_DUMB_FWDG_EN; 62 core_writel(priv, reg, CORE_SWITCH_CTRL); 63 64 /* Configure Traffic Class to QoS mapping, allow each priority to map 65 * to a different queue number 66 */ 67 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 68 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 69 reg |= i << (PRT_TO_QID_SHIFT * i); 70 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 71 72 b53_brcm_hdr_setup(ds, port); 73 74 /* Force link status for IMP port */ 75 reg = core_readl(priv, offset); 76 reg |= (MII_SW_OR | LINK_STS); 77 core_writel(priv, reg, offset); 78 } 79 80 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 81 { 82 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 83 u32 reg; 84 85 reg = reg_readl(priv, REG_SPHY_CNTRL); 86 if (enable) { 87 reg |= PHY_RESET; 88 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 89 reg_writel(priv, reg, REG_SPHY_CNTRL); 90 udelay(21); 91 reg = reg_readl(priv, REG_SPHY_CNTRL); 92 reg &= ~PHY_RESET; 93 } else { 94 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 95 reg_writel(priv, reg, REG_SPHY_CNTRL); 96 mdelay(1); 97 reg |= CK25_DIS; 98 } 99 reg_writel(priv, reg, REG_SPHY_CNTRL); 100 101 /* Use PHY-driven LED signaling */ 102 if (!enable) { 103 reg = reg_readl(priv, REG_LED_CNTRL(0)); 104 reg |= SPDLNK_SRC_SEL; 105 reg_writel(priv, reg, REG_LED_CNTRL(0)); 106 } 107 } 108 109 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 110 int port) 111 { 112 unsigned int off; 113 114 switch (port) { 115 case 7: 116 off = P7_IRQ_OFF; 117 break; 118 case 0: 119 /* Port 0 interrupts are located on the first bank */ 120 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 121 return; 122 default: 123 off = P_IRQ_OFF(port); 124 break; 125 } 126 127 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 128 } 129 130 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 131 int port) 132 { 133 unsigned int off; 134 135 switch (port) { 136 case 7: 137 off = P7_IRQ_OFF; 138 break; 139 case 0: 140 /* Port 0 interrupts are located on the first bank */ 141 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 142 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 143 return; 144 default: 145 off = P_IRQ_OFF(port); 146 break; 147 } 148 149 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 150 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 151 } 152 153 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 154 struct phy_device *phy) 155 { 156 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 157 unsigned int i; 158 u32 reg; 159 160 /* Clear the memory power down */ 161 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 162 reg &= ~P_TXQ_PSM_VDD(port); 163 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 164 165 /* Enable learning */ 166 reg = core_readl(priv, CORE_DIS_LEARN); 167 reg &= ~BIT(port); 168 core_writel(priv, reg, CORE_DIS_LEARN); 169 170 /* Enable Broadcom tags for that port if requested */ 171 if (priv->brcm_tag_mask & BIT(port)) 172 b53_brcm_hdr_setup(ds, port); 173 174 /* Configure Traffic Class to QoS mapping, allow each priority to map 175 * to a different queue number 176 */ 177 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 178 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 179 reg |= i << (PRT_TO_QID_SHIFT * i); 180 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 181 182 /* Re-enable the GPHY and re-apply workarounds */ 183 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 184 bcm_sf2_gphy_enable_set(ds, true); 185 if (phy) { 186 /* if phy_stop() has been called before, phy 187 * will be in halted state, and phy_start() 188 * will call resume. 189 * 190 * the resume path does not configure back 191 * autoneg settings, and since we hard reset 192 * the phy manually here, we need to reset the 193 * state machine also. 194 */ 195 phy->state = PHY_READY; 196 phy_init_hw(phy); 197 } 198 } 199 200 /* Enable MoCA port interrupts to get notified */ 201 if (port == priv->moca_port) 202 bcm_sf2_port_intr_enable(priv, port); 203 204 /* Set per-queue pause threshold to 32 */ 205 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 206 207 /* Set ACB threshold to 24 */ 208 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 209 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 210 SF2_NUM_EGRESS_QUEUES + i)); 211 reg &= ~XOFF_THRESHOLD_MASK; 212 reg |= 24; 213 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 214 SF2_NUM_EGRESS_QUEUES + i)); 215 } 216 217 return b53_enable_port(ds, port, phy); 218 } 219 220 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 221 { 222 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 223 u32 reg; 224 225 /* Disable learning while in WoL mode */ 226 if (priv->wol_ports_mask & (1 << port)) { 227 reg = core_readl(priv, CORE_DIS_LEARN); 228 reg |= BIT(port); 229 core_writel(priv, reg, CORE_DIS_LEARN); 230 return; 231 } 232 233 if (port == priv->moca_port) 234 bcm_sf2_port_intr_disable(priv, port); 235 236 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 237 bcm_sf2_gphy_enable_set(ds, false); 238 239 b53_disable_port(ds, port); 240 241 /* Power down the port memory */ 242 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 243 reg |= P_TXQ_PSM_VDD(port); 244 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 245 } 246 247 248 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 249 int regnum, u16 val) 250 { 251 int ret = 0; 252 u32 reg; 253 254 reg = reg_readl(priv, REG_SWITCH_CNTRL); 255 reg |= MDIO_MASTER_SEL; 256 reg_writel(priv, reg, REG_SWITCH_CNTRL); 257 258 /* Page << 8 | offset */ 259 reg = 0x70; 260 reg <<= 2; 261 core_writel(priv, addr, reg); 262 263 /* Page << 8 | offset */ 264 reg = 0x80 << 8 | regnum << 1; 265 reg <<= 2; 266 267 if (op) 268 ret = core_readl(priv, reg); 269 else 270 core_writel(priv, val, reg); 271 272 reg = reg_readl(priv, REG_SWITCH_CNTRL); 273 reg &= ~MDIO_MASTER_SEL; 274 reg_writel(priv, reg, REG_SWITCH_CNTRL); 275 276 return ret & 0xffff; 277 } 278 279 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 280 { 281 struct bcm_sf2_priv *priv = bus->priv; 282 283 /* Intercept reads from Broadcom pseudo-PHY address, else, send 284 * them to our master MDIO bus controller 285 */ 286 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 287 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 288 else 289 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 290 } 291 292 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 293 u16 val) 294 { 295 struct bcm_sf2_priv *priv = bus->priv; 296 297 /* Intercept writes to the Broadcom pseudo-PHY address, else, 298 * send them to our master MDIO bus controller 299 */ 300 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 301 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 302 else 303 return mdiobus_write_nested(priv->master_mii_bus, addr, 304 regnum, val); 305 } 306 307 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 308 { 309 struct dsa_switch *ds = dev_id; 310 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 311 312 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 313 ~priv->irq0_mask; 314 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 315 316 return IRQ_HANDLED; 317 } 318 319 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 320 { 321 struct dsa_switch *ds = dev_id; 322 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 323 324 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 325 ~priv->irq1_mask; 326 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 327 328 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 329 priv->port_sts[7].link = true; 330 dsa_port_phylink_mac_change(ds, 7, true); 331 } 332 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 333 priv->port_sts[7].link = false; 334 dsa_port_phylink_mac_change(ds, 7, false); 335 } 336 337 return IRQ_HANDLED; 338 } 339 340 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 341 { 342 unsigned int timeout = 1000; 343 u32 reg; 344 345 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 346 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 347 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 348 349 do { 350 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 351 if (!(reg & SOFTWARE_RESET)) 352 break; 353 354 usleep_range(1000, 2000); 355 } while (timeout-- > 0); 356 357 if (timeout == 0) 358 return -ETIMEDOUT; 359 360 return 0; 361 } 362 363 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 364 { 365 intrl2_0_mask_set(priv, 0xffffffff); 366 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 367 intrl2_1_mask_set(priv, 0xffffffff); 368 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 369 } 370 371 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 372 struct device_node *dn) 373 { 374 struct device_node *port; 375 int mode; 376 unsigned int port_num; 377 378 priv->moca_port = -1; 379 380 for_each_available_child_of_node(dn, port) { 381 if (of_property_read_u32(port, "reg", &port_num)) 382 continue; 383 384 /* Internal PHYs get assigned a specific 'phy-mode' property 385 * value: "internal" to help flag them before MDIO probing 386 * has completed, since they might be turned off at that 387 * time 388 */ 389 mode = of_get_phy_mode(port); 390 if (mode < 0) 391 continue; 392 393 if (mode == PHY_INTERFACE_MODE_INTERNAL) 394 priv->int_phy_mask |= 1 << port_num; 395 396 if (mode == PHY_INTERFACE_MODE_MOCA) 397 priv->moca_port = port_num; 398 399 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 400 priv->brcm_tag_mask |= 1 << port_num; 401 } 402 } 403 404 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 405 { 406 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 407 struct device_node *dn; 408 static int index; 409 int err; 410 411 /* Find our integrated MDIO bus node */ 412 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 413 priv->master_mii_bus = of_mdio_find_bus(dn); 414 if (!priv->master_mii_bus) 415 return -EPROBE_DEFER; 416 417 get_device(&priv->master_mii_bus->dev); 418 priv->master_mii_dn = dn; 419 420 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 421 if (!priv->slave_mii_bus) 422 return -ENOMEM; 423 424 priv->slave_mii_bus->priv = priv; 425 priv->slave_mii_bus->name = "sf2 slave mii"; 426 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 427 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 428 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 429 index++); 430 priv->slave_mii_bus->dev.of_node = dn; 431 432 /* Include the pseudo-PHY address to divert reads towards our 433 * workaround. This is only required for 7445D0, since 7445E0 434 * disconnects the internal switch pseudo-PHY such that we can use the 435 * regular SWITCH_MDIO master controller instead. 436 * 437 * Here we flag the pseudo PHY as needing special treatment and would 438 * otherwise make all other PHY read/writes go to the master MDIO bus 439 * controller that comes with this switch backed by the "mdio-unimac" 440 * driver. 441 */ 442 if (of_machine_is_compatible("brcm,bcm7445d0")) 443 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 444 else 445 priv->indir_phy_mask = 0; 446 447 ds->phys_mii_mask = priv->indir_phy_mask; 448 ds->slave_mii_bus = priv->slave_mii_bus; 449 priv->slave_mii_bus->parent = ds->dev->parent; 450 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 451 452 err = of_mdiobus_register(priv->slave_mii_bus, dn); 453 if (err && dn) 454 of_node_put(dn); 455 456 return err; 457 } 458 459 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 460 { 461 mdiobus_unregister(priv->slave_mii_bus); 462 of_node_put(priv->master_mii_dn); 463 } 464 465 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 466 { 467 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 468 469 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 470 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 471 * the REG_PHY_REVISION register layout is. 472 */ 473 474 return priv->hw_params.gphy_rev; 475 } 476 477 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 478 unsigned long *supported, 479 struct phylink_link_state *state) 480 { 481 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 482 483 if (!phy_interface_mode_is_rgmii(state->interface) && 484 state->interface != PHY_INTERFACE_MODE_MII && 485 state->interface != PHY_INTERFACE_MODE_REVMII && 486 state->interface != PHY_INTERFACE_MODE_GMII && 487 state->interface != PHY_INTERFACE_MODE_INTERNAL && 488 state->interface != PHY_INTERFACE_MODE_MOCA) { 489 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 490 dev_err(ds->dev, 491 "Unsupported interface: %d\n", state->interface); 492 return; 493 } 494 495 /* Allow all the expected bits */ 496 phylink_set(mask, Autoneg); 497 phylink_set_port_modes(mask); 498 phylink_set(mask, Pause); 499 phylink_set(mask, Asym_Pause); 500 501 /* With the exclusion of MII and Reverse MII, we support Gigabit, 502 * including Half duplex 503 */ 504 if (state->interface != PHY_INTERFACE_MODE_MII && 505 state->interface != PHY_INTERFACE_MODE_REVMII) { 506 phylink_set(mask, 1000baseT_Full); 507 phylink_set(mask, 1000baseT_Half); 508 } 509 510 phylink_set(mask, 10baseT_Half); 511 phylink_set(mask, 10baseT_Full); 512 phylink_set(mask, 100baseT_Half); 513 phylink_set(mask, 100baseT_Full); 514 515 bitmap_and(supported, supported, mask, 516 __ETHTOOL_LINK_MODE_MASK_NBITS); 517 bitmap_and(state->advertising, state->advertising, mask, 518 __ETHTOOL_LINK_MODE_MASK_NBITS); 519 } 520 521 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 522 unsigned int mode, 523 const struct phylink_link_state *state) 524 { 525 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 526 u32 id_mode_dis = 0, port_mode; 527 u32 reg, offset; 528 529 if (priv->type == BCM7445_DEVICE_ID) 530 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 531 else 532 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 533 534 switch (state->interface) { 535 case PHY_INTERFACE_MODE_RGMII: 536 id_mode_dis = 1; 537 /* fallthrough */ 538 case PHY_INTERFACE_MODE_RGMII_TXID: 539 port_mode = EXT_GPHY; 540 break; 541 case PHY_INTERFACE_MODE_MII: 542 port_mode = EXT_EPHY; 543 break; 544 case PHY_INTERFACE_MODE_REVMII: 545 port_mode = EXT_REVMII; 546 break; 547 default: 548 /* all other PHYs: internal and MoCA */ 549 goto force_link; 550 } 551 552 /* Clear id_mode_dis bit, and the existing port mode, let 553 * RGMII_MODE_EN bet set by mac_link_{up,down} 554 */ 555 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 556 reg &= ~ID_MODE_DIS; 557 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 558 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 559 560 reg |= port_mode; 561 if (id_mode_dis) 562 reg |= ID_MODE_DIS; 563 564 if (state->pause & MLO_PAUSE_TXRX_MASK) { 565 if (state->pause & MLO_PAUSE_TX) 566 reg |= TX_PAUSE_EN; 567 reg |= RX_PAUSE_EN; 568 } 569 570 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 571 572 force_link: 573 /* Force link settings detected from the PHY */ 574 reg = SW_OVERRIDE; 575 switch (state->speed) { 576 case SPEED_1000: 577 reg |= SPDSTS_1000 << SPEED_SHIFT; 578 break; 579 case SPEED_100: 580 reg |= SPDSTS_100 << SPEED_SHIFT; 581 break; 582 } 583 584 if (state->link) 585 reg |= LINK_STS; 586 if (state->duplex == DUPLEX_FULL) 587 reg |= DUPLX_MODE; 588 589 core_writel(priv, reg, offset); 590 } 591 592 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 593 phy_interface_t interface, bool link) 594 { 595 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 596 u32 reg; 597 598 if (!phy_interface_mode_is_rgmii(interface) && 599 interface != PHY_INTERFACE_MODE_MII && 600 interface != PHY_INTERFACE_MODE_REVMII) 601 return; 602 603 /* If the link is down, just disable the interface to conserve power */ 604 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 605 if (link) 606 reg |= RGMII_MODE_EN; 607 else 608 reg &= ~RGMII_MODE_EN; 609 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 610 } 611 612 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 613 unsigned int mode, 614 phy_interface_t interface) 615 { 616 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 617 } 618 619 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 620 unsigned int mode, 621 phy_interface_t interface, 622 struct phy_device *phydev) 623 { 624 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 625 struct ethtool_eee *p = &priv->dev->ports[port].eee; 626 627 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 628 629 if (mode == MLO_AN_PHY && phydev) 630 p->eee_enabled = b53_eee_init(ds, port, phydev); 631 } 632 633 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 634 struct phylink_link_state *status) 635 { 636 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 637 638 status->link = false; 639 640 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 641 * which means that we need to force the link at the port override 642 * level to get the data to flow. We do use what the interrupt handler 643 * did determine before. 644 * 645 * For the other ports, we just force the link status, since this is 646 * a fixed PHY device. 647 */ 648 if (port == priv->moca_port) { 649 status->link = priv->port_sts[port].link; 650 /* For MoCA interfaces, also force a link down notification 651 * since some version of the user-space daemon (mocad) use 652 * cmd->autoneg to force the link, which messes up the PHY 653 * state machine and make it go in PHY_FORCING state instead. 654 */ 655 if (!status->link) 656 netif_carrier_off(ds->ports[port].slave); 657 status->duplex = DUPLEX_FULL; 658 } else { 659 status->link = true; 660 } 661 } 662 663 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 664 { 665 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 666 u32 reg; 667 668 /* Enable ACB globally */ 669 reg = acb_readl(priv, ACB_CONTROL); 670 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 671 acb_writel(priv, reg, ACB_CONTROL); 672 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 673 reg |= ACB_EN | ACB_ALGORITHM; 674 acb_writel(priv, reg, ACB_CONTROL); 675 } 676 677 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 678 { 679 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 680 unsigned int port; 681 682 bcm_sf2_intr_disable(priv); 683 684 /* Disable all ports physically present including the IMP 685 * port, the other ones have already been disabled during 686 * bcm_sf2_sw_setup 687 */ 688 for (port = 0; port < ds->num_ports; port++) { 689 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 690 bcm_sf2_port_disable(ds, port); 691 } 692 693 return 0; 694 } 695 696 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 697 { 698 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 699 int ret; 700 701 ret = bcm_sf2_sw_rst(priv); 702 if (ret) { 703 pr_err("%s: failed to software reset switch\n", __func__); 704 return ret; 705 } 706 707 ret = bcm_sf2_cfp_resume(ds); 708 if (ret) 709 return ret; 710 711 if (priv->hw_params.num_gphy == 1) 712 bcm_sf2_gphy_enable_set(ds, true); 713 714 ds->ops->setup(ds); 715 716 return 0; 717 } 718 719 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 720 struct ethtool_wolinfo *wol) 721 { 722 struct net_device *p = ds->ports[port].cpu_dp->master; 723 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 724 struct ethtool_wolinfo pwol = { }; 725 726 /* Get the parent device WoL settings */ 727 if (p->ethtool_ops->get_wol) 728 p->ethtool_ops->get_wol(p, &pwol); 729 730 /* Advertise the parent device supported settings */ 731 wol->supported = pwol.supported; 732 memset(&wol->sopass, 0, sizeof(wol->sopass)); 733 734 if (pwol.wolopts & WAKE_MAGICSECURE) 735 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 736 737 if (priv->wol_ports_mask & (1 << port)) 738 wol->wolopts = pwol.wolopts; 739 else 740 wol->wolopts = 0; 741 } 742 743 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 744 struct ethtool_wolinfo *wol) 745 { 746 struct net_device *p = ds->ports[port].cpu_dp->master; 747 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 748 s8 cpu_port = ds->ports[port].cpu_dp->index; 749 struct ethtool_wolinfo pwol = { }; 750 751 if (p->ethtool_ops->get_wol) 752 p->ethtool_ops->get_wol(p, &pwol); 753 if (wol->wolopts & ~pwol.supported) 754 return -EINVAL; 755 756 if (wol->wolopts) 757 priv->wol_ports_mask |= (1 << port); 758 else 759 priv->wol_ports_mask &= ~(1 << port); 760 761 /* If we have at least one port enabled, make sure the CPU port 762 * is also enabled. If the CPU port is the last one enabled, we disable 763 * it since this configuration does not make sense. 764 */ 765 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 766 priv->wol_ports_mask |= (1 << cpu_port); 767 else 768 priv->wol_ports_mask &= ~(1 << cpu_port); 769 770 return p->ethtool_ops->set_wol(p, wol); 771 } 772 773 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 774 { 775 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 776 unsigned int port; 777 778 /* Enable all valid ports and disable those unused */ 779 for (port = 0; port < priv->hw_params.num_ports; port++) { 780 /* IMP port receives special treatment */ 781 if (dsa_is_user_port(ds, port)) 782 bcm_sf2_port_setup(ds, port, NULL); 783 else if (dsa_is_cpu_port(ds, port)) 784 bcm_sf2_imp_setup(ds, port); 785 else 786 bcm_sf2_port_disable(ds, port); 787 } 788 789 b53_configure_vlan(ds); 790 bcm_sf2_enable_acb(ds); 791 792 return 0; 793 } 794 795 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 796 * register basis so we need to translate that into an address that the 797 * bus-glue understands. 798 */ 799 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 800 801 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 802 u8 *val) 803 { 804 struct bcm_sf2_priv *priv = dev->priv; 805 806 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 807 808 return 0; 809 } 810 811 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 812 u16 *val) 813 { 814 struct bcm_sf2_priv *priv = dev->priv; 815 816 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 817 818 return 0; 819 } 820 821 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 822 u32 *val) 823 { 824 struct bcm_sf2_priv *priv = dev->priv; 825 826 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 827 828 return 0; 829 } 830 831 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 832 u64 *val) 833 { 834 struct bcm_sf2_priv *priv = dev->priv; 835 836 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 837 838 return 0; 839 } 840 841 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 842 u8 value) 843 { 844 struct bcm_sf2_priv *priv = dev->priv; 845 846 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 847 848 return 0; 849 } 850 851 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 852 u16 value) 853 { 854 struct bcm_sf2_priv *priv = dev->priv; 855 856 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 857 858 return 0; 859 } 860 861 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 862 u32 value) 863 { 864 struct bcm_sf2_priv *priv = dev->priv; 865 866 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 867 868 return 0; 869 } 870 871 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 872 u64 value) 873 { 874 struct bcm_sf2_priv *priv = dev->priv; 875 876 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 877 878 return 0; 879 } 880 881 static const struct b53_io_ops bcm_sf2_io_ops = { 882 .read8 = bcm_sf2_core_read8, 883 .read16 = bcm_sf2_core_read16, 884 .read32 = bcm_sf2_core_read32, 885 .read48 = bcm_sf2_core_read64, 886 .read64 = bcm_sf2_core_read64, 887 .write8 = bcm_sf2_core_write8, 888 .write16 = bcm_sf2_core_write16, 889 .write32 = bcm_sf2_core_write32, 890 .write48 = bcm_sf2_core_write64, 891 .write64 = bcm_sf2_core_write64, 892 }; 893 894 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 895 u32 stringset, uint8_t *data) 896 { 897 int cnt = b53_get_sset_count(ds, port, stringset); 898 899 b53_get_strings(ds, port, stringset, data); 900 bcm_sf2_cfp_get_strings(ds, port, stringset, 901 data + cnt * ETH_GSTRING_LEN); 902 } 903 904 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 905 uint64_t *data) 906 { 907 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 908 909 b53_get_ethtool_stats(ds, port, data); 910 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 911 } 912 913 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 914 int sset) 915 { 916 int cnt = b53_get_sset_count(ds, port, sset); 917 918 if (cnt < 0) 919 return cnt; 920 921 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 922 923 return cnt; 924 } 925 926 static const struct dsa_switch_ops bcm_sf2_ops = { 927 .get_tag_protocol = b53_get_tag_protocol, 928 .setup = bcm_sf2_sw_setup, 929 .get_strings = bcm_sf2_sw_get_strings, 930 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 931 .get_sset_count = bcm_sf2_sw_get_sset_count, 932 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 933 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 934 .phylink_validate = bcm_sf2_sw_validate, 935 .phylink_mac_config = bcm_sf2_sw_mac_config, 936 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 937 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 938 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 939 .suspend = bcm_sf2_sw_suspend, 940 .resume = bcm_sf2_sw_resume, 941 .get_wol = bcm_sf2_sw_get_wol, 942 .set_wol = bcm_sf2_sw_set_wol, 943 .port_enable = bcm_sf2_port_setup, 944 .port_disable = bcm_sf2_port_disable, 945 .get_mac_eee = b53_get_mac_eee, 946 .set_mac_eee = b53_set_mac_eee, 947 .port_bridge_join = b53_br_join, 948 .port_bridge_leave = b53_br_leave, 949 .port_stp_state_set = b53_br_set_stp_state, 950 .port_fast_age = b53_br_fast_age, 951 .port_vlan_filtering = b53_vlan_filtering, 952 .port_vlan_prepare = b53_vlan_prepare, 953 .port_vlan_add = b53_vlan_add, 954 .port_vlan_del = b53_vlan_del, 955 .port_fdb_dump = b53_fdb_dump, 956 .port_fdb_add = b53_fdb_add, 957 .port_fdb_del = b53_fdb_del, 958 .get_rxnfc = bcm_sf2_get_rxnfc, 959 .set_rxnfc = bcm_sf2_set_rxnfc, 960 .port_mirror_add = b53_mirror_add, 961 .port_mirror_del = b53_mirror_del, 962 }; 963 964 struct bcm_sf2_of_data { 965 u32 type; 966 const u16 *reg_offsets; 967 unsigned int core_reg_align; 968 unsigned int num_cfp_rules; 969 }; 970 971 /* Register offsets for the SWITCH_REG_* block */ 972 static const u16 bcm_sf2_7445_reg_offsets[] = { 973 [REG_SWITCH_CNTRL] = 0x00, 974 [REG_SWITCH_STATUS] = 0x04, 975 [REG_DIR_DATA_WRITE] = 0x08, 976 [REG_DIR_DATA_READ] = 0x0C, 977 [REG_SWITCH_REVISION] = 0x18, 978 [REG_PHY_REVISION] = 0x1C, 979 [REG_SPHY_CNTRL] = 0x2C, 980 [REG_RGMII_0_CNTRL] = 0x34, 981 [REG_RGMII_1_CNTRL] = 0x40, 982 [REG_RGMII_2_CNTRL] = 0x4c, 983 [REG_LED_0_CNTRL] = 0x90, 984 [REG_LED_1_CNTRL] = 0x94, 985 [REG_LED_2_CNTRL] = 0x98, 986 }; 987 988 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 989 .type = BCM7445_DEVICE_ID, 990 .core_reg_align = 0, 991 .reg_offsets = bcm_sf2_7445_reg_offsets, 992 .num_cfp_rules = 256, 993 }; 994 995 static const u16 bcm_sf2_7278_reg_offsets[] = { 996 [REG_SWITCH_CNTRL] = 0x00, 997 [REG_SWITCH_STATUS] = 0x04, 998 [REG_DIR_DATA_WRITE] = 0x08, 999 [REG_DIR_DATA_READ] = 0x0c, 1000 [REG_SWITCH_REVISION] = 0x10, 1001 [REG_PHY_REVISION] = 0x14, 1002 [REG_SPHY_CNTRL] = 0x24, 1003 [REG_RGMII_0_CNTRL] = 0xe0, 1004 [REG_RGMII_1_CNTRL] = 0xec, 1005 [REG_RGMII_2_CNTRL] = 0xf8, 1006 [REG_LED_0_CNTRL] = 0x40, 1007 [REG_LED_1_CNTRL] = 0x4c, 1008 [REG_LED_2_CNTRL] = 0x58, 1009 }; 1010 1011 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1012 .type = BCM7278_DEVICE_ID, 1013 .core_reg_align = 1, 1014 .reg_offsets = bcm_sf2_7278_reg_offsets, 1015 .num_cfp_rules = 128, 1016 }; 1017 1018 static const struct of_device_id bcm_sf2_of_match[] = { 1019 { .compatible = "brcm,bcm7445-switch-v4.0", 1020 .data = &bcm_sf2_7445_data 1021 }, 1022 { .compatible = "brcm,bcm7278-switch-v4.0", 1023 .data = &bcm_sf2_7278_data 1024 }, 1025 { .compatible = "brcm,bcm7278-switch-v4.8", 1026 .data = &bcm_sf2_7278_data 1027 }, 1028 { /* sentinel */ }, 1029 }; 1030 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1031 1032 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1033 { 1034 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1035 struct device_node *dn = pdev->dev.of_node; 1036 const struct of_device_id *of_id = NULL; 1037 const struct bcm_sf2_of_data *data; 1038 struct b53_platform_data *pdata; 1039 struct dsa_switch_ops *ops; 1040 struct bcm_sf2_priv *priv; 1041 struct b53_device *dev; 1042 struct dsa_switch *ds; 1043 void __iomem **base; 1044 struct resource *r; 1045 unsigned int i; 1046 u32 reg, rev; 1047 int ret; 1048 1049 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1050 if (!priv) 1051 return -ENOMEM; 1052 1053 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1054 if (!ops) 1055 return -ENOMEM; 1056 1057 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1058 if (!dev) 1059 return -ENOMEM; 1060 1061 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1062 if (!pdata) 1063 return -ENOMEM; 1064 1065 of_id = of_match_node(bcm_sf2_of_match, dn); 1066 if (!of_id || !of_id->data) 1067 return -EINVAL; 1068 1069 data = of_id->data; 1070 1071 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1072 priv->type = data->type; 1073 priv->reg_offsets = data->reg_offsets; 1074 priv->core_reg_align = data->core_reg_align; 1075 priv->num_cfp_rules = data->num_cfp_rules; 1076 1077 /* Auto-detection using standard registers will not work, so 1078 * provide an indication of what kind of device we are for 1079 * b53_common to work with 1080 */ 1081 pdata->chip_id = priv->type; 1082 dev->pdata = pdata; 1083 1084 priv->dev = dev; 1085 ds = dev->ds; 1086 ds->ops = &bcm_sf2_ops; 1087 1088 /* Advertise the 8 egress queues */ 1089 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1090 1091 dev_set_drvdata(&pdev->dev, priv); 1092 1093 spin_lock_init(&priv->indir_lock); 1094 mutex_init(&priv->cfp.lock); 1095 INIT_LIST_HEAD(&priv->cfp.rules_list); 1096 1097 /* CFP rule #0 cannot be used for specific classifications, flag it as 1098 * permanently used 1099 */ 1100 set_bit(0, priv->cfp.used); 1101 set_bit(0, priv->cfp.unique); 1102 1103 bcm_sf2_identify_ports(priv, dn->child); 1104 1105 priv->irq0 = irq_of_parse_and_map(dn, 0); 1106 priv->irq1 = irq_of_parse_and_map(dn, 1); 1107 1108 base = &priv->core; 1109 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1110 r = platform_get_resource(pdev, IORESOURCE_MEM, i); 1111 *base = devm_ioremap_resource(&pdev->dev, r); 1112 if (IS_ERR(*base)) { 1113 pr_err("unable to find register: %s\n", reg_names[i]); 1114 return PTR_ERR(*base); 1115 } 1116 base++; 1117 } 1118 1119 ret = bcm_sf2_sw_rst(priv); 1120 if (ret) { 1121 pr_err("unable to software reset switch: %d\n", ret); 1122 return ret; 1123 } 1124 1125 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1126 1127 ret = bcm_sf2_mdio_register(ds); 1128 if (ret) { 1129 pr_err("failed to register MDIO bus\n"); 1130 return ret; 1131 } 1132 1133 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1134 1135 ret = bcm_sf2_cfp_rst(priv); 1136 if (ret) { 1137 pr_err("failed to reset CFP\n"); 1138 goto out_mdio; 1139 } 1140 1141 /* Disable all interrupts and request them */ 1142 bcm_sf2_intr_disable(priv); 1143 1144 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1145 "switch_0", ds); 1146 if (ret < 0) { 1147 pr_err("failed to request switch_0 IRQ\n"); 1148 goto out_mdio; 1149 } 1150 1151 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1152 "switch_1", ds); 1153 if (ret < 0) { 1154 pr_err("failed to request switch_1 IRQ\n"); 1155 goto out_mdio; 1156 } 1157 1158 /* Reset the MIB counters */ 1159 reg = core_readl(priv, CORE_GMNCFGCFG); 1160 reg |= RST_MIB_CNT; 1161 core_writel(priv, reg, CORE_GMNCFGCFG); 1162 reg &= ~RST_MIB_CNT; 1163 core_writel(priv, reg, CORE_GMNCFGCFG); 1164 1165 /* Get the maximum number of ports for this switch */ 1166 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1167 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1168 priv->hw_params.num_ports = DSA_MAX_PORTS; 1169 1170 /* Assume a single GPHY setup if we can't read that property */ 1171 if (of_property_read_u32(dn, "brcm,num-gphy", 1172 &priv->hw_params.num_gphy)) 1173 priv->hw_params.num_gphy = 1; 1174 1175 rev = reg_readl(priv, REG_SWITCH_REVISION); 1176 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1177 SWITCH_TOP_REV_MASK; 1178 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1179 1180 rev = reg_readl(priv, REG_PHY_REVISION); 1181 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1182 1183 ret = b53_switch_register(dev); 1184 if (ret) 1185 goto out_mdio; 1186 1187 dev_info(&pdev->dev, 1188 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1189 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1190 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1191 priv->irq0, priv->irq1); 1192 1193 return 0; 1194 1195 out_mdio: 1196 bcm_sf2_mdio_unregister(priv); 1197 return ret; 1198 } 1199 1200 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1201 { 1202 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1203 1204 priv->wol_ports_mask = 0; 1205 dsa_unregister_switch(priv->dev->ds); 1206 bcm_sf2_cfp_exit(priv->dev->ds); 1207 /* Disable all ports and interrupts */ 1208 bcm_sf2_sw_suspend(priv->dev->ds); 1209 bcm_sf2_mdio_unregister(priv); 1210 1211 return 0; 1212 } 1213 1214 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1215 { 1216 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1217 1218 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1219 * successful MDIO bus scan to occur. If we did turn off the GPHY 1220 * before (e.g: port_disable), this will also power it back on. 1221 * 1222 * Do not rely on kexec_in_progress, just power the PHY on. 1223 */ 1224 if (priv->hw_params.num_gphy == 1) 1225 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1226 } 1227 1228 #ifdef CONFIG_PM_SLEEP 1229 static int bcm_sf2_suspend(struct device *dev) 1230 { 1231 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1232 1233 return dsa_switch_suspend(priv->dev->ds); 1234 } 1235 1236 static int bcm_sf2_resume(struct device *dev) 1237 { 1238 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1239 1240 return dsa_switch_resume(priv->dev->ds); 1241 } 1242 #endif /* CONFIG_PM_SLEEP */ 1243 1244 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1245 bcm_sf2_suspend, bcm_sf2_resume); 1246 1247 1248 static struct platform_driver bcm_sf2_driver = { 1249 .probe = bcm_sf2_sw_probe, 1250 .remove = bcm_sf2_sw_remove, 1251 .shutdown = bcm_sf2_sw_shutdown, 1252 .driver = { 1253 .name = "brcm-sf2", 1254 .of_match_table = bcm_sf2_of_match, 1255 .pm = &bcm_sf2_pm_ops, 1256 }, 1257 }; 1258 module_platform_driver(bcm_sf2_driver); 1259 1260 MODULE_AUTHOR("Broadcom Corporation"); 1261 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1262 MODULE_LICENSE("GPL"); 1263 MODULE_ALIAS("platform:brcm-sf2"); 1264