1 /* 2 * Broadcom Starfighter 2 DSA switch driver 3 * 4 * Copyright (C) 2014, Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/list.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/of.h> 18 #include <linux/phy.h> 19 #include <linux/phy_fixed.h> 20 #include <linux/mii.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_address.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <net/dsa.h> 27 #include <linux/ethtool.h> 28 #include <linux/if_bridge.h> 29 #include <linux/brcmphy.h> 30 #include <linux/etherdevice.h> 31 #include <linux/platform_data/b53.h> 32 33 #include "bcm_sf2.h" 34 #include "bcm_sf2_regs.h" 35 #include "b53/b53_priv.h" 36 #include "b53/b53_regs.h" 37 38 static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds) 39 { 40 return DSA_TAG_PROTO_BRCM; 41 } 42 43 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 44 { 45 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 46 unsigned int i; 47 u32 reg, offset; 48 49 if (priv->type == BCM7445_DEVICE_ID) 50 offset = CORE_STS_OVERRIDE_IMP; 51 else 52 offset = CORE_STS_OVERRIDE_IMP2; 53 54 /* Enable the port memories */ 55 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 56 reg &= ~P_TXQ_PSM_VDD(port); 57 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 58 59 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 60 reg = core_readl(priv, CORE_IMP_CTL); 61 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 62 reg &= ~(RX_DIS | TX_DIS); 63 core_writel(priv, reg, CORE_IMP_CTL); 64 65 /* Enable forwarding */ 66 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 67 68 /* Enable IMP port in dumb mode */ 69 reg = core_readl(priv, CORE_SWITCH_CTRL); 70 reg |= MII_DUMB_FWDG_EN; 71 core_writel(priv, reg, CORE_SWITCH_CTRL); 72 73 /* Configure Traffic Class to QoS mapping, allow each priority to map 74 * to a different queue number 75 */ 76 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 77 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 78 reg |= i << (PRT_TO_QID_SHIFT * i); 79 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 80 81 b53_brcm_hdr_setup(ds, port); 82 83 /* Force link status for IMP port */ 84 reg = core_readl(priv, offset); 85 reg |= (MII_SW_OR | LINK_STS); 86 core_writel(priv, reg, offset); 87 } 88 89 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 90 { 91 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 92 u32 reg; 93 94 reg = reg_readl(priv, REG_SPHY_CNTRL); 95 if (enable) { 96 reg |= PHY_RESET; 97 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS); 98 reg_writel(priv, reg, REG_SPHY_CNTRL); 99 udelay(21); 100 reg = reg_readl(priv, REG_SPHY_CNTRL); 101 reg &= ~PHY_RESET; 102 } else { 103 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 104 reg_writel(priv, reg, REG_SPHY_CNTRL); 105 mdelay(1); 106 reg |= CK25_DIS; 107 } 108 reg_writel(priv, reg, REG_SPHY_CNTRL); 109 110 /* Use PHY-driven LED signaling */ 111 if (!enable) { 112 reg = reg_readl(priv, REG_LED_CNTRL(0)); 113 reg |= SPDLNK_SRC_SEL; 114 reg_writel(priv, reg, REG_LED_CNTRL(0)); 115 } 116 } 117 118 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 119 int port) 120 { 121 unsigned int off; 122 123 switch (port) { 124 case 7: 125 off = P7_IRQ_OFF; 126 break; 127 case 0: 128 /* Port 0 interrupts are located on the first bank */ 129 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 130 return; 131 default: 132 off = P_IRQ_OFF(port); 133 break; 134 } 135 136 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 137 } 138 139 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 140 int port) 141 { 142 unsigned int off; 143 144 switch (port) { 145 case 7: 146 off = P7_IRQ_OFF; 147 break; 148 case 0: 149 /* Port 0 interrupts are located on the first bank */ 150 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 151 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 152 return; 153 default: 154 off = P_IRQ_OFF(port); 155 break; 156 } 157 158 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 159 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 160 } 161 162 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 163 struct phy_device *phy) 164 { 165 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 166 unsigned int i; 167 u32 reg; 168 169 /* Clear the memory power down */ 170 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 171 reg &= ~P_TXQ_PSM_VDD(port); 172 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 173 174 /* Enable Broadcom tags for that port if requested */ 175 if (priv->brcm_tag_mask & BIT(port)) 176 b53_brcm_hdr_setup(ds, port); 177 178 /* Configure Traffic Class to QoS mapping, allow each priority to map 179 * to a different queue number 180 */ 181 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 182 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 183 reg |= i << (PRT_TO_QID_SHIFT * i); 184 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 185 186 /* Re-enable the GPHY and re-apply workarounds */ 187 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 188 bcm_sf2_gphy_enable_set(ds, true); 189 if (phy) { 190 /* if phy_stop() has been called before, phy 191 * will be in halted state, and phy_start() 192 * will call resume. 193 * 194 * the resume path does not configure back 195 * autoneg settings, and since we hard reset 196 * the phy manually here, we need to reset the 197 * state machine also. 198 */ 199 phy->state = PHY_READY; 200 phy_init_hw(phy); 201 } 202 } 203 204 /* Enable MoCA port interrupts to get notified */ 205 if (port == priv->moca_port) 206 bcm_sf2_port_intr_enable(priv, port); 207 208 return b53_enable_port(ds, port, phy); 209 } 210 211 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port, 212 struct phy_device *phy) 213 { 214 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 215 u32 off, reg; 216 217 if (priv->wol_ports_mask & (1 << port)) 218 return; 219 220 if (port == priv->moca_port) 221 bcm_sf2_port_intr_disable(priv, port); 222 223 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 224 bcm_sf2_gphy_enable_set(ds, false); 225 226 if (dsa_is_cpu_port(ds, port)) 227 off = CORE_IMP_CTL; 228 else 229 off = CORE_G_PCTL_PORT(port); 230 231 b53_disable_port(ds, port, phy); 232 233 /* Power down the port memory */ 234 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 235 reg |= P_TXQ_PSM_VDD(port); 236 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 237 } 238 239 240 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 241 int regnum, u16 val) 242 { 243 int ret = 0; 244 u32 reg; 245 246 reg = reg_readl(priv, REG_SWITCH_CNTRL); 247 reg |= MDIO_MASTER_SEL; 248 reg_writel(priv, reg, REG_SWITCH_CNTRL); 249 250 /* Page << 8 | offset */ 251 reg = 0x70; 252 reg <<= 2; 253 core_writel(priv, addr, reg); 254 255 /* Page << 8 | offset */ 256 reg = 0x80 << 8 | regnum << 1; 257 reg <<= 2; 258 259 if (op) 260 ret = core_readl(priv, reg); 261 else 262 core_writel(priv, val, reg); 263 264 reg = reg_readl(priv, REG_SWITCH_CNTRL); 265 reg &= ~MDIO_MASTER_SEL; 266 reg_writel(priv, reg, REG_SWITCH_CNTRL); 267 268 return ret & 0xffff; 269 } 270 271 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 272 { 273 struct bcm_sf2_priv *priv = bus->priv; 274 275 /* Intercept reads from Broadcom pseudo-PHY address, else, send 276 * them to our master MDIO bus controller 277 */ 278 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 279 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 280 else 281 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 282 } 283 284 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 285 u16 val) 286 { 287 struct bcm_sf2_priv *priv = bus->priv; 288 289 /* Intercept writes to the Broadcom pseudo-PHY address, else, 290 * send them to our master MDIO bus controller 291 */ 292 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 293 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 294 else 295 mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val); 296 297 return 0; 298 } 299 300 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 301 { 302 struct bcm_sf2_priv *priv = dev_id; 303 304 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 305 ~priv->irq0_mask; 306 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 307 308 return IRQ_HANDLED; 309 } 310 311 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 312 { 313 struct bcm_sf2_priv *priv = dev_id; 314 315 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 316 ~priv->irq1_mask; 317 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 318 319 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) 320 priv->port_sts[7].link = 1; 321 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) 322 priv->port_sts[7].link = 0; 323 324 return IRQ_HANDLED; 325 } 326 327 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 328 { 329 unsigned int timeout = 1000; 330 u32 reg; 331 332 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 333 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 334 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 335 336 do { 337 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 338 if (!(reg & SOFTWARE_RESET)) 339 break; 340 341 usleep_range(1000, 2000); 342 } while (timeout-- > 0); 343 344 if (timeout == 0) 345 return -ETIMEDOUT; 346 347 return 0; 348 } 349 350 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 351 { 352 intrl2_0_mask_set(priv, 0xffffffff); 353 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 354 intrl2_1_mask_set(priv, 0xffffffff); 355 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 356 } 357 358 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 359 struct device_node *dn) 360 { 361 struct device_node *port; 362 int mode; 363 unsigned int port_num; 364 365 priv->moca_port = -1; 366 367 for_each_available_child_of_node(dn, port) { 368 if (of_property_read_u32(port, "reg", &port_num)) 369 continue; 370 371 /* Internal PHYs get assigned a specific 'phy-mode' property 372 * value: "internal" to help flag them before MDIO probing 373 * has completed, since they might be turned off at that 374 * time 375 */ 376 mode = of_get_phy_mode(port); 377 if (mode < 0) 378 continue; 379 380 if (mode == PHY_INTERFACE_MODE_INTERNAL) 381 priv->int_phy_mask |= 1 << port_num; 382 383 if (mode == PHY_INTERFACE_MODE_MOCA) 384 priv->moca_port = port_num; 385 386 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 387 priv->brcm_tag_mask |= 1 << port_num; 388 } 389 } 390 391 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 392 { 393 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 394 struct device_node *dn; 395 static int index; 396 int err; 397 398 /* Find our integrated MDIO bus node */ 399 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 400 priv->master_mii_bus = of_mdio_find_bus(dn); 401 if (!priv->master_mii_bus) 402 return -EPROBE_DEFER; 403 404 get_device(&priv->master_mii_bus->dev); 405 priv->master_mii_dn = dn; 406 407 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 408 if (!priv->slave_mii_bus) 409 return -ENOMEM; 410 411 priv->slave_mii_bus->priv = priv; 412 priv->slave_mii_bus->name = "sf2 slave mii"; 413 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 414 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 415 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 416 index++); 417 priv->slave_mii_bus->dev.of_node = dn; 418 419 /* Include the pseudo-PHY address to divert reads towards our 420 * workaround. This is only required for 7445D0, since 7445E0 421 * disconnects the internal switch pseudo-PHY such that we can use the 422 * regular SWITCH_MDIO master controller instead. 423 * 424 * Here we flag the pseudo PHY as needing special treatment and would 425 * otherwise make all other PHY read/writes go to the master MDIO bus 426 * controller that comes with this switch backed by the "mdio-unimac" 427 * driver. 428 */ 429 if (of_machine_is_compatible("brcm,bcm7445d0")) 430 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 431 else 432 priv->indir_phy_mask = 0; 433 434 ds->phys_mii_mask = priv->indir_phy_mask; 435 ds->slave_mii_bus = priv->slave_mii_bus; 436 priv->slave_mii_bus->parent = ds->dev->parent; 437 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 438 439 if (dn) 440 err = of_mdiobus_register(priv->slave_mii_bus, dn); 441 else 442 err = mdiobus_register(priv->slave_mii_bus); 443 444 if (err) 445 of_node_put(dn); 446 447 return err; 448 } 449 450 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 451 { 452 mdiobus_unregister(priv->slave_mii_bus); 453 if (priv->master_mii_dn) 454 of_node_put(priv->master_mii_dn); 455 } 456 457 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 458 { 459 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 460 461 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 462 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 463 * the REG_PHY_REVISION register layout is. 464 */ 465 466 return priv->hw_params.gphy_rev; 467 } 468 469 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port, 470 struct phy_device *phydev) 471 { 472 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 473 struct ethtool_eee *p = &priv->dev->ports[port].eee; 474 u32 id_mode_dis = 0, port_mode; 475 const char *str = NULL; 476 u32 reg, offset; 477 478 if (priv->type == BCM7445_DEVICE_ID) 479 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 480 else 481 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 482 483 switch (phydev->interface) { 484 case PHY_INTERFACE_MODE_RGMII: 485 str = "RGMII (no delay)"; 486 id_mode_dis = 1; 487 case PHY_INTERFACE_MODE_RGMII_TXID: 488 if (!str) 489 str = "RGMII (TX delay)"; 490 port_mode = EXT_GPHY; 491 break; 492 case PHY_INTERFACE_MODE_MII: 493 str = "MII"; 494 port_mode = EXT_EPHY; 495 break; 496 case PHY_INTERFACE_MODE_REVMII: 497 str = "Reverse MII"; 498 port_mode = EXT_REVMII; 499 break; 500 default: 501 /* All other PHYs: internal and MoCA */ 502 goto force_link; 503 } 504 505 /* If the link is down, just disable the interface to conserve power */ 506 if (!phydev->link) { 507 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 508 reg &= ~RGMII_MODE_EN; 509 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 510 goto force_link; 511 } 512 513 /* Clear id_mode_dis bit, and the existing port mode, but 514 * make sure we enable the RGMII block for data to pass 515 */ 516 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 517 reg &= ~ID_MODE_DIS; 518 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 519 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 520 521 reg |= port_mode | RGMII_MODE_EN; 522 if (id_mode_dis) 523 reg |= ID_MODE_DIS; 524 525 if (phydev->pause) { 526 if (phydev->asym_pause) 527 reg |= TX_PAUSE_EN; 528 reg |= RX_PAUSE_EN; 529 } 530 531 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 532 533 pr_info("Port %d configured for %s\n", port, str); 534 535 force_link: 536 /* Force link settings detected from the PHY */ 537 reg = SW_OVERRIDE; 538 switch (phydev->speed) { 539 case SPEED_1000: 540 reg |= SPDSTS_1000 << SPEED_SHIFT; 541 break; 542 case SPEED_100: 543 reg |= SPDSTS_100 << SPEED_SHIFT; 544 break; 545 } 546 547 if (phydev->link) 548 reg |= LINK_STS; 549 if (phydev->duplex == DUPLEX_FULL) 550 reg |= DUPLX_MODE; 551 552 core_writel(priv, reg, offset); 553 554 if (!phydev->is_pseudo_fixed_link) 555 p->eee_enabled = b53_eee_init(ds, port, phydev); 556 } 557 558 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port, 559 struct fixed_phy_status *status) 560 { 561 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 562 u32 duplex, pause, offset; 563 u32 reg; 564 565 if (priv->type == BCM7445_DEVICE_ID) 566 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 567 else 568 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 569 570 duplex = core_readl(priv, CORE_DUPSTS); 571 pause = core_readl(priv, CORE_PAUSESTS); 572 573 status->link = 0; 574 575 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 576 * which means that we need to force the link at the port override 577 * level to get the data to flow. We do use what the interrupt handler 578 * did determine before. 579 * 580 * For the other ports, we just force the link status, since this is 581 * a fixed PHY device. 582 */ 583 if (port == priv->moca_port) { 584 status->link = priv->port_sts[port].link; 585 /* For MoCA interfaces, also force a link down notification 586 * since some version of the user-space daemon (mocad) use 587 * cmd->autoneg to force the link, which messes up the PHY 588 * state machine and make it go in PHY_FORCING state instead. 589 */ 590 if (!status->link) 591 netif_carrier_off(ds->ports[port].netdev); 592 status->duplex = 1; 593 } else { 594 status->link = 1; 595 status->duplex = !!(duplex & (1 << port)); 596 } 597 598 reg = core_readl(priv, offset); 599 reg |= SW_OVERRIDE; 600 if (status->link) 601 reg |= LINK_STS; 602 else 603 reg &= ~LINK_STS; 604 core_writel(priv, reg, offset); 605 606 if ((pause & (1 << port)) && 607 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) { 608 status->asym_pause = 1; 609 status->pause = 1; 610 } 611 612 if (pause & (1 << port)) 613 status->pause = 1; 614 } 615 616 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 617 { 618 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 619 unsigned int port; 620 621 bcm_sf2_intr_disable(priv); 622 623 /* Disable all ports physically present including the IMP 624 * port, the other ones have already been disabled during 625 * bcm_sf2_sw_setup 626 */ 627 for (port = 0; port < DSA_MAX_PORTS; port++) { 628 if ((1 << port) & ds->enabled_port_mask || 629 dsa_is_cpu_port(ds, port)) 630 bcm_sf2_port_disable(ds, port, NULL); 631 } 632 633 return 0; 634 } 635 636 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 637 { 638 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 639 unsigned int port; 640 int ret; 641 642 ret = bcm_sf2_sw_rst(priv); 643 if (ret) { 644 pr_err("%s: failed to software reset switch\n", __func__); 645 return ret; 646 } 647 648 if (priv->hw_params.num_gphy == 1) 649 bcm_sf2_gphy_enable_set(ds, true); 650 651 for (port = 0; port < DSA_MAX_PORTS; port++) { 652 if ((1 << port) & ds->enabled_port_mask) 653 bcm_sf2_port_setup(ds, port, NULL); 654 else if (dsa_is_cpu_port(ds, port)) 655 bcm_sf2_imp_setup(ds, port); 656 } 657 658 return 0; 659 } 660 661 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 662 struct ethtool_wolinfo *wol) 663 { 664 struct net_device *p = ds->ports[port].cpu_dp->netdev; 665 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 666 struct ethtool_wolinfo pwol; 667 668 /* Get the parent device WoL settings */ 669 p->ethtool_ops->get_wol(p, &pwol); 670 671 /* Advertise the parent device supported settings */ 672 wol->supported = pwol.supported; 673 memset(&wol->sopass, 0, sizeof(wol->sopass)); 674 675 if (pwol.wolopts & WAKE_MAGICSECURE) 676 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 677 678 if (priv->wol_ports_mask & (1 << port)) 679 wol->wolopts = pwol.wolopts; 680 else 681 wol->wolopts = 0; 682 } 683 684 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 685 struct ethtool_wolinfo *wol) 686 { 687 struct net_device *p = ds->ports[port].cpu_dp->netdev; 688 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 689 s8 cpu_port = ds->ports[port].cpu_dp->index; 690 struct ethtool_wolinfo pwol; 691 692 p->ethtool_ops->get_wol(p, &pwol); 693 if (wol->wolopts & ~pwol.supported) 694 return -EINVAL; 695 696 if (wol->wolopts) 697 priv->wol_ports_mask |= (1 << port); 698 else 699 priv->wol_ports_mask &= ~(1 << port); 700 701 /* If we have at least one port enabled, make sure the CPU port 702 * is also enabled. If the CPU port is the last one enabled, we disable 703 * it since this configuration does not make sense. 704 */ 705 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 706 priv->wol_ports_mask |= (1 << cpu_port); 707 else 708 priv->wol_ports_mask &= ~(1 << cpu_port); 709 710 return p->ethtool_ops->set_wol(p, wol); 711 } 712 713 static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv) 714 { 715 unsigned int timeout = 10; 716 u32 reg; 717 718 do { 719 reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL); 720 if (!(reg & ARLA_VTBL_STDN)) 721 return 0; 722 723 usleep_range(1000, 2000); 724 } while (timeout--); 725 726 return -ETIMEDOUT; 727 } 728 729 static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op) 730 { 731 core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL); 732 733 return bcm_sf2_vlan_op_wait(priv); 734 } 735 736 static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds) 737 { 738 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 739 unsigned int port; 740 741 /* Clear all VLANs */ 742 bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR); 743 744 for (port = 0; port < priv->hw_params.num_ports; port++) { 745 if (!((1 << port) & ds->enabled_port_mask)) 746 continue; 747 748 core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port)); 749 } 750 } 751 752 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 753 { 754 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 755 unsigned int port; 756 757 /* Enable all valid ports and disable those unused */ 758 for (port = 0; port < priv->hw_params.num_ports; port++) { 759 /* IMP port receives special treatment */ 760 if ((1 << port) & ds->enabled_port_mask) 761 bcm_sf2_port_setup(ds, port, NULL); 762 else if (dsa_is_cpu_port(ds, port)) 763 bcm_sf2_imp_setup(ds, port); 764 else 765 bcm_sf2_port_disable(ds, port, NULL); 766 } 767 768 bcm_sf2_sw_configure_vlan(ds); 769 770 return 0; 771 } 772 773 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 774 * register basis so we need to translate that into an address that the 775 * bus-glue understands. 776 */ 777 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 778 779 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 780 u8 *val) 781 { 782 struct bcm_sf2_priv *priv = dev->priv; 783 784 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 785 786 return 0; 787 } 788 789 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 790 u16 *val) 791 { 792 struct bcm_sf2_priv *priv = dev->priv; 793 794 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 795 796 return 0; 797 } 798 799 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 800 u32 *val) 801 { 802 struct bcm_sf2_priv *priv = dev->priv; 803 804 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 805 806 return 0; 807 } 808 809 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 810 u64 *val) 811 { 812 struct bcm_sf2_priv *priv = dev->priv; 813 814 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 815 816 return 0; 817 } 818 819 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 820 u8 value) 821 { 822 struct bcm_sf2_priv *priv = dev->priv; 823 824 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 825 826 return 0; 827 } 828 829 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 830 u16 value) 831 { 832 struct bcm_sf2_priv *priv = dev->priv; 833 834 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 835 836 return 0; 837 } 838 839 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 840 u32 value) 841 { 842 struct bcm_sf2_priv *priv = dev->priv; 843 844 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 845 846 return 0; 847 } 848 849 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 850 u64 value) 851 { 852 struct bcm_sf2_priv *priv = dev->priv; 853 854 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 855 856 return 0; 857 } 858 859 static const struct b53_io_ops bcm_sf2_io_ops = { 860 .read8 = bcm_sf2_core_read8, 861 .read16 = bcm_sf2_core_read16, 862 .read32 = bcm_sf2_core_read32, 863 .read48 = bcm_sf2_core_read64, 864 .read64 = bcm_sf2_core_read64, 865 .write8 = bcm_sf2_core_write8, 866 .write16 = bcm_sf2_core_write16, 867 .write32 = bcm_sf2_core_write32, 868 .write48 = bcm_sf2_core_write64, 869 .write64 = bcm_sf2_core_write64, 870 }; 871 872 static const struct dsa_switch_ops bcm_sf2_ops = { 873 .get_tag_protocol = bcm_sf2_sw_get_tag_protocol, 874 .setup = bcm_sf2_sw_setup, 875 .get_strings = b53_get_strings, 876 .get_ethtool_stats = b53_get_ethtool_stats, 877 .get_sset_count = b53_get_sset_count, 878 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 879 .adjust_link = bcm_sf2_sw_adjust_link, 880 .fixed_link_update = bcm_sf2_sw_fixed_link_update, 881 .suspend = bcm_sf2_sw_suspend, 882 .resume = bcm_sf2_sw_resume, 883 .get_wol = bcm_sf2_sw_get_wol, 884 .set_wol = bcm_sf2_sw_set_wol, 885 .port_enable = bcm_sf2_port_setup, 886 .port_disable = bcm_sf2_port_disable, 887 .get_mac_eee = b53_get_mac_eee, 888 .set_mac_eee = b53_set_mac_eee, 889 .port_bridge_join = b53_br_join, 890 .port_bridge_leave = b53_br_leave, 891 .port_stp_state_set = b53_br_set_stp_state, 892 .port_fast_age = b53_br_fast_age, 893 .port_vlan_filtering = b53_vlan_filtering, 894 .port_vlan_prepare = b53_vlan_prepare, 895 .port_vlan_add = b53_vlan_add, 896 .port_vlan_del = b53_vlan_del, 897 .port_fdb_dump = b53_fdb_dump, 898 .port_fdb_add = b53_fdb_add, 899 .port_fdb_del = b53_fdb_del, 900 .get_rxnfc = bcm_sf2_get_rxnfc, 901 .set_rxnfc = bcm_sf2_set_rxnfc, 902 .port_mirror_add = b53_mirror_add, 903 .port_mirror_del = b53_mirror_del, 904 }; 905 906 struct bcm_sf2_of_data { 907 u32 type; 908 const u16 *reg_offsets; 909 unsigned int core_reg_align; 910 unsigned int num_cfp_rules; 911 }; 912 913 /* Register offsets for the SWITCH_REG_* block */ 914 static const u16 bcm_sf2_7445_reg_offsets[] = { 915 [REG_SWITCH_CNTRL] = 0x00, 916 [REG_SWITCH_STATUS] = 0x04, 917 [REG_DIR_DATA_WRITE] = 0x08, 918 [REG_DIR_DATA_READ] = 0x0C, 919 [REG_SWITCH_REVISION] = 0x18, 920 [REG_PHY_REVISION] = 0x1C, 921 [REG_SPHY_CNTRL] = 0x2C, 922 [REG_RGMII_0_CNTRL] = 0x34, 923 [REG_RGMII_1_CNTRL] = 0x40, 924 [REG_RGMII_2_CNTRL] = 0x4c, 925 [REG_LED_0_CNTRL] = 0x90, 926 [REG_LED_1_CNTRL] = 0x94, 927 [REG_LED_2_CNTRL] = 0x98, 928 }; 929 930 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 931 .type = BCM7445_DEVICE_ID, 932 .core_reg_align = 0, 933 .reg_offsets = bcm_sf2_7445_reg_offsets, 934 .num_cfp_rules = 256, 935 }; 936 937 static const u16 bcm_sf2_7278_reg_offsets[] = { 938 [REG_SWITCH_CNTRL] = 0x00, 939 [REG_SWITCH_STATUS] = 0x04, 940 [REG_DIR_DATA_WRITE] = 0x08, 941 [REG_DIR_DATA_READ] = 0x0c, 942 [REG_SWITCH_REVISION] = 0x10, 943 [REG_PHY_REVISION] = 0x14, 944 [REG_SPHY_CNTRL] = 0x24, 945 [REG_RGMII_0_CNTRL] = 0xe0, 946 [REG_RGMII_1_CNTRL] = 0xec, 947 [REG_RGMII_2_CNTRL] = 0xf8, 948 [REG_LED_0_CNTRL] = 0x40, 949 [REG_LED_1_CNTRL] = 0x4c, 950 [REG_LED_2_CNTRL] = 0x58, 951 }; 952 953 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 954 .type = BCM7278_DEVICE_ID, 955 .core_reg_align = 1, 956 .reg_offsets = bcm_sf2_7278_reg_offsets, 957 .num_cfp_rules = 128, 958 }; 959 960 static const struct of_device_id bcm_sf2_of_match[] = { 961 { .compatible = "brcm,bcm7445-switch-v4.0", 962 .data = &bcm_sf2_7445_data 963 }, 964 { .compatible = "brcm,bcm7278-switch-v4.0", 965 .data = &bcm_sf2_7278_data 966 }, 967 { /* sentinel */ }, 968 }; 969 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 970 971 static int bcm_sf2_sw_probe(struct platform_device *pdev) 972 { 973 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 974 struct device_node *dn = pdev->dev.of_node; 975 const struct of_device_id *of_id = NULL; 976 const struct bcm_sf2_of_data *data; 977 struct b53_platform_data *pdata; 978 struct dsa_switch_ops *ops; 979 struct bcm_sf2_priv *priv; 980 struct b53_device *dev; 981 struct dsa_switch *ds; 982 void __iomem **base; 983 struct resource *r; 984 unsigned int i; 985 u32 reg, rev; 986 int ret; 987 988 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 989 if (!priv) 990 return -ENOMEM; 991 992 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 993 if (!ops) 994 return -ENOMEM; 995 996 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 997 if (!dev) 998 return -ENOMEM; 999 1000 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1001 if (!pdata) 1002 return -ENOMEM; 1003 1004 of_id = of_match_node(bcm_sf2_of_match, dn); 1005 if (!of_id || !of_id->data) 1006 return -EINVAL; 1007 1008 data = of_id->data; 1009 1010 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1011 priv->type = data->type; 1012 priv->reg_offsets = data->reg_offsets; 1013 priv->core_reg_align = data->core_reg_align; 1014 priv->num_cfp_rules = data->num_cfp_rules; 1015 1016 /* Auto-detection using standard registers will not work, so 1017 * provide an indication of what kind of device we are for 1018 * b53_common to work with 1019 */ 1020 pdata->chip_id = priv->type; 1021 dev->pdata = pdata; 1022 1023 priv->dev = dev; 1024 ds = dev->ds; 1025 ds->ops = &bcm_sf2_ops; 1026 1027 /* Advertise the 8 egress queues */ 1028 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1029 1030 dev_set_drvdata(&pdev->dev, priv); 1031 1032 spin_lock_init(&priv->indir_lock); 1033 mutex_init(&priv->stats_mutex); 1034 mutex_init(&priv->cfp.lock); 1035 1036 /* CFP rule #0 cannot be used for specific classifications, flag it as 1037 * permanently used 1038 */ 1039 set_bit(0, priv->cfp.used); 1040 1041 bcm_sf2_identify_ports(priv, dn->child); 1042 1043 priv->irq0 = irq_of_parse_and_map(dn, 0); 1044 priv->irq1 = irq_of_parse_and_map(dn, 1); 1045 1046 base = &priv->core; 1047 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1048 r = platform_get_resource(pdev, IORESOURCE_MEM, i); 1049 *base = devm_ioremap_resource(&pdev->dev, r); 1050 if (IS_ERR(*base)) { 1051 pr_err("unable to find register: %s\n", reg_names[i]); 1052 return PTR_ERR(*base); 1053 } 1054 base++; 1055 } 1056 1057 ret = bcm_sf2_sw_rst(priv); 1058 if (ret) { 1059 pr_err("unable to software reset switch: %d\n", ret); 1060 return ret; 1061 } 1062 1063 ret = bcm_sf2_mdio_register(ds); 1064 if (ret) { 1065 pr_err("failed to register MDIO bus\n"); 1066 return ret; 1067 } 1068 1069 ret = bcm_sf2_cfp_rst(priv); 1070 if (ret) { 1071 pr_err("failed to reset CFP\n"); 1072 goto out_mdio; 1073 } 1074 1075 /* Disable all interrupts and request them */ 1076 bcm_sf2_intr_disable(priv); 1077 1078 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1079 "switch_0", priv); 1080 if (ret < 0) { 1081 pr_err("failed to request switch_0 IRQ\n"); 1082 goto out_mdio; 1083 } 1084 1085 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1086 "switch_1", priv); 1087 if (ret < 0) { 1088 pr_err("failed to request switch_1 IRQ\n"); 1089 goto out_mdio; 1090 } 1091 1092 /* Reset the MIB counters */ 1093 reg = core_readl(priv, CORE_GMNCFGCFG); 1094 reg |= RST_MIB_CNT; 1095 core_writel(priv, reg, CORE_GMNCFGCFG); 1096 reg &= ~RST_MIB_CNT; 1097 core_writel(priv, reg, CORE_GMNCFGCFG); 1098 1099 /* Get the maximum number of ports for this switch */ 1100 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1101 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1102 priv->hw_params.num_ports = DSA_MAX_PORTS; 1103 1104 /* Assume a single GPHY setup if we can't read that property */ 1105 if (of_property_read_u32(dn, "brcm,num-gphy", 1106 &priv->hw_params.num_gphy)) 1107 priv->hw_params.num_gphy = 1; 1108 1109 rev = reg_readl(priv, REG_SWITCH_REVISION); 1110 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1111 SWITCH_TOP_REV_MASK; 1112 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1113 1114 rev = reg_readl(priv, REG_PHY_REVISION); 1115 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1116 1117 ret = b53_switch_register(dev); 1118 if (ret) 1119 goto out_mdio; 1120 1121 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n", 1122 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1123 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1124 priv->core, priv->irq0, priv->irq1); 1125 1126 return 0; 1127 1128 out_mdio: 1129 bcm_sf2_mdio_unregister(priv); 1130 return ret; 1131 } 1132 1133 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1134 { 1135 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1136 1137 /* Disable all ports and interrupts */ 1138 priv->wol_ports_mask = 0; 1139 bcm_sf2_sw_suspend(priv->dev->ds); 1140 dsa_unregister_switch(priv->dev->ds); 1141 bcm_sf2_mdio_unregister(priv); 1142 1143 return 0; 1144 } 1145 1146 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1147 { 1148 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1149 1150 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1151 * successful MDIO bus scan to occur. If we did turn off the GPHY 1152 * before (e.g: port_disable), this will also power it back on. 1153 * 1154 * Do not rely on kexec_in_progress, just power the PHY on. 1155 */ 1156 if (priv->hw_params.num_gphy == 1) 1157 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1158 } 1159 1160 #ifdef CONFIG_PM_SLEEP 1161 static int bcm_sf2_suspend(struct device *dev) 1162 { 1163 struct platform_device *pdev = to_platform_device(dev); 1164 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1165 1166 return dsa_switch_suspend(priv->dev->ds); 1167 } 1168 1169 static int bcm_sf2_resume(struct device *dev) 1170 { 1171 struct platform_device *pdev = to_platform_device(dev); 1172 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1173 1174 return dsa_switch_resume(priv->dev->ds); 1175 } 1176 #endif /* CONFIG_PM_SLEEP */ 1177 1178 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1179 bcm_sf2_suspend, bcm_sf2_resume); 1180 1181 1182 static struct platform_driver bcm_sf2_driver = { 1183 .probe = bcm_sf2_sw_probe, 1184 .remove = bcm_sf2_sw_remove, 1185 .shutdown = bcm_sf2_sw_shutdown, 1186 .driver = { 1187 .name = "brcm-sf2", 1188 .of_match_table = bcm_sf2_of_match, 1189 .pm = &bcm_sf2_pm_ops, 1190 }, 1191 }; 1192 module_platform_driver(bcm_sf2_driver); 1193 1194 MODULE_AUTHOR("Broadcom Corporation"); 1195 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1196 MODULE_LICENSE("GPL"); 1197 MODULE_ALIAS("platform:brcm-sf2"); 1198