1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom Starfighter 2 DSA switch driver 4 * 5 * Copyright (C) 2014, Broadcom Corporation 6 */ 7 8 #include <linux/list.h> 9 #include <linux/module.h> 10 #include <linux/netdevice.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy.h> 14 #include <linux/phy_fixed.h> 15 #include <linux/phylink.h> 16 #include <linux/mii.h> 17 #include <linux/clk.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <net/dsa.h> 24 #include <linux/ethtool.h> 25 #include <linux/if_bridge.h> 26 #include <linux/brcmphy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/platform_data/b53.h> 29 30 #include "bcm_sf2.h" 31 #include "bcm_sf2_regs.h" 32 #include "b53/b53_priv.h" 33 #include "b53/b53_regs.h" 34 35 /* Return the number of active ports, not counting the IMP (CPU) port */ 36 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds) 37 { 38 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 39 unsigned int port, count = 0; 40 41 for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) { 42 if (dsa_is_cpu_port(ds, port)) 43 continue; 44 if (priv->port_sts[port].enabled) 45 count++; 46 } 47 48 return count; 49 } 50 51 static void bcm_sf2_recalc_clock(struct dsa_switch *ds) 52 { 53 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 54 unsigned long new_rate; 55 unsigned int ports_active; 56 /* Frequenty in Mhz */ 57 const unsigned long rate_table[] = { 58 59220000, 59 60820000, 60 62500000, 61 62500000, 62 }; 63 64 ports_active = bcm_sf2_num_active_ports(ds); 65 if (ports_active == 0 || !priv->clk_mdiv) 66 return; 67 68 /* If we overflow our table, just use the recommended operational 69 * frequency 70 */ 71 if (ports_active > ARRAY_SIZE(rate_table)) 72 new_rate = 90000000; 73 else 74 new_rate = rate_table[ports_active - 1]; 75 clk_set_rate(priv->clk_mdiv, new_rate); 76 } 77 78 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) 79 { 80 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 81 unsigned int i; 82 u32 reg, offset; 83 84 /* Enable the port memories */ 85 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 86 reg &= ~P_TXQ_PSM_VDD(port); 87 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 88 89 /* Enable forwarding */ 90 core_writel(priv, SW_FWDG_EN, CORE_SWMODE); 91 92 /* Enable IMP port in dumb mode */ 93 reg = core_readl(priv, CORE_SWITCH_CTRL); 94 reg |= MII_DUMB_FWDG_EN; 95 core_writel(priv, reg, CORE_SWITCH_CTRL); 96 97 /* Configure Traffic Class to QoS mapping, allow each priority to map 98 * to a different queue number 99 */ 100 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 101 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 102 reg |= i << (PRT_TO_QID_SHIFT * i); 103 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 104 105 b53_brcm_hdr_setup(ds, port); 106 107 if (port == 8) { 108 if (priv->type == BCM7445_DEVICE_ID) 109 offset = CORE_STS_OVERRIDE_IMP; 110 else 111 offset = CORE_STS_OVERRIDE_IMP2; 112 113 /* Force link status for IMP port */ 114 reg = core_readl(priv, offset); 115 reg |= (MII_SW_OR | LINK_STS); 116 reg &= ~GMII_SPEED_UP_2G; 117 core_writel(priv, reg, offset); 118 119 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ 120 reg = core_readl(priv, CORE_IMP_CTL); 121 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); 122 reg &= ~(RX_DIS | TX_DIS); 123 core_writel(priv, reg, CORE_IMP_CTL); 124 } else { 125 reg = core_readl(priv, CORE_G_PCTL_PORT(port)); 126 reg &= ~(RX_DIS | TX_DIS); 127 core_writel(priv, reg, CORE_G_PCTL_PORT(port)); 128 } 129 130 priv->port_sts[port].enabled = true; 131 } 132 133 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) 134 { 135 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 136 u32 reg; 137 138 reg = reg_readl(priv, REG_SPHY_CNTRL); 139 if (enable) { 140 reg |= PHY_RESET; 141 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); 142 reg_writel(priv, reg, REG_SPHY_CNTRL); 143 udelay(21); 144 reg = reg_readl(priv, REG_SPHY_CNTRL); 145 reg &= ~PHY_RESET; 146 } else { 147 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; 148 reg_writel(priv, reg, REG_SPHY_CNTRL); 149 mdelay(1); 150 reg |= CK25_DIS; 151 } 152 reg_writel(priv, reg, REG_SPHY_CNTRL); 153 154 /* Use PHY-driven LED signaling */ 155 if (!enable) { 156 reg = reg_readl(priv, REG_LED_CNTRL(0)); 157 reg |= SPDLNK_SRC_SEL; 158 reg_writel(priv, reg, REG_LED_CNTRL(0)); 159 } 160 } 161 162 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, 163 int port) 164 { 165 unsigned int off; 166 167 switch (port) { 168 case 7: 169 off = P7_IRQ_OFF; 170 break; 171 case 0: 172 /* Port 0 interrupts are located on the first bank */ 173 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); 174 return; 175 default: 176 off = P_IRQ_OFF(port); 177 break; 178 } 179 180 intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); 181 } 182 183 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, 184 int port) 185 { 186 unsigned int off; 187 188 switch (port) { 189 case 7: 190 off = P7_IRQ_OFF; 191 break; 192 case 0: 193 /* Port 0 interrupts are located on the first bank */ 194 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); 195 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); 196 return; 197 default: 198 off = P_IRQ_OFF(port); 199 break; 200 } 201 202 intrl2_1_mask_set(priv, P_IRQ_MASK(off)); 203 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); 204 } 205 206 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, 207 struct phy_device *phy) 208 { 209 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 210 unsigned int i; 211 u32 reg; 212 213 if (!dsa_is_user_port(ds, port)) 214 return 0; 215 216 priv->port_sts[port].enabled = true; 217 218 bcm_sf2_recalc_clock(ds); 219 220 /* Clear the memory power down */ 221 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 222 reg &= ~P_TXQ_PSM_VDD(port); 223 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 224 225 /* Enable learning */ 226 reg = core_readl(priv, CORE_DIS_LEARN); 227 reg &= ~BIT(port); 228 core_writel(priv, reg, CORE_DIS_LEARN); 229 230 /* Enable Broadcom tags for that port if requested */ 231 if (priv->brcm_tag_mask & BIT(port)) { 232 b53_brcm_hdr_setup(ds, port); 233 234 /* Disable learning on ASP port */ 235 if (port == 7) { 236 reg = core_readl(priv, CORE_DIS_LEARN); 237 reg |= BIT(port); 238 core_writel(priv, reg, CORE_DIS_LEARN); 239 } 240 } 241 242 /* Configure Traffic Class to QoS mapping, allow each priority to map 243 * to a different queue number 244 */ 245 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); 246 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) 247 reg |= i << (PRT_TO_QID_SHIFT * i); 248 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); 249 250 /* Re-enable the GPHY and re-apply workarounds */ 251 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { 252 bcm_sf2_gphy_enable_set(ds, true); 253 if (phy) { 254 /* if phy_stop() has been called before, phy 255 * will be in halted state, and phy_start() 256 * will call resume. 257 * 258 * the resume path does not configure back 259 * autoneg settings, and since we hard reset 260 * the phy manually here, we need to reset the 261 * state machine also. 262 */ 263 phy->state = PHY_READY; 264 phy_init_hw(phy); 265 } 266 } 267 268 /* Enable MoCA port interrupts to get notified */ 269 if (port == priv->moca_port) 270 bcm_sf2_port_intr_enable(priv, port); 271 272 /* Set per-queue pause threshold to 32 */ 273 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port)); 274 275 /* Set ACB threshold to 24 */ 276 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) { 277 reg = acb_readl(priv, ACB_QUEUE_CFG(port * 278 SF2_NUM_EGRESS_QUEUES + i)); 279 reg &= ~XOFF_THRESHOLD_MASK; 280 reg |= 24; 281 acb_writel(priv, reg, ACB_QUEUE_CFG(port * 282 SF2_NUM_EGRESS_QUEUES + i)); 283 } 284 285 return b53_enable_port(ds, port, phy); 286 } 287 288 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port) 289 { 290 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 291 u32 reg; 292 293 /* Disable learning while in WoL mode */ 294 if (priv->wol_ports_mask & (1 << port)) { 295 reg = core_readl(priv, CORE_DIS_LEARN); 296 reg |= BIT(port); 297 core_writel(priv, reg, CORE_DIS_LEARN); 298 return; 299 } 300 301 if (port == priv->moca_port) 302 bcm_sf2_port_intr_disable(priv, port); 303 304 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) 305 bcm_sf2_gphy_enable_set(ds, false); 306 307 b53_disable_port(ds, port); 308 309 /* Power down the port memory */ 310 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); 311 reg |= P_TXQ_PSM_VDD(port); 312 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); 313 314 priv->port_sts[port].enabled = false; 315 316 bcm_sf2_recalc_clock(ds); 317 } 318 319 320 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, 321 int regnum, u16 val) 322 { 323 int ret = 0; 324 u32 reg; 325 326 reg = reg_readl(priv, REG_SWITCH_CNTRL); 327 reg |= MDIO_MASTER_SEL; 328 reg_writel(priv, reg, REG_SWITCH_CNTRL); 329 330 /* Page << 8 | offset */ 331 reg = 0x70; 332 reg <<= 2; 333 core_writel(priv, addr, reg); 334 335 /* Page << 8 | offset */ 336 reg = 0x80 << 8 | regnum << 1; 337 reg <<= 2; 338 339 if (op) 340 ret = core_readl(priv, reg); 341 else 342 core_writel(priv, val, reg); 343 344 reg = reg_readl(priv, REG_SWITCH_CNTRL); 345 reg &= ~MDIO_MASTER_SEL; 346 reg_writel(priv, reg, REG_SWITCH_CNTRL); 347 348 return ret & 0xffff; 349 } 350 351 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 352 { 353 struct bcm_sf2_priv *priv = bus->priv; 354 355 /* Intercept reads from Broadcom pseudo-PHY address, else, send 356 * them to our master MDIO bus controller 357 */ 358 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 359 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); 360 else 361 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); 362 } 363 364 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 365 u16 val) 366 { 367 struct bcm_sf2_priv *priv = bus->priv; 368 369 /* Intercept writes to the Broadcom pseudo-PHY address, else, 370 * send them to our master MDIO bus controller 371 */ 372 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) 373 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); 374 else 375 return mdiobus_write_nested(priv->master_mii_bus, addr, 376 regnum, val); 377 } 378 379 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) 380 { 381 struct dsa_switch *ds = dev_id; 382 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 383 384 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & 385 ~priv->irq0_mask; 386 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 387 388 return IRQ_HANDLED; 389 } 390 391 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) 392 { 393 struct dsa_switch *ds = dev_id; 394 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 395 396 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & 397 ~priv->irq1_mask; 398 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 399 400 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) { 401 priv->port_sts[7].link = true; 402 dsa_port_phylink_mac_change(ds, 7, true); 403 } 404 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) { 405 priv->port_sts[7].link = false; 406 dsa_port_phylink_mac_change(ds, 7, false); 407 } 408 409 return IRQ_HANDLED; 410 } 411 412 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) 413 { 414 unsigned int timeout = 1000; 415 u32 reg; 416 int ret; 417 418 /* The watchdog reset does not work on 7278, we need to hit the 419 * "external" reset line through the reset controller. 420 */ 421 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) { 422 ret = reset_control_assert(priv->rcdev); 423 if (ret) 424 return ret; 425 426 return reset_control_deassert(priv->rcdev); 427 } 428 429 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 430 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; 431 core_writel(priv, reg, CORE_WATCHDOG_CTRL); 432 433 do { 434 reg = core_readl(priv, CORE_WATCHDOG_CTRL); 435 if (!(reg & SOFTWARE_RESET)) 436 break; 437 438 usleep_range(1000, 2000); 439 } while (timeout-- > 0); 440 441 if (timeout == 0) 442 return -ETIMEDOUT; 443 444 return 0; 445 } 446 447 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) 448 { 449 intrl2_0_mask_set(priv, 0xffffffff); 450 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 451 intrl2_1_mask_set(priv, 0xffffffff); 452 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); 453 } 454 455 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, 456 struct device_node *dn) 457 { 458 struct device_node *port; 459 unsigned int port_num; 460 phy_interface_t mode; 461 int err; 462 463 priv->moca_port = -1; 464 465 for_each_available_child_of_node(dn, port) { 466 if (of_property_read_u32(port, "reg", &port_num)) 467 continue; 468 469 /* Internal PHYs get assigned a specific 'phy-mode' property 470 * value: "internal" to help flag them before MDIO probing 471 * has completed, since they might be turned off at that 472 * time 473 */ 474 err = of_get_phy_mode(port, &mode); 475 if (err) 476 continue; 477 478 if (mode == PHY_INTERFACE_MODE_INTERNAL) 479 priv->int_phy_mask |= 1 << port_num; 480 481 if (mode == PHY_INTERFACE_MODE_MOCA) 482 priv->moca_port = port_num; 483 484 if (of_property_read_bool(port, "brcm,use-bcm-hdr")) 485 priv->brcm_tag_mask |= 1 << port_num; 486 } 487 } 488 489 static int bcm_sf2_mdio_register(struct dsa_switch *ds) 490 { 491 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 492 struct device_node *dn, *child; 493 struct phy_device *phydev; 494 struct property *prop; 495 static int index; 496 int err, reg; 497 498 /* Find our integrated MDIO bus node */ 499 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); 500 priv->master_mii_bus = of_mdio_find_bus(dn); 501 if (!priv->master_mii_bus) 502 return -EPROBE_DEFER; 503 504 get_device(&priv->master_mii_bus->dev); 505 priv->master_mii_dn = dn; 506 507 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); 508 if (!priv->slave_mii_bus) 509 return -ENOMEM; 510 511 priv->slave_mii_bus->priv = priv; 512 priv->slave_mii_bus->name = "sf2 slave mii"; 513 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; 514 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; 515 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", 516 index++); 517 priv->slave_mii_bus->dev.of_node = dn; 518 519 /* Include the pseudo-PHY address to divert reads towards our 520 * workaround. This is only required for 7445D0, since 7445E0 521 * disconnects the internal switch pseudo-PHY such that we can use the 522 * regular SWITCH_MDIO master controller instead. 523 * 524 * Here we flag the pseudo PHY as needing special treatment and would 525 * otherwise make all other PHY read/writes go to the master MDIO bus 526 * controller that comes with this switch backed by the "mdio-unimac" 527 * driver. 528 */ 529 if (of_machine_is_compatible("brcm,bcm7445d0")) 530 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); 531 else 532 priv->indir_phy_mask = 0; 533 534 ds->phys_mii_mask = priv->indir_phy_mask; 535 ds->slave_mii_bus = priv->slave_mii_bus; 536 priv->slave_mii_bus->parent = ds->dev->parent; 537 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; 538 539 /* We need to make sure that of_phy_connect() will not work by 540 * removing the 'phandle' and 'linux,phandle' properties and 541 * unregister the existing PHY device that was already registered. 542 */ 543 for_each_available_child_of_node(dn, child) { 544 if (of_property_read_u32(child, "reg", ®) || 545 reg >= PHY_MAX_ADDR) 546 continue; 547 548 if (!(priv->indir_phy_mask & BIT(reg))) 549 continue; 550 551 prop = of_find_property(child, "phandle", NULL); 552 if (prop) 553 of_remove_property(child, prop); 554 555 prop = of_find_property(child, "linux,phandle", NULL); 556 if (prop) 557 of_remove_property(child, prop); 558 559 phydev = of_phy_find_device(child); 560 if (phydev) 561 phy_device_remove(phydev); 562 } 563 564 err = mdiobus_register(priv->slave_mii_bus); 565 if (err && dn) 566 of_node_put(dn); 567 568 return err; 569 } 570 571 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 572 { 573 mdiobus_unregister(priv->slave_mii_bus); 574 of_node_put(priv->master_mii_dn); 575 } 576 577 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) 578 { 579 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 580 581 /* The BCM7xxx PHY driver expects to find the integrated PHY revision 582 * in bits 15:8 and the patch level in bits 7:0 which is exactly what 583 * the REG_PHY_REVISION register layout is. 584 */ 585 586 return priv->hw_params.gphy_rev; 587 } 588 589 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port, 590 unsigned long *supported, 591 struct phylink_link_state *state) 592 { 593 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 594 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 595 596 if (!phy_interface_mode_is_rgmii(state->interface) && 597 state->interface != PHY_INTERFACE_MODE_MII && 598 state->interface != PHY_INTERFACE_MODE_REVMII && 599 state->interface != PHY_INTERFACE_MODE_GMII && 600 state->interface != PHY_INTERFACE_MODE_INTERNAL && 601 state->interface != PHY_INTERFACE_MODE_MOCA) { 602 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 603 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) 604 dev_err(ds->dev, 605 "Unsupported interface: %d for port %d\n", 606 state->interface, port); 607 return; 608 } 609 610 /* Allow all the expected bits */ 611 phylink_set(mask, Autoneg); 612 phylink_set_port_modes(mask); 613 phylink_set(mask, Pause); 614 phylink_set(mask, Asym_Pause); 615 616 /* With the exclusion of MII and Reverse MII, we support Gigabit, 617 * including Half duplex 618 */ 619 if (state->interface != PHY_INTERFACE_MODE_MII && 620 state->interface != PHY_INTERFACE_MODE_REVMII) { 621 phylink_set(mask, 1000baseT_Full); 622 phylink_set(mask, 1000baseT_Half); 623 } 624 625 phylink_set(mask, 10baseT_Half); 626 phylink_set(mask, 10baseT_Full); 627 phylink_set(mask, 100baseT_Half); 628 phylink_set(mask, 100baseT_Full); 629 630 bitmap_and(supported, supported, mask, 631 __ETHTOOL_LINK_MODE_MASK_NBITS); 632 bitmap_and(state->advertising, state->advertising, mask, 633 __ETHTOOL_LINK_MODE_MASK_NBITS); 634 } 635 636 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, 637 unsigned int mode, 638 const struct phylink_link_state *state) 639 { 640 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 641 u32 id_mode_dis = 0, port_mode; 642 u32 reg; 643 644 if (port == core_readl(priv, CORE_IMP0_PRT_ID)) 645 return; 646 647 switch (state->interface) { 648 case PHY_INTERFACE_MODE_RGMII: 649 id_mode_dis = 1; 650 fallthrough; 651 case PHY_INTERFACE_MODE_RGMII_TXID: 652 port_mode = EXT_GPHY; 653 break; 654 case PHY_INTERFACE_MODE_MII: 655 port_mode = EXT_EPHY; 656 break; 657 case PHY_INTERFACE_MODE_REVMII: 658 port_mode = EXT_REVMII; 659 break; 660 default: 661 /* Nothing required for all other PHYs: internal and MoCA */ 662 return; 663 } 664 665 /* Clear id_mode_dis bit, and the existing port mode, let 666 * RGMII_MODE_EN bet set by mac_link_{up,down} 667 */ 668 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 669 reg &= ~ID_MODE_DIS; 670 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); 671 672 reg |= port_mode; 673 if (id_mode_dis) 674 reg |= ID_MODE_DIS; 675 676 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 677 } 678 679 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, 680 phy_interface_t interface, bool link) 681 { 682 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 683 u32 reg; 684 685 if (!phy_interface_mode_is_rgmii(interface) && 686 interface != PHY_INTERFACE_MODE_MII && 687 interface != PHY_INTERFACE_MODE_REVMII) 688 return; 689 690 /* If the link is down, just disable the interface to conserve power */ 691 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 692 if (link) 693 reg |= RGMII_MODE_EN; 694 else 695 reg &= ~RGMII_MODE_EN; 696 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 697 } 698 699 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, 700 unsigned int mode, 701 phy_interface_t interface) 702 { 703 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 704 u32 reg, offset; 705 706 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 707 if (priv->type == BCM7445_DEVICE_ID) 708 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 709 else 710 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 711 712 reg = core_readl(priv, offset); 713 reg &= ~LINK_STS; 714 core_writel(priv, reg, offset); 715 } 716 717 bcm_sf2_sw_mac_link_set(ds, port, interface, false); 718 } 719 720 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port, 721 unsigned int mode, 722 phy_interface_t interface, 723 struct phy_device *phydev, 724 int speed, int duplex, 725 bool tx_pause, bool rx_pause) 726 { 727 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 728 struct ethtool_eee *p = &priv->dev->ports[port].eee; 729 u32 reg, offset; 730 731 bcm_sf2_sw_mac_link_set(ds, port, interface, true); 732 733 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { 734 if (priv->type == BCM7445_DEVICE_ID) 735 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); 736 else 737 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); 738 739 if (interface == PHY_INTERFACE_MODE_RGMII || 740 interface == PHY_INTERFACE_MODE_RGMII_TXID || 741 interface == PHY_INTERFACE_MODE_MII || 742 interface == PHY_INTERFACE_MODE_REVMII) { 743 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); 744 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); 745 746 if (tx_pause) 747 reg |= TX_PAUSE_EN; 748 if (rx_pause) 749 reg |= RX_PAUSE_EN; 750 751 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); 752 } 753 754 reg = SW_OVERRIDE | LINK_STS; 755 switch (speed) { 756 case SPEED_1000: 757 reg |= SPDSTS_1000 << SPEED_SHIFT; 758 break; 759 case SPEED_100: 760 reg |= SPDSTS_100 << SPEED_SHIFT; 761 break; 762 } 763 764 if (duplex == DUPLEX_FULL) 765 reg |= DUPLX_MODE; 766 767 core_writel(priv, reg, offset); 768 } 769 770 if (mode == MLO_AN_PHY && phydev) 771 p->eee_enabled = b53_eee_init(ds, port, phydev); 772 } 773 774 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port, 775 struct phylink_link_state *status) 776 { 777 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 778 779 status->link = false; 780 781 /* MoCA port is special as we do not get link status from CORE_LNKSTS, 782 * which means that we need to force the link at the port override 783 * level to get the data to flow. We do use what the interrupt handler 784 * did determine before. 785 * 786 * For the other ports, we just force the link status, since this is 787 * a fixed PHY device. 788 */ 789 if (port == priv->moca_port) { 790 status->link = priv->port_sts[port].link; 791 /* For MoCA interfaces, also force a link down notification 792 * since some version of the user-space daemon (mocad) use 793 * cmd->autoneg to force the link, which messes up the PHY 794 * state machine and make it go in PHY_FORCING state instead. 795 */ 796 if (!status->link) 797 netif_carrier_off(dsa_to_port(ds, port)->slave); 798 status->duplex = DUPLEX_FULL; 799 } else { 800 status->link = true; 801 } 802 } 803 804 static void bcm_sf2_enable_acb(struct dsa_switch *ds) 805 { 806 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 807 u32 reg; 808 809 /* Enable ACB globally */ 810 reg = acb_readl(priv, ACB_CONTROL); 811 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 812 acb_writel(priv, reg, ACB_CONTROL); 813 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); 814 reg |= ACB_EN | ACB_ALGORITHM; 815 acb_writel(priv, reg, ACB_CONTROL); 816 } 817 818 static int bcm_sf2_sw_suspend(struct dsa_switch *ds) 819 { 820 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 821 unsigned int port; 822 823 bcm_sf2_intr_disable(priv); 824 825 /* Disable all ports physically present including the IMP 826 * port, the other ones have already been disabled during 827 * bcm_sf2_sw_setup 828 */ 829 for (port = 0; port < ds->num_ports; port++) { 830 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port)) 831 bcm_sf2_port_disable(ds, port); 832 } 833 834 if (!priv->wol_ports_mask) 835 clk_disable_unprepare(priv->clk); 836 837 return 0; 838 } 839 840 static int bcm_sf2_sw_resume(struct dsa_switch *ds) 841 { 842 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 843 int ret; 844 845 if (!priv->wol_ports_mask) 846 clk_prepare_enable(priv->clk); 847 848 ret = bcm_sf2_sw_rst(priv); 849 if (ret) { 850 pr_err("%s: failed to software reset switch\n", __func__); 851 return ret; 852 } 853 854 ret = bcm_sf2_cfp_resume(ds); 855 if (ret) 856 return ret; 857 858 if (priv->hw_params.num_gphy == 1) 859 bcm_sf2_gphy_enable_set(ds, true); 860 861 ds->ops->setup(ds); 862 863 return 0; 864 } 865 866 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, 867 struct ethtool_wolinfo *wol) 868 { 869 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 870 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 871 struct ethtool_wolinfo pwol = { }; 872 873 /* Get the parent device WoL settings */ 874 if (p->ethtool_ops->get_wol) 875 p->ethtool_ops->get_wol(p, &pwol); 876 877 /* Advertise the parent device supported settings */ 878 wol->supported = pwol.supported; 879 memset(&wol->sopass, 0, sizeof(wol->sopass)); 880 881 if (pwol.wolopts & WAKE_MAGICSECURE) 882 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); 883 884 if (priv->wol_ports_mask & (1 << port)) 885 wol->wolopts = pwol.wolopts; 886 else 887 wol->wolopts = 0; 888 } 889 890 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 891 struct ethtool_wolinfo *wol) 892 { 893 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master; 894 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 895 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 896 struct ethtool_wolinfo pwol = { }; 897 898 if (p->ethtool_ops->get_wol) 899 p->ethtool_ops->get_wol(p, &pwol); 900 if (wol->wolopts & ~pwol.supported) 901 return -EINVAL; 902 903 if (wol->wolopts) 904 priv->wol_ports_mask |= (1 << port); 905 else 906 priv->wol_ports_mask &= ~(1 << port); 907 908 /* If we have at least one port enabled, make sure the CPU port 909 * is also enabled. If the CPU port is the last one enabled, we disable 910 * it since this configuration does not make sense. 911 */ 912 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) 913 priv->wol_ports_mask |= (1 << cpu_port); 914 else 915 priv->wol_ports_mask &= ~(1 << cpu_port); 916 917 return p->ethtool_ops->set_wol(p, wol); 918 } 919 920 static int bcm_sf2_sw_setup(struct dsa_switch *ds) 921 { 922 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); 923 unsigned int port; 924 925 /* Enable all valid ports and disable those unused */ 926 for (port = 0; port < priv->hw_params.num_ports; port++) { 927 /* IMP port receives special treatment */ 928 if (dsa_is_user_port(ds, port)) 929 bcm_sf2_port_setup(ds, port, NULL); 930 else if (dsa_is_cpu_port(ds, port)) 931 bcm_sf2_imp_setup(ds, port); 932 else 933 bcm_sf2_port_disable(ds, port); 934 } 935 936 b53_configure_vlan(ds); 937 bcm_sf2_enable_acb(ds); 938 939 return b53_setup_devlink_resources(ds); 940 } 941 942 static void bcm_sf2_sw_teardown(struct dsa_switch *ds) 943 { 944 dsa_devlink_resources_unregister(ds); 945 } 946 947 /* The SWITCH_CORE register space is managed by b53 but operates on a page + 948 * register basis so we need to translate that into an address that the 949 * bus-glue understands. 950 */ 951 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) 952 953 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, 954 u8 *val) 955 { 956 struct bcm_sf2_priv *priv = dev->priv; 957 958 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 959 960 return 0; 961 } 962 963 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, 964 u16 *val) 965 { 966 struct bcm_sf2_priv *priv = dev->priv; 967 968 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 969 970 return 0; 971 } 972 973 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, 974 u32 *val) 975 { 976 struct bcm_sf2_priv *priv = dev->priv; 977 978 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); 979 980 return 0; 981 } 982 983 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, 984 u64 *val) 985 { 986 struct bcm_sf2_priv *priv = dev->priv; 987 988 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); 989 990 return 0; 991 } 992 993 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, 994 u8 value) 995 { 996 struct bcm_sf2_priv *priv = dev->priv; 997 998 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 999 1000 return 0; 1001 } 1002 1003 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, 1004 u16 value) 1005 { 1006 struct bcm_sf2_priv *priv = dev->priv; 1007 1008 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1009 1010 return 0; 1011 } 1012 1013 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, 1014 u32 value) 1015 { 1016 struct bcm_sf2_priv *priv = dev->priv; 1017 1018 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1019 1020 return 0; 1021 } 1022 1023 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, 1024 u64 value) 1025 { 1026 struct bcm_sf2_priv *priv = dev->priv; 1027 1028 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); 1029 1030 return 0; 1031 } 1032 1033 static const struct b53_io_ops bcm_sf2_io_ops = { 1034 .read8 = bcm_sf2_core_read8, 1035 .read16 = bcm_sf2_core_read16, 1036 .read32 = bcm_sf2_core_read32, 1037 .read48 = bcm_sf2_core_read64, 1038 .read64 = bcm_sf2_core_read64, 1039 .write8 = bcm_sf2_core_write8, 1040 .write16 = bcm_sf2_core_write16, 1041 .write32 = bcm_sf2_core_write32, 1042 .write48 = bcm_sf2_core_write64, 1043 .write64 = bcm_sf2_core_write64, 1044 }; 1045 1046 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port, 1047 u32 stringset, uint8_t *data) 1048 { 1049 int cnt = b53_get_sset_count(ds, port, stringset); 1050 1051 b53_get_strings(ds, port, stringset, data); 1052 bcm_sf2_cfp_get_strings(ds, port, stringset, 1053 data + cnt * ETH_GSTRING_LEN); 1054 } 1055 1056 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port, 1057 uint64_t *data) 1058 { 1059 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS); 1060 1061 b53_get_ethtool_stats(ds, port, data); 1062 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt); 1063 } 1064 1065 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port, 1066 int sset) 1067 { 1068 int cnt = b53_get_sset_count(ds, port, sset); 1069 1070 if (cnt < 0) 1071 return cnt; 1072 1073 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset); 1074 1075 return cnt; 1076 } 1077 1078 static const struct dsa_switch_ops bcm_sf2_ops = { 1079 .get_tag_protocol = b53_get_tag_protocol, 1080 .setup = bcm_sf2_sw_setup, 1081 .teardown = bcm_sf2_sw_teardown, 1082 .get_strings = bcm_sf2_sw_get_strings, 1083 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats, 1084 .get_sset_count = bcm_sf2_sw_get_sset_count, 1085 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1086 .get_phy_flags = bcm_sf2_sw_get_phy_flags, 1087 .phylink_validate = bcm_sf2_sw_validate, 1088 .phylink_mac_config = bcm_sf2_sw_mac_config, 1089 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down, 1090 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up, 1091 .phylink_fixed_state = bcm_sf2_sw_fixed_state, 1092 .suspend = bcm_sf2_sw_suspend, 1093 .resume = bcm_sf2_sw_resume, 1094 .get_wol = bcm_sf2_sw_get_wol, 1095 .set_wol = bcm_sf2_sw_set_wol, 1096 .port_enable = bcm_sf2_port_setup, 1097 .port_disable = bcm_sf2_port_disable, 1098 .get_mac_eee = b53_get_mac_eee, 1099 .set_mac_eee = b53_set_mac_eee, 1100 .port_bridge_join = b53_br_join, 1101 .port_bridge_leave = b53_br_leave, 1102 .port_stp_state_set = b53_br_set_stp_state, 1103 .port_fast_age = b53_br_fast_age, 1104 .port_vlan_filtering = b53_vlan_filtering, 1105 .port_vlan_prepare = b53_vlan_prepare, 1106 .port_vlan_add = b53_vlan_add, 1107 .port_vlan_del = b53_vlan_del, 1108 .port_fdb_dump = b53_fdb_dump, 1109 .port_fdb_add = b53_fdb_add, 1110 .port_fdb_del = b53_fdb_del, 1111 .get_rxnfc = bcm_sf2_get_rxnfc, 1112 .set_rxnfc = bcm_sf2_set_rxnfc, 1113 .port_mirror_add = b53_mirror_add, 1114 .port_mirror_del = b53_mirror_del, 1115 .port_mdb_prepare = b53_mdb_prepare, 1116 .port_mdb_add = b53_mdb_add, 1117 .port_mdb_del = b53_mdb_del, 1118 }; 1119 1120 struct bcm_sf2_of_data { 1121 u32 type; 1122 const u16 *reg_offsets; 1123 unsigned int core_reg_align; 1124 unsigned int num_cfp_rules; 1125 }; 1126 1127 /* Register offsets for the SWITCH_REG_* block */ 1128 static const u16 bcm_sf2_7445_reg_offsets[] = { 1129 [REG_SWITCH_CNTRL] = 0x00, 1130 [REG_SWITCH_STATUS] = 0x04, 1131 [REG_DIR_DATA_WRITE] = 0x08, 1132 [REG_DIR_DATA_READ] = 0x0C, 1133 [REG_SWITCH_REVISION] = 0x18, 1134 [REG_PHY_REVISION] = 0x1C, 1135 [REG_SPHY_CNTRL] = 0x2C, 1136 [REG_RGMII_0_CNTRL] = 0x34, 1137 [REG_RGMII_1_CNTRL] = 0x40, 1138 [REG_RGMII_2_CNTRL] = 0x4c, 1139 [REG_LED_0_CNTRL] = 0x90, 1140 [REG_LED_1_CNTRL] = 0x94, 1141 [REG_LED_2_CNTRL] = 0x98, 1142 }; 1143 1144 static const struct bcm_sf2_of_data bcm_sf2_7445_data = { 1145 .type = BCM7445_DEVICE_ID, 1146 .core_reg_align = 0, 1147 .reg_offsets = bcm_sf2_7445_reg_offsets, 1148 .num_cfp_rules = 256, 1149 }; 1150 1151 static const u16 bcm_sf2_7278_reg_offsets[] = { 1152 [REG_SWITCH_CNTRL] = 0x00, 1153 [REG_SWITCH_STATUS] = 0x04, 1154 [REG_DIR_DATA_WRITE] = 0x08, 1155 [REG_DIR_DATA_READ] = 0x0c, 1156 [REG_SWITCH_REVISION] = 0x10, 1157 [REG_PHY_REVISION] = 0x14, 1158 [REG_SPHY_CNTRL] = 0x24, 1159 [REG_RGMII_0_CNTRL] = 0xe0, 1160 [REG_RGMII_1_CNTRL] = 0xec, 1161 [REG_RGMII_2_CNTRL] = 0xf8, 1162 [REG_LED_0_CNTRL] = 0x40, 1163 [REG_LED_1_CNTRL] = 0x4c, 1164 [REG_LED_2_CNTRL] = 0x58, 1165 }; 1166 1167 static const struct bcm_sf2_of_data bcm_sf2_7278_data = { 1168 .type = BCM7278_DEVICE_ID, 1169 .core_reg_align = 1, 1170 .reg_offsets = bcm_sf2_7278_reg_offsets, 1171 .num_cfp_rules = 128, 1172 }; 1173 1174 static const struct of_device_id bcm_sf2_of_match[] = { 1175 { .compatible = "brcm,bcm7445-switch-v4.0", 1176 .data = &bcm_sf2_7445_data 1177 }, 1178 { .compatible = "brcm,bcm7278-switch-v4.0", 1179 .data = &bcm_sf2_7278_data 1180 }, 1181 { .compatible = "brcm,bcm7278-switch-v4.8", 1182 .data = &bcm_sf2_7278_data 1183 }, 1184 { /* sentinel */ }, 1185 }; 1186 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); 1187 1188 static int bcm_sf2_sw_probe(struct platform_device *pdev) 1189 { 1190 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; 1191 struct device_node *dn = pdev->dev.of_node; 1192 const struct of_device_id *of_id = NULL; 1193 const struct bcm_sf2_of_data *data; 1194 struct b53_platform_data *pdata; 1195 struct dsa_switch_ops *ops; 1196 struct device_node *ports; 1197 struct bcm_sf2_priv *priv; 1198 struct b53_device *dev; 1199 struct dsa_switch *ds; 1200 void __iomem **base; 1201 unsigned int i; 1202 u32 reg, rev; 1203 int ret; 1204 1205 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1206 if (!priv) 1207 return -ENOMEM; 1208 1209 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); 1210 if (!ops) 1211 return -ENOMEM; 1212 1213 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); 1214 if (!dev) 1215 return -ENOMEM; 1216 1217 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1218 if (!pdata) 1219 return -ENOMEM; 1220 1221 of_id = of_match_node(bcm_sf2_of_match, dn); 1222 if (!of_id || !of_id->data) 1223 return -EINVAL; 1224 1225 data = of_id->data; 1226 1227 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ 1228 priv->type = data->type; 1229 priv->reg_offsets = data->reg_offsets; 1230 priv->core_reg_align = data->core_reg_align; 1231 priv->num_cfp_rules = data->num_cfp_rules; 1232 1233 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, 1234 "switch"); 1235 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER) 1236 return PTR_ERR(priv->rcdev); 1237 1238 /* Auto-detection using standard registers will not work, so 1239 * provide an indication of what kind of device we are for 1240 * b53_common to work with 1241 */ 1242 pdata->chip_id = priv->type; 1243 dev->pdata = pdata; 1244 1245 priv->dev = dev; 1246 ds = dev->ds; 1247 ds->ops = &bcm_sf2_ops; 1248 1249 /* Advertise the 8 egress queues */ 1250 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES; 1251 1252 dev_set_drvdata(&pdev->dev, priv); 1253 1254 spin_lock_init(&priv->indir_lock); 1255 mutex_init(&priv->cfp.lock); 1256 INIT_LIST_HEAD(&priv->cfp.rules_list); 1257 1258 /* CFP rule #0 cannot be used for specific classifications, flag it as 1259 * permanently used 1260 */ 1261 set_bit(0, priv->cfp.used); 1262 set_bit(0, priv->cfp.unique); 1263 1264 /* Balance of_node_put() done by of_find_node_by_name() */ 1265 of_node_get(dn); 1266 ports = of_find_node_by_name(dn, "ports"); 1267 if (ports) { 1268 bcm_sf2_identify_ports(priv, ports); 1269 of_node_put(ports); 1270 } 1271 1272 priv->irq0 = irq_of_parse_and_map(dn, 0); 1273 priv->irq1 = irq_of_parse_and_map(dn, 1); 1274 1275 base = &priv->core; 1276 for (i = 0; i < BCM_SF2_REGS_NUM; i++) { 1277 *base = devm_platform_ioremap_resource(pdev, i); 1278 if (IS_ERR(*base)) { 1279 pr_err("unable to find register: %s\n", reg_names[i]); 1280 return PTR_ERR(*base); 1281 } 1282 base++; 1283 } 1284 1285 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch"); 1286 if (IS_ERR(priv->clk)) 1287 return PTR_ERR(priv->clk); 1288 1289 clk_prepare_enable(priv->clk); 1290 1291 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv"); 1292 if (IS_ERR(priv->clk_mdiv)) { 1293 ret = PTR_ERR(priv->clk_mdiv); 1294 goto out_clk; 1295 } 1296 1297 clk_prepare_enable(priv->clk_mdiv); 1298 1299 ret = bcm_sf2_sw_rst(priv); 1300 if (ret) { 1301 pr_err("unable to software reset switch: %d\n", ret); 1302 goto out_clk_mdiv; 1303 } 1304 1305 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1306 1307 ret = bcm_sf2_mdio_register(ds); 1308 if (ret) { 1309 pr_err("failed to register MDIO bus\n"); 1310 goto out_clk_mdiv; 1311 } 1312 1313 bcm_sf2_gphy_enable_set(priv->dev->ds, false); 1314 1315 ret = bcm_sf2_cfp_rst(priv); 1316 if (ret) { 1317 pr_err("failed to reset CFP\n"); 1318 goto out_mdio; 1319 } 1320 1321 /* Disable all interrupts and request them */ 1322 bcm_sf2_intr_disable(priv); 1323 1324 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, 1325 "switch_0", ds); 1326 if (ret < 0) { 1327 pr_err("failed to request switch_0 IRQ\n"); 1328 goto out_mdio; 1329 } 1330 1331 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, 1332 "switch_1", ds); 1333 if (ret < 0) { 1334 pr_err("failed to request switch_1 IRQ\n"); 1335 goto out_mdio; 1336 } 1337 1338 /* Reset the MIB counters */ 1339 reg = core_readl(priv, CORE_GMNCFGCFG); 1340 reg |= RST_MIB_CNT; 1341 core_writel(priv, reg, CORE_GMNCFGCFG); 1342 reg &= ~RST_MIB_CNT; 1343 core_writel(priv, reg, CORE_GMNCFGCFG); 1344 1345 /* Get the maximum number of ports for this switch */ 1346 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; 1347 if (priv->hw_params.num_ports > DSA_MAX_PORTS) 1348 priv->hw_params.num_ports = DSA_MAX_PORTS; 1349 1350 /* Assume a single GPHY setup if we can't read that property */ 1351 if (of_property_read_u32(dn, "brcm,num-gphy", 1352 &priv->hw_params.num_gphy)) 1353 priv->hw_params.num_gphy = 1; 1354 1355 rev = reg_readl(priv, REG_SWITCH_REVISION); 1356 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & 1357 SWITCH_TOP_REV_MASK; 1358 priv->hw_params.core_rev = (rev & SF2_REV_MASK); 1359 1360 rev = reg_readl(priv, REG_PHY_REVISION); 1361 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; 1362 1363 ret = b53_switch_register(dev); 1364 if (ret) 1365 goto out_mdio; 1366 1367 dev_info(&pdev->dev, 1368 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", 1369 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, 1370 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, 1371 priv->irq0, priv->irq1); 1372 1373 return 0; 1374 1375 out_mdio: 1376 bcm_sf2_mdio_unregister(priv); 1377 out_clk_mdiv: 1378 clk_disable_unprepare(priv->clk_mdiv); 1379 out_clk: 1380 clk_disable_unprepare(priv->clk); 1381 return ret; 1382 } 1383 1384 static int bcm_sf2_sw_remove(struct platform_device *pdev) 1385 { 1386 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1387 1388 priv->wol_ports_mask = 0; 1389 /* Disable interrupts */ 1390 bcm_sf2_intr_disable(priv); 1391 dsa_unregister_switch(priv->dev->ds); 1392 bcm_sf2_cfp_exit(priv->dev->ds); 1393 bcm_sf2_mdio_unregister(priv); 1394 clk_disable_unprepare(priv->clk_mdiv); 1395 clk_disable_unprepare(priv->clk); 1396 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) 1397 reset_control_assert(priv->rcdev); 1398 1399 return 0; 1400 } 1401 1402 static void bcm_sf2_sw_shutdown(struct platform_device *pdev) 1403 { 1404 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); 1405 1406 /* For a kernel about to be kexec'd we want to keep the GPHY on for a 1407 * successful MDIO bus scan to occur. If we did turn off the GPHY 1408 * before (e.g: port_disable), this will also power it back on. 1409 * 1410 * Do not rely on kexec_in_progress, just power the PHY on. 1411 */ 1412 if (priv->hw_params.num_gphy == 1) 1413 bcm_sf2_gphy_enable_set(priv->dev->ds, true); 1414 } 1415 1416 #ifdef CONFIG_PM_SLEEP 1417 static int bcm_sf2_suspend(struct device *dev) 1418 { 1419 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1420 1421 return dsa_switch_suspend(priv->dev->ds); 1422 } 1423 1424 static int bcm_sf2_resume(struct device *dev) 1425 { 1426 struct bcm_sf2_priv *priv = dev_get_drvdata(dev); 1427 1428 return dsa_switch_resume(priv->dev->ds); 1429 } 1430 #endif /* CONFIG_PM_SLEEP */ 1431 1432 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, 1433 bcm_sf2_suspend, bcm_sf2_resume); 1434 1435 1436 static struct platform_driver bcm_sf2_driver = { 1437 .probe = bcm_sf2_sw_probe, 1438 .remove = bcm_sf2_sw_remove, 1439 .shutdown = bcm_sf2_sw_shutdown, 1440 .driver = { 1441 .name = "brcm-sf2", 1442 .of_match_table = bcm_sf2_of_match, 1443 .pm = &bcm_sf2_pm_ops, 1444 }, 1445 }; 1446 module_platform_driver(bcm_sf2_driver); 1447 1448 MODULE_AUTHOR("Broadcom Corporation"); 1449 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); 1450 MODULE_LICENSE("GPL"); 1451 MODULE_ALIAS("platform:brcm-sf2"); 1452