1*59da9885SKrzysztof Kozlowski /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2938e4d49SNishad Kamdar /*
30e01491dSFlorian Fainelli * Northstar Plus switch SerDes/SGMII PHY definitions
40e01491dSFlorian Fainelli *
50e01491dSFlorian Fainelli * Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>
60e01491dSFlorian Fainelli */
70e01491dSFlorian Fainelli
80e01491dSFlorian Fainelli #include <linux/phy.h>
90e01491dSFlorian Fainelli #include <linux/types.h>
100e01491dSFlorian Fainelli
110e01491dSFlorian Fainelli /* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
120e01491dSFlorian Fainelli #define B53_SERDES_PAGE 0x16
130e01491dSFlorian Fainelli #define B53_SERDES_BLKADDR 0x3e
140e01491dSFlorian Fainelli #define B53_SERDES_LANE 0x3c
150e01491dSFlorian Fainelli
160e01491dSFlorian Fainelli #define B53_SERDES_ID0 0x20
170e01491dSFlorian Fainelli #define SERDES_ID0_MODEL_MASK 0x3f
180e01491dSFlorian Fainelli #define SERDES_ID0_REV_NUM_SHIFT 11
190e01491dSFlorian Fainelli #define SERDES_ID0_REV_NUM_MASK 0x7
200e01491dSFlorian Fainelli #define SERDES_ID0_REV_LETTER_SHIFT 14
210e01491dSFlorian Fainelli
220e01491dSFlorian Fainelli #define B53_SERDES_MII_REG(x) (0x20 + (x) * 2)
232cae8c07SFlorian Fainelli #define B53_SERDES_DIGITAL_CONTROL(x) (0x1e + (x) * 2)
240e01491dSFlorian Fainelli #define B53_SERDES_DIGITAL_STATUS 0x28
250e01491dSFlorian Fainelli
260e01491dSFlorian Fainelli /* SERDES_DIGITAL_CONTROL1 */
270e01491dSFlorian Fainelli #define FIBER_MODE_1000X BIT(0)
280e01491dSFlorian Fainelli #define TBI_INTERFACE BIT(1)
290e01491dSFlorian Fainelli #define SIGNAL_DETECT_EN BIT(2)
300e01491dSFlorian Fainelli #define INVERT_SIGNAL_DETECT BIT(3)
310e01491dSFlorian Fainelli #define AUTODET_EN BIT(4)
320e01491dSFlorian Fainelli #define SGMII_MASTER_MODE BIT(5)
330e01491dSFlorian Fainelli #define DISABLE_DLL_PWRDOWN BIT(6)
340e01491dSFlorian Fainelli #define CRC_CHECKER_DIS BIT(7)
350e01491dSFlorian Fainelli #define COMMA_DET_EN BIT(8)
360e01491dSFlorian Fainelli #define ZERO_COMMA_DET_EN BIT(9)
370e01491dSFlorian Fainelli #define REMOTE_LOOPBACK BIT(10)
380e01491dSFlorian Fainelli #define SEL_RX_PKTS_FOR_CNTR BIT(11)
390e01491dSFlorian Fainelli #define MASTER_MDIO_PHY_SEL BIT(13)
400e01491dSFlorian Fainelli #define DISABLE_SIGNAL_DETECT_FLT BIT(14)
410e01491dSFlorian Fainelli
420e01491dSFlorian Fainelli /* SERDES_DIGITAL_CONTROL2 */
430e01491dSFlorian Fainelli #define EN_PARALLEL_DET BIT(0)
440e01491dSFlorian Fainelli #define DIS_FALSE_LINK BIT(1)
450e01491dSFlorian Fainelli #define FLT_FORCE_LINK BIT(2)
460e01491dSFlorian Fainelli #define EN_AUTONEG_ERR_TIMER BIT(3)
470e01491dSFlorian Fainelli #define DIS_REMOTE_FAULT_SENSING BIT(4)
480e01491dSFlorian Fainelli #define FORCE_XMIT_DATA BIT(5)
490e01491dSFlorian Fainelli #define AUTONEG_FAST_TIMERS BIT(6)
500e01491dSFlorian Fainelli #define DIS_CARRIER_EXTEND BIT(7)
510e01491dSFlorian Fainelli #define DIS_TRRR_GENERATION BIT(8)
520e01491dSFlorian Fainelli #define BYPASS_PCS_RX BIT(9)
530e01491dSFlorian Fainelli #define BYPASS_PCS_TX BIT(10)
540e01491dSFlorian Fainelli #define TEST_CNTR_EN BIT(11)
550e01491dSFlorian Fainelli #define TX_PACKET_SEQ_TEST BIT(12)
560e01491dSFlorian Fainelli #define TX_IDLE_JAM_SEQ_TEST BIT(13)
570e01491dSFlorian Fainelli #define CLR_BER_CNTR BIT(14)
580e01491dSFlorian Fainelli
590e01491dSFlorian Fainelli /* SERDES_DIGITAL_CONTROL3 */
600e01491dSFlorian Fainelli #define TX_FIFO_RST BIT(0)
610e01491dSFlorian Fainelli #define FIFO_ELAST_TX_RX_SHIFT 1
620e01491dSFlorian Fainelli #define FIFO_ELAST_TX_RX_5K 0
630e01491dSFlorian Fainelli #define FIFO_ELAST_TX_RX_10K 1
640e01491dSFlorian Fainelli #define FIFO_ELAST_TX_RX_13_5K 2
650e01491dSFlorian Fainelli #define FIFO_ELAST_TX_RX_18_5K 3
660e01491dSFlorian Fainelli #define BLOCK_TXEN_MODE BIT(9)
670e01491dSFlorian Fainelli #define JAM_FALSE_CARRIER_MODE BIT(10)
680e01491dSFlorian Fainelli #define EXT_PHY_CRS_MODE BIT(11)
690e01491dSFlorian Fainelli #define INVERT_EXT_PHY_CRS BIT(12)
700e01491dSFlorian Fainelli #define DISABLE_TX_CRS BIT(13)
710e01491dSFlorian Fainelli
720e01491dSFlorian Fainelli /* SERDES_DIGITAL_STATUS */
730e01491dSFlorian Fainelli #define SGMII_MODE BIT(0)
740e01491dSFlorian Fainelli #define LINK_STATUS BIT(1)
750e01491dSFlorian Fainelli #define DUPLEX_STATUS BIT(2)
760e01491dSFlorian Fainelli #define SPEED_STATUS_SHIFT 3
770e01491dSFlorian Fainelli #define SPEED_STATUS_10 0
780e01491dSFlorian Fainelli #define SPEED_STATUS_100 1
790e01491dSFlorian Fainelli #define SPEED_STATUS_1000 2
800e01491dSFlorian Fainelli #define SPEED_STATUS_2500 3
810e01491dSFlorian Fainelli #define SPEED_STATUS_MASK SPEED_STATUS_2500
820e01491dSFlorian Fainelli #define PAUSE_RESOLUTION_TX_SIDE BIT(5)
830e01491dSFlorian Fainelli #define PAUSE_RESOLUTION_RX_SIDE BIT(6)
840e01491dSFlorian Fainelli #define LINK_STATUS_CHANGE BIT(7)
850e01491dSFlorian Fainelli #define EARLY_END_EXT_DET BIT(8)
860e01491dSFlorian Fainelli #define CARRIER_EXT_ERR_DET BIT(9)
870e01491dSFlorian Fainelli #define RX_ERR_DET BIT(10)
880e01491dSFlorian Fainelli #define TX_ERR_DET BIT(11)
890e01491dSFlorian Fainelli #define CRC_ERR_DET BIT(12)
900e01491dSFlorian Fainelli #define FALSE_CARRIER_ERR_DET BIT(13)
910e01491dSFlorian Fainelli #define RXFIFO_ERR_DET BIT(14)
920e01491dSFlorian Fainelli #define TXFIFO_ERR_DET BIT(15)
930e01491dSFlorian Fainelli
940e01491dSFlorian Fainelli /* Block offsets */
950e01491dSFlorian Fainelli #define SERDES_DIGITAL_BLK 0x8300
960e01491dSFlorian Fainelli #define SERDES_ID0 0x8310
970e01491dSFlorian Fainelli #define SERDES_MII_BLK 0xffe0
980e01491dSFlorian Fainelli #define SERDES_XGXSBLK0_BLOCKADDRESS 0xffd0
990e01491dSFlorian Fainelli
1000e01491dSFlorian Fainelli struct phylink_link_state;
1010e01491dSFlorian Fainelli
b53_serdes_map_lane(struct b53_device * dev,int port)1020e01491dSFlorian Fainelli static inline u8 b53_serdes_map_lane(struct b53_device *dev, int port)
1030e01491dSFlorian Fainelli {
1040e01491dSFlorian Fainelli if (!dev->ops->serdes_map_lane)
1050e01491dSFlorian Fainelli return B53_INVALID_LANE;
1060e01491dSFlorian Fainelli
1070e01491dSFlorian Fainelli return dev->ops->serdes_map_lane(dev, port);
1080e01491dSFlorian Fainelli }
1090e01491dSFlorian Fainelli
1100e01491dSFlorian Fainelli void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
1110e01491dSFlorian Fainelli phy_interface_t interface, bool link_up);
11279396934SRussell King (Oracle) struct phylink_pcs *b53_serdes_phylink_mac_select_pcs(struct b53_device *dev,
11379396934SRussell King (Oracle) int port,
11479396934SRussell King (Oracle) phy_interface_t interface);
115dda1c257SRussell King (Oracle) void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
116dda1c257SRussell King (Oracle) struct phylink_config *config);
1177a8c7f5cSFlorian Fainelli #if IS_ENABLED(CONFIG_B53_SERDES)
1180e01491dSFlorian Fainelli int b53_serdes_init(struct b53_device *dev, int port);
1197a8c7f5cSFlorian Fainelli #else
b53_serdes_init(struct b53_device * dev,int port)1207a8c7f5cSFlorian Fainelli static inline int b53_serdes_init(struct b53_device *dev, int port)
1217a8c7f5cSFlorian Fainelli {
1227a8c7f5cSFlorian Fainelli return -ENODEV;
1237a8c7f5cSFlorian Fainelli }
1247a8c7f5cSFlorian Fainelli #endif
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