1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 2 /* 3 * Northstar Plus switch SerDes/SGMII PHY main logic 4 * 5 * Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/delay.h> 11 #include <linux/kernel.h> 12 #include <linux/phy.h> 13 #include <linux/phylink.h> 14 #include <net/dsa.h> 15 16 #include "b53_priv.h" 17 #include "b53_serdes.h" 18 #include "b53_regs.h" 19 20 static void b53_serdes_write_blk(struct b53_device *dev, u8 offset, u16 block, 21 u16 value) 22 { 23 b53_write16(dev, B53_SERDES_PAGE, B53_SERDES_BLKADDR, block); 24 b53_write16(dev, B53_SERDES_PAGE, offset, value); 25 } 26 27 static u16 b53_serdes_read_blk(struct b53_device *dev, u8 offset, u16 block) 28 { 29 u16 value; 30 31 b53_write16(dev, B53_SERDES_PAGE, B53_SERDES_BLKADDR, block); 32 b53_read16(dev, B53_SERDES_PAGE, offset, &value); 33 34 return value; 35 } 36 37 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) 38 { 39 if (dev->serdes_lane == lane) 40 return; 41 42 WARN_ON(lane > 1); 43 44 b53_serdes_write_blk(dev, B53_SERDES_LANE, 45 SERDES_XGXSBLK0_BLOCKADDRESS, lane); 46 dev->serdes_lane = lane; 47 } 48 49 static void b53_serdes_write(struct b53_device *dev, u8 lane, 50 u8 offset, u16 block, u16 value) 51 { 52 b53_serdes_set_lane(dev, lane); 53 b53_serdes_write_blk(dev, offset, block, value); 54 } 55 56 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, 57 u8 offset, u16 block) 58 { 59 b53_serdes_set_lane(dev, lane); 60 return b53_serdes_read_blk(dev, offset, block); 61 } 62 63 void b53_serdes_config(struct b53_device *dev, int port, unsigned int mode, 64 const struct phylink_link_state *state) 65 { 66 u8 lane = b53_serdes_map_lane(dev, port); 67 u16 reg; 68 69 if (lane == B53_INVALID_LANE) 70 return; 71 72 reg = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_CONTROL(1), 73 SERDES_DIGITAL_BLK); 74 if (state->interface == PHY_INTERFACE_MODE_1000BASEX) 75 reg |= FIBER_MODE_1000X; 76 else 77 reg &= ~FIBER_MODE_1000X; 78 b53_serdes_write(dev, lane, B53_SERDES_DIGITAL_CONTROL(1), 79 SERDES_DIGITAL_BLK, reg); 80 } 81 EXPORT_SYMBOL(b53_serdes_config); 82 83 void b53_serdes_an_restart(struct b53_device *dev, int port) 84 { 85 u8 lane = b53_serdes_map_lane(dev, port); 86 u16 reg; 87 88 if (lane == B53_INVALID_LANE) 89 return; 90 91 reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR), 92 SERDES_MII_BLK); 93 reg |= BMCR_ANRESTART; 94 b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR), 95 SERDES_MII_BLK, reg); 96 } 97 EXPORT_SYMBOL(b53_serdes_an_restart); 98 99 int b53_serdes_link_state(struct b53_device *dev, int port, 100 struct phylink_link_state *state) 101 { 102 u8 lane = b53_serdes_map_lane(dev, port); 103 u16 dig, bmcr, bmsr; 104 105 if (lane == B53_INVALID_LANE) 106 return 1; 107 108 dig = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_STATUS, 109 SERDES_DIGITAL_BLK); 110 bmcr = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR), 111 SERDES_MII_BLK); 112 bmsr = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMSR), 113 SERDES_MII_BLK); 114 115 switch ((dig >> SPEED_STATUS_SHIFT) & SPEED_STATUS_MASK) { 116 case SPEED_STATUS_10: 117 state->speed = SPEED_10; 118 break; 119 case SPEED_STATUS_100: 120 state->speed = SPEED_100; 121 break; 122 case SPEED_STATUS_1000: 123 state->speed = SPEED_1000; 124 break; 125 default: 126 case SPEED_STATUS_2500: 127 state->speed = SPEED_2500; 128 break; 129 } 130 131 state->duplex = dig & DUPLEX_STATUS ? DUPLEX_FULL : DUPLEX_HALF; 132 state->an_enabled = !!(bmcr & BMCR_ANENABLE); 133 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE); 134 state->link = !!(dig & LINK_STATUS); 135 if (dig & PAUSE_RESOLUTION_RX_SIDE) 136 state->pause |= MLO_PAUSE_RX; 137 if (dig & PAUSE_RESOLUTION_TX_SIDE) 138 state->pause |= MLO_PAUSE_TX; 139 140 return 0; 141 } 142 EXPORT_SYMBOL(b53_serdes_link_state); 143 144 void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode, 145 phy_interface_t interface, bool link_up) 146 { 147 u8 lane = b53_serdes_map_lane(dev, port); 148 u16 reg; 149 150 if (lane == B53_INVALID_LANE) 151 return; 152 153 reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR), 154 SERDES_MII_BLK); 155 if (link_up) 156 reg &= ~BMCR_PDOWN; 157 else 158 reg |= BMCR_PDOWN; 159 b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR), 160 SERDES_MII_BLK, reg); 161 } 162 EXPORT_SYMBOL(b53_serdes_link_set); 163 164 void b53_serdes_phylink_validate(struct b53_device *dev, int port, 165 unsigned long *supported, 166 struct phylink_link_state *state) 167 { 168 u8 lane = b53_serdes_map_lane(dev, port); 169 170 if (lane == B53_INVALID_LANE) 171 return; 172 173 switch (lane) { 174 case 0: 175 phylink_set(supported, 2500baseX_Full); 176 /* fallthrough */ 177 case 1: 178 phylink_set(supported, 1000baseX_Full); 179 break; 180 default: 181 break; 182 } 183 } 184 EXPORT_SYMBOL(b53_serdes_phylink_validate); 185 186 int b53_serdes_init(struct b53_device *dev, int port) 187 { 188 u8 lane = b53_serdes_map_lane(dev, port); 189 u16 id0, msb, lsb; 190 191 if (lane == B53_INVALID_LANE) 192 return -EINVAL; 193 194 id0 = b53_serdes_read(dev, lane, B53_SERDES_ID0, SERDES_ID0); 195 msb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID1), 196 SERDES_MII_BLK); 197 lsb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID2), 198 SERDES_MII_BLK); 199 if (id0 == 0 || id0 == 0xffff) { 200 dev_err(dev->dev, "SerDes not initialized, check settings\n"); 201 return -ENODEV; 202 } 203 204 dev_info(dev->dev, 205 "SerDes lane %d, model: %d, rev %c%d (OUI: 0x%08x)\n", 206 lane, id0 & SERDES_ID0_MODEL_MASK, 207 (id0 >> SERDES_ID0_REV_LETTER_SHIFT) + 0x41, 208 (id0 >> SERDES_ID0_REV_NUM_SHIFT) & SERDES_ID0_REV_NUM_MASK, 209 (u32)msb << 16 | lsb); 210 211 return 0; 212 } 213 EXPORT_SYMBOL(b53_serdes_init); 214 215 MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>"); 216 MODULE_DESCRIPTION("B53 Switch SerDes driver"); 217 MODULE_LICENSE("Dual BSD/GPL"); 218