1 /* 2 * B53 register definitions 3 * 4 * Copyright (C) 2004 Broadcom Corporation 5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef __B53_REGS_H 21 #define __B53_REGS_H 22 23 /* Management Port (SMP) Page offsets */ 24 #define B53_CTRL_PAGE 0x00 /* Control */ 25 #define B53_STAT_PAGE 0x01 /* Status */ 26 #define B53_MGMT_PAGE 0x02 /* Management Mode */ 27 #define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */ 28 #define B53_ARLCTRL_PAGE 0x04 /* ARL Control */ 29 #define B53_ARLIO_PAGE 0x05 /* ARL Access */ 30 #define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */ 31 #define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */ 32 33 /* PHY Registers */ 34 #define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */ 35 #define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */ 36 #define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */ 37 38 /* MIB registers */ 39 #define B53_MIB_PAGE(i) (0x20 + (i)) 40 41 /* Quality of Service (QoS) Registers */ 42 #define B53_QOS_PAGE 0x30 43 44 /* Port VLAN Page */ 45 #define B53_PVLAN_PAGE 0x31 46 47 /* VLAN Registers */ 48 #define B53_VLAN_PAGE 0x34 49 50 /* Jumbo Frame Registers */ 51 #define B53_JUMBO_PAGE 0x40 52 53 /* CFP Configuration Registers Page */ 54 #define B53_CFP_PAGE 0xa1 55 56 /************************************************************************* 57 * Control Page registers 58 *************************************************************************/ 59 60 /* Port Control Register (8 bit) */ 61 #define B53_PORT_CTRL(i) (0x00 + (i)) 62 #define PORT_CTRL_RX_DISABLE BIT(0) 63 #define PORT_CTRL_TX_DISABLE BIT(1) 64 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */ 65 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */ 66 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */ 67 #define PORT_CTRL_STP_STATE_S 5 68 #define PORT_CTRL_NO_STP (0 << PORT_CTRL_STP_STATE_S) 69 #define PORT_CTRL_DIS_STATE (1 << PORT_CTRL_STP_STATE_S) 70 #define PORT_CTRL_BLOCK_STATE (2 << PORT_CTRL_STP_STATE_S) 71 #define PORT_CTRL_LISTEN_STATE (3 << PORT_CTRL_STP_STATE_S) 72 #define PORT_CTRL_LEARN_STATE (4 << PORT_CTRL_STP_STATE_S) 73 #define PORT_CTRL_FWD_STATE (5 << PORT_CTRL_STP_STATE_S) 74 #define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S) 75 76 /* SMP Control Register (8 bit) */ 77 #define B53_SMP_CTRL 0x0a 78 79 /* Switch Mode Control Register (8 bit) */ 80 #define B53_SWITCH_MODE 0x0b 81 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */ 82 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */ 83 84 /* IMP Port state override register (8 bit) */ 85 #define B53_PORT_OVERRIDE_CTRL 0x0e 86 #define PORT_OVERRIDE_LINK BIT(0) 87 #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ 88 #define PORT_OVERRIDE_SPEED_S 2 89 #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S) 90 #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S) 91 #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S) 92 #define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */ 93 #define PORT_OVERRIDE_RX_FLOW BIT(4) 94 #define PORT_OVERRIDE_TX_FLOW BIT(5) 95 #define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */ 96 #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */ 97 98 /* Power-down mode control */ 99 #define B53_PD_MODE_CTRL_25 0x0f 100 101 /* IP Multicast control (8 bit) */ 102 #define B53_IP_MULTICAST_CTRL 0x21 103 #define B53_IPMC_FWD_EN BIT(1) 104 #define B53_UC_FWD_EN BIT(6) 105 #define B53_MC_FWD_EN BIT(7) 106 107 /* (16 bit) */ 108 #define B53_UC_FLOOD_MASK 0x32 109 #define B53_MC_FLOOD_MASK 0x34 110 #define B53_IPMC_FLOOD_MASK 0x36 111 112 /* 113 * Override Ports 0-7 State on devices with xMII interfaces (8 bit) 114 * 115 * For port 8 still use B53_PORT_OVERRIDE_CTRL 116 * Please note that not all ports are available on every hardware, e.g. BCM5301X 117 * don't include overriding port 6, BCM63xx also have some limitations. 118 */ 119 #define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i)) 120 #define GMII_PO_LINK BIT(0) 121 #define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ 122 #define GMII_PO_SPEED_S 2 123 #define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S) 124 #define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S) 125 #define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S) 126 #define GMII_PO_RX_FLOW BIT(4) 127 #define GMII_PO_TX_FLOW BIT(5) 128 #define GMII_PO_EN BIT(6) /* Use the register contents */ 129 #define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */ 130 131 #define B53_RGMII_CTRL_IMP 0x60 132 #define RGMII_CTRL_ENABLE_GMII BIT(7) 133 #define RGMII_CTRL_TIMING_SEL BIT(2) 134 #define RGMII_CTRL_DLL_RXC BIT(1) 135 #define RGMII_CTRL_DLL_TXC BIT(0) 136 137 #define B53_RGMII_CTRL_P(i) (B53_RGMII_CTRL_IMP + (i)) 138 139 /* Software reset register (8 bit) */ 140 #define B53_SOFTRESET 0x79 141 #define SW_RST BIT(7) 142 #define EN_SW_RST BIT(4) 143 144 /* Fast Aging Control register (8 bit) */ 145 #define B53_FAST_AGE_CTRL 0x88 146 #define FAST_AGE_STATIC BIT(0) 147 #define FAST_AGE_DYNAMIC BIT(1) 148 #define FAST_AGE_PORT BIT(2) 149 #define FAST_AGE_VLAN BIT(3) 150 #define FAST_AGE_STP BIT(4) 151 #define FAST_AGE_MC BIT(5) 152 #define FAST_AGE_DONE BIT(7) 153 154 /* Fast Aging Port Control register (8 bit) */ 155 #define B53_FAST_AGE_PORT_CTRL 0x89 156 157 /* Fast Aging VID Control register (16 bit) */ 158 #define B53_FAST_AGE_VID_CTRL 0x8a 159 160 /************************************************************************* 161 * Status Page registers 162 *************************************************************************/ 163 164 /* Link Status Summary Register (16bit) */ 165 #define B53_LINK_STAT 0x00 166 167 /* Link Status Change Register (16 bit) */ 168 #define B53_LINK_STAT_CHANGE 0x02 169 170 /* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */ 171 #define B53_SPEED_STAT 0x04 172 #define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1) 173 #define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3) 174 #define SPEED_STAT_10M 0 175 #define SPEED_STAT_100M 1 176 #define SPEED_STAT_1000M 2 177 178 /* Duplex Status Summary (16 bit) */ 179 #define B53_DUPLEX_STAT_FE 0x06 180 #define B53_DUPLEX_STAT_GE 0x08 181 #define B53_DUPLEX_STAT_63XX 0x0c 182 183 /* Revision ID register for BCM5325 */ 184 #define B53_REV_ID_25 0x50 185 186 /* Strap Value (48 bit) */ 187 #define B53_STRAP_VALUE 0x70 188 #define SV_GMII_CTRL_115 BIT(27) 189 190 /************************************************************************* 191 * Management Mode Page Registers 192 *************************************************************************/ 193 194 /* Global Management Config Register (8 bit) */ 195 #define B53_GLOBAL_CONFIG 0x00 196 #define GC_RESET_MIB 0x01 197 #define GC_RX_BPDU_EN 0x02 198 #define GC_MIB_AC_HDR_EN 0x10 199 #define GC_MIB_AC_EN 0x20 200 #define GC_FRM_MGMT_PORT_M 0xC0 201 #define GC_FRM_MGMT_PORT_04 0x00 202 #define GC_FRM_MGMT_PORT_MII 0x80 203 204 /* Broadcom Header control register (8 bit) */ 205 #define B53_BRCM_HDR 0x03 206 #define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */ 207 #define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */ 208 209 /* Device ID register (8 or 32 bit) */ 210 #define B53_DEVICE_ID 0x30 211 212 /* Revision ID register (8 bit) */ 213 #define B53_REV_ID 0x40 214 215 /************************************************************************* 216 * ARL Access Page Registers 217 *************************************************************************/ 218 219 /* VLAN Table Access Register (8 bit) */ 220 #define B53_VT_ACCESS 0x80 221 #define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */ 222 #define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */ 223 #define VTA_CMD_WRITE 0 224 #define VTA_CMD_READ 1 225 #define VTA_CMD_CLEAR 2 226 #define VTA_START_CMD BIT(7) 227 228 /* VLAN Table Index Register (16 bit) */ 229 #define B53_VT_INDEX 0x81 230 #define B53_VT_INDEX_9798 0x61 231 #define B53_VT_INDEX_63XX 0x62 232 233 /* VLAN Table Entry Register (32 bit) */ 234 #define B53_VT_ENTRY 0x83 235 #define B53_VT_ENTRY_9798 0x63 236 #define B53_VT_ENTRY_63XX 0x64 237 #define VTE_MEMBERS 0x1ff 238 #define VTE_UNTAG_S 9 239 #define VTE_UNTAG (0x1ff << 9) 240 241 /************************************************************************* 242 * ARL I/O Registers 243 *************************************************************************/ 244 245 /* ARL Table Read/Write Register (8 bit) */ 246 #define B53_ARLTBL_RW_CTRL 0x00 247 #define ARLTBL_RW BIT(0) 248 #define ARLTBL_START_DONE BIT(7) 249 250 /* MAC Address Index Register (48 bit) */ 251 #define B53_MAC_ADDR_IDX 0x02 252 253 /* VLAN ID Index Register (16 bit) */ 254 #define B53_VLAN_ID_IDX 0x08 255 256 /* ARL Table MAC/VID Entry N Registers (64 bit) 257 * 258 * BCM5325 and BCM5365 share most definitions below 259 */ 260 #define B53_ARLTBL_MAC_VID_ENTRY(n) (0x10 * (n)) 261 #define ARLTBL_MAC_MASK 0xffffffffffffULL 262 #define ARLTBL_VID_S 48 263 #define ARLTBL_VID_MASK_25 0xff 264 #define ARLTBL_VID_MASK 0xfff 265 #define ARLTBL_DATA_PORT_ID_S_25 48 266 #define ARLTBL_DATA_PORT_ID_MASK_25 0xf 267 #define ARLTBL_AGE_25 BIT(61) 268 #define ARLTBL_STATIC_25 BIT(62) 269 #define ARLTBL_VALID_25 BIT(63) 270 271 /* ARL Table Data Entry N Registers (32 bit) */ 272 #define B53_ARLTBL_DATA_ENTRY(n) ((0x10 * (n)) + 0x08) 273 #define ARLTBL_DATA_PORT_ID_MASK 0x1ff 274 #define ARLTBL_TC(tc) ((3 & tc) << 11) 275 #define ARLTBL_AGE BIT(14) 276 #define ARLTBL_STATIC BIT(15) 277 #define ARLTBL_VALID BIT(16) 278 279 /* ARL Search Control Register (8 bit) */ 280 #define B53_ARL_SRCH_CTL 0x50 281 #define B53_ARL_SRCH_CTL_25 0x20 282 #define ARL_SRCH_VLID BIT(0) 283 #define ARL_SRCH_STDN BIT(7) 284 285 /* ARL Search Address Register (16 bit) */ 286 #define B53_ARL_SRCH_ADDR 0x51 287 #define B53_ARL_SRCH_ADDR_25 0x22 288 #define B53_ARL_SRCH_ADDR_65 0x24 289 #define ARL_ADDR_MASK GENMASK(14, 0) 290 291 /* ARL Search MAC/VID Result (64 bit) */ 292 #define B53_ARL_SRCH_RSTL_0_MACVID 0x60 293 294 /* Single register search result on 5325 */ 295 #define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24 296 /* Single register search result on 5365 */ 297 #define B53_ARL_SRCH_RSTL_0_MACVID_65 0x30 298 299 /* ARL Search Data Result (32 bit) */ 300 #define B53_ARL_SRCH_RSTL_0 0x68 301 302 #define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10)) 303 #define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10)) 304 305 /************************************************************************* 306 * Port VLAN Registers 307 *************************************************************************/ 308 309 /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */ 310 #define B53_PVLAN_PORT_MASK(i) ((i) * 2) 311 312 /************************************************************************* 313 * 802.1Q Page Registers 314 *************************************************************************/ 315 316 /* Global QoS Control (8 bit) */ 317 #define B53_QOS_GLOBAL_CTL 0x00 318 319 /* Enable 802.1Q for individual Ports (16 bit) */ 320 #define B53_802_1P_EN 0x04 321 322 /************************************************************************* 323 * VLAN Page Registers 324 *************************************************************************/ 325 326 /* VLAN Control 0 (8 bit) */ 327 #define B53_VLAN_CTRL0 0x00 328 #define VC0_8021PF_CTRL_MASK 0x3 329 #define VC0_8021PF_CTRL_NONE 0x0 330 #define VC0_8021PF_CTRL_CHANGE_PRI 0x1 331 #define VC0_8021PF_CTRL_CHANGE_VID 0x2 332 #define VC0_8021PF_CTRL_CHANGE_BOTH 0x3 333 #define VC0_8021QF_CTRL_MASK 0xc 334 #define VC0_8021QF_CTRL_CHANGE_PRI 0x1 335 #define VC0_8021QF_CTRL_CHANGE_VID 0x2 336 #define VC0_8021QF_CTRL_CHANGE_BOTH 0x3 337 #define VC0_RESERVED_1 BIT(1) 338 #define VC0_DROP_VID_MISS BIT(4) 339 #define VC0_VID_HASH_VID BIT(5) 340 #define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */ 341 #define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */ 342 343 /* VLAN Control 1 (8 bit) */ 344 #define B53_VLAN_CTRL1 0x01 345 #define VC1_RX_MCST_TAG_EN BIT(1) 346 #define VC1_RX_MCST_FWD_EN BIT(2) 347 #define VC1_RX_MCST_UNTAG_EN BIT(3) 348 349 /* VLAN Control 2 (8 bit) */ 350 #define B53_VLAN_CTRL2 0x02 351 352 /* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */ 353 #define B53_VLAN_CTRL3 0x03 354 #define B53_VLAN_CTRL3_63XX 0x04 355 #define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */ 356 #define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */ 357 358 /* VLAN Control 4 (8 bit) */ 359 #define B53_VLAN_CTRL4 0x05 360 #define B53_VLAN_CTRL4_25 0x04 361 #define B53_VLAN_CTRL4_63XX 0x06 362 #define VC4_ING_VID_CHECK_S 6 363 #define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S) 364 #define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */ 365 #define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */ 366 #define VC4_NO_ING_VID_CHK 2 /* do not check */ 367 #define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */ 368 369 /* VLAN Control 5 (8 bit) */ 370 #define B53_VLAN_CTRL5 0x06 371 #define B53_VLAN_CTRL5_25 0x05 372 #define B53_VLAN_CTRL5_63XX 0x07 373 #define VC5_VID_FFF_EN BIT(2) 374 #define VC5_DROP_VTABLE_MISS BIT(3) 375 376 /* VLAN Control 6 (8 bit) */ 377 #define B53_VLAN_CTRL6 0x07 378 #define B53_VLAN_CTRL6_63XX 0x08 379 380 /* VLAN Table Access Register (16 bit) */ 381 #define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */ 382 #define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */ 383 #define VTA_VID_LOW_MASK_25 0xf 384 #define VTA_VID_LOW_MASK_65 0xff 385 #define VTA_VID_HIGH_S_25 4 386 #define VTA_VID_HIGH_S_65 8 387 #define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E) 388 #define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65) 389 #define VTA_RW_STATE BIT(12) 390 #define VTA_RW_STATE_RD 0 391 #define VTA_RW_STATE_WR BIT(12) 392 #define VTA_RW_OP_EN BIT(13) 393 394 /* VLAN Read/Write Registers for (16/32 bit) */ 395 #define B53_VLAN_WRITE_25 0x08 396 #define B53_VLAN_WRITE_65 0x0a 397 #define B53_VLAN_READ 0x0c 398 #define VA_MEMBER_MASK 0x3f 399 #define VA_UNTAG_S_25 6 400 #define VA_UNTAG_MASK_25 0x3f 401 #define VA_UNTAG_S_65 7 402 #define VA_UNTAG_MASK_65 0x1f 403 #define VA_VID_HIGH_S 12 404 #define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S) 405 #define VA_VALID_25 BIT(20) 406 #define VA_VALID_25_R4 BIT(24) 407 #define VA_VALID_65 BIT(14) 408 409 /* VLAN Port Default Tag (16 bit) */ 410 #define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i)) 411 412 /************************************************************************* 413 * Jumbo Frame Page Registers 414 *************************************************************************/ 415 416 /* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */ 417 #define B53_JUMBO_PORT_MASK 0x01 418 #define B53_JUMBO_PORT_MASK_63XX 0x04 419 #define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */ 420 421 /* Good Frame Max Size without 802.1Q TAG (16 bit) */ 422 #define B53_JUMBO_MAX_SIZE 0x05 423 #define B53_JUMBO_MAX_SIZE_63XX 0x08 424 #define JMS_MIN_SIZE 1518 425 #define JMS_MAX_SIZE 9724 426 427 /************************************************************************* 428 * CFP Configuration Page Registers 429 *************************************************************************/ 430 431 /* CFP Control Register with ports map (8 bit) */ 432 #define B53_CFP_CTRL 0x00 433 434 #endif /* !__B53_REGS_H */ 435