1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if_bridge.h> 32 #include <net/dsa.h> 33 34 #include "b53_regs.h" 35 #include "b53_priv.h" 36 37 struct b53_mib_desc { 38 u8 size; 39 u8 offset; 40 const char *name; 41 }; 42 43 /* BCM5365 MIB counters */ 44 static const struct b53_mib_desc b53_mibs_65[] = { 45 { 8, 0x00, "TxOctets" }, 46 { 4, 0x08, "TxDropPkts" }, 47 { 4, 0x10, "TxBroadcastPkts" }, 48 { 4, 0x14, "TxMulticastPkts" }, 49 { 4, 0x18, "TxUnicastPkts" }, 50 { 4, 0x1c, "TxCollisions" }, 51 { 4, 0x20, "TxSingleCollision" }, 52 { 4, 0x24, "TxMultipleCollision" }, 53 { 4, 0x28, "TxDeferredTransmit" }, 54 { 4, 0x2c, "TxLateCollision" }, 55 { 4, 0x30, "TxExcessiveCollision" }, 56 { 4, 0x38, "TxPausePkts" }, 57 { 8, 0x44, "RxOctets" }, 58 { 4, 0x4c, "RxUndersizePkts" }, 59 { 4, 0x50, "RxPausePkts" }, 60 { 4, 0x54, "Pkts64Octets" }, 61 { 4, 0x58, "Pkts65to127Octets" }, 62 { 4, 0x5c, "Pkts128to255Octets" }, 63 { 4, 0x60, "Pkts256to511Octets" }, 64 { 4, 0x64, "Pkts512to1023Octets" }, 65 { 4, 0x68, "Pkts1024to1522Octets" }, 66 { 4, 0x6c, "RxOversizePkts" }, 67 { 4, 0x70, "RxJabbers" }, 68 { 4, 0x74, "RxAlignmentErrors" }, 69 { 4, 0x78, "RxFCSErrors" }, 70 { 8, 0x7c, "RxGoodOctets" }, 71 { 4, 0x84, "RxDropPkts" }, 72 { 4, 0x88, "RxUnicastPkts" }, 73 { 4, 0x8c, "RxMulticastPkts" }, 74 { 4, 0x90, "RxBroadcastPkts" }, 75 { 4, 0x94, "RxSAChanges" }, 76 { 4, 0x98, "RxFragments" }, 77 }; 78 79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 80 81 /* BCM63xx MIB counters */ 82 static const struct b53_mib_desc b53_mibs_63xx[] = { 83 { 8, 0x00, "TxOctets" }, 84 { 4, 0x08, "TxDropPkts" }, 85 { 4, 0x0c, "TxQoSPkts" }, 86 { 4, 0x10, "TxBroadcastPkts" }, 87 { 4, 0x14, "TxMulticastPkts" }, 88 { 4, 0x18, "TxUnicastPkts" }, 89 { 4, 0x1c, "TxCollisions" }, 90 { 4, 0x20, "TxSingleCollision" }, 91 { 4, 0x24, "TxMultipleCollision" }, 92 { 4, 0x28, "TxDeferredTransmit" }, 93 { 4, 0x2c, "TxLateCollision" }, 94 { 4, 0x30, "TxExcessiveCollision" }, 95 { 4, 0x38, "TxPausePkts" }, 96 { 8, 0x3c, "TxQoSOctets" }, 97 { 8, 0x44, "RxOctets" }, 98 { 4, 0x4c, "RxUndersizePkts" }, 99 { 4, 0x50, "RxPausePkts" }, 100 { 4, 0x54, "Pkts64Octets" }, 101 { 4, 0x58, "Pkts65to127Octets" }, 102 { 4, 0x5c, "Pkts128to255Octets" }, 103 { 4, 0x60, "Pkts256to511Octets" }, 104 { 4, 0x64, "Pkts512to1023Octets" }, 105 { 4, 0x68, "Pkts1024to1522Octets" }, 106 { 4, 0x6c, "RxOversizePkts" }, 107 { 4, 0x70, "RxJabbers" }, 108 { 4, 0x74, "RxAlignmentErrors" }, 109 { 4, 0x78, "RxFCSErrors" }, 110 { 8, 0x7c, "RxGoodOctets" }, 111 { 4, 0x84, "RxDropPkts" }, 112 { 4, 0x88, "RxUnicastPkts" }, 113 { 4, 0x8c, "RxMulticastPkts" }, 114 { 4, 0x90, "RxBroadcastPkts" }, 115 { 4, 0x94, "RxSAChanges" }, 116 { 4, 0x98, "RxFragments" }, 117 { 4, 0xa0, "RxSymbolErrors" }, 118 { 4, 0xa4, "RxQoSPkts" }, 119 { 8, 0xa8, "RxQoSOctets" }, 120 { 4, 0xb0, "Pkts1523to2047Octets" }, 121 { 4, 0xb4, "Pkts2048to4095Octets" }, 122 { 4, 0xb8, "Pkts4096to8191Octets" }, 123 { 4, 0xbc, "Pkts8192to9728Octets" }, 124 { 4, 0xc0, "RxDiscarded" }, 125 }; 126 127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 128 129 /* MIB counters */ 130 static const struct b53_mib_desc b53_mibs[] = { 131 { 8, 0x00, "TxOctets" }, 132 { 4, 0x08, "TxDropPkts" }, 133 { 4, 0x10, "TxBroadcastPkts" }, 134 { 4, 0x14, "TxMulticastPkts" }, 135 { 4, 0x18, "TxUnicastPkts" }, 136 { 4, 0x1c, "TxCollisions" }, 137 { 4, 0x20, "TxSingleCollision" }, 138 { 4, 0x24, "TxMultipleCollision" }, 139 { 4, 0x28, "TxDeferredTransmit" }, 140 { 4, 0x2c, "TxLateCollision" }, 141 { 4, 0x30, "TxExcessiveCollision" }, 142 { 4, 0x38, "TxPausePkts" }, 143 { 8, 0x50, "RxOctets" }, 144 { 4, 0x58, "RxUndersizePkts" }, 145 { 4, 0x5c, "RxPausePkts" }, 146 { 4, 0x60, "Pkts64Octets" }, 147 { 4, 0x64, "Pkts65to127Octets" }, 148 { 4, 0x68, "Pkts128to255Octets" }, 149 { 4, 0x6c, "Pkts256to511Octets" }, 150 { 4, 0x70, "Pkts512to1023Octets" }, 151 { 4, 0x74, "Pkts1024to1522Octets" }, 152 { 4, 0x78, "RxOversizePkts" }, 153 { 4, 0x7c, "RxJabbers" }, 154 { 4, 0x80, "RxAlignmentErrors" }, 155 { 4, 0x84, "RxFCSErrors" }, 156 { 8, 0x88, "RxGoodOctets" }, 157 { 4, 0x90, "RxDropPkts" }, 158 { 4, 0x94, "RxUnicastPkts" }, 159 { 4, 0x98, "RxMulticastPkts" }, 160 { 4, 0x9c, "RxBroadcastPkts" }, 161 { 4, 0xa0, "RxSAChanges" }, 162 { 4, 0xa4, "RxFragments" }, 163 { 4, 0xa8, "RxJumboPkts" }, 164 { 4, 0xac, "RxSymbolErrors" }, 165 { 4, 0xc0, "RxDiscarded" }, 166 }; 167 168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 169 170 static const struct b53_mib_desc b53_mibs_58xx[] = { 171 { 8, 0x00, "TxOctets" }, 172 { 4, 0x08, "TxDropPkts" }, 173 { 4, 0x0c, "TxQPKTQ0" }, 174 { 4, 0x10, "TxBroadcastPkts" }, 175 { 4, 0x14, "TxMulticastPkts" }, 176 { 4, 0x18, "TxUnicastPKts" }, 177 { 4, 0x1c, "TxCollisions" }, 178 { 4, 0x20, "TxSingleCollision" }, 179 { 4, 0x24, "TxMultipleCollision" }, 180 { 4, 0x28, "TxDeferredCollision" }, 181 { 4, 0x2c, "TxLateCollision" }, 182 { 4, 0x30, "TxExcessiveCollision" }, 183 { 4, 0x34, "TxFrameInDisc" }, 184 { 4, 0x38, "TxPausePkts" }, 185 { 4, 0x3c, "TxQPKTQ1" }, 186 { 4, 0x40, "TxQPKTQ2" }, 187 { 4, 0x44, "TxQPKTQ3" }, 188 { 4, 0x48, "TxQPKTQ4" }, 189 { 4, 0x4c, "TxQPKTQ5" }, 190 { 8, 0x50, "RxOctets" }, 191 { 4, 0x58, "RxUndersizePkts" }, 192 { 4, 0x5c, "RxPausePkts" }, 193 { 4, 0x60, "RxPkts64Octets" }, 194 { 4, 0x64, "RxPkts65to127Octets" }, 195 { 4, 0x68, "RxPkts128to255Octets" }, 196 { 4, 0x6c, "RxPkts256to511Octets" }, 197 { 4, 0x70, "RxPkts512to1023Octets" }, 198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 199 { 4, 0x78, "RxOversizePkts" }, 200 { 4, 0x7c, "RxJabbers" }, 201 { 4, 0x80, "RxAlignmentErrors" }, 202 { 4, 0x84, "RxFCSErrors" }, 203 { 8, 0x88, "RxGoodOctets" }, 204 { 4, 0x90, "RxDropPkts" }, 205 { 4, 0x94, "RxUnicastPkts" }, 206 { 4, 0x98, "RxMulticastPkts" }, 207 { 4, 0x9c, "RxBroadcastPkts" }, 208 { 4, 0xa0, "RxSAChanges" }, 209 { 4, 0xa4, "RxFragments" }, 210 { 4, 0xa8, "RxJumboPkt" }, 211 { 4, 0xac, "RxSymblErr" }, 212 { 4, 0xb0, "InRangeErrCount" }, 213 { 4, 0xb4, "OutRangeErrCount" }, 214 { 4, 0xb8, "EEELpiEvent" }, 215 { 4, 0xbc, "EEELpiDuration" }, 216 { 4, 0xc0, "RxDiscard" }, 217 { 4, 0xc8, "TxQPKTQ6" }, 218 { 4, 0xcc, "TxQPKTQ7" }, 219 { 4, 0xd0, "TxPkts64Octets" }, 220 { 4, 0xd4, "TxPkts65to127Octets" }, 221 { 4, 0xd8, "TxPkts128to255Octets" }, 222 { 4, 0xdc, "TxPkts256to511Ocets" }, 223 { 4, 0xe0, "TxPkts512to1023Ocets" }, 224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 225 }; 226 227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 228 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 230 { 231 unsigned int i; 232 233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 234 235 for (i = 0; i < 10; i++) { 236 u8 vta; 237 238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 239 if (!(vta & VTA_START_CMD)) 240 return 0; 241 242 usleep_range(100, 200); 243 } 244 245 return -EIO; 246 } 247 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 249 struct b53_vlan *vlan) 250 { 251 if (is5325(dev)) { 252 u32 entry = 0; 253 254 if (vlan->members) { 255 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 256 VA_UNTAG_S_25) | vlan->members; 257 if (dev->core_rev >= 3) 258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 259 else 260 entry |= VA_VALID_25; 261 } 262 263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 265 VTA_RW_STATE_WR | VTA_RW_OP_EN); 266 } else if (is5365(dev)) { 267 u16 entry = 0; 268 269 if (vlan->members) 270 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 272 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 275 VTA_RW_STATE_WR | VTA_RW_OP_EN); 276 } else { 277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 279 (vlan->untag << VTE_UNTAG_S) | vlan->members); 280 281 b53_do_vlan_op(dev, VTA_CMD_WRITE); 282 } 283 284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 285 vid, vlan->members, vlan->untag); 286 } 287 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 289 struct b53_vlan *vlan) 290 { 291 if (is5325(dev)) { 292 u32 entry = 0; 293 294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 295 VTA_RW_STATE_RD | VTA_RW_OP_EN); 296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 297 298 if (dev->core_rev >= 3) 299 vlan->valid = !!(entry & VA_VALID_25_R4); 300 else 301 vlan->valid = !!(entry & VA_VALID_25); 302 vlan->members = entry & VA_MEMBER_MASK; 303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 304 305 } else if (is5365(dev)) { 306 u16 entry = 0; 307 308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 309 VTA_RW_STATE_WR | VTA_RW_OP_EN); 310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 311 312 vlan->valid = !!(entry & VA_VALID_65); 313 vlan->members = entry & VA_MEMBER_MASK; 314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 315 } else { 316 u32 entry = 0; 317 318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 319 b53_do_vlan_op(dev, VTA_CMD_READ); 320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 321 vlan->members = entry & VTE_MEMBERS; 322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 323 vlan->valid = true; 324 } 325 } 326 327 static void b53_set_forwarding(struct b53_device *dev, int enable) 328 { 329 u8 mgmt; 330 331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 332 333 if (enable) 334 mgmt |= SM_SW_FWD_EN; 335 else 336 mgmt &= ~SM_SW_FWD_EN; 337 338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 339 340 /* Include IMP port in dumb forwarding mode 341 */ 342 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 343 mgmt |= B53_MII_DUMB_FWDG_EN; 344 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 345 } 346 347 static void b53_enable_vlan(struct b53_device *dev, bool enable) 348 { 349 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 350 351 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 352 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 353 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 354 355 if (is5325(dev) || is5365(dev)) { 356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 358 } else if (is63xx(dev)) { 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 361 } else { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 364 } 365 366 mgmt &= ~SM_SW_FWD_MODE; 367 368 if (enable) { 369 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 370 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 371 vc4 &= ~VC4_ING_VID_CHECK_MASK; 372 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 373 vc5 |= VC5_DROP_VTABLE_MISS; 374 375 if (is5325(dev)) 376 vc0 &= ~VC0_RESERVED_1; 377 378 if (is5325(dev) || is5365(dev)) 379 vc1 |= VC1_RX_MCST_TAG_EN; 380 381 } else { 382 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 383 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 384 vc4 &= ~VC4_ING_VID_CHECK_MASK; 385 vc5 &= ~VC5_DROP_VTABLE_MISS; 386 387 if (is5325(dev) || is5365(dev)) 388 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 389 else 390 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 391 392 if (is5325(dev) || is5365(dev)) 393 vc1 &= ~VC1_RX_MCST_TAG_EN; 394 } 395 396 if (!is5325(dev) && !is5365(dev)) 397 vc5 &= ~VC5_VID_FFF_EN; 398 399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 400 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 401 402 if (is5325(dev) || is5365(dev)) { 403 /* enable the high 8 bit vid check on 5325 */ 404 if (is5325(dev) && enable) 405 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 406 VC3_HIGH_8BIT_EN); 407 else 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 409 410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 412 } else if (is63xx(dev)) { 413 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 415 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 416 } else { 417 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 420 } 421 422 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 423 } 424 425 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 426 { 427 u32 port_mask = 0; 428 u16 max_size = JMS_MIN_SIZE; 429 430 if (is5325(dev) || is5365(dev)) 431 return -EINVAL; 432 433 if (enable) { 434 port_mask = dev->enabled_ports; 435 max_size = JMS_MAX_SIZE; 436 if (allow_10_100) 437 port_mask |= JPM_10_100_JUMBO_EN; 438 } 439 440 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 441 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 442 } 443 444 static int b53_flush_arl(struct b53_device *dev, u8 mask) 445 { 446 unsigned int i; 447 448 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 449 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 450 451 for (i = 0; i < 10; i++) { 452 u8 fast_age_ctrl; 453 454 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 455 &fast_age_ctrl); 456 457 if (!(fast_age_ctrl & FAST_AGE_DONE)) 458 goto out; 459 460 msleep(1); 461 } 462 463 return -ETIMEDOUT; 464 out: 465 /* Only age dynamic entries (default behavior) */ 466 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 467 return 0; 468 } 469 470 static int b53_fast_age_port(struct b53_device *dev, int port) 471 { 472 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 473 474 return b53_flush_arl(dev, FAST_AGE_PORT); 475 } 476 477 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 478 { 479 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 480 481 return b53_flush_arl(dev, FAST_AGE_VLAN); 482 } 483 484 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 485 { 486 struct b53_device *dev = ds->priv; 487 unsigned int i; 488 u16 pvlan; 489 490 /* Enable the IMP port to be in the same VLAN as the other ports 491 * on a per-port basis such that we only have Port i and IMP in 492 * the same VLAN. 493 */ 494 b53_for_each_port(dev, i) { 495 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 496 pvlan |= BIT(cpu_port); 497 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 498 } 499 } 500 EXPORT_SYMBOL(b53_imp_vlan_setup); 501 502 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 503 { 504 struct b53_device *dev = ds->priv; 505 unsigned int cpu_port = ds->ports[port].cpu_dp->index; 506 int ret = 0; 507 u16 pvlan; 508 509 if (dev->ops->irq_enable) 510 ret = dev->ops->irq_enable(dev, port); 511 if (ret) 512 return ret; 513 514 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 515 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 516 517 /* Set this port, and only this one to be in the default VLAN, 518 * if member of a bridge, restore its membership prior to 519 * bringing down this port. 520 */ 521 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 522 pvlan &= ~0x1ff; 523 pvlan |= BIT(port); 524 pvlan |= dev->ports[port].vlan_ctl_mask; 525 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 526 527 b53_imp_vlan_setup(ds, cpu_port); 528 529 /* If EEE was enabled, restore it */ 530 if (dev->ports[port].eee.eee_enabled) 531 b53_eee_enable_set(ds, port, true); 532 533 return 0; 534 } 535 EXPORT_SYMBOL(b53_enable_port); 536 537 void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 538 { 539 struct b53_device *dev = ds->priv; 540 u8 reg; 541 542 /* Disable Tx/Rx for the port */ 543 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 544 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 545 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 546 547 if (dev->ops->irq_disable) 548 dev->ops->irq_disable(dev, port); 549 } 550 EXPORT_SYMBOL(b53_disable_port); 551 552 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 553 { 554 bool tag_en = !(ds->ops->get_tag_protocol(ds, port) == 555 DSA_TAG_PROTO_NONE); 556 struct b53_device *dev = ds->priv; 557 u8 hdr_ctl, val; 558 u16 reg; 559 560 /* Resolve which bit controls the Broadcom tag */ 561 switch (port) { 562 case 8: 563 val = BRCM_HDR_P8_EN; 564 break; 565 case 7: 566 val = BRCM_HDR_P7_EN; 567 break; 568 case 5: 569 val = BRCM_HDR_P5_EN; 570 break; 571 default: 572 val = 0; 573 break; 574 } 575 576 /* Enable Broadcom tags for IMP port */ 577 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 578 if (tag_en) 579 hdr_ctl |= val; 580 else 581 hdr_ctl &= ~val; 582 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 583 584 /* Registers below are only accessible on newer devices */ 585 if (!is58xx(dev)) 586 return; 587 588 /* Enable reception Broadcom tag for CPU TX (switch RX) to 589 * allow us to tag outgoing frames 590 */ 591 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 592 if (tag_en) 593 reg &= ~BIT(port); 594 else 595 reg |= BIT(port); 596 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 597 598 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 599 * allow delivering frames to the per-port net_devices 600 */ 601 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 602 if (tag_en) 603 reg &= ~BIT(port); 604 else 605 reg |= BIT(port); 606 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 607 } 608 EXPORT_SYMBOL(b53_brcm_hdr_setup); 609 610 static void b53_enable_cpu_port(struct b53_device *dev, int port) 611 { 612 u8 port_ctrl; 613 614 /* BCM5325 CPU port is at 8 */ 615 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 616 port = B53_CPU_PORT; 617 618 port_ctrl = PORT_CTRL_RX_BCST_EN | 619 PORT_CTRL_RX_MCST_EN | 620 PORT_CTRL_RX_UCST_EN; 621 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 622 623 b53_brcm_hdr_setup(dev->ds, port); 624 } 625 626 static void b53_enable_mib(struct b53_device *dev) 627 { 628 u8 gc; 629 630 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 631 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 632 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 633 } 634 635 static u16 b53_default_pvid(struct b53_device *dev) 636 { 637 if (is5325(dev) || is5365(dev)) 638 return 1; 639 else 640 return 0; 641 } 642 643 int b53_configure_vlan(struct dsa_switch *ds) 644 { 645 struct b53_device *dev = ds->priv; 646 struct b53_vlan vl = { 0 }; 647 int i, def_vid; 648 649 def_vid = b53_default_pvid(dev); 650 651 /* clear all vlan entries */ 652 if (is5325(dev) || is5365(dev)) { 653 for (i = def_vid; i < dev->num_vlans; i++) 654 b53_set_vlan_entry(dev, i, &vl); 655 } else { 656 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 657 } 658 659 b53_enable_vlan(dev, false); 660 661 b53_for_each_port(dev, i) 662 b53_write16(dev, B53_VLAN_PAGE, 663 B53_VLAN_PORT_DEF_TAG(i), def_vid); 664 665 if (!is5325(dev) && !is5365(dev)) 666 b53_set_jumbo(dev, dev->enable_jumbo, false); 667 668 return 0; 669 } 670 EXPORT_SYMBOL(b53_configure_vlan); 671 672 static void b53_switch_reset_gpio(struct b53_device *dev) 673 { 674 int gpio = dev->reset_gpio; 675 676 if (gpio < 0) 677 return; 678 679 /* Reset sequence: RESET low(50ms)->high(20ms) 680 */ 681 gpio_set_value(gpio, 0); 682 mdelay(50); 683 684 gpio_set_value(gpio, 1); 685 mdelay(20); 686 687 dev->current_page = 0xff; 688 } 689 690 static int b53_switch_reset(struct b53_device *dev) 691 { 692 unsigned int timeout = 1000; 693 u8 mgmt, reg; 694 695 b53_switch_reset_gpio(dev); 696 697 if (is539x(dev)) { 698 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 699 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 700 } 701 702 /* This is specific to 58xx devices here, do not use is58xx() which 703 * covers the larger Starfigther 2 family, including 7445/7278 which 704 * still use this driver as a library and need to perform the reset 705 * earlier. 706 */ 707 if (dev->chip_id == BCM58XX_DEVICE_ID || 708 dev->chip_id == BCM583XX_DEVICE_ID) { 709 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 710 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 711 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 712 713 do { 714 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 715 if (!(reg & SW_RST)) 716 break; 717 718 usleep_range(1000, 2000); 719 } while (timeout-- > 0); 720 721 if (timeout == 0) 722 return -ETIMEDOUT; 723 } 724 725 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 726 727 if (!(mgmt & SM_SW_FWD_EN)) { 728 mgmt &= ~SM_SW_FWD_MODE; 729 mgmt |= SM_SW_FWD_EN; 730 731 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 732 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 733 734 if (!(mgmt & SM_SW_FWD_EN)) { 735 dev_err(dev->dev, "Failed to enable switch!\n"); 736 return -EINVAL; 737 } 738 } 739 740 b53_enable_mib(dev); 741 742 return b53_flush_arl(dev, FAST_AGE_STATIC); 743 } 744 745 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 746 { 747 struct b53_device *priv = ds->priv; 748 u16 value = 0; 749 int ret; 750 751 if (priv->ops->phy_read16) 752 ret = priv->ops->phy_read16(priv, addr, reg, &value); 753 else 754 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 755 reg * 2, &value); 756 757 return ret ? ret : value; 758 } 759 760 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 761 { 762 struct b53_device *priv = ds->priv; 763 764 if (priv->ops->phy_write16) 765 return priv->ops->phy_write16(priv, addr, reg, val); 766 767 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 768 } 769 770 static int b53_reset_switch(struct b53_device *priv) 771 { 772 /* reset vlans */ 773 priv->enable_jumbo = false; 774 775 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 776 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 777 778 priv->serdes_lane = B53_INVALID_LANE; 779 780 return b53_switch_reset(priv); 781 } 782 783 static int b53_apply_config(struct b53_device *priv) 784 { 785 /* disable switching */ 786 b53_set_forwarding(priv, 0); 787 788 b53_configure_vlan(priv->ds); 789 790 /* enable switching */ 791 b53_set_forwarding(priv, 1); 792 793 return 0; 794 } 795 796 static void b53_reset_mib(struct b53_device *priv) 797 { 798 u8 gc; 799 800 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 801 802 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 803 msleep(1); 804 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 805 msleep(1); 806 } 807 808 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 809 { 810 if (is5365(dev)) 811 return b53_mibs_65; 812 else if (is63xx(dev)) 813 return b53_mibs_63xx; 814 else if (is58xx(dev)) 815 return b53_mibs_58xx; 816 else 817 return b53_mibs; 818 } 819 820 static unsigned int b53_get_mib_size(struct b53_device *dev) 821 { 822 if (is5365(dev)) 823 return B53_MIBS_65_SIZE; 824 else if (is63xx(dev)) 825 return B53_MIBS_63XX_SIZE; 826 else if (is58xx(dev)) 827 return B53_MIBS_58XX_SIZE; 828 else 829 return B53_MIBS_SIZE; 830 } 831 832 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 833 { 834 /* These ports typically do not have built-in PHYs */ 835 switch (port) { 836 case B53_CPU_PORT_25: 837 case 7: 838 case B53_CPU_PORT: 839 return NULL; 840 } 841 842 return mdiobus_get_phy(ds->slave_mii_bus, port); 843 } 844 845 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 846 uint8_t *data) 847 { 848 struct b53_device *dev = ds->priv; 849 const struct b53_mib_desc *mibs = b53_get_mib(dev); 850 unsigned int mib_size = b53_get_mib_size(dev); 851 struct phy_device *phydev; 852 unsigned int i; 853 854 if (stringset == ETH_SS_STATS) { 855 for (i = 0; i < mib_size; i++) 856 strlcpy(data + i * ETH_GSTRING_LEN, 857 mibs[i].name, ETH_GSTRING_LEN); 858 } else if (stringset == ETH_SS_PHY_STATS) { 859 phydev = b53_get_phy_device(ds, port); 860 if (!phydev) 861 return; 862 863 phy_ethtool_get_strings(phydev, data); 864 } 865 } 866 EXPORT_SYMBOL(b53_get_strings); 867 868 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 869 { 870 struct b53_device *dev = ds->priv; 871 const struct b53_mib_desc *mibs = b53_get_mib(dev); 872 unsigned int mib_size = b53_get_mib_size(dev); 873 const struct b53_mib_desc *s; 874 unsigned int i; 875 u64 val = 0; 876 877 if (is5365(dev) && port == 5) 878 port = 8; 879 880 mutex_lock(&dev->stats_mutex); 881 882 for (i = 0; i < mib_size; i++) { 883 s = &mibs[i]; 884 885 if (s->size == 8) { 886 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 887 } else { 888 u32 val32; 889 890 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 891 &val32); 892 val = val32; 893 } 894 data[i] = (u64)val; 895 } 896 897 mutex_unlock(&dev->stats_mutex); 898 } 899 EXPORT_SYMBOL(b53_get_ethtool_stats); 900 901 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 902 { 903 struct phy_device *phydev; 904 905 phydev = b53_get_phy_device(ds, port); 906 if (!phydev) 907 return; 908 909 phy_ethtool_get_stats(phydev, NULL, data); 910 } 911 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 912 913 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 914 { 915 struct b53_device *dev = ds->priv; 916 struct phy_device *phydev; 917 918 if (sset == ETH_SS_STATS) { 919 return b53_get_mib_size(dev); 920 } else if (sset == ETH_SS_PHY_STATS) { 921 phydev = b53_get_phy_device(ds, port); 922 if (!phydev) 923 return 0; 924 925 return phy_ethtool_get_sset_count(phydev); 926 } 927 928 return 0; 929 } 930 EXPORT_SYMBOL(b53_get_sset_count); 931 932 static int b53_setup(struct dsa_switch *ds) 933 { 934 struct b53_device *dev = ds->priv; 935 unsigned int port; 936 int ret; 937 938 ret = b53_reset_switch(dev); 939 if (ret) { 940 dev_err(ds->dev, "failed to reset switch\n"); 941 return ret; 942 } 943 944 b53_reset_mib(dev); 945 946 ret = b53_apply_config(dev); 947 if (ret) 948 dev_err(ds->dev, "failed to apply configuration\n"); 949 950 /* Configure IMP/CPU port, disable unused ports. Enabled 951 * ports will be configured with .port_enable 952 */ 953 for (port = 0; port < dev->num_ports; port++) { 954 if (dsa_is_cpu_port(ds, port)) 955 b53_enable_cpu_port(dev, port); 956 else if (dsa_is_unused_port(ds, port)) 957 b53_disable_port(ds, port, NULL); 958 } 959 960 return ret; 961 } 962 963 static void b53_force_link(struct b53_device *dev, int port, int link) 964 { 965 u8 reg, val, off; 966 967 /* Override the port settings */ 968 if (port == dev->cpu_port) { 969 off = B53_PORT_OVERRIDE_CTRL; 970 val = PORT_OVERRIDE_EN; 971 } else { 972 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 973 val = GMII_PO_EN; 974 } 975 976 b53_read8(dev, B53_CTRL_PAGE, off, ®); 977 reg |= val; 978 if (link) 979 reg |= PORT_OVERRIDE_LINK; 980 else 981 reg &= ~PORT_OVERRIDE_LINK; 982 b53_write8(dev, B53_CTRL_PAGE, off, reg); 983 } 984 985 static void b53_force_port_config(struct b53_device *dev, int port, 986 int speed, int duplex, int pause) 987 { 988 u8 reg, val, off; 989 990 /* Override the port settings */ 991 if (port == dev->cpu_port) { 992 off = B53_PORT_OVERRIDE_CTRL; 993 val = PORT_OVERRIDE_EN; 994 } else { 995 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 996 val = GMII_PO_EN; 997 } 998 999 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1000 reg |= val; 1001 if (duplex == DUPLEX_FULL) 1002 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1003 else 1004 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1005 1006 switch (speed) { 1007 case 2000: 1008 reg |= PORT_OVERRIDE_SPEED_2000M; 1009 /* fallthrough */ 1010 case SPEED_1000: 1011 reg |= PORT_OVERRIDE_SPEED_1000M; 1012 break; 1013 case SPEED_100: 1014 reg |= PORT_OVERRIDE_SPEED_100M; 1015 break; 1016 case SPEED_10: 1017 reg |= PORT_OVERRIDE_SPEED_10M; 1018 break; 1019 default: 1020 dev_err(dev->dev, "unknown speed: %d\n", speed); 1021 return; 1022 } 1023 1024 if (pause & MLO_PAUSE_RX) 1025 reg |= PORT_OVERRIDE_RX_FLOW; 1026 if (pause & MLO_PAUSE_TX) 1027 reg |= PORT_OVERRIDE_TX_FLOW; 1028 1029 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1030 } 1031 1032 static void b53_adjust_link(struct dsa_switch *ds, int port, 1033 struct phy_device *phydev) 1034 { 1035 struct b53_device *dev = ds->priv; 1036 struct ethtool_eee *p = &dev->ports[port].eee; 1037 u8 rgmii_ctrl = 0, reg = 0, off; 1038 int pause = 0; 1039 1040 if (!phy_is_pseudo_fixed_link(phydev)) 1041 return; 1042 1043 /* Enable flow control on BCM5301x's CPU port */ 1044 if (is5301x(dev) && port == dev->cpu_port) 1045 pause = MLO_PAUSE_TXRX_MASK; 1046 1047 if (phydev->pause) { 1048 if (phydev->asym_pause) 1049 pause |= MLO_PAUSE_TX; 1050 pause |= MLO_PAUSE_RX; 1051 } 1052 1053 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause); 1054 b53_force_link(dev, port, phydev->link); 1055 1056 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1057 if (port == 8) 1058 off = B53_RGMII_CTRL_IMP; 1059 else 1060 off = B53_RGMII_CTRL_P(port); 1061 1062 /* Configure the port RGMII clock delay by DLL disabled and 1063 * tx_clk aligned timing (restoring to reset defaults) 1064 */ 1065 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1066 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1067 RGMII_CTRL_TIMING_SEL); 1068 1069 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1070 * sure that we enable the port TX clock internal delay to 1071 * account for this internal delay that is inserted, otherwise 1072 * the switch won't be able to receive correctly. 1073 * 1074 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1075 * any delay neither on transmission nor reception, so the 1076 * BCM53125 must also be configured accordingly to account for 1077 * the lack of delay and introduce 1078 * 1079 * The BCM53125 switch has its RX clock and TX clock control 1080 * swapped, hence the reason why we modify the TX clock path in 1081 * the "RGMII" case 1082 */ 1083 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1084 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1085 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1086 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1087 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1088 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1089 1090 dev_info(ds->dev, "Configured port %d for %s\n", port, 1091 phy_modes(phydev->interface)); 1092 } 1093 1094 /* configure MII port if necessary */ 1095 if (is5325(dev)) { 1096 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1097 ®); 1098 1099 /* reverse mii needs to be enabled */ 1100 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1101 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1102 reg | PORT_OVERRIDE_RV_MII_25); 1103 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1104 ®); 1105 1106 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1107 dev_err(ds->dev, 1108 "Failed to enable reverse MII mode\n"); 1109 return; 1110 } 1111 } 1112 } else if (is5301x(dev)) { 1113 if (port != dev->cpu_port) { 1114 b53_force_port_config(dev, dev->cpu_port, 2000, 1115 DUPLEX_FULL, MLO_PAUSE_TXRX_MASK); 1116 b53_force_link(dev, dev->cpu_port, 1); 1117 } 1118 } 1119 1120 /* Re-negotiate EEE if it was enabled already */ 1121 p->eee_enabled = b53_eee_init(ds, port, phydev); 1122 } 1123 1124 void b53_port_event(struct dsa_switch *ds, int port) 1125 { 1126 struct b53_device *dev = ds->priv; 1127 bool link; 1128 u16 sts; 1129 1130 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1131 link = !!(sts & BIT(port)); 1132 dsa_port_phylink_mac_change(ds, port, link); 1133 } 1134 EXPORT_SYMBOL(b53_port_event); 1135 1136 void b53_phylink_validate(struct dsa_switch *ds, int port, 1137 unsigned long *supported, 1138 struct phylink_link_state *state) 1139 { 1140 struct b53_device *dev = ds->priv; 1141 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1142 1143 if (dev->ops->serdes_phylink_validate) 1144 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1145 1146 /* Allow all the expected bits */ 1147 phylink_set(mask, Autoneg); 1148 phylink_set_port_modes(mask); 1149 phylink_set(mask, Pause); 1150 phylink_set(mask, Asym_Pause); 1151 1152 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1153 * support Gigabit, including Half duplex. 1154 */ 1155 if (state->interface != PHY_INTERFACE_MODE_MII && 1156 state->interface != PHY_INTERFACE_MODE_REVMII && 1157 !phy_interface_mode_is_8023z(state->interface) && 1158 !(is5325(dev) || is5365(dev))) { 1159 phylink_set(mask, 1000baseT_Full); 1160 phylink_set(mask, 1000baseT_Half); 1161 } 1162 1163 if (!phy_interface_mode_is_8023z(state->interface)) { 1164 phylink_set(mask, 10baseT_Half); 1165 phylink_set(mask, 10baseT_Full); 1166 phylink_set(mask, 100baseT_Half); 1167 phylink_set(mask, 100baseT_Full); 1168 } 1169 1170 bitmap_and(supported, supported, mask, 1171 __ETHTOOL_LINK_MODE_MASK_NBITS); 1172 bitmap_and(state->advertising, state->advertising, mask, 1173 __ETHTOOL_LINK_MODE_MASK_NBITS); 1174 1175 phylink_helper_basex_speed(state); 1176 } 1177 EXPORT_SYMBOL(b53_phylink_validate); 1178 1179 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1180 struct phylink_link_state *state) 1181 { 1182 struct b53_device *dev = ds->priv; 1183 int ret = -EOPNOTSUPP; 1184 1185 if ((phy_interface_mode_is_8023z(state->interface) || 1186 state->interface == PHY_INTERFACE_MODE_SGMII) && 1187 dev->ops->serdes_link_state) 1188 ret = dev->ops->serdes_link_state(dev, port, state); 1189 1190 return ret; 1191 } 1192 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1193 1194 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1195 unsigned int mode, 1196 const struct phylink_link_state *state) 1197 { 1198 struct b53_device *dev = ds->priv; 1199 1200 if (mode == MLO_AN_PHY) 1201 return; 1202 1203 if (mode == MLO_AN_FIXED) { 1204 b53_force_port_config(dev, port, state->speed, 1205 state->duplex, state->pause); 1206 return; 1207 } 1208 1209 if ((phy_interface_mode_is_8023z(state->interface) || 1210 state->interface == PHY_INTERFACE_MODE_SGMII) && 1211 dev->ops->serdes_config) 1212 dev->ops->serdes_config(dev, port, mode, state); 1213 } 1214 EXPORT_SYMBOL(b53_phylink_mac_config); 1215 1216 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1217 { 1218 struct b53_device *dev = ds->priv; 1219 1220 if (dev->ops->serdes_an_restart) 1221 dev->ops->serdes_an_restart(dev, port); 1222 } 1223 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1224 1225 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1226 unsigned int mode, 1227 phy_interface_t interface) 1228 { 1229 struct b53_device *dev = ds->priv; 1230 1231 if (mode == MLO_AN_PHY) 1232 return; 1233 1234 if (mode == MLO_AN_FIXED) { 1235 b53_force_link(dev, port, false); 1236 return; 1237 } 1238 1239 if (phy_interface_mode_is_8023z(interface) && 1240 dev->ops->serdes_link_set) 1241 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1242 } 1243 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1244 1245 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1246 unsigned int mode, 1247 phy_interface_t interface, 1248 struct phy_device *phydev) 1249 { 1250 struct b53_device *dev = ds->priv; 1251 1252 if (mode == MLO_AN_PHY) 1253 return; 1254 1255 if (mode == MLO_AN_FIXED) { 1256 b53_force_link(dev, port, true); 1257 return; 1258 } 1259 1260 if (phy_interface_mode_is_8023z(interface) && 1261 dev->ops->serdes_link_set) 1262 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1263 } 1264 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1265 1266 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 1267 { 1268 return 0; 1269 } 1270 EXPORT_SYMBOL(b53_vlan_filtering); 1271 1272 int b53_vlan_prepare(struct dsa_switch *ds, int port, 1273 const struct switchdev_obj_port_vlan *vlan) 1274 { 1275 struct b53_device *dev = ds->priv; 1276 1277 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 1278 return -EOPNOTSUPP; 1279 1280 if (vlan->vid_end > dev->num_vlans) 1281 return -ERANGE; 1282 1283 b53_enable_vlan(dev, true); 1284 1285 return 0; 1286 } 1287 EXPORT_SYMBOL(b53_vlan_prepare); 1288 1289 void b53_vlan_add(struct dsa_switch *ds, int port, 1290 const struct switchdev_obj_port_vlan *vlan) 1291 { 1292 struct b53_device *dev = ds->priv; 1293 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1294 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1295 struct b53_vlan *vl; 1296 u16 vid; 1297 1298 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1299 vl = &dev->vlans[vid]; 1300 1301 b53_get_vlan_entry(dev, vid, vl); 1302 1303 vl->members |= BIT(port); 1304 if (untagged && !dsa_is_cpu_port(ds, port)) 1305 vl->untag |= BIT(port); 1306 else 1307 vl->untag &= ~BIT(port); 1308 1309 b53_set_vlan_entry(dev, vid, vl); 1310 b53_fast_age_vlan(dev, vid); 1311 } 1312 1313 if (pvid) { 1314 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1315 vlan->vid_end); 1316 b53_fast_age_vlan(dev, vid); 1317 } 1318 } 1319 EXPORT_SYMBOL(b53_vlan_add); 1320 1321 int b53_vlan_del(struct dsa_switch *ds, int port, 1322 const struct switchdev_obj_port_vlan *vlan) 1323 { 1324 struct b53_device *dev = ds->priv; 1325 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1326 struct b53_vlan *vl; 1327 u16 vid; 1328 u16 pvid; 1329 1330 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1331 1332 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1333 vl = &dev->vlans[vid]; 1334 1335 b53_get_vlan_entry(dev, vid, vl); 1336 1337 vl->members &= ~BIT(port); 1338 1339 if (pvid == vid) 1340 pvid = b53_default_pvid(dev); 1341 1342 if (untagged && !dsa_is_cpu_port(ds, port)) 1343 vl->untag &= ~(BIT(port)); 1344 1345 b53_set_vlan_entry(dev, vid, vl); 1346 b53_fast_age_vlan(dev, vid); 1347 } 1348 1349 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1350 b53_fast_age_vlan(dev, pvid); 1351 1352 return 0; 1353 } 1354 EXPORT_SYMBOL(b53_vlan_del); 1355 1356 /* Address Resolution Logic routines */ 1357 static int b53_arl_op_wait(struct b53_device *dev) 1358 { 1359 unsigned int timeout = 10; 1360 u8 reg; 1361 1362 do { 1363 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1364 if (!(reg & ARLTBL_START_DONE)) 1365 return 0; 1366 1367 usleep_range(1000, 2000); 1368 } while (timeout--); 1369 1370 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1371 1372 return -ETIMEDOUT; 1373 } 1374 1375 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1376 { 1377 u8 reg; 1378 1379 if (op > ARLTBL_RW) 1380 return -EINVAL; 1381 1382 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1383 reg |= ARLTBL_START_DONE; 1384 if (op) 1385 reg |= ARLTBL_RW; 1386 else 1387 reg &= ~ARLTBL_RW; 1388 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1389 1390 return b53_arl_op_wait(dev); 1391 } 1392 1393 static int b53_arl_read(struct b53_device *dev, u64 mac, 1394 u16 vid, struct b53_arl_entry *ent, u8 *idx, 1395 bool is_valid) 1396 { 1397 unsigned int i; 1398 int ret; 1399 1400 ret = b53_arl_op_wait(dev); 1401 if (ret) 1402 return ret; 1403 1404 /* Read the bins */ 1405 for (i = 0; i < dev->num_arl_entries; i++) { 1406 u64 mac_vid; 1407 u32 fwd_entry; 1408 1409 b53_read64(dev, B53_ARLIO_PAGE, 1410 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1411 b53_read32(dev, B53_ARLIO_PAGE, 1412 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1413 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1414 1415 if (!(fwd_entry & ARLTBL_VALID)) 1416 continue; 1417 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1418 continue; 1419 *idx = i; 1420 } 1421 1422 return -ENOENT; 1423 } 1424 1425 static int b53_arl_op(struct b53_device *dev, int op, int port, 1426 const unsigned char *addr, u16 vid, bool is_valid) 1427 { 1428 struct b53_arl_entry ent; 1429 u32 fwd_entry; 1430 u64 mac, mac_vid = 0; 1431 u8 idx = 0; 1432 int ret; 1433 1434 /* Convert the array into a 64-bit MAC */ 1435 mac = ether_addr_to_u64(addr); 1436 1437 /* Perform a read for the given MAC and VID */ 1438 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1439 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1440 1441 /* Issue a read operation for this MAC */ 1442 ret = b53_arl_rw_op(dev, 1); 1443 if (ret) 1444 return ret; 1445 1446 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid); 1447 /* If this is a read, just finish now */ 1448 if (op) 1449 return ret; 1450 1451 /* We could not find a matching MAC, so reset to a new entry */ 1452 if (ret) { 1453 fwd_entry = 0; 1454 idx = 1; 1455 } 1456 1457 memset(&ent, 0, sizeof(ent)); 1458 ent.port = port; 1459 ent.is_valid = is_valid; 1460 ent.vid = vid; 1461 ent.is_static = true; 1462 memcpy(ent.mac, addr, ETH_ALEN); 1463 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1464 1465 b53_write64(dev, B53_ARLIO_PAGE, 1466 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1467 b53_write32(dev, B53_ARLIO_PAGE, 1468 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1469 1470 return b53_arl_rw_op(dev, 0); 1471 } 1472 1473 int b53_fdb_add(struct dsa_switch *ds, int port, 1474 const unsigned char *addr, u16 vid) 1475 { 1476 struct b53_device *priv = ds->priv; 1477 1478 /* 5325 and 5365 require some more massaging, but could 1479 * be supported eventually 1480 */ 1481 if (is5325(priv) || is5365(priv)) 1482 return -EOPNOTSUPP; 1483 1484 return b53_arl_op(priv, 0, port, addr, vid, true); 1485 } 1486 EXPORT_SYMBOL(b53_fdb_add); 1487 1488 int b53_fdb_del(struct dsa_switch *ds, int port, 1489 const unsigned char *addr, u16 vid) 1490 { 1491 struct b53_device *priv = ds->priv; 1492 1493 return b53_arl_op(priv, 0, port, addr, vid, false); 1494 } 1495 EXPORT_SYMBOL(b53_fdb_del); 1496 1497 static int b53_arl_search_wait(struct b53_device *dev) 1498 { 1499 unsigned int timeout = 1000; 1500 u8 reg; 1501 1502 do { 1503 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1504 if (!(reg & ARL_SRCH_STDN)) 1505 return 0; 1506 1507 if (reg & ARL_SRCH_VLID) 1508 return 0; 1509 1510 usleep_range(1000, 2000); 1511 } while (timeout--); 1512 1513 return -ETIMEDOUT; 1514 } 1515 1516 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1517 struct b53_arl_entry *ent) 1518 { 1519 u64 mac_vid; 1520 u32 fwd_entry; 1521 1522 b53_read64(dev, B53_ARLIO_PAGE, 1523 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1524 b53_read32(dev, B53_ARLIO_PAGE, 1525 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1526 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1527 } 1528 1529 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1530 dsa_fdb_dump_cb_t *cb, void *data) 1531 { 1532 if (!ent->is_valid) 1533 return 0; 1534 1535 if (port != ent->port) 1536 return 0; 1537 1538 return cb(ent->mac, ent->vid, ent->is_static, data); 1539 } 1540 1541 int b53_fdb_dump(struct dsa_switch *ds, int port, 1542 dsa_fdb_dump_cb_t *cb, void *data) 1543 { 1544 struct b53_device *priv = ds->priv; 1545 struct b53_arl_entry results[2]; 1546 unsigned int count = 0; 1547 int ret; 1548 u8 reg; 1549 1550 /* Start search operation */ 1551 reg = ARL_SRCH_STDN; 1552 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1553 1554 do { 1555 ret = b53_arl_search_wait(priv); 1556 if (ret) 1557 return ret; 1558 1559 b53_arl_search_rd(priv, 0, &results[0]); 1560 ret = b53_fdb_copy(port, &results[0], cb, data); 1561 if (ret) 1562 return ret; 1563 1564 if (priv->num_arl_entries > 2) { 1565 b53_arl_search_rd(priv, 1, &results[1]); 1566 ret = b53_fdb_copy(port, &results[1], cb, data); 1567 if (ret) 1568 return ret; 1569 1570 if (!results[0].is_valid && !results[1].is_valid) 1571 break; 1572 } 1573 1574 } while (count++ < 1024); 1575 1576 return 0; 1577 } 1578 EXPORT_SYMBOL(b53_fdb_dump); 1579 1580 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1581 { 1582 struct b53_device *dev = ds->priv; 1583 s8 cpu_port = ds->ports[port].cpu_dp->index; 1584 u16 pvlan, reg; 1585 unsigned int i; 1586 1587 /* Make this port leave the all VLANs join since we will have proper 1588 * VLAN entries from now on 1589 */ 1590 if (is58xx(dev)) { 1591 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1592 reg &= ~BIT(port); 1593 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1594 reg &= ~BIT(cpu_port); 1595 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1596 } 1597 1598 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1599 1600 b53_for_each_port(dev, i) { 1601 if (dsa_to_port(ds, i)->bridge_dev != br) 1602 continue; 1603 1604 /* Add this local port to the remote port VLAN control 1605 * membership and update the remote port bitmask 1606 */ 1607 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1608 reg |= BIT(port); 1609 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1610 dev->ports[i].vlan_ctl_mask = reg; 1611 1612 pvlan |= BIT(i); 1613 } 1614 1615 /* Configure the local port VLAN control membership to include 1616 * remote ports and update the local port bitmask 1617 */ 1618 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1619 dev->ports[port].vlan_ctl_mask = pvlan; 1620 1621 return 0; 1622 } 1623 EXPORT_SYMBOL(b53_br_join); 1624 1625 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1626 { 1627 struct b53_device *dev = ds->priv; 1628 struct b53_vlan *vl = &dev->vlans[0]; 1629 s8 cpu_port = ds->ports[port].cpu_dp->index; 1630 unsigned int i; 1631 u16 pvlan, reg, pvid; 1632 1633 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1634 1635 b53_for_each_port(dev, i) { 1636 /* Don't touch the remaining ports */ 1637 if (dsa_to_port(ds, i)->bridge_dev != br) 1638 continue; 1639 1640 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1641 reg &= ~BIT(port); 1642 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1643 dev->ports[port].vlan_ctl_mask = reg; 1644 1645 /* Prevent self removal to preserve isolation */ 1646 if (port != i) 1647 pvlan &= ~BIT(i); 1648 } 1649 1650 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1651 dev->ports[port].vlan_ctl_mask = pvlan; 1652 1653 pvid = b53_default_pvid(dev); 1654 1655 /* Make this port join all VLANs without VLAN entries */ 1656 if (is58xx(dev)) { 1657 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1658 reg |= BIT(port); 1659 if (!(reg & BIT(cpu_port))) 1660 reg |= BIT(cpu_port); 1661 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1662 } else { 1663 b53_get_vlan_entry(dev, pvid, vl); 1664 vl->members |= BIT(port) | BIT(cpu_port); 1665 vl->untag |= BIT(port) | BIT(cpu_port); 1666 b53_set_vlan_entry(dev, pvid, vl); 1667 } 1668 } 1669 EXPORT_SYMBOL(b53_br_leave); 1670 1671 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1672 { 1673 struct b53_device *dev = ds->priv; 1674 u8 hw_state; 1675 u8 reg; 1676 1677 switch (state) { 1678 case BR_STATE_DISABLED: 1679 hw_state = PORT_CTRL_DIS_STATE; 1680 break; 1681 case BR_STATE_LISTENING: 1682 hw_state = PORT_CTRL_LISTEN_STATE; 1683 break; 1684 case BR_STATE_LEARNING: 1685 hw_state = PORT_CTRL_LEARN_STATE; 1686 break; 1687 case BR_STATE_FORWARDING: 1688 hw_state = PORT_CTRL_FWD_STATE; 1689 break; 1690 case BR_STATE_BLOCKING: 1691 hw_state = PORT_CTRL_BLOCK_STATE; 1692 break; 1693 default: 1694 dev_err(ds->dev, "invalid STP state: %d\n", state); 1695 return; 1696 } 1697 1698 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1699 reg &= ~PORT_CTRL_STP_STATE_MASK; 1700 reg |= hw_state; 1701 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1702 } 1703 EXPORT_SYMBOL(b53_br_set_stp_state); 1704 1705 void b53_br_fast_age(struct dsa_switch *ds, int port) 1706 { 1707 struct b53_device *dev = ds->priv; 1708 1709 if (b53_fast_age_port(dev, port)) 1710 dev_err(ds->dev, "fast ageing failed\n"); 1711 } 1712 EXPORT_SYMBOL(b53_br_fast_age); 1713 1714 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 1715 { 1716 /* Broadcom switches will accept enabling Broadcom tags on the 1717 * following ports: 5, 7 and 8, any other port is not supported 1718 */ 1719 switch (port) { 1720 case B53_CPU_PORT_25: 1721 case 7: 1722 case B53_CPU_PORT: 1723 return true; 1724 } 1725 1726 return false; 1727 } 1728 1729 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port) 1730 { 1731 bool ret = b53_possible_cpu_port(ds, port); 1732 1733 if (!ret) 1734 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 1735 port); 1736 return ret; 1737 } 1738 1739 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port) 1740 { 1741 struct b53_device *dev = ds->priv; 1742 1743 /* Older models (5325, 5365) support a different tag format that we do 1744 * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed 1745 * mode to be turned on which means we need to specifically manage ARL 1746 * misses on multicast addresses (TBD). 1747 */ 1748 if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) || 1749 !b53_can_enable_brcm_tags(ds, port)) 1750 return DSA_TAG_PROTO_NONE; 1751 1752 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 1753 * which requires us to use the prepended Broadcom tag type 1754 */ 1755 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) 1756 return DSA_TAG_PROTO_BRCM_PREPEND; 1757 1758 return DSA_TAG_PROTO_BRCM; 1759 } 1760 EXPORT_SYMBOL(b53_get_tag_protocol); 1761 1762 int b53_mirror_add(struct dsa_switch *ds, int port, 1763 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1764 { 1765 struct b53_device *dev = ds->priv; 1766 u16 reg, loc; 1767 1768 if (ingress) 1769 loc = B53_IG_MIR_CTL; 1770 else 1771 loc = B53_EG_MIR_CTL; 1772 1773 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1774 reg &= ~MIRROR_MASK; 1775 reg |= BIT(port); 1776 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1777 1778 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1779 reg &= ~CAP_PORT_MASK; 1780 reg |= mirror->to_local_port; 1781 reg |= MIRROR_EN; 1782 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1783 1784 return 0; 1785 } 1786 EXPORT_SYMBOL(b53_mirror_add); 1787 1788 void b53_mirror_del(struct dsa_switch *ds, int port, 1789 struct dsa_mall_mirror_tc_entry *mirror) 1790 { 1791 struct b53_device *dev = ds->priv; 1792 bool loc_disable = false, other_loc_disable = false; 1793 u16 reg, loc; 1794 1795 if (mirror->ingress) 1796 loc = B53_IG_MIR_CTL; 1797 else 1798 loc = B53_EG_MIR_CTL; 1799 1800 /* Update the desired ingress/egress register */ 1801 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1802 reg &= ~BIT(port); 1803 if (!(reg & MIRROR_MASK)) 1804 loc_disable = true; 1805 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1806 1807 /* Now look at the other one to know if we can disable mirroring 1808 * entirely 1809 */ 1810 if (mirror->ingress) 1811 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 1812 else 1813 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 1814 if (!(reg & MIRROR_MASK)) 1815 other_loc_disable = true; 1816 1817 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1818 /* Both no longer have ports, let's disable mirroring */ 1819 if (loc_disable && other_loc_disable) { 1820 reg &= ~MIRROR_EN; 1821 reg &= ~mirror->to_local_port; 1822 } 1823 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1824 } 1825 EXPORT_SYMBOL(b53_mirror_del); 1826 1827 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 1828 { 1829 struct b53_device *dev = ds->priv; 1830 u16 reg; 1831 1832 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 1833 if (enable) 1834 reg |= BIT(port); 1835 else 1836 reg &= ~BIT(port); 1837 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 1838 } 1839 EXPORT_SYMBOL(b53_eee_enable_set); 1840 1841 1842 /* Returns 0 if EEE was not enabled, or 1 otherwise 1843 */ 1844 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 1845 { 1846 int ret; 1847 1848 ret = phy_init_eee(phy, 0); 1849 if (ret) 1850 return 0; 1851 1852 b53_eee_enable_set(ds, port, true); 1853 1854 return 1; 1855 } 1856 EXPORT_SYMBOL(b53_eee_init); 1857 1858 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1859 { 1860 struct b53_device *dev = ds->priv; 1861 struct ethtool_eee *p = &dev->ports[port].eee; 1862 u16 reg; 1863 1864 if (is5325(dev) || is5365(dev)) 1865 return -EOPNOTSUPP; 1866 1867 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 1868 e->eee_enabled = p->eee_enabled; 1869 e->eee_active = !!(reg & BIT(port)); 1870 1871 return 0; 1872 } 1873 EXPORT_SYMBOL(b53_get_mac_eee); 1874 1875 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1876 { 1877 struct b53_device *dev = ds->priv; 1878 struct ethtool_eee *p = &dev->ports[port].eee; 1879 1880 if (is5325(dev) || is5365(dev)) 1881 return -EOPNOTSUPP; 1882 1883 p->eee_enabled = e->eee_enabled; 1884 b53_eee_enable_set(ds, port, e->eee_enabled); 1885 1886 return 0; 1887 } 1888 EXPORT_SYMBOL(b53_set_mac_eee); 1889 1890 static const struct dsa_switch_ops b53_switch_ops = { 1891 .get_tag_protocol = b53_get_tag_protocol, 1892 .setup = b53_setup, 1893 .get_strings = b53_get_strings, 1894 .get_ethtool_stats = b53_get_ethtool_stats, 1895 .get_sset_count = b53_get_sset_count, 1896 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1897 .phy_read = b53_phy_read16, 1898 .phy_write = b53_phy_write16, 1899 .adjust_link = b53_adjust_link, 1900 .phylink_validate = b53_phylink_validate, 1901 .phylink_mac_link_state = b53_phylink_mac_link_state, 1902 .phylink_mac_config = b53_phylink_mac_config, 1903 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 1904 .phylink_mac_link_down = b53_phylink_mac_link_down, 1905 .phylink_mac_link_up = b53_phylink_mac_link_up, 1906 .port_enable = b53_enable_port, 1907 .port_disable = b53_disable_port, 1908 .get_mac_eee = b53_get_mac_eee, 1909 .set_mac_eee = b53_set_mac_eee, 1910 .port_bridge_join = b53_br_join, 1911 .port_bridge_leave = b53_br_leave, 1912 .port_stp_state_set = b53_br_set_stp_state, 1913 .port_fast_age = b53_br_fast_age, 1914 .port_vlan_filtering = b53_vlan_filtering, 1915 .port_vlan_prepare = b53_vlan_prepare, 1916 .port_vlan_add = b53_vlan_add, 1917 .port_vlan_del = b53_vlan_del, 1918 .port_fdb_dump = b53_fdb_dump, 1919 .port_fdb_add = b53_fdb_add, 1920 .port_fdb_del = b53_fdb_del, 1921 .port_mirror_add = b53_mirror_add, 1922 .port_mirror_del = b53_mirror_del, 1923 }; 1924 1925 struct b53_chip_data { 1926 u32 chip_id; 1927 const char *dev_name; 1928 u16 vlans; 1929 u16 enabled_ports; 1930 u8 cpu_port; 1931 u8 vta_regs[3]; 1932 u8 arl_entries; 1933 u8 duplex_reg; 1934 u8 jumbo_pm_reg; 1935 u8 jumbo_size_reg; 1936 }; 1937 1938 #define B53_VTA_REGS \ 1939 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 1940 #define B53_VTA_REGS_9798 \ 1941 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 1942 #define B53_VTA_REGS_63XX \ 1943 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 1944 1945 static const struct b53_chip_data b53_switch_chips[] = { 1946 { 1947 .chip_id = BCM5325_DEVICE_ID, 1948 .dev_name = "BCM5325", 1949 .vlans = 16, 1950 .enabled_ports = 0x1f, 1951 .arl_entries = 2, 1952 .cpu_port = B53_CPU_PORT_25, 1953 .duplex_reg = B53_DUPLEX_STAT_FE, 1954 }, 1955 { 1956 .chip_id = BCM5365_DEVICE_ID, 1957 .dev_name = "BCM5365", 1958 .vlans = 256, 1959 .enabled_ports = 0x1f, 1960 .arl_entries = 2, 1961 .cpu_port = B53_CPU_PORT_25, 1962 .duplex_reg = B53_DUPLEX_STAT_FE, 1963 }, 1964 { 1965 .chip_id = BCM5389_DEVICE_ID, 1966 .dev_name = "BCM5389", 1967 .vlans = 4096, 1968 .enabled_ports = 0x1f, 1969 .arl_entries = 4, 1970 .cpu_port = B53_CPU_PORT, 1971 .vta_regs = B53_VTA_REGS, 1972 .duplex_reg = B53_DUPLEX_STAT_GE, 1973 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1974 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1975 }, 1976 { 1977 .chip_id = BCM5395_DEVICE_ID, 1978 .dev_name = "BCM5395", 1979 .vlans = 4096, 1980 .enabled_ports = 0x1f, 1981 .arl_entries = 4, 1982 .cpu_port = B53_CPU_PORT, 1983 .vta_regs = B53_VTA_REGS, 1984 .duplex_reg = B53_DUPLEX_STAT_GE, 1985 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1986 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1987 }, 1988 { 1989 .chip_id = BCM5397_DEVICE_ID, 1990 .dev_name = "BCM5397", 1991 .vlans = 4096, 1992 .enabled_ports = 0x1f, 1993 .arl_entries = 4, 1994 .cpu_port = B53_CPU_PORT, 1995 .vta_regs = B53_VTA_REGS_9798, 1996 .duplex_reg = B53_DUPLEX_STAT_GE, 1997 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1998 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1999 }, 2000 { 2001 .chip_id = BCM5398_DEVICE_ID, 2002 .dev_name = "BCM5398", 2003 .vlans = 4096, 2004 .enabled_ports = 0x7f, 2005 .arl_entries = 4, 2006 .cpu_port = B53_CPU_PORT, 2007 .vta_regs = B53_VTA_REGS_9798, 2008 .duplex_reg = B53_DUPLEX_STAT_GE, 2009 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2010 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2011 }, 2012 { 2013 .chip_id = BCM53115_DEVICE_ID, 2014 .dev_name = "BCM53115", 2015 .vlans = 4096, 2016 .enabled_ports = 0x1f, 2017 .arl_entries = 4, 2018 .vta_regs = B53_VTA_REGS, 2019 .cpu_port = B53_CPU_PORT, 2020 .duplex_reg = B53_DUPLEX_STAT_GE, 2021 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2022 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2023 }, 2024 { 2025 .chip_id = BCM53125_DEVICE_ID, 2026 .dev_name = "BCM53125", 2027 .vlans = 4096, 2028 .enabled_ports = 0xff, 2029 .arl_entries = 4, 2030 .cpu_port = B53_CPU_PORT, 2031 .vta_regs = B53_VTA_REGS, 2032 .duplex_reg = B53_DUPLEX_STAT_GE, 2033 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2034 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2035 }, 2036 { 2037 .chip_id = BCM53128_DEVICE_ID, 2038 .dev_name = "BCM53128", 2039 .vlans = 4096, 2040 .enabled_ports = 0x1ff, 2041 .arl_entries = 4, 2042 .cpu_port = B53_CPU_PORT, 2043 .vta_regs = B53_VTA_REGS, 2044 .duplex_reg = B53_DUPLEX_STAT_GE, 2045 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2046 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2047 }, 2048 { 2049 .chip_id = BCM63XX_DEVICE_ID, 2050 .dev_name = "BCM63xx", 2051 .vlans = 4096, 2052 .enabled_ports = 0, /* pdata must provide them */ 2053 .arl_entries = 4, 2054 .cpu_port = B53_CPU_PORT, 2055 .vta_regs = B53_VTA_REGS_63XX, 2056 .duplex_reg = B53_DUPLEX_STAT_63XX, 2057 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2058 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2059 }, 2060 { 2061 .chip_id = BCM53010_DEVICE_ID, 2062 .dev_name = "BCM53010", 2063 .vlans = 4096, 2064 .enabled_ports = 0x1f, 2065 .arl_entries = 4, 2066 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2067 .vta_regs = B53_VTA_REGS, 2068 .duplex_reg = B53_DUPLEX_STAT_GE, 2069 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2070 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2071 }, 2072 { 2073 .chip_id = BCM53011_DEVICE_ID, 2074 .dev_name = "BCM53011", 2075 .vlans = 4096, 2076 .enabled_ports = 0x1bf, 2077 .arl_entries = 4, 2078 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2079 .vta_regs = B53_VTA_REGS, 2080 .duplex_reg = B53_DUPLEX_STAT_GE, 2081 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2082 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2083 }, 2084 { 2085 .chip_id = BCM53012_DEVICE_ID, 2086 .dev_name = "BCM53012", 2087 .vlans = 4096, 2088 .enabled_ports = 0x1bf, 2089 .arl_entries = 4, 2090 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2091 .vta_regs = B53_VTA_REGS, 2092 .duplex_reg = B53_DUPLEX_STAT_GE, 2093 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2094 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2095 }, 2096 { 2097 .chip_id = BCM53018_DEVICE_ID, 2098 .dev_name = "BCM53018", 2099 .vlans = 4096, 2100 .enabled_ports = 0x1f, 2101 .arl_entries = 4, 2102 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2103 .vta_regs = B53_VTA_REGS, 2104 .duplex_reg = B53_DUPLEX_STAT_GE, 2105 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2106 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2107 }, 2108 { 2109 .chip_id = BCM53019_DEVICE_ID, 2110 .dev_name = "BCM53019", 2111 .vlans = 4096, 2112 .enabled_ports = 0x1f, 2113 .arl_entries = 4, 2114 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2115 .vta_regs = B53_VTA_REGS, 2116 .duplex_reg = B53_DUPLEX_STAT_GE, 2117 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2118 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2119 }, 2120 { 2121 .chip_id = BCM58XX_DEVICE_ID, 2122 .dev_name = "BCM585xx/586xx/88312", 2123 .vlans = 4096, 2124 .enabled_ports = 0x1ff, 2125 .arl_entries = 4, 2126 .cpu_port = B53_CPU_PORT, 2127 .vta_regs = B53_VTA_REGS, 2128 .duplex_reg = B53_DUPLEX_STAT_GE, 2129 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2130 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2131 }, 2132 { 2133 .chip_id = BCM583XX_DEVICE_ID, 2134 .dev_name = "BCM583xx/11360", 2135 .vlans = 4096, 2136 .enabled_ports = 0x103, 2137 .arl_entries = 4, 2138 .cpu_port = B53_CPU_PORT, 2139 .vta_regs = B53_VTA_REGS, 2140 .duplex_reg = B53_DUPLEX_STAT_GE, 2141 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2142 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2143 }, 2144 { 2145 .chip_id = BCM7445_DEVICE_ID, 2146 .dev_name = "BCM7445", 2147 .vlans = 4096, 2148 .enabled_ports = 0x1ff, 2149 .arl_entries = 4, 2150 .cpu_port = B53_CPU_PORT, 2151 .vta_regs = B53_VTA_REGS, 2152 .duplex_reg = B53_DUPLEX_STAT_GE, 2153 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2154 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2155 }, 2156 { 2157 .chip_id = BCM7278_DEVICE_ID, 2158 .dev_name = "BCM7278", 2159 .vlans = 4096, 2160 .enabled_ports = 0x1ff, 2161 .arl_entries= 4, 2162 .cpu_port = B53_CPU_PORT, 2163 .vta_regs = B53_VTA_REGS, 2164 .duplex_reg = B53_DUPLEX_STAT_GE, 2165 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2166 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2167 }, 2168 }; 2169 2170 static int b53_switch_init(struct b53_device *dev) 2171 { 2172 unsigned int i; 2173 int ret; 2174 2175 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2176 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2177 2178 if (chip->chip_id == dev->chip_id) { 2179 if (!dev->enabled_ports) 2180 dev->enabled_ports = chip->enabled_ports; 2181 dev->name = chip->dev_name; 2182 dev->duplex_reg = chip->duplex_reg; 2183 dev->vta_regs[0] = chip->vta_regs[0]; 2184 dev->vta_regs[1] = chip->vta_regs[1]; 2185 dev->vta_regs[2] = chip->vta_regs[2]; 2186 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2187 dev->cpu_port = chip->cpu_port; 2188 dev->num_vlans = chip->vlans; 2189 dev->num_arl_entries = chip->arl_entries; 2190 break; 2191 } 2192 } 2193 2194 /* check which BCM5325x version we have */ 2195 if (is5325(dev)) { 2196 u8 vc4; 2197 2198 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2199 2200 /* check reserved bits */ 2201 switch (vc4 & 3) { 2202 case 1: 2203 /* BCM5325E */ 2204 break; 2205 case 3: 2206 /* BCM5325F - do not use port 4 */ 2207 dev->enabled_ports &= ~BIT(4); 2208 break; 2209 default: 2210 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2211 #ifndef CONFIG_BCM47XX 2212 /* BCM5325M */ 2213 return -EINVAL; 2214 #else 2215 break; 2216 #endif 2217 } 2218 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2219 u64 strap_value; 2220 2221 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2222 /* use second IMP port if GMII is enabled */ 2223 if (strap_value & SV_GMII_CTRL_115) 2224 dev->cpu_port = 5; 2225 } 2226 2227 /* cpu port is always last */ 2228 dev->num_ports = dev->cpu_port + 1; 2229 dev->enabled_ports |= BIT(dev->cpu_port); 2230 2231 /* Include non standard CPU port built-in PHYs to be probed */ 2232 if (is539x(dev) || is531x5(dev)) { 2233 for (i = 0; i < dev->num_ports; i++) { 2234 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2235 !b53_possible_cpu_port(dev->ds, i)) 2236 dev->ds->phys_mii_mask |= BIT(i); 2237 } 2238 } 2239 2240 dev->ports = devm_kcalloc(dev->dev, 2241 dev->num_ports, sizeof(struct b53_port), 2242 GFP_KERNEL); 2243 if (!dev->ports) 2244 return -ENOMEM; 2245 2246 dev->vlans = devm_kcalloc(dev->dev, 2247 dev->num_vlans, sizeof(struct b53_vlan), 2248 GFP_KERNEL); 2249 if (!dev->vlans) 2250 return -ENOMEM; 2251 2252 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2253 if (dev->reset_gpio >= 0) { 2254 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2255 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2256 if (ret) 2257 return ret; 2258 } 2259 2260 return 0; 2261 } 2262 2263 struct b53_device *b53_switch_alloc(struct device *base, 2264 const struct b53_io_ops *ops, 2265 void *priv) 2266 { 2267 struct dsa_switch *ds; 2268 struct b53_device *dev; 2269 2270 ds = dsa_switch_alloc(base, DSA_MAX_PORTS); 2271 if (!ds) 2272 return NULL; 2273 2274 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2275 if (!dev) 2276 return NULL; 2277 2278 ds->priv = dev; 2279 dev->dev = base; 2280 2281 dev->ds = ds; 2282 dev->priv = priv; 2283 dev->ops = ops; 2284 ds->ops = &b53_switch_ops; 2285 mutex_init(&dev->reg_mutex); 2286 mutex_init(&dev->stats_mutex); 2287 2288 return dev; 2289 } 2290 EXPORT_SYMBOL(b53_switch_alloc); 2291 2292 int b53_switch_detect(struct b53_device *dev) 2293 { 2294 u32 id32; 2295 u16 tmp; 2296 u8 id8; 2297 int ret; 2298 2299 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2300 if (ret) 2301 return ret; 2302 2303 switch (id8) { 2304 case 0: 2305 /* BCM5325 and BCM5365 do not have this register so reads 2306 * return 0. But the read operation did succeed, so assume this 2307 * is one of them. 2308 * 2309 * Next check if we can write to the 5325's VTA register; for 2310 * 5365 it is read only. 2311 */ 2312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2313 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2314 2315 if (tmp == 0xf) 2316 dev->chip_id = BCM5325_DEVICE_ID; 2317 else 2318 dev->chip_id = BCM5365_DEVICE_ID; 2319 break; 2320 case BCM5389_DEVICE_ID: 2321 case BCM5395_DEVICE_ID: 2322 case BCM5397_DEVICE_ID: 2323 case BCM5398_DEVICE_ID: 2324 dev->chip_id = id8; 2325 break; 2326 default: 2327 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2328 if (ret) 2329 return ret; 2330 2331 switch (id32) { 2332 case BCM53115_DEVICE_ID: 2333 case BCM53125_DEVICE_ID: 2334 case BCM53128_DEVICE_ID: 2335 case BCM53010_DEVICE_ID: 2336 case BCM53011_DEVICE_ID: 2337 case BCM53012_DEVICE_ID: 2338 case BCM53018_DEVICE_ID: 2339 case BCM53019_DEVICE_ID: 2340 dev->chip_id = id32; 2341 break; 2342 default: 2343 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 2344 id8, id32); 2345 return -ENODEV; 2346 } 2347 } 2348 2349 if (dev->chip_id == BCM5325_DEVICE_ID) 2350 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2351 &dev->core_rev); 2352 else 2353 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2354 &dev->core_rev); 2355 } 2356 EXPORT_SYMBOL(b53_switch_detect); 2357 2358 int b53_switch_register(struct b53_device *dev) 2359 { 2360 int ret; 2361 2362 if (dev->pdata) { 2363 dev->chip_id = dev->pdata->chip_id; 2364 dev->enabled_ports = dev->pdata->enabled_ports; 2365 } 2366 2367 if (!dev->chip_id && b53_switch_detect(dev)) 2368 return -EINVAL; 2369 2370 ret = b53_switch_init(dev); 2371 if (ret) 2372 return ret; 2373 2374 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 2375 2376 return dsa_register_switch(dev->ds); 2377 } 2378 EXPORT_SYMBOL(b53_switch_register); 2379 2380 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2381 MODULE_DESCRIPTION("B53 switch library"); 2382 MODULE_LICENSE("Dual BSD/GPL"); 2383