1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <net/dsa.h> 31 32 #include "b53_regs.h" 33 #include "b53_priv.h" 34 35 struct b53_mib_desc { 36 u8 size; 37 u8 offset; 38 const char *name; 39 }; 40 41 /* BCM5365 MIB counters */ 42 static const struct b53_mib_desc b53_mibs_65[] = { 43 { 8, 0x00, "TxOctets" }, 44 { 4, 0x08, "TxDropPkts" }, 45 { 4, 0x10, "TxBroadcastPkts" }, 46 { 4, 0x14, "TxMulticastPkts" }, 47 { 4, 0x18, "TxUnicastPkts" }, 48 { 4, 0x1c, "TxCollisions" }, 49 { 4, 0x20, "TxSingleCollision" }, 50 { 4, 0x24, "TxMultipleCollision" }, 51 { 4, 0x28, "TxDeferredTransmit" }, 52 { 4, 0x2c, "TxLateCollision" }, 53 { 4, 0x30, "TxExcessiveCollision" }, 54 { 4, 0x38, "TxPausePkts" }, 55 { 8, 0x44, "RxOctets" }, 56 { 4, 0x4c, "RxUndersizePkts" }, 57 { 4, 0x50, "RxPausePkts" }, 58 { 4, 0x54, "Pkts64Octets" }, 59 { 4, 0x58, "Pkts65to127Octets" }, 60 { 4, 0x5c, "Pkts128to255Octets" }, 61 { 4, 0x60, "Pkts256to511Octets" }, 62 { 4, 0x64, "Pkts512to1023Octets" }, 63 { 4, 0x68, "Pkts1024to1522Octets" }, 64 { 4, 0x6c, "RxOversizePkts" }, 65 { 4, 0x70, "RxJabbers" }, 66 { 4, 0x74, "RxAlignmentErrors" }, 67 { 4, 0x78, "RxFCSErrors" }, 68 { 8, 0x7c, "RxGoodOctets" }, 69 { 4, 0x84, "RxDropPkts" }, 70 { 4, 0x88, "RxUnicastPkts" }, 71 { 4, 0x8c, "RxMulticastPkts" }, 72 { 4, 0x90, "RxBroadcastPkts" }, 73 { 4, 0x94, "RxSAChanges" }, 74 { 4, 0x98, "RxFragments" }, 75 }; 76 77 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 78 79 /* BCM63xx MIB counters */ 80 static const struct b53_mib_desc b53_mibs_63xx[] = { 81 { 8, 0x00, "TxOctets" }, 82 { 4, 0x08, "TxDropPkts" }, 83 { 4, 0x0c, "TxQoSPkts" }, 84 { 4, 0x10, "TxBroadcastPkts" }, 85 { 4, 0x14, "TxMulticastPkts" }, 86 { 4, 0x18, "TxUnicastPkts" }, 87 { 4, 0x1c, "TxCollisions" }, 88 { 4, 0x20, "TxSingleCollision" }, 89 { 4, 0x24, "TxMultipleCollision" }, 90 { 4, 0x28, "TxDeferredTransmit" }, 91 { 4, 0x2c, "TxLateCollision" }, 92 { 4, 0x30, "TxExcessiveCollision" }, 93 { 4, 0x38, "TxPausePkts" }, 94 { 8, 0x3c, "TxQoSOctets" }, 95 { 8, 0x44, "RxOctets" }, 96 { 4, 0x4c, "RxUndersizePkts" }, 97 { 4, 0x50, "RxPausePkts" }, 98 { 4, 0x54, "Pkts64Octets" }, 99 { 4, 0x58, "Pkts65to127Octets" }, 100 { 4, 0x5c, "Pkts128to255Octets" }, 101 { 4, 0x60, "Pkts256to511Octets" }, 102 { 4, 0x64, "Pkts512to1023Octets" }, 103 { 4, 0x68, "Pkts1024to1522Octets" }, 104 { 4, 0x6c, "RxOversizePkts" }, 105 { 4, 0x70, "RxJabbers" }, 106 { 4, 0x74, "RxAlignmentErrors" }, 107 { 4, 0x78, "RxFCSErrors" }, 108 { 8, 0x7c, "RxGoodOctets" }, 109 { 4, 0x84, "RxDropPkts" }, 110 { 4, 0x88, "RxUnicastPkts" }, 111 { 4, 0x8c, "RxMulticastPkts" }, 112 { 4, 0x90, "RxBroadcastPkts" }, 113 { 4, 0x94, "RxSAChanges" }, 114 { 4, 0x98, "RxFragments" }, 115 { 4, 0xa0, "RxSymbolErrors" }, 116 { 4, 0xa4, "RxQoSPkts" }, 117 { 8, 0xa8, "RxQoSOctets" }, 118 { 4, 0xb0, "Pkts1523to2047Octets" }, 119 { 4, 0xb4, "Pkts2048to4095Octets" }, 120 { 4, 0xb8, "Pkts4096to8191Octets" }, 121 { 4, 0xbc, "Pkts8192to9728Octets" }, 122 { 4, 0xc0, "RxDiscarded" }, 123 }; 124 125 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 126 127 /* MIB counters */ 128 static const struct b53_mib_desc b53_mibs[] = { 129 { 8, 0x00, "TxOctets" }, 130 { 4, 0x08, "TxDropPkts" }, 131 { 4, 0x10, "TxBroadcastPkts" }, 132 { 4, 0x14, "TxMulticastPkts" }, 133 { 4, 0x18, "TxUnicastPkts" }, 134 { 4, 0x1c, "TxCollisions" }, 135 { 4, 0x20, "TxSingleCollision" }, 136 { 4, 0x24, "TxMultipleCollision" }, 137 { 4, 0x28, "TxDeferredTransmit" }, 138 { 4, 0x2c, "TxLateCollision" }, 139 { 4, 0x30, "TxExcessiveCollision" }, 140 { 4, 0x38, "TxPausePkts" }, 141 { 8, 0x50, "RxOctets" }, 142 { 4, 0x58, "RxUndersizePkts" }, 143 { 4, 0x5c, "RxPausePkts" }, 144 { 4, 0x60, "Pkts64Octets" }, 145 { 4, 0x64, "Pkts65to127Octets" }, 146 { 4, 0x68, "Pkts128to255Octets" }, 147 { 4, 0x6c, "Pkts256to511Octets" }, 148 { 4, 0x70, "Pkts512to1023Octets" }, 149 { 4, 0x74, "Pkts1024to1522Octets" }, 150 { 4, 0x78, "RxOversizePkts" }, 151 { 4, 0x7c, "RxJabbers" }, 152 { 4, 0x80, "RxAlignmentErrors" }, 153 { 4, 0x84, "RxFCSErrors" }, 154 { 8, 0x88, "RxGoodOctets" }, 155 { 4, 0x90, "RxDropPkts" }, 156 { 4, 0x94, "RxUnicastPkts" }, 157 { 4, 0x98, "RxMulticastPkts" }, 158 { 4, 0x9c, "RxBroadcastPkts" }, 159 { 4, 0xa0, "RxSAChanges" }, 160 { 4, 0xa4, "RxFragments" }, 161 { 4, 0xa8, "RxJumboPkts" }, 162 { 4, 0xac, "RxSymbolErrors" }, 163 { 4, 0xc0, "RxDiscarded" }, 164 }; 165 166 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 167 168 static const struct b53_mib_desc b53_mibs_58xx[] = { 169 { 8, 0x00, "TxOctets" }, 170 { 4, 0x08, "TxDropPkts" }, 171 { 4, 0x0c, "TxQPKTQ0" }, 172 { 4, 0x10, "TxBroadcastPkts" }, 173 { 4, 0x14, "TxMulticastPkts" }, 174 { 4, 0x18, "TxUnicastPKts" }, 175 { 4, 0x1c, "TxCollisions" }, 176 { 4, 0x20, "TxSingleCollision" }, 177 { 4, 0x24, "TxMultipleCollision" }, 178 { 4, 0x28, "TxDeferredCollision" }, 179 { 4, 0x2c, "TxLateCollision" }, 180 { 4, 0x30, "TxExcessiveCollision" }, 181 { 4, 0x34, "TxFrameInDisc" }, 182 { 4, 0x38, "TxPausePkts" }, 183 { 4, 0x3c, "TxQPKTQ1" }, 184 { 4, 0x40, "TxQPKTQ2" }, 185 { 4, 0x44, "TxQPKTQ3" }, 186 { 4, 0x48, "TxQPKTQ4" }, 187 { 4, 0x4c, "TxQPKTQ5" }, 188 { 8, 0x50, "RxOctets" }, 189 { 4, 0x58, "RxUndersizePkts" }, 190 { 4, 0x5c, "RxPausePkts" }, 191 { 4, 0x60, "RxPkts64Octets" }, 192 { 4, 0x64, "RxPkts65to127Octets" }, 193 { 4, 0x68, "RxPkts128to255Octets" }, 194 { 4, 0x6c, "RxPkts256to511Octets" }, 195 { 4, 0x70, "RxPkts512to1023Octets" }, 196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 197 { 4, 0x78, "RxOversizePkts" }, 198 { 4, 0x7c, "RxJabbers" }, 199 { 4, 0x80, "RxAlignmentErrors" }, 200 { 4, 0x84, "RxFCSErrors" }, 201 { 8, 0x88, "RxGoodOctets" }, 202 { 4, 0x90, "RxDropPkts" }, 203 { 4, 0x94, "RxUnicastPkts" }, 204 { 4, 0x98, "RxMulticastPkts" }, 205 { 4, 0x9c, "RxBroadcastPkts" }, 206 { 4, 0xa0, "RxSAChanges" }, 207 { 4, 0xa4, "RxFragments" }, 208 { 4, 0xa8, "RxJumboPkt" }, 209 { 4, 0xac, "RxSymblErr" }, 210 { 4, 0xb0, "InRangeErrCount" }, 211 { 4, 0xb4, "OutRangeErrCount" }, 212 { 4, 0xb8, "EEELpiEvent" }, 213 { 4, 0xbc, "EEELpiDuration" }, 214 { 4, 0xc0, "RxDiscard" }, 215 { 4, 0xc8, "TxQPKTQ6" }, 216 { 4, 0xcc, "TxQPKTQ7" }, 217 { 4, 0xd0, "TxPkts64Octets" }, 218 { 4, 0xd4, "TxPkts65to127Octets" }, 219 { 4, 0xd8, "TxPkts128to255Octets" }, 220 { 4, 0xdc, "TxPkts256to511Ocets" }, 221 { 4, 0xe0, "TxPkts512to1023Ocets" }, 222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 223 }; 224 225 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 226 227 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 228 { 229 unsigned int i; 230 231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 232 233 for (i = 0; i < 10; i++) { 234 u8 vta; 235 236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 237 if (!(vta & VTA_START_CMD)) 238 return 0; 239 240 usleep_range(100, 200); 241 } 242 243 return -EIO; 244 } 245 246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 247 struct b53_vlan *vlan) 248 { 249 if (is5325(dev)) { 250 u32 entry = 0; 251 252 if (vlan->members) { 253 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 254 VA_UNTAG_S_25) | vlan->members; 255 if (dev->core_rev >= 3) 256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 257 else 258 entry |= VA_VALID_25; 259 } 260 261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 263 VTA_RW_STATE_WR | VTA_RW_OP_EN); 264 } else if (is5365(dev)) { 265 u16 entry = 0; 266 267 if (vlan->members) 268 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 270 271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 273 VTA_RW_STATE_WR | VTA_RW_OP_EN); 274 } else { 275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 277 (vlan->untag << VTE_UNTAG_S) | vlan->members); 278 279 b53_do_vlan_op(dev, VTA_CMD_WRITE); 280 } 281 282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 283 vid, vlan->members, vlan->untag); 284 } 285 286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 287 struct b53_vlan *vlan) 288 { 289 if (is5325(dev)) { 290 u32 entry = 0; 291 292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 293 VTA_RW_STATE_RD | VTA_RW_OP_EN); 294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 295 296 if (dev->core_rev >= 3) 297 vlan->valid = !!(entry & VA_VALID_25_R4); 298 else 299 vlan->valid = !!(entry & VA_VALID_25); 300 vlan->members = entry & VA_MEMBER_MASK; 301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 302 303 } else if (is5365(dev)) { 304 u16 entry = 0; 305 306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 307 VTA_RW_STATE_WR | VTA_RW_OP_EN); 308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 309 310 vlan->valid = !!(entry & VA_VALID_65); 311 vlan->members = entry & VA_MEMBER_MASK; 312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 313 } else { 314 u32 entry = 0; 315 316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 317 b53_do_vlan_op(dev, VTA_CMD_READ); 318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 319 vlan->members = entry & VTE_MEMBERS; 320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 321 vlan->valid = true; 322 } 323 } 324 325 static void b53_set_forwarding(struct b53_device *dev, int enable) 326 { 327 u8 mgmt; 328 329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 330 331 if (enable) 332 mgmt |= SM_SW_FWD_EN; 333 else 334 mgmt &= ~SM_SW_FWD_EN; 335 336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 337 338 /* Include IMP port in dumb forwarding mode 339 */ 340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 341 mgmt |= B53_MII_DUMB_FWDG_EN; 342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 343 344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 345 * frames should be flooded or not. 346 */ 347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 350 } 351 352 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 353 bool enable_filtering) 354 { 355 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 356 357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 360 361 if (is5325(dev) || is5365(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 364 } else if (is63xx(dev)) { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 367 } else { 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 370 } 371 372 if (enable) { 373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 375 vc4 &= ~VC4_ING_VID_CHECK_MASK; 376 if (enable_filtering) { 377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 378 vc5 |= VC5_DROP_VTABLE_MISS; 379 } else { 380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 381 vc5 &= ~VC5_DROP_VTABLE_MISS; 382 } 383 384 if (is5325(dev)) 385 vc0 &= ~VC0_RESERVED_1; 386 387 if (is5325(dev) || is5365(dev)) 388 vc1 |= VC1_RX_MCST_TAG_EN; 389 390 } else { 391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 393 vc4 &= ~VC4_ING_VID_CHECK_MASK; 394 vc5 &= ~VC5_DROP_VTABLE_MISS; 395 396 if (is5325(dev) || is5365(dev)) 397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 398 else 399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 400 401 if (is5325(dev) || is5365(dev)) 402 vc1 &= ~VC1_RX_MCST_TAG_EN; 403 } 404 405 if (!is5325(dev) && !is5365(dev)) 406 vc5 &= ~VC5_VID_FFF_EN; 407 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 410 411 if (is5325(dev) || is5365(dev)) { 412 /* enable the high 8 bit vid check on 5325 */ 413 if (is5325(dev) && enable) 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 415 VC3_HIGH_8BIT_EN); 416 else 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 418 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 421 } else if (is63xx(dev)) { 422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 425 } else { 426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 429 } 430 431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 432 433 dev->vlan_enabled = enable; 434 435 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 436 port, enable, enable_filtering); 437 } 438 439 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 440 { 441 u32 port_mask = 0; 442 u16 max_size = JMS_MIN_SIZE; 443 444 if (is5325(dev) || is5365(dev)) 445 return -EINVAL; 446 447 if (enable) { 448 port_mask = dev->enabled_ports; 449 max_size = JMS_MAX_SIZE; 450 if (allow_10_100) 451 port_mask |= JPM_10_100_JUMBO_EN; 452 } 453 454 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 455 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 456 } 457 458 static int b53_flush_arl(struct b53_device *dev, u8 mask) 459 { 460 unsigned int i; 461 462 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 463 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 464 465 for (i = 0; i < 10; i++) { 466 u8 fast_age_ctrl; 467 468 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 469 &fast_age_ctrl); 470 471 if (!(fast_age_ctrl & FAST_AGE_DONE)) 472 goto out; 473 474 msleep(1); 475 } 476 477 return -ETIMEDOUT; 478 out: 479 /* Only age dynamic entries (default behavior) */ 480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 481 return 0; 482 } 483 484 static int b53_fast_age_port(struct b53_device *dev, int port) 485 { 486 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 487 488 return b53_flush_arl(dev, FAST_AGE_PORT); 489 } 490 491 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 492 { 493 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 494 495 return b53_flush_arl(dev, FAST_AGE_VLAN); 496 } 497 498 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 499 { 500 struct b53_device *dev = ds->priv; 501 unsigned int i; 502 u16 pvlan; 503 504 /* Enable the IMP port to be in the same VLAN as the other ports 505 * on a per-port basis such that we only have Port i and IMP in 506 * the same VLAN. 507 */ 508 b53_for_each_port(dev, i) { 509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 510 pvlan |= BIT(cpu_port); 511 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 512 } 513 } 514 EXPORT_SYMBOL(b53_imp_vlan_setup); 515 516 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 517 bool unicast) 518 { 519 u16 uc; 520 521 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 522 if (unicast) 523 uc |= BIT(port); 524 else 525 uc &= ~BIT(port); 526 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 527 } 528 529 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 530 bool multicast) 531 { 532 u16 mc; 533 534 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 535 if (multicast) 536 mc |= BIT(port); 537 else 538 mc &= ~BIT(port); 539 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 540 541 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 542 if (multicast) 543 mc |= BIT(port); 544 else 545 mc &= ~BIT(port); 546 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 547 } 548 549 static void b53_port_set_learning(struct b53_device *dev, int port, 550 bool learning) 551 { 552 u16 reg; 553 554 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 555 if (learning) 556 reg &= ~BIT(port); 557 else 558 reg |= BIT(port); 559 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 560 } 561 562 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 563 { 564 struct b53_device *dev = ds->priv; 565 unsigned int cpu_port; 566 int ret = 0; 567 u16 pvlan; 568 569 if (!dsa_is_user_port(ds, port)) 570 return 0; 571 572 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 573 574 b53_port_set_ucast_flood(dev, port, true); 575 b53_port_set_mcast_flood(dev, port, true); 576 b53_port_set_learning(dev, port, false); 577 578 if (dev->ops->irq_enable) 579 ret = dev->ops->irq_enable(dev, port); 580 if (ret) 581 return ret; 582 583 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 584 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 585 586 /* Set this port, and only this one to be in the default VLAN, 587 * if member of a bridge, restore its membership prior to 588 * bringing down this port. 589 */ 590 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 591 pvlan &= ~0x1ff; 592 pvlan |= BIT(port); 593 pvlan |= dev->ports[port].vlan_ctl_mask; 594 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 595 596 b53_imp_vlan_setup(ds, cpu_port); 597 598 /* If EEE was enabled, restore it */ 599 if (dev->ports[port].eee.eee_enabled) 600 b53_eee_enable_set(ds, port, true); 601 602 return 0; 603 } 604 EXPORT_SYMBOL(b53_enable_port); 605 606 void b53_disable_port(struct dsa_switch *ds, int port) 607 { 608 struct b53_device *dev = ds->priv; 609 u8 reg; 610 611 /* Disable Tx/Rx for the port */ 612 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 613 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 614 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 615 616 if (dev->ops->irq_disable) 617 dev->ops->irq_disable(dev, port); 618 } 619 EXPORT_SYMBOL(b53_disable_port); 620 621 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 622 { 623 struct b53_device *dev = ds->priv; 624 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 625 u8 hdr_ctl, val; 626 u16 reg; 627 628 /* Resolve which bit controls the Broadcom tag */ 629 switch (port) { 630 case 8: 631 val = BRCM_HDR_P8_EN; 632 break; 633 case 7: 634 val = BRCM_HDR_P7_EN; 635 break; 636 case 5: 637 val = BRCM_HDR_P5_EN; 638 break; 639 default: 640 val = 0; 641 break; 642 } 643 644 /* Enable management mode if tagging is requested */ 645 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 646 if (tag_en) 647 hdr_ctl |= SM_SW_FWD_MODE; 648 else 649 hdr_ctl &= ~SM_SW_FWD_MODE; 650 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 651 652 /* Configure the appropriate IMP port */ 653 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 654 if (port == 8) 655 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 656 else if (port == 5) 657 hdr_ctl |= GC_FRM_MGMT_PORT_M; 658 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 659 660 /* Enable Broadcom tags for IMP port */ 661 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 662 if (tag_en) 663 hdr_ctl |= val; 664 else 665 hdr_ctl &= ~val; 666 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 667 668 /* Registers below are only accessible on newer devices */ 669 if (!is58xx(dev)) 670 return; 671 672 /* Enable reception Broadcom tag for CPU TX (switch RX) to 673 * allow us to tag outgoing frames 674 */ 675 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 676 if (tag_en) 677 reg &= ~BIT(port); 678 else 679 reg |= BIT(port); 680 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 681 682 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 683 * allow delivering frames to the per-port net_devices 684 */ 685 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 686 if (tag_en) 687 reg &= ~BIT(port); 688 else 689 reg |= BIT(port); 690 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 691 } 692 EXPORT_SYMBOL(b53_brcm_hdr_setup); 693 694 static void b53_enable_cpu_port(struct b53_device *dev, int port) 695 { 696 u8 port_ctrl; 697 698 /* BCM5325 CPU port is at 8 */ 699 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 700 port = B53_CPU_PORT; 701 702 port_ctrl = PORT_CTRL_RX_BCST_EN | 703 PORT_CTRL_RX_MCST_EN | 704 PORT_CTRL_RX_UCST_EN; 705 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 706 707 b53_brcm_hdr_setup(dev->ds, port); 708 709 b53_port_set_ucast_flood(dev, port, true); 710 b53_port_set_mcast_flood(dev, port, true); 711 b53_port_set_learning(dev, port, false); 712 } 713 714 static void b53_enable_mib(struct b53_device *dev) 715 { 716 u8 gc; 717 718 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 719 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 720 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 721 } 722 723 static u16 b53_default_pvid(struct b53_device *dev) 724 { 725 if (is5325(dev) || is5365(dev)) 726 return 1; 727 else 728 return 0; 729 } 730 731 int b53_configure_vlan(struct dsa_switch *ds) 732 { 733 struct b53_device *dev = ds->priv; 734 struct b53_vlan vl = { 0 }; 735 struct b53_vlan *v; 736 int i, def_vid; 737 u16 vid; 738 739 def_vid = b53_default_pvid(dev); 740 741 /* clear all vlan entries */ 742 if (is5325(dev) || is5365(dev)) { 743 for (i = def_vid; i < dev->num_vlans; i++) 744 b53_set_vlan_entry(dev, i, &vl); 745 } else { 746 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 747 } 748 749 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering); 750 751 b53_for_each_port(dev, i) 752 b53_write16(dev, B53_VLAN_PAGE, 753 B53_VLAN_PORT_DEF_TAG(i), def_vid); 754 755 /* Upon initial call we have not set-up any VLANs, but upon 756 * system resume, we need to restore all VLAN entries. 757 */ 758 for (vid = def_vid; vid < dev->num_vlans; vid++) { 759 v = &dev->vlans[vid]; 760 761 if (!v->members) 762 continue; 763 764 b53_set_vlan_entry(dev, vid, v); 765 b53_fast_age_vlan(dev, vid); 766 } 767 768 return 0; 769 } 770 EXPORT_SYMBOL(b53_configure_vlan); 771 772 static void b53_switch_reset_gpio(struct b53_device *dev) 773 { 774 int gpio = dev->reset_gpio; 775 776 if (gpio < 0) 777 return; 778 779 /* Reset sequence: RESET low(50ms)->high(20ms) 780 */ 781 gpio_set_value(gpio, 0); 782 mdelay(50); 783 784 gpio_set_value(gpio, 1); 785 mdelay(20); 786 787 dev->current_page = 0xff; 788 } 789 790 static int b53_switch_reset(struct b53_device *dev) 791 { 792 unsigned int timeout = 1000; 793 u8 mgmt, reg; 794 795 b53_switch_reset_gpio(dev); 796 797 if (is539x(dev)) { 798 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 799 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 800 } 801 802 /* This is specific to 58xx devices here, do not use is58xx() which 803 * covers the larger Starfigther 2 family, including 7445/7278 which 804 * still use this driver as a library and need to perform the reset 805 * earlier. 806 */ 807 if (dev->chip_id == BCM58XX_DEVICE_ID || 808 dev->chip_id == BCM583XX_DEVICE_ID) { 809 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 810 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 811 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 812 813 do { 814 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 815 if (!(reg & SW_RST)) 816 break; 817 818 usleep_range(1000, 2000); 819 } while (timeout-- > 0); 820 821 if (timeout == 0) { 822 dev_err(dev->dev, 823 "Timeout waiting for SW_RST to clear!\n"); 824 return -ETIMEDOUT; 825 } 826 } 827 828 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 829 830 if (!(mgmt & SM_SW_FWD_EN)) { 831 mgmt &= ~SM_SW_FWD_MODE; 832 mgmt |= SM_SW_FWD_EN; 833 834 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 835 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 836 837 if (!(mgmt & SM_SW_FWD_EN)) { 838 dev_err(dev->dev, "Failed to enable switch!\n"); 839 return -EINVAL; 840 } 841 } 842 843 b53_enable_mib(dev); 844 845 return b53_flush_arl(dev, FAST_AGE_STATIC); 846 } 847 848 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 849 { 850 struct b53_device *priv = ds->priv; 851 u16 value = 0; 852 int ret; 853 854 if (priv->ops->phy_read16) 855 ret = priv->ops->phy_read16(priv, addr, reg, &value); 856 else 857 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 858 reg * 2, &value); 859 860 return ret ? ret : value; 861 } 862 863 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 864 { 865 struct b53_device *priv = ds->priv; 866 867 if (priv->ops->phy_write16) 868 return priv->ops->phy_write16(priv, addr, reg, val); 869 870 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 871 } 872 873 static int b53_reset_switch(struct b53_device *priv) 874 { 875 /* reset vlans */ 876 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 877 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 878 879 priv->serdes_lane = B53_INVALID_LANE; 880 881 return b53_switch_reset(priv); 882 } 883 884 static int b53_apply_config(struct b53_device *priv) 885 { 886 /* disable switching */ 887 b53_set_forwarding(priv, 0); 888 889 b53_configure_vlan(priv->ds); 890 891 /* enable switching */ 892 b53_set_forwarding(priv, 1); 893 894 return 0; 895 } 896 897 static void b53_reset_mib(struct b53_device *priv) 898 { 899 u8 gc; 900 901 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 902 903 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 904 msleep(1); 905 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 906 msleep(1); 907 } 908 909 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 910 { 911 if (is5365(dev)) 912 return b53_mibs_65; 913 else if (is63xx(dev)) 914 return b53_mibs_63xx; 915 else if (is58xx(dev)) 916 return b53_mibs_58xx; 917 else 918 return b53_mibs; 919 } 920 921 static unsigned int b53_get_mib_size(struct b53_device *dev) 922 { 923 if (is5365(dev)) 924 return B53_MIBS_65_SIZE; 925 else if (is63xx(dev)) 926 return B53_MIBS_63XX_SIZE; 927 else if (is58xx(dev)) 928 return B53_MIBS_58XX_SIZE; 929 else 930 return B53_MIBS_SIZE; 931 } 932 933 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 934 { 935 /* These ports typically do not have built-in PHYs */ 936 switch (port) { 937 case B53_CPU_PORT_25: 938 case 7: 939 case B53_CPU_PORT: 940 return NULL; 941 } 942 943 return mdiobus_get_phy(ds->slave_mii_bus, port); 944 } 945 946 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 947 uint8_t *data) 948 { 949 struct b53_device *dev = ds->priv; 950 const struct b53_mib_desc *mibs = b53_get_mib(dev); 951 unsigned int mib_size = b53_get_mib_size(dev); 952 struct phy_device *phydev; 953 unsigned int i; 954 955 if (stringset == ETH_SS_STATS) { 956 for (i = 0; i < mib_size; i++) 957 strlcpy(data + i * ETH_GSTRING_LEN, 958 mibs[i].name, ETH_GSTRING_LEN); 959 } else if (stringset == ETH_SS_PHY_STATS) { 960 phydev = b53_get_phy_device(ds, port); 961 if (!phydev) 962 return; 963 964 phy_ethtool_get_strings(phydev, data); 965 } 966 } 967 EXPORT_SYMBOL(b53_get_strings); 968 969 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 970 { 971 struct b53_device *dev = ds->priv; 972 const struct b53_mib_desc *mibs = b53_get_mib(dev); 973 unsigned int mib_size = b53_get_mib_size(dev); 974 const struct b53_mib_desc *s; 975 unsigned int i; 976 u64 val = 0; 977 978 if (is5365(dev) && port == 5) 979 port = 8; 980 981 mutex_lock(&dev->stats_mutex); 982 983 for (i = 0; i < mib_size; i++) { 984 s = &mibs[i]; 985 986 if (s->size == 8) { 987 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 988 } else { 989 u32 val32; 990 991 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 992 &val32); 993 val = val32; 994 } 995 data[i] = (u64)val; 996 } 997 998 mutex_unlock(&dev->stats_mutex); 999 } 1000 EXPORT_SYMBOL(b53_get_ethtool_stats); 1001 1002 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1003 { 1004 struct phy_device *phydev; 1005 1006 phydev = b53_get_phy_device(ds, port); 1007 if (!phydev) 1008 return; 1009 1010 phy_ethtool_get_stats(phydev, NULL, data); 1011 } 1012 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1013 1014 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1015 { 1016 struct b53_device *dev = ds->priv; 1017 struct phy_device *phydev; 1018 1019 if (sset == ETH_SS_STATS) { 1020 return b53_get_mib_size(dev); 1021 } else if (sset == ETH_SS_PHY_STATS) { 1022 phydev = b53_get_phy_device(ds, port); 1023 if (!phydev) 1024 return 0; 1025 1026 return phy_ethtool_get_sset_count(phydev); 1027 } 1028 1029 return 0; 1030 } 1031 EXPORT_SYMBOL(b53_get_sset_count); 1032 1033 enum b53_devlink_resource_id { 1034 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1035 }; 1036 1037 static u64 b53_devlink_vlan_table_get(void *priv) 1038 { 1039 struct b53_device *dev = priv; 1040 struct b53_vlan *vl; 1041 unsigned int i; 1042 u64 count = 0; 1043 1044 for (i = 0; i < dev->num_vlans; i++) { 1045 vl = &dev->vlans[i]; 1046 if (vl->members) 1047 count++; 1048 } 1049 1050 return count; 1051 } 1052 1053 int b53_setup_devlink_resources(struct dsa_switch *ds) 1054 { 1055 struct devlink_resource_size_params size_params; 1056 struct b53_device *dev = ds->priv; 1057 int err; 1058 1059 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1060 dev->num_vlans, 1061 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1062 1063 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1064 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1065 DEVLINK_RESOURCE_ID_PARENT_TOP, 1066 &size_params); 1067 if (err) 1068 goto out; 1069 1070 dsa_devlink_resource_occ_get_register(ds, 1071 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1072 b53_devlink_vlan_table_get, dev); 1073 1074 return 0; 1075 out: 1076 dsa_devlink_resources_unregister(ds); 1077 return err; 1078 } 1079 EXPORT_SYMBOL(b53_setup_devlink_resources); 1080 1081 static int b53_setup(struct dsa_switch *ds) 1082 { 1083 struct b53_device *dev = ds->priv; 1084 unsigned int port; 1085 int ret; 1086 1087 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1088 * which forces the CPU port to be tagged in all VLANs. 1089 */ 1090 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1091 1092 ret = b53_reset_switch(dev); 1093 if (ret) { 1094 dev_err(ds->dev, "failed to reset switch\n"); 1095 return ret; 1096 } 1097 1098 b53_reset_mib(dev); 1099 1100 ret = b53_apply_config(dev); 1101 if (ret) { 1102 dev_err(ds->dev, "failed to apply configuration\n"); 1103 return ret; 1104 } 1105 1106 /* Configure IMP/CPU port, disable all other ports. Enabled 1107 * ports will be configured with .port_enable 1108 */ 1109 for (port = 0; port < dev->num_ports; port++) { 1110 if (dsa_is_cpu_port(ds, port)) 1111 b53_enable_cpu_port(dev, port); 1112 else 1113 b53_disable_port(ds, port); 1114 } 1115 1116 return b53_setup_devlink_resources(ds); 1117 } 1118 1119 static void b53_teardown(struct dsa_switch *ds) 1120 { 1121 dsa_devlink_resources_unregister(ds); 1122 } 1123 1124 static void b53_force_link(struct b53_device *dev, int port, int link) 1125 { 1126 u8 reg, val, off; 1127 1128 /* Override the port settings */ 1129 if (port == dev->cpu_port) { 1130 off = B53_PORT_OVERRIDE_CTRL; 1131 val = PORT_OVERRIDE_EN; 1132 } else { 1133 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1134 val = GMII_PO_EN; 1135 } 1136 1137 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1138 reg |= val; 1139 if (link) 1140 reg |= PORT_OVERRIDE_LINK; 1141 else 1142 reg &= ~PORT_OVERRIDE_LINK; 1143 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1144 } 1145 1146 static void b53_force_port_config(struct b53_device *dev, int port, 1147 int speed, int duplex, 1148 bool tx_pause, bool rx_pause) 1149 { 1150 u8 reg, val, off; 1151 1152 /* Override the port settings */ 1153 if (port == dev->cpu_port) { 1154 off = B53_PORT_OVERRIDE_CTRL; 1155 val = PORT_OVERRIDE_EN; 1156 } else { 1157 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1158 val = GMII_PO_EN; 1159 } 1160 1161 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1162 reg |= val; 1163 if (duplex == DUPLEX_FULL) 1164 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1165 else 1166 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1167 1168 switch (speed) { 1169 case 2000: 1170 reg |= PORT_OVERRIDE_SPEED_2000M; 1171 fallthrough; 1172 case SPEED_1000: 1173 reg |= PORT_OVERRIDE_SPEED_1000M; 1174 break; 1175 case SPEED_100: 1176 reg |= PORT_OVERRIDE_SPEED_100M; 1177 break; 1178 case SPEED_10: 1179 reg |= PORT_OVERRIDE_SPEED_10M; 1180 break; 1181 default: 1182 dev_err(dev->dev, "unknown speed: %d\n", speed); 1183 return; 1184 } 1185 1186 if (rx_pause) 1187 reg |= PORT_OVERRIDE_RX_FLOW; 1188 if (tx_pause) 1189 reg |= PORT_OVERRIDE_TX_FLOW; 1190 1191 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1192 } 1193 1194 static void b53_adjust_link(struct dsa_switch *ds, int port, 1195 struct phy_device *phydev) 1196 { 1197 struct b53_device *dev = ds->priv; 1198 struct ethtool_eee *p = &dev->ports[port].eee; 1199 u8 rgmii_ctrl = 0, reg = 0, off; 1200 bool tx_pause = false; 1201 bool rx_pause = false; 1202 1203 if (!phy_is_pseudo_fixed_link(phydev)) 1204 return; 1205 1206 /* Enable flow control on BCM5301x's CPU port */ 1207 if (is5301x(dev) && port == dev->cpu_port) 1208 tx_pause = rx_pause = true; 1209 1210 if (phydev->pause) { 1211 if (phydev->asym_pause) 1212 tx_pause = true; 1213 rx_pause = true; 1214 } 1215 1216 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, 1217 tx_pause, rx_pause); 1218 b53_force_link(dev, port, phydev->link); 1219 1220 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1221 if (port == 8) 1222 off = B53_RGMII_CTRL_IMP; 1223 else 1224 off = B53_RGMII_CTRL_P(port); 1225 1226 /* Configure the port RGMII clock delay by DLL disabled and 1227 * tx_clk aligned timing (restoring to reset defaults) 1228 */ 1229 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1230 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1231 RGMII_CTRL_TIMING_SEL); 1232 1233 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1234 * sure that we enable the port TX clock internal delay to 1235 * account for this internal delay that is inserted, otherwise 1236 * the switch won't be able to receive correctly. 1237 * 1238 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1239 * any delay neither on transmission nor reception, so the 1240 * BCM53125 must also be configured accordingly to account for 1241 * the lack of delay and introduce 1242 * 1243 * The BCM53125 switch has its RX clock and TX clock control 1244 * swapped, hence the reason why we modify the TX clock path in 1245 * the "RGMII" case 1246 */ 1247 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1248 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1249 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1250 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1251 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1252 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1253 1254 dev_info(ds->dev, "Configured port %d for %s\n", port, 1255 phy_modes(phydev->interface)); 1256 } 1257 1258 /* configure MII port if necessary */ 1259 if (is5325(dev)) { 1260 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1261 ®); 1262 1263 /* reverse mii needs to be enabled */ 1264 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1265 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1266 reg | PORT_OVERRIDE_RV_MII_25); 1267 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1268 ®); 1269 1270 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1271 dev_err(ds->dev, 1272 "Failed to enable reverse MII mode\n"); 1273 return; 1274 } 1275 } 1276 } else if (is5301x(dev)) { 1277 if (port != dev->cpu_port) { 1278 b53_force_port_config(dev, dev->cpu_port, 2000, 1279 DUPLEX_FULL, true, true); 1280 b53_force_link(dev, dev->cpu_port, 1); 1281 } 1282 } 1283 1284 /* Re-negotiate EEE if it was enabled already */ 1285 p->eee_enabled = b53_eee_init(ds, port, phydev); 1286 } 1287 1288 void b53_port_event(struct dsa_switch *ds, int port) 1289 { 1290 struct b53_device *dev = ds->priv; 1291 bool link; 1292 u16 sts; 1293 1294 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1295 link = !!(sts & BIT(port)); 1296 dsa_port_phylink_mac_change(ds, port, link); 1297 } 1298 EXPORT_SYMBOL(b53_port_event); 1299 1300 void b53_phylink_validate(struct dsa_switch *ds, int port, 1301 unsigned long *supported, 1302 struct phylink_link_state *state) 1303 { 1304 struct b53_device *dev = ds->priv; 1305 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1306 1307 if (dev->ops->serdes_phylink_validate) 1308 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1309 1310 /* Allow all the expected bits */ 1311 phylink_set(mask, Autoneg); 1312 phylink_set_port_modes(mask); 1313 phylink_set(mask, Pause); 1314 phylink_set(mask, Asym_Pause); 1315 1316 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1317 * support Gigabit, including Half duplex. 1318 */ 1319 if (state->interface != PHY_INTERFACE_MODE_MII && 1320 state->interface != PHY_INTERFACE_MODE_REVMII && 1321 !phy_interface_mode_is_8023z(state->interface) && 1322 !(is5325(dev) || is5365(dev))) { 1323 phylink_set(mask, 1000baseT_Full); 1324 phylink_set(mask, 1000baseT_Half); 1325 } 1326 1327 if (!phy_interface_mode_is_8023z(state->interface)) { 1328 phylink_set(mask, 10baseT_Half); 1329 phylink_set(mask, 10baseT_Full); 1330 phylink_set(mask, 100baseT_Half); 1331 phylink_set(mask, 100baseT_Full); 1332 } 1333 1334 bitmap_and(supported, supported, mask, 1335 __ETHTOOL_LINK_MODE_MASK_NBITS); 1336 bitmap_and(state->advertising, state->advertising, mask, 1337 __ETHTOOL_LINK_MODE_MASK_NBITS); 1338 1339 phylink_helper_basex_speed(state); 1340 } 1341 EXPORT_SYMBOL(b53_phylink_validate); 1342 1343 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1344 struct phylink_link_state *state) 1345 { 1346 struct b53_device *dev = ds->priv; 1347 int ret = -EOPNOTSUPP; 1348 1349 if ((phy_interface_mode_is_8023z(state->interface) || 1350 state->interface == PHY_INTERFACE_MODE_SGMII) && 1351 dev->ops->serdes_link_state) 1352 ret = dev->ops->serdes_link_state(dev, port, state); 1353 1354 return ret; 1355 } 1356 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1357 1358 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1359 unsigned int mode, 1360 const struct phylink_link_state *state) 1361 { 1362 struct b53_device *dev = ds->priv; 1363 1364 if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED) 1365 return; 1366 1367 if ((phy_interface_mode_is_8023z(state->interface) || 1368 state->interface == PHY_INTERFACE_MODE_SGMII) && 1369 dev->ops->serdes_config) 1370 dev->ops->serdes_config(dev, port, mode, state); 1371 } 1372 EXPORT_SYMBOL(b53_phylink_mac_config); 1373 1374 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1375 { 1376 struct b53_device *dev = ds->priv; 1377 1378 if (dev->ops->serdes_an_restart) 1379 dev->ops->serdes_an_restart(dev, port); 1380 } 1381 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1382 1383 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1384 unsigned int mode, 1385 phy_interface_t interface) 1386 { 1387 struct b53_device *dev = ds->priv; 1388 1389 if (mode == MLO_AN_PHY) 1390 return; 1391 1392 if (mode == MLO_AN_FIXED) { 1393 b53_force_link(dev, port, false); 1394 return; 1395 } 1396 1397 if (phy_interface_mode_is_8023z(interface) && 1398 dev->ops->serdes_link_set) 1399 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1400 } 1401 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1402 1403 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1404 unsigned int mode, 1405 phy_interface_t interface, 1406 struct phy_device *phydev, 1407 int speed, int duplex, 1408 bool tx_pause, bool rx_pause) 1409 { 1410 struct b53_device *dev = ds->priv; 1411 1412 if (mode == MLO_AN_PHY) 1413 return; 1414 1415 if (mode == MLO_AN_FIXED) { 1416 b53_force_port_config(dev, port, speed, duplex, 1417 tx_pause, rx_pause); 1418 b53_force_link(dev, port, true); 1419 return; 1420 } 1421 1422 if (phy_interface_mode_is_8023z(interface) && 1423 dev->ops->serdes_link_set) 1424 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1425 } 1426 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1427 1428 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1429 struct netlink_ext_ack *extack) 1430 { 1431 struct b53_device *dev = ds->priv; 1432 1433 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering); 1434 1435 return 0; 1436 } 1437 EXPORT_SYMBOL(b53_vlan_filtering); 1438 1439 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1440 const struct switchdev_obj_port_vlan *vlan) 1441 { 1442 struct b53_device *dev = ds->priv; 1443 1444 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1445 return -EOPNOTSUPP; 1446 1447 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1448 * receiving VLAN tagged frames at all, we can still allow the port to 1449 * be configured for egress untagged. 1450 */ 1451 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1452 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1453 return -EINVAL; 1454 1455 if (vlan->vid >= dev->num_vlans) 1456 return -ERANGE; 1457 1458 b53_enable_vlan(dev, port, true, ds->vlan_filtering); 1459 1460 return 0; 1461 } 1462 1463 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 1464 { 1465 struct b53_device *dev = ds->priv; 1466 1467 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 1468 } 1469 1470 int b53_vlan_add(struct dsa_switch *ds, int port, 1471 const struct switchdev_obj_port_vlan *vlan, 1472 struct netlink_ext_ack *extack) 1473 { 1474 struct b53_device *dev = ds->priv; 1475 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1476 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1477 struct b53_vlan *vl; 1478 int err; 1479 1480 err = b53_vlan_prepare(ds, port, vlan); 1481 if (err) 1482 return err; 1483 1484 vl = &dev->vlans[vlan->vid]; 1485 1486 b53_get_vlan_entry(dev, vlan->vid, vl); 1487 1488 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1489 untagged = true; 1490 1491 vl->members |= BIT(port); 1492 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1493 vl->untag |= BIT(port); 1494 else 1495 vl->untag &= ~BIT(port); 1496 1497 b53_set_vlan_entry(dev, vlan->vid, vl); 1498 b53_fast_age_vlan(dev, vlan->vid); 1499 1500 if (pvid && !dsa_is_cpu_port(ds, port)) { 1501 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1502 vlan->vid); 1503 b53_fast_age_vlan(dev, vlan->vid); 1504 } 1505 1506 return 0; 1507 } 1508 EXPORT_SYMBOL(b53_vlan_add); 1509 1510 int b53_vlan_del(struct dsa_switch *ds, int port, 1511 const struct switchdev_obj_port_vlan *vlan) 1512 { 1513 struct b53_device *dev = ds->priv; 1514 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1515 struct b53_vlan *vl; 1516 u16 pvid; 1517 1518 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1519 1520 vl = &dev->vlans[vlan->vid]; 1521 1522 b53_get_vlan_entry(dev, vlan->vid, vl); 1523 1524 vl->members &= ~BIT(port); 1525 1526 if (pvid == vlan->vid) 1527 pvid = b53_default_pvid(dev); 1528 1529 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1530 vl->untag &= ~(BIT(port)); 1531 1532 b53_set_vlan_entry(dev, vlan->vid, vl); 1533 b53_fast_age_vlan(dev, vlan->vid); 1534 1535 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1536 b53_fast_age_vlan(dev, pvid); 1537 1538 return 0; 1539 } 1540 EXPORT_SYMBOL(b53_vlan_del); 1541 1542 /* Address Resolution Logic routines */ 1543 static int b53_arl_op_wait(struct b53_device *dev) 1544 { 1545 unsigned int timeout = 10; 1546 u8 reg; 1547 1548 do { 1549 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1550 if (!(reg & ARLTBL_START_DONE)) 1551 return 0; 1552 1553 usleep_range(1000, 2000); 1554 } while (timeout--); 1555 1556 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1557 1558 return -ETIMEDOUT; 1559 } 1560 1561 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1562 { 1563 u8 reg; 1564 1565 if (op > ARLTBL_RW) 1566 return -EINVAL; 1567 1568 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1569 reg |= ARLTBL_START_DONE; 1570 if (op) 1571 reg |= ARLTBL_RW; 1572 else 1573 reg &= ~ARLTBL_RW; 1574 if (dev->vlan_enabled) 1575 reg &= ~ARLTBL_IVL_SVL_SELECT; 1576 else 1577 reg |= ARLTBL_IVL_SVL_SELECT; 1578 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1579 1580 return b53_arl_op_wait(dev); 1581 } 1582 1583 static int b53_arl_read(struct b53_device *dev, u64 mac, 1584 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1585 { 1586 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1587 unsigned int i; 1588 int ret; 1589 1590 ret = b53_arl_op_wait(dev); 1591 if (ret) 1592 return ret; 1593 1594 bitmap_zero(free_bins, dev->num_arl_bins); 1595 1596 /* Read the bins */ 1597 for (i = 0; i < dev->num_arl_bins; i++) { 1598 u64 mac_vid; 1599 u32 fwd_entry; 1600 1601 b53_read64(dev, B53_ARLIO_PAGE, 1602 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1603 b53_read32(dev, B53_ARLIO_PAGE, 1604 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1605 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1606 1607 if (!(fwd_entry & ARLTBL_VALID)) { 1608 set_bit(i, free_bins); 1609 continue; 1610 } 1611 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1612 continue; 1613 if (dev->vlan_enabled && 1614 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1615 continue; 1616 *idx = i; 1617 return 0; 1618 } 1619 1620 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0) 1621 return -ENOSPC; 1622 1623 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1624 1625 return -ENOENT; 1626 } 1627 1628 static int b53_arl_op(struct b53_device *dev, int op, int port, 1629 const unsigned char *addr, u16 vid, bool is_valid) 1630 { 1631 struct b53_arl_entry ent; 1632 u32 fwd_entry; 1633 u64 mac, mac_vid = 0; 1634 u8 idx = 0; 1635 int ret; 1636 1637 /* Convert the array into a 64-bit MAC */ 1638 mac = ether_addr_to_u64(addr); 1639 1640 /* Perform a read for the given MAC and VID */ 1641 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1642 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1643 1644 /* Issue a read operation for this MAC */ 1645 ret = b53_arl_rw_op(dev, 1); 1646 if (ret) 1647 return ret; 1648 1649 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1650 1651 /* If this is a read, just finish now */ 1652 if (op) 1653 return ret; 1654 1655 switch (ret) { 1656 case -ETIMEDOUT: 1657 return ret; 1658 case -ENOSPC: 1659 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1660 addr, vid); 1661 return is_valid ? ret : 0; 1662 case -ENOENT: 1663 /* We could not find a matching MAC, so reset to a new entry */ 1664 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1665 addr, vid, idx); 1666 fwd_entry = 0; 1667 break; 1668 default: 1669 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1670 addr, vid, idx); 1671 break; 1672 } 1673 1674 /* For multicast address, the port is a bitmask and the validity 1675 * is determined by having at least one port being still active 1676 */ 1677 if (!is_multicast_ether_addr(addr)) { 1678 ent.port = port; 1679 ent.is_valid = is_valid; 1680 } else { 1681 if (is_valid) 1682 ent.port |= BIT(port); 1683 else 1684 ent.port &= ~BIT(port); 1685 1686 ent.is_valid = !!(ent.port); 1687 } 1688 1689 ent.vid = vid; 1690 ent.is_static = true; 1691 ent.is_age = false; 1692 memcpy(ent.mac, addr, ETH_ALEN); 1693 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1694 1695 b53_write64(dev, B53_ARLIO_PAGE, 1696 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1697 b53_write32(dev, B53_ARLIO_PAGE, 1698 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1699 1700 return b53_arl_rw_op(dev, 0); 1701 } 1702 1703 int b53_fdb_add(struct dsa_switch *ds, int port, 1704 const unsigned char *addr, u16 vid) 1705 { 1706 struct b53_device *priv = ds->priv; 1707 1708 /* 5325 and 5365 require some more massaging, but could 1709 * be supported eventually 1710 */ 1711 if (is5325(priv) || is5365(priv)) 1712 return -EOPNOTSUPP; 1713 1714 return b53_arl_op(priv, 0, port, addr, vid, true); 1715 } 1716 EXPORT_SYMBOL(b53_fdb_add); 1717 1718 int b53_fdb_del(struct dsa_switch *ds, int port, 1719 const unsigned char *addr, u16 vid) 1720 { 1721 struct b53_device *priv = ds->priv; 1722 1723 return b53_arl_op(priv, 0, port, addr, vid, false); 1724 } 1725 EXPORT_SYMBOL(b53_fdb_del); 1726 1727 static int b53_arl_search_wait(struct b53_device *dev) 1728 { 1729 unsigned int timeout = 1000; 1730 u8 reg; 1731 1732 do { 1733 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1734 if (!(reg & ARL_SRCH_STDN)) 1735 return 0; 1736 1737 if (reg & ARL_SRCH_VLID) 1738 return 0; 1739 1740 usleep_range(1000, 2000); 1741 } while (timeout--); 1742 1743 return -ETIMEDOUT; 1744 } 1745 1746 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1747 struct b53_arl_entry *ent) 1748 { 1749 u64 mac_vid; 1750 u32 fwd_entry; 1751 1752 b53_read64(dev, B53_ARLIO_PAGE, 1753 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1754 b53_read32(dev, B53_ARLIO_PAGE, 1755 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1756 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1757 } 1758 1759 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1760 dsa_fdb_dump_cb_t *cb, void *data) 1761 { 1762 if (!ent->is_valid) 1763 return 0; 1764 1765 if (port != ent->port) 1766 return 0; 1767 1768 return cb(ent->mac, ent->vid, ent->is_static, data); 1769 } 1770 1771 int b53_fdb_dump(struct dsa_switch *ds, int port, 1772 dsa_fdb_dump_cb_t *cb, void *data) 1773 { 1774 struct b53_device *priv = ds->priv; 1775 struct b53_arl_entry results[2]; 1776 unsigned int count = 0; 1777 int ret; 1778 u8 reg; 1779 1780 /* Start search operation */ 1781 reg = ARL_SRCH_STDN; 1782 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1783 1784 do { 1785 ret = b53_arl_search_wait(priv); 1786 if (ret) 1787 return ret; 1788 1789 b53_arl_search_rd(priv, 0, &results[0]); 1790 ret = b53_fdb_copy(port, &results[0], cb, data); 1791 if (ret) 1792 return ret; 1793 1794 if (priv->num_arl_bins > 2) { 1795 b53_arl_search_rd(priv, 1, &results[1]); 1796 ret = b53_fdb_copy(port, &results[1], cb, data); 1797 if (ret) 1798 return ret; 1799 1800 if (!results[0].is_valid && !results[1].is_valid) 1801 break; 1802 } 1803 1804 } while (count++ < b53_max_arl_entries(priv) / 2); 1805 1806 return 0; 1807 } 1808 EXPORT_SYMBOL(b53_fdb_dump); 1809 1810 int b53_mdb_add(struct dsa_switch *ds, int port, 1811 const struct switchdev_obj_port_mdb *mdb) 1812 { 1813 struct b53_device *priv = ds->priv; 1814 1815 /* 5325 and 5365 require some more massaging, but could 1816 * be supported eventually 1817 */ 1818 if (is5325(priv) || is5365(priv)) 1819 return -EOPNOTSUPP; 1820 1821 return b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1822 } 1823 EXPORT_SYMBOL(b53_mdb_add); 1824 1825 int b53_mdb_del(struct dsa_switch *ds, int port, 1826 const struct switchdev_obj_port_mdb *mdb) 1827 { 1828 struct b53_device *priv = ds->priv; 1829 int ret; 1830 1831 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1832 if (ret) 1833 dev_err(ds->dev, "failed to delete MDB entry\n"); 1834 1835 return ret; 1836 } 1837 EXPORT_SYMBOL(b53_mdb_del); 1838 1839 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1840 { 1841 struct b53_device *dev = ds->priv; 1842 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1843 u16 pvlan, reg; 1844 unsigned int i; 1845 1846 /* On 7278, port 7 which connects to the ASP should only receive 1847 * traffic from matching CFP rules. 1848 */ 1849 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1850 return -EINVAL; 1851 1852 /* Make this port leave the all VLANs join since we will have proper 1853 * VLAN entries from now on 1854 */ 1855 if (is58xx(dev)) { 1856 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1857 reg &= ~BIT(port); 1858 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1859 reg &= ~BIT(cpu_port); 1860 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1861 } 1862 1863 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1864 1865 b53_for_each_port(dev, i) { 1866 if (dsa_to_port(ds, i)->bridge_dev != br) 1867 continue; 1868 1869 /* Add this local port to the remote port VLAN control 1870 * membership and update the remote port bitmask 1871 */ 1872 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1873 reg |= BIT(port); 1874 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1875 dev->ports[i].vlan_ctl_mask = reg; 1876 1877 pvlan |= BIT(i); 1878 } 1879 1880 /* Configure the local port VLAN control membership to include 1881 * remote ports and update the local port bitmask 1882 */ 1883 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1884 dev->ports[port].vlan_ctl_mask = pvlan; 1885 1886 return 0; 1887 } 1888 EXPORT_SYMBOL(b53_br_join); 1889 1890 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1891 { 1892 struct b53_device *dev = ds->priv; 1893 struct b53_vlan *vl = &dev->vlans[0]; 1894 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1895 unsigned int i; 1896 u16 pvlan, reg, pvid; 1897 1898 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1899 1900 b53_for_each_port(dev, i) { 1901 /* Don't touch the remaining ports */ 1902 if (dsa_to_port(ds, i)->bridge_dev != br) 1903 continue; 1904 1905 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1906 reg &= ~BIT(port); 1907 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1908 dev->ports[port].vlan_ctl_mask = reg; 1909 1910 /* Prevent self removal to preserve isolation */ 1911 if (port != i) 1912 pvlan &= ~BIT(i); 1913 } 1914 1915 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1916 dev->ports[port].vlan_ctl_mask = pvlan; 1917 1918 pvid = b53_default_pvid(dev); 1919 1920 /* Make this port join all VLANs without VLAN entries */ 1921 if (is58xx(dev)) { 1922 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1923 reg |= BIT(port); 1924 if (!(reg & BIT(cpu_port))) 1925 reg |= BIT(cpu_port); 1926 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1927 } else { 1928 b53_get_vlan_entry(dev, pvid, vl); 1929 vl->members |= BIT(port) | BIT(cpu_port); 1930 vl->untag |= BIT(port) | BIT(cpu_port); 1931 b53_set_vlan_entry(dev, pvid, vl); 1932 } 1933 } 1934 EXPORT_SYMBOL(b53_br_leave); 1935 1936 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1937 { 1938 struct b53_device *dev = ds->priv; 1939 u8 hw_state; 1940 u8 reg; 1941 1942 switch (state) { 1943 case BR_STATE_DISABLED: 1944 hw_state = PORT_CTRL_DIS_STATE; 1945 break; 1946 case BR_STATE_LISTENING: 1947 hw_state = PORT_CTRL_LISTEN_STATE; 1948 break; 1949 case BR_STATE_LEARNING: 1950 hw_state = PORT_CTRL_LEARN_STATE; 1951 break; 1952 case BR_STATE_FORWARDING: 1953 hw_state = PORT_CTRL_FWD_STATE; 1954 break; 1955 case BR_STATE_BLOCKING: 1956 hw_state = PORT_CTRL_BLOCK_STATE; 1957 break; 1958 default: 1959 dev_err(ds->dev, "invalid STP state: %d\n", state); 1960 return; 1961 } 1962 1963 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1964 reg &= ~PORT_CTRL_STP_STATE_MASK; 1965 reg |= hw_state; 1966 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1967 } 1968 EXPORT_SYMBOL(b53_br_set_stp_state); 1969 1970 void b53_br_fast_age(struct dsa_switch *ds, int port) 1971 { 1972 struct b53_device *dev = ds->priv; 1973 1974 if (b53_fast_age_port(dev, port)) 1975 dev_err(ds->dev, "fast ageing failed\n"); 1976 } 1977 EXPORT_SYMBOL(b53_br_fast_age); 1978 1979 int b53_br_flags_pre(struct dsa_switch *ds, int port, 1980 struct switchdev_brport_flags flags, 1981 struct netlink_ext_ack *extack) 1982 { 1983 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 1984 return -EINVAL; 1985 1986 return 0; 1987 } 1988 EXPORT_SYMBOL(b53_br_flags_pre); 1989 1990 int b53_br_flags(struct dsa_switch *ds, int port, 1991 struct switchdev_brport_flags flags, 1992 struct netlink_ext_ack *extack) 1993 { 1994 if (flags.mask & BR_FLOOD) 1995 b53_port_set_ucast_flood(ds->priv, port, 1996 !!(flags.val & BR_FLOOD)); 1997 if (flags.mask & BR_MCAST_FLOOD) 1998 b53_port_set_mcast_flood(ds->priv, port, 1999 !!(flags.val & BR_MCAST_FLOOD)); 2000 if (flags.mask & BR_LEARNING) 2001 b53_port_set_learning(ds->priv, port, 2002 !!(flags.val & BR_LEARNING)); 2003 2004 return 0; 2005 } 2006 EXPORT_SYMBOL(b53_br_flags); 2007 2008 int b53_set_mrouter(struct dsa_switch *ds, int port, bool mrouter, 2009 struct netlink_ext_ack *extack) 2010 { 2011 b53_port_set_mcast_flood(ds->priv, port, mrouter); 2012 2013 return 0; 2014 } 2015 EXPORT_SYMBOL(b53_set_mrouter); 2016 2017 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2018 { 2019 /* Broadcom switches will accept enabling Broadcom tags on the 2020 * following ports: 5, 7 and 8, any other port is not supported 2021 */ 2022 switch (port) { 2023 case B53_CPU_PORT_25: 2024 case 7: 2025 case B53_CPU_PORT: 2026 return true; 2027 } 2028 2029 return false; 2030 } 2031 2032 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2033 enum dsa_tag_protocol tag_protocol) 2034 { 2035 bool ret = b53_possible_cpu_port(ds, port); 2036 2037 if (!ret) { 2038 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2039 port); 2040 return ret; 2041 } 2042 2043 switch (tag_protocol) { 2044 case DSA_TAG_PROTO_BRCM: 2045 case DSA_TAG_PROTO_BRCM_PREPEND: 2046 dev_warn(ds->dev, 2047 "Port %d is stacked to Broadcom tag switch\n", port); 2048 ret = false; 2049 break; 2050 default: 2051 ret = true; 2052 break; 2053 } 2054 2055 return ret; 2056 } 2057 2058 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2059 enum dsa_tag_protocol mprot) 2060 { 2061 struct b53_device *dev = ds->priv; 2062 2063 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2064 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2065 goto out; 2066 } 2067 2068 /* Older models require a different 6 byte tag */ 2069 if (is5325(dev) || is5365(dev) || is63xx(dev)) { 2070 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2071 goto out; 2072 } 2073 2074 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2075 * which requires us to use the prepended Broadcom tag type 2076 */ 2077 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2078 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2079 goto out; 2080 } 2081 2082 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2083 out: 2084 return dev->tag_protocol; 2085 } 2086 EXPORT_SYMBOL(b53_get_tag_protocol); 2087 2088 int b53_mirror_add(struct dsa_switch *ds, int port, 2089 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 2090 { 2091 struct b53_device *dev = ds->priv; 2092 u16 reg, loc; 2093 2094 if (ingress) 2095 loc = B53_IG_MIR_CTL; 2096 else 2097 loc = B53_EG_MIR_CTL; 2098 2099 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2100 reg |= BIT(port); 2101 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2102 2103 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2104 reg &= ~CAP_PORT_MASK; 2105 reg |= mirror->to_local_port; 2106 reg |= MIRROR_EN; 2107 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2108 2109 return 0; 2110 } 2111 EXPORT_SYMBOL(b53_mirror_add); 2112 2113 void b53_mirror_del(struct dsa_switch *ds, int port, 2114 struct dsa_mall_mirror_tc_entry *mirror) 2115 { 2116 struct b53_device *dev = ds->priv; 2117 bool loc_disable = false, other_loc_disable = false; 2118 u16 reg, loc; 2119 2120 if (mirror->ingress) 2121 loc = B53_IG_MIR_CTL; 2122 else 2123 loc = B53_EG_MIR_CTL; 2124 2125 /* Update the desired ingress/egress register */ 2126 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2127 reg &= ~BIT(port); 2128 if (!(reg & MIRROR_MASK)) 2129 loc_disable = true; 2130 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2131 2132 /* Now look at the other one to know if we can disable mirroring 2133 * entirely 2134 */ 2135 if (mirror->ingress) 2136 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2137 else 2138 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2139 if (!(reg & MIRROR_MASK)) 2140 other_loc_disable = true; 2141 2142 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2143 /* Both no longer have ports, let's disable mirroring */ 2144 if (loc_disable && other_loc_disable) { 2145 reg &= ~MIRROR_EN; 2146 reg &= ~mirror->to_local_port; 2147 } 2148 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2149 } 2150 EXPORT_SYMBOL(b53_mirror_del); 2151 2152 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 2153 { 2154 struct b53_device *dev = ds->priv; 2155 u16 reg; 2156 2157 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 2158 if (enable) 2159 reg |= BIT(port); 2160 else 2161 reg &= ~BIT(port); 2162 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 2163 } 2164 EXPORT_SYMBOL(b53_eee_enable_set); 2165 2166 2167 /* Returns 0 if EEE was not enabled, or 1 otherwise 2168 */ 2169 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2170 { 2171 int ret; 2172 2173 ret = phy_init_eee(phy, 0); 2174 if (ret) 2175 return 0; 2176 2177 b53_eee_enable_set(ds, port, true); 2178 2179 return 1; 2180 } 2181 EXPORT_SYMBOL(b53_eee_init); 2182 2183 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2184 { 2185 struct b53_device *dev = ds->priv; 2186 struct ethtool_eee *p = &dev->ports[port].eee; 2187 u16 reg; 2188 2189 if (is5325(dev) || is5365(dev)) 2190 return -EOPNOTSUPP; 2191 2192 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 2193 e->eee_enabled = p->eee_enabled; 2194 e->eee_active = !!(reg & BIT(port)); 2195 2196 return 0; 2197 } 2198 EXPORT_SYMBOL(b53_get_mac_eee); 2199 2200 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2201 { 2202 struct b53_device *dev = ds->priv; 2203 struct ethtool_eee *p = &dev->ports[port].eee; 2204 2205 if (is5325(dev) || is5365(dev)) 2206 return -EOPNOTSUPP; 2207 2208 p->eee_enabled = e->eee_enabled; 2209 b53_eee_enable_set(ds, port, e->eee_enabled); 2210 2211 return 0; 2212 } 2213 EXPORT_SYMBOL(b53_set_mac_eee); 2214 2215 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2216 { 2217 struct b53_device *dev = ds->priv; 2218 bool enable_jumbo; 2219 bool allow_10_100; 2220 2221 if (is5325(dev) || is5365(dev)) 2222 return -EOPNOTSUPP; 2223 2224 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2225 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2226 2227 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2228 } 2229 2230 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2231 { 2232 return JMS_MAX_SIZE; 2233 } 2234 2235 static const struct dsa_switch_ops b53_switch_ops = { 2236 .get_tag_protocol = b53_get_tag_protocol, 2237 .setup = b53_setup, 2238 .teardown = b53_teardown, 2239 .get_strings = b53_get_strings, 2240 .get_ethtool_stats = b53_get_ethtool_stats, 2241 .get_sset_count = b53_get_sset_count, 2242 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2243 .phy_read = b53_phy_read16, 2244 .phy_write = b53_phy_write16, 2245 .adjust_link = b53_adjust_link, 2246 .phylink_validate = b53_phylink_validate, 2247 .phylink_mac_link_state = b53_phylink_mac_link_state, 2248 .phylink_mac_config = b53_phylink_mac_config, 2249 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 2250 .phylink_mac_link_down = b53_phylink_mac_link_down, 2251 .phylink_mac_link_up = b53_phylink_mac_link_up, 2252 .port_enable = b53_enable_port, 2253 .port_disable = b53_disable_port, 2254 .get_mac_eee = b53_get_mac_eee, 2255 .set_mac_eee = b53_set_mac_eee, 2256 .port_bridge_join = b53_br_join, 2257 .port_bridge_leave = b53_br_leave, 2258 .port_pre_bridge_flags = b53_br_flags_pre, 2259 .port_bridge_flags = b53_br_flags, 2260 .port_set_mrouter = b53_set_mrouter, 2261 .port_stp_state_set = b53_br_set_stp_state, 2262 .port_fast_age = b53_br_fast_age, 2263 .port_vlan_filtering = b53_vlan_filtering, 2264 .port_vlan_add = b53_vlan_add, 2265 .port_vlan_del = b53_vlan_del, 2266 .port_fdb_dump = b53_fdb_dump, 2267 .port_fdb_add = b53_fdb_add, 2268 .port_fdb_del = b53_fdb_del, 2269 .port_mirror_add = b53_mirror_add, 2270 .port_mirror_del = b53_mirror_del, 2271 .port_mdb_add = b53_mdb_add, 2272 .port_mdb_del = b53_mdb_del, 2273 .port_max_mtu = b53_get_max_mtu, 2274 .port_change_mtu = b53_change_mtu, 2275 }; 2276 2277 struct b53_chip_data { 2278 u32 chip_id; 2279 const char *dev_name; 2280 u16 vlans; 2281 u16 enabled_ports; 2282 u8 cpu_port; 2283 u8 vta_regs[3]; 2284 u8 arl_bins; 2285 u16 arl_buckets; 2286 u8 duplex_reg; 2287 u8 jumbo_pm_reg; 2288 u8 jumbo_size_reg; 2289 }; 2290 2291 #define B53_VTA_REGS \ 2292 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2293 #define B53_VTA_REGS_9798 \ 2294 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2295 #define B53_VTA_REGS_63XX \ 2296 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2297 2298 static const struct b53_chip_data b53_switch_chips[] = { 2299 { 2300 .chip_id = BCM5325_DEVICE_ID, 2301 .dev_name = "BCM5325", 2302 .vlans = 16, 2303 .enabled_ports = 0x1f, 2304 .arl_bins = 2, 2305 .arl_buckets = 1024, 2306 .cpu_port = B53_CPU_PORT_25, 2307 .duplex_reg = B53_DUPLEX_STAT_FE, 2308 }, 2309 { 2310 .chip_id = BCM5365_DEVICE_ID, 2311 .dev_name = "BCM5365", 2312 .vlans = 256, 2313 .enabled_ports = 0x1f, 2314 .arl_bins = 2, 2315 .arl_buckets = 1024, 2316 .cpu_port = B53_CPU_PORT_25, 2317 .duplex_reg = B53_DUPLEX_STAT_FE, 2318 }, 2319 { 2320 .chip_id = BCM5389_DEVICE_ID, 2321 .dev_name = "BCM5389", 2322 .vlans = 4096, 2323 .enabled_ports = 0x1f, 2324 .arl_bins = 4, 2325 .arl_buckets = 1024, 2326 .cpu_port = B53_CPU_PORT, 2327 .vta_regs = B53_VTA_REGS, 2328 .duplex_reg = B53_DUPLEX_STAT_GE, 2329 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2330 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2331 }, 2332 { 2333 .chip_id = BCM5395_DEVICE_ID, 2334 .dev_name = "BCM5395", 2335 .vlans = 4096, 2336 .enabled_ports = 0x1f, 2337 .arl_bins = 4, 2338 .arl_buckets = 1024, 2339 .cpu_port = B53_CPU_PORT, 2340 .vta_regs = B53_VTA_REGS, 2341 .duplex_reg = B53_DUPLEX_STAT_GE, 2342 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2343 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2344 }, 2345 { 2346 .chip_id = BCM5397_DEVICE_ID, 2347 .dev_name = "BCM5397", 2348 .vlans = 4096, 2349 .enabled_ports = 0x1f, 2350 .arl_bins = 4, 2351 .arl_buckets = 1024, 2352 .cpu_port = B53_CPU_PORT, 2353 .vta_regs = B53_VTA_REGS_9798, 2354 .duplex_reg = B53_DUPLEX_STAT_GE, 2355 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2356 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2357 }, 2358 { 2359 .chip_id = BCM5398_DEVICE_ID, 2360 .dev_name = "BCM5398", 2361 .vlans = 4096, 2362 .enabled_ports = 0x7f, 2363 .arl_bins = 4, 2364 .arl_buckets = 1024, 2365 .cpu_port = B53_CPU_PORT, 2366 .vta_regs = B53_VTA_REGS_9798, 2367 .duplex_reg = B53_DUPLEX_STAT_GE, 2368 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2369 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2370 }, 2371 { 2372 .chip_id = BCM53115_DEVICE_ID, 2373 .dev_name = "BCM53115", 2374 .vlans = 4096, 2375 .enabled_ports = 0x1f, 2376 .arl_bins = 4, 2377 .arl_buckets = 1024, 2378 .vta_regs = B53_VTA_REGS, 2379 .cpu_port = B53_CPU_PORT, 2380 .duplex_reg = B53_DUPLEX_STAT_GE, 2381 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2382 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2383 }, 2384 { 2385 .chip_id = BCM53125_DEVICE_ID, 2386 .dev_name = "BCM53125", 2387 .vlans = 4096, 2388 .enabled_ports = 0xff, 2389 .arl_bins = 4, 2390 .arl_buckets = 1024, 2391 .cpu_port = B53_CPU_PORT, 2392 .vta_regs = B53_VTA_REGS, 2393 .duplex_reg = B53_DUPLEX_STAT_GE, 2394 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2395 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2396 }, 2397 { 2398 .chip_id = BCM53128_DEVICE_ID, 2399 .dev_name = "BCM53128", 2400 .vlans = 4096, 2401 .enabled_ports = 0x1ff, 2402 .arl_bins = 4, 2403 .arl_buckets = 1024, 2404 .cpu_port = B53_CPU_PORT, 2405 .vta_regs = B53_VTA_REGS, 2406 .duplex_reg = B53_DUPLEX_STAT_GE, 2407 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2408 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2409 }, 2410 { 2411 .chip_id = BCM63XX_DEVICE_ID, 2412 .dev_name = "BCM63xx", 2413 .vlans = 4096, 2414 .enabled_ports = 0, /* pdata must provide them */ 2415 .arl_bins = 4, 2416 .arl_buckets = 1024, 2417 .cpu_port = B53_CPU_PORT, 2418 .vta_regs = B53_VTA_REGS_63XX, 2419 .duplex_reg = B53_DUPLEX_STAT_63XX, 2420 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2421 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2422 }, 2423 { 2424 .chip_id = BCM53010_DEVICE_ID, 2425 .dev_name = "BCM53010", 2426 .vlans = 4096, 2427 .enabled_ports = 0x1f, 2428 .arl_bins = 4, 2429 .arl_buckets = 1024, 2430 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2431 .vta_regs = B53_VTA_REGS, 2432 .duplex_reg = B53_DUPLEX_STAT_GE, 2433 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2434 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2435 }, 2436 { 2437 .chip_id = BCM53011_DEVICE_ID, 2438 .dev_name = "BCM53011", 2439 .vlans = 4096, 2440 .enabled_ports = 0x1bf, 2441 .arl_bins = 4, 2442 .arl_buckets = 1024, 2443 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2444 .vta_regs = B53_VTA_REGS, 2445 .duplex_reg = B53_DUPLEX_STAT_GE, 2446 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2447 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2448 }, 2449 { 2450 .chip_id = BCM53012_DEVICE_ID, 2451 .dev_name = "BCM53012", 2452 .vlans = 4096, 2453 .enabled_ports = 0x1bf, 2454 .arl_bins = 4, 2455 .arl_buckets = 1024, 2456 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2457 .vta_regs = B53_VTA_REGS, 2458 .duplex_reg = B53_DUPLEX_STAT_GE, 2459 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2460 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2461 }, 2462 { 2463 .chip_id = BCM53018_DEVICE_ID, 2464 .dev_name = "BCM53018", 2465 .vlans = 4096, 2466 .enabled_ports = 0x1f, 2467 .arl_bins = 4, 2468 .arl_buckets = 1024, 2469 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2470 .vta_regs = B53_VTA_REGS, 2471 .duplex_reg = B53_DUPLEX_STAT_GE, 2472 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2473 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2474 }, 2475 { 2476 .chip_id = BCM53019_DEVICE_ID, 2477 .dev_name = "BCM53019", 2478 .vlans = 4096, 2479 .enabled_ports = 0x1f, 2480 .arl_bins = 4, 2481 .arl_buckets = 1024, 2482 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2483 .vta_regs = B53_VTA_REGS, 2484 .duplex_reg = B53_DUPLEX_STAT_GE, 2485 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2486 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2487 }, 2488 { 2489 .chip_id = BCM58XX_DEVICE_ID, 2490 .dev_name = "BCM585xx/586xx/88312", 2491 .vlans = 4096, 2492 .enabled_ports = 0x1ff, 2493 .arl_bins = 4, 2494 .arl_buckets = 1024, 2495 .cpu_port = B53_CPU_PORT, 2496 .vta_regs = B53_VTA_REGS, 2497 .duplex_reg = B53_DUPLEX_STAT_GE, 2498 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2499 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2500 }, 2501 { 2502 .chip_id = BCM583XX_DEVICE_ID, 2503 .dev_name = "BCM583xx/11360", 2504 .vlans = 4096, 2505 .enabled_ports = 0x103, 2506 .arl_bins = 4, 2507 .arl_buckets = 1024, 2508 .cpu_port = B53_CPU_PORT, 2509 .vta_regs = B53_VTA_REGS, 2510 .duplex_reg = B53_DUPLEX_STAT_GE, 2511 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2512 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2513 }, 2514 /* Starfighter 2 */ 2515 { 2516 .chip_id = BCM4908_DEVICE_ID, 2517 .dev_name = "BCM4908", 2518 .vlans = 4096, 2519 .enabled_ports = 0x1bf, 2520 .arl_bins = 4, 2521 .arl_buckets = 256, 2522 .cpu_port = 8, /* TODO: ports 4, 5, 8 */ 2523 .vta_regs = B53_VTA_REGS, 2524 .duplex_reg = B53_DUPLEX_STAT_GE, 2525 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2526 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2527 }, 2528 { 2529 .chip_id = BCM7445_DEVICE_ID, 2530 .dev_name = "BCM7445", 2531 .vlans = 4096, 2532 .enabled_ports = 0x1ff, 2533 .arl_bins = 4, 2534 .arl_buckets = 1024, 2535 .cpu_port = B53_CPU_PORT, 2536 .vta_regs = B53_VTA_REGS, 2537 .duplex_reg = B53_DUPLEX_STAT_GE, 2538 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2539 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2540 }, 2541 { 2542 .chip_id = BCM7278_DEVICE_ID, 2543 .dev_name = "BCM7278", 2544 .vlans = 4096, 2545 .enabled_ports = 0x1ff, 2546 .arl_bins = 4, 2547 .arl_buckets = 256, 2548 .cpu_port = B53_CPU_PORT, 2549 .vta_regs = B53_VTA_REGS, 2550 .duplex_reg = B53_DUPLEX_STAT_GE, 2551 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2552 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2553 }, 2554 }; 2555 2556 static int b53_switch_init(struct b53_device *dev) 2557 { 2558 unsigned int i; 2559 int ret; 2560 2561 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2562 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2563 2564 if (chip->chip_id == dev->chip_id) { 2565 if (!dev->enabled_ports) 2566 dev->enabled_ports = chip->enabled_ports; 2567 dev->name = chip->dev_name; 2568 dev->duplex_reg = chip->duplex_reg; 2569 dev->vta_regs[0] = chip->vta_regs[0]; 2570 dev->vta_regs[1] = chip->vta_regs[1]; 2571 dev->vta_regs[2] = chip->vta_regs[2]; 2572 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2573 dev->cpu_port = chip->cpu_port; 2574 dev->num_vlans = chip->vlans; 2575 dev->num_arl_bins = chip->arl_bins; 2576 dev->num_arl_buckets = chip->arl_buckets; 2577 break; 2578 } 2579 } 2580 2581 /* check which BCM5325x version we have */ 2582 if (is5325(dev)) { 2583 u8 vc4; 2584 2585 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2586 2587 /* check reserved bits */ 2588 switch (vc4 & 3) { 2589 case 1: 2590 /* BCM5325E */ 2591 break; 2592 case 3: 2593 /* BCM5325F - do not use port 4 */ 2594 dev->enabled_ports &= ~BIT(4); 2595 break; 2596 default: 2597 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2598 #ifndef CONFIG_BCM47XX 2599 /* BCM5325M */ 2600 return -EINVAL; 2601 #else 2602 break; 2603 #endif 2604 } 2605 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2606 u64 strap_value; 2607 2608 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2609 /* use second IMP port if GMII is enabled */ 2610 if (strap_value & SV_GMII_CTRL_115) 2611 dev->cpu_port = 5; 2612 } 2613 2614 /* cpu port is always last */ 2615 dev->num_ports = dev->cpu_port + 1; 2616 dev->enabled_ports |= BIT(dev->cpu_port); 2617 2618 /* Include non standard CPU port built-in PHYs to be probed */ 2619 if (is539x(dev) || is531x5(dev)) { 2620 for (i = 0; i < dev->num_ports; i++) { 2621 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2622 !b53_possible_cpu_port(dev->ds, i)) 2623 dev->ds->phys_mii_mask |= BIT(i); 2624 } 2625 } 2626 2627 dev->ports = devm_kcalloc(dev->dev, 2628 dev->num_ports, sizeof(struct b53_port), 2629 GFP_KERNEL); 2630 if (!dev->ports) 2631 return -ENOMEM; 2632 2633 dev->vlans = devm_kcalloc(dev->dev, 2634 dev->num_vlans, sizeof(struct b53_vlan), 2635 GFP_KERNEL); 2636 if (!dev->vlans) 2637 return -ENOMEM; 2638 2639 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2640 if (dev->reset_gpio >= 0) { 2641 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2642 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2643 if (ret) 2644 return ret; 2645 } 2646 2647 return 0; 2648 } 2649 2650 struct b53_device *b53_switch_alloc(struct device *base, 2651 const struct b53_io_ops *ops, 2652 void *priv) 2653 { 2654 struct dsa_switch *ds; 2655 struct b53_device *dev; 2656 2657 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2658 if (!ds) 2659 return NULL; 2660 2661 ds->dev = base; 2662 ds->num_ports = DSA_MAX_PORTS; 2663 2664 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2665 if (!dev) 2666 return NULL; 2667 2668 ds->priv = dev; 2669 dev->dev = base; 2670 2671 dev->ds = ds; 2672 dev->priv = priv; 2673 dev->ops = ops; 2674 ds->ops = &b53_switch_ops; 2675 dev->vlan_enabled = true; 2676 /* Let DSA handle the case were multiple bridges span the same switch 2677 * device and different VLAN awareness settings are requested, which 2678 * would be breaking filtering semantics for any of the other bridge 2679 * devices. (not hardware supported) 2680 */ 2681 ds->vlan_filtering_is_global = true; 2682 2683 mutex_init(&dev->reg_mutex); 2684 mutex_init(&dev->stats_mutex); 2685 2686 return dev; 2687 } 2688 EXPORT_SYMBOL(b53_switch_alloc); 2689 2690 int b53_switch_detect(struct b53_device *dev) 2691 { 2692 u32 id32; 2693 u16 tmp; 2694 u8 id8; 2695 int ret; 2696 2697 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2698 if (ret) 2699 return ret; 2700 2701 switch (id8) { 2702 case 0: 2703 /* BCM5325 and BCM5365 do not have this register so reads 2704 * return 0. But the read operation did succeed, so assume this 2705 * is one of them. 2706 * 2707 * Next check if we can write to the 5325's VTA register; for 2708 * 5365 it is read only. 2709 */ 2710 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2711 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2712 2713 if (tmp == 0xf) 2714 dev->chip_id = BCM5325_DEVICE_ID; 2715 else 2716 dev->chip_id = BCM5365_DEVICE_ID; 2717 break; 2718 case BCM5389_DEVICE_ID: 2719 case BCM5395_DEVICE_ID: 2720 case BCM5397_DEVICE_ID: 2721 case BCM5398_DEVICE_ID: 2722 dev->chip_id = id8; 2723 break; 2724 default: 2725 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2726 if (ret) 2727 return ret; 2728 2729 switch (id32) { 2730 case BCM53115_DEVICE_ID: 2731 case BCM53125_DEVICE_ID: 2732 case BCM53128_DEVICE_ID: 2733 case BCM53010_DEVICE_ID: 2734 case BCM53011_DEVICE_ID: 2735 case BCM53012_DEVICE_ID: 2736 case BCM53018_DEVICE_ID: 2737 case BCM53019_DEVICE_ID: 2738 dev->chip_id = id32; 2739 break; 2740 default: 2741 dev_err(dev->dev, 2742 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2743 id8, id32); 2744 return -ENODEV; 2745 } 2746 } 2747 2748 if (dev->chip_id == BCM5325_DEVICE_ID) 2749 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2750 &dev->core_rev); 2751 else 2752 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2753 &dev->core_rev); 2754 } 2755 EXPORT_SYMBOL(b53_switch_detect); 2756 2757 int b53_switch_register(struct b53_device *dev) 2758 { 2759 int ret; 2760 2761 if (dev->pdata) { 2762 dev->chip_id = dev->pdata->chip_id; 2763 dev->enabled_ports = dev->pdata->enabled_ports; 2764 } 2765 2766 if (!dev->chip_id && b53_switch_detect(dev)) 2767 return -EINVAL; 2768 2769 ret = b53_switch_init(dev); 2770 if (ret) 2771 return ret; 2772 2773 dev_info(dev->dev, "found switch: %s, rev %i\n", 2774 dev->name, dev->core_rev); 2775 2776 return dsa_register_switch(dev->ds); 2777 } 2778 EXPORT_SYMBOL(b53_switch_register); 2779 2780 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2781 MODULE_DESCRIPTION("B53 switch library"); 2782 MODULE_LICENSE("Dual BSD/GPL"); 2783