1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <net/dsa.h> 31 32 #include "b53_regs.h" 33 #include "b53_priv.h" 34 35 struct b53_mib_desc { 36 u8 size; 37 u8 offset; 38 const char *name; 39 }; 40 41 /* BCM5365 MIB counters */ 42 static const struct b53_mib_desc b53_mibs_65[] = { 43 { 8, 0x00, "TxOctets" }, 44 { 4, 0x08, "TxDropPkts" }, 45 { 4, 0x10, "TxBroadcastPkts" }, 46 { 4, 0x14, "TxMulticastPkts" }, 47 { 4, 0x18, "TxUnicastPkts" }, 48 { 4, 0x1c, "TxCollisions" }, 49 { 4, 0x20, "TxSingleCollision" }, 50 { 4, 0x24, "TxMultipleCollision" }, 51 { 4, 0x28, "TxDeferredTransmit" }, 52 { 4, 0x2c, "TxLateCollision" }, 53 { 4, 0x30, "TxExcessiveCollision" }, 54 { 4, 0x38, "TxPausePkts" }, 55 { 8, 0x44, "RxOctets" }, 56 { 4, 0x4c, "RxUndersizePkts" }, 57 { 4, 0x50, "RxPausePkts" }, 58 { 4, 0x54, "Pkts64Octets" }, 59 { 4, 0x58, "Pkts65to127Octets" }, 60 { 4, 0x5c, "Pkts128to255Octets" }, 61 { 4, 0x60, "Pkts256to511Octets" }, 62 { 4, 0x64, "Pkts512to1023Octets" }, 63 { 4, 0x68, "Pkts1024to1522Octets" }, 64 { 4, 0x6c, "RxOversizePkts" }, 65 { 4, 0x70, "RxJabbers" }, 66 { 4, 0x74, "RxAlignmentErrors" }, 67 { 4, 0x78, "RxFCSErrors" }, 68 { 8, 0x7c, "RxGoodOctets" }, 69 { 4, 0x84, "RxDropPkts" }, 70 { 4, 0x88, "RxUnicastPkts" }, 71 { 4, 0x8c, "RxMulticastPkts" }, 72 { 4, 0x90, "RxBroadcastPkts" }, 73 { 4, 0x94, "RxSAChanges" }, 74 { 4, 0x98, "RxFragments" }, 75 }; 76 77 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 78 79 /* BCM63xx MIB counters */ 80 static const struct b53_mib_desc b53_mibs_63xx[] = { 81 { 8, 0x00, "TxOctets" }, 82 { 4, 0x08, "TxDropPkts" }, 83 { 4, 0x0c, "TxQoSPkts" }, 84 { 4, 0x10, "TxBroadcastPkts" }, 85 { 4, 0x14, "TxMulticastPkts" }, 86 { 4, 0x18, "TxUnicastPkts" }, 87 { 4, 0x1c, "TxCollisions" }, 88 { 4, 0x20, "TxSingleCollision" }, 89 { 4, 0x24, "TxMultipleCollision" }, 90 { 4, 0x28, "TxDeferredTransmit" }, 91 { 4, 0x2c, "TxLateCollision" }, 92 { 4, 0x30, "TxExcessiveCollision" }, 93 { 4, 0x38, "TxPausePkts" }, 94 { 8, 0x3c, "TxQoSOctets" }, 95 { 8, 0x44, "RxOctets" }, 96 { 4, 0x4c, "RxUndersizePkts" }, 97 { 4, 0x50, "RxPausePkts" }, 98 { 4, 0x54, "Pkts64Octets" }, 99 { 4, 0x58, "Pkts65to127Octets" }, 100 { 4, 0x5c, "Pkts128to255Octets" }, 101 { 4, 0x60, "Pkts256to511Octets" }, 102 { 4, 0x64, "Pkts512to1023Octets" }, 103 { 4, 0x68, "Pkts1024to1522Octets" }, 104 { 4, 0x6c, "RxOversizePkts" }, 105 { 4, 0x70, "RxJabbers" }, 106 { 4, 0x74, "RxAlignmentErrors" }, 107 { 4, 0x78, "RxFCSErrors" }, 108 { 8, 0x7c, "RxGoodOctets" }, 109 { 4, 0x84, "RxDropPkts" }, 110 { 4, 0x88, "RxUnicastPkts" }, 111 { 4, 0x8c, "RxMulticastPkts" }, 112 { 4, 0x90, "RxBroadcastPkts" }, 113 { 4, 0x94, "RxSAChanges" }, 114 { 4, 0x98, "RxFragments" }, 115 { 4, 0xa0, "RxSymbolErrors" }, 116 { 4, 0xa4, "RxQoSPkts" }, 117 { 8, 0xa8, "RxQoSOctets" }, 118 { 4, 0xb0, "Pkts1523to2047Octets" }, 119 { 4, 0xb4, "Pkts2048to4095Octets" }, 120 { 4, 0xb8, "Pkts4096to8191Octets" }, 121 { 4, 0xbc, "Pkts8192to9728Octets" }, 122 { 4, 0xc0, "RxDiscarded" }, 123 }; 124 125 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 126 127 /* MIB counters */ 128 static const struct b53_mib_desc b53_mibs[] = { 129 { 8, 0x00, "TxOctets" }, 130 { 4, 0x08, "TxDropPkts" }, 131 { 4, 0x10, "TxBroadcastPkts" }, 132 { 4, 0x14, "TxMulticastPkts" }, 133 { 4, 0x18, "TxUnicastPkts" }, 134 { 4, 0x1c, "TxCollisions" }, 135 { 4, 0x20, "TxSingleCollision" }, 136 { 4, 0x24, "TxMultipleCollision" }, 137 { 4, 0x28, "TxDeferredTransmit" }, 138 { 4, 0x2c, "TxLateCollision" }, 139 { 4, 0x30, "TxExcessiveCollision" }, 140 { 4, 0x38, "TxPausePkts" }, 141 { 8, 0x50, "RxOctets" }, 142 { 4, 0x58, "RxUndersizePkts" }, 143 { 4, 0x5c, "RxPausePkts" }, 144 { 4, 0x60, "Pkts64Octets" }, 145 { 4, 0x64, "Pkts65to127Octets" }, 146 { 4, 0x68, "Pkts128to255Octets" }, 147 { 4, 0x6c, "Pkts256to511Octets" }, 148 { 4, 0x70, "Pkts512to1023Octets" }, 149 { 4, 0x74, "Pkts1024to1522Octets" }, 150 { 4, 0x78, "RxOversizePkts" }, 151 { 4, 0x7c, "RxJabbers" }, 152 { 4, 0x80, "RxAlignmentErrors" }, 153 { 4, 0x84, "RxFCSErrors" }, 154 { 8, 0x88, "RxGoodOctets" }, 155 { 4, 0x90, "RxDropPkts" }, 156 { 4, 0x94, "RxUnicastPkts" }, 157 { 4, 0x98, "RxMulticastPkts" }, 158 { 4, 0x9c, "RxBroadcastPkts" }, 159 { 4, 0xa0, "RxSAChanges" }, 160 { 4, 0xa4, "RxFragments" }, 161 { 4, 0xa8, "RxJumboPkts" }, 162 { 4, 0xac, "RxSymbolErrors" }, 163 { 4, 0xc0, "RxDiscarded" }, 164 }; 165 166 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 167 168 static const struct b53_mib_desc b53_mibs_58xx[] = { 169 { 8, 0x00, "TxOctets" }, 170 { 4, 0x08, "TxDropPkts" }, 171 { 4, 0x0c, "TxQPKTQ0" }, 172 { 4, 0x10, "TxBroadcastPkts" }, 173 { 4, 0x14, "TxMulticastPkts" }, 174 { 4, 0x18, "TxUnicastPKts" }, 175 { 4, 0x1c, "TxCollisions" }, 176 { 4, 0x20, "TxSingleCollision" }, 177 { 4, 0x24, "TxMultipleCollision" }, 178 { 4, 0x28, "TxDeferredCollision" }, 179 { 4, 0x2c, "TxLateCollision" }, 180 { 4, 0x30, "TxExcessiveCollision" }, 181 { 4, 0x34, "TxFrameInDisc" }, 182 { 4, 0x38, "TxPausePkts" }, 183 { 4, 0x3c, "TxQPKTQ1" }, 184 { 4, 0x40, "TxQPKTQ2" }, 185 { 4, 0x44, "TxQPKTQ3" }, 186 { 4, 0x48, "TxQPKTQ4" }, 187 { 4, 0x4c, "TxQPKTQ5" }, 188 { 8, 0x50, "RxOctets" }, 189 { 4, 0x58, "RxUndersizePkts" }, 190 { 4, 0x5c, "RxPausePkts" }, 191 { 4, 0x60, "RxPkts64Octets" }, 192 { 4, 0x64, "RxPkts65to127Octets" }, 193 { 4, 0x68, "RxPkts128to255Octets" }, 194 { 4, 0x6c, "RxPkts256to511Octets" }, 195 { 4, 0x70, "RxPkts512to1023Octets" }, 196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 197 { 4, 0x78, "RxOversizePkts" }, 198 { 4, 0x7c, "RxJabbers" }, 199 { 4, 0x80, "RxAlignmentErrors" }, 200 { 4, 0x84, "RxFCSErrors" }, 201 { 8, 0x88, "RxGoodOctets" }, 202 { 4, 0x90, "RxDropPkts" }, 203 { 4, 0x94, "RxUnicastPkts" }, 204 { 4, 0x98, "RxMulticastPkts" }, 205 { 4, 0x9c, "RxBroadcastPkts" }, 206 { 4, 0xa0, "RxSAChanges" }, 207 { 4, 0xa4, "RxFragments" }, 208 { 4, 0xa8, "RxJumboPkt" }, 209 { 4, 0xac, "RxSymblErr" }, 210 { 4, 0xb0, "InRangeErrCount" }, 211 { 4, 0xb4, "OutRangeErrCount" }, 212 { 4, 0xb8, "EEELpiEvent" }, 213 { 4, 0xbc, "EEELpiDuration" }, 214 { 4, 0xc0, "RxDiscard" }, 215 { 4, 0xc8, "TxQPKTQ6" }, 216 { 4, 0xcc, "TxQPKTQ7" }, 217 { 4, 0xd0, "TxPkts64Octets" }, 218 { 4, 0xd4, "TxPkts65to127Octets" }, 219 { 4, 0xd8, "TxPkts128to255Octets" }, 220 { 4, 0xdc, "TxPkts256to511Ocets" }, 221 { 4, 0xe0, "TxPkts512to1023Ocets" }, 222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 223 }; 224 225 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 226 227 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 228 { 229 unsigned int i; 230 231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 232 233 for (i = 0; i < 10; i++) { 234 u8 vta; 235 236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 237 if (!(vta & VTA_START_CMD)) 238 return 0; 239 240 usleep_range(100, 200); 241 } 242 243 return -EIO; 244 } 245 246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 247 struct b53_vlan *vlan) 248 { 249 if (is5325(dev)) { 250 u32 entry = 0; 251 252 if (vlan->members) { 253 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 254 VA_UNTAG_S_25) | vlan->members; 255 if (dev->core_rev >= 3) 256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 257 else 258 entry |= VA_VALID_25; 259 } 260 261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 263 VTA_RW_STATE_WR | VTA_RW_OP_EN); 264 } else if (is5365(dev)) { 265 u16 entry = 0; 266 267 if (vlan->members) 268 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 270 271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 273 VTA_RW_STATE_WR | VTA_RW_OP_EN); 274 } else { 275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 277 (vlan->untag << VTE_UNTAG_S) | vlan->members); 278 279 b53_do_vlan_op(dev, VTA_CMD_WRITE); 280 } 281 282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 283 vid, vlan->members, vlan->untag); 284 } 285 286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 287 struct b53_vlan *vlan) 288 { 289 if (is5325(dev)) { 290 u32 entry = 0; 291 292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 293 VTA_RW_STATE_RD | VTA_RW_OP_EN); 294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 295 296 if (dev->core_rev >= 3) 297 vlan->valid = !!(entry & VA_VALID_25_R4); 298 else 299 vlan->valid = !!(entry & VA_VALID_25); 300 vlan->members = entry & VA_MEMBER_MASK; 301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 302 303 } else if (is5365(dev)) { 304 u16 entry = 0; 305 306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 307 VTA_RW_STATE_WR | VTA_RW_OP_EN); 308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 309 310 vlan->valid = !!(entry & VA_VALID_65); 311 vlan->members = entry & VA_MEMBER_MASK; 312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 313 } else { 314 u32 entry = 0; 315 316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 317 b53_do_vlan_op(dev, VTA_CMD_READ); 318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 319 vlan->members = entry & VTE_MEMBERS; 320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 321 vlan->valid = true; 322 } 323 } 324 325 static void b53_set_forwarding(struct b53_device *dev, int enable) 326 { 327 u8 mgmt; 328 329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 330 331 if (enable) 332 mgmt |= SM_SW_FWD_EN; 333 else 334 mgmt &= ~SM_SW_FWD_EN; 335 336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 337 338 /* Include IMP port in dumb forwarding mode 339 */ 340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 341 mgmt |= B53_MII_DUMB_FWDG_EN; 342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 343 344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 345 * frames should be flooded or not. 346 */ 347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 350 } 351 352 static void b53_enable_vlan(struct b53_device *dev, bool enable, 353 bool enable_filtering) 354 { 355 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 356 357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 360 361 if (is5325(dev) || is5365(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 364 } else if (is63xx(dev)) { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 367 } else { 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 370 } 371 372 if (enable) { 373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 375 vc4 &= ~VC4_ING_VID_CHECK_MASK; 376 if (enable_filtering) { 377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 378 vc5 |= VC5_DROP_VTABLE_MISS; 379 } else { 380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 381 vc5 &= ~VC5_DROP_VTABLE_MISS; 382 } 383 384 if (is5325(dev)) 385 vc0 &= ~VC0_RESERVED_1; 386 387 if (is5325(dev) || is5365(dev)) 388 vc1 |= VC1_RX_MCST_TAG_EN; 389 390 } else { 391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 393 vc4 &= ~VC4_ING_VID_CHECK_MASK; 394 vc5 &= ~VC5_DROP_VTABLE_MISS; 395 396 if (is5325(dev) || is5365(dev)) 397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 398 else 399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 400 401 if (is5325(dev) || is5365(dev)) 402 vc1 &= ~VC1_RX_MCST_TAG_EN; 403 } 404 405 if (!is5325(dev) && !is5365(dev)) 406 vc5 &= ~VC5_VID_FFF_EN; 407 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 410 411 if (is5325(dev) || is5365(dev)) { 412 /* enable the high 8 bit vid check on 5325 */ 413 if (is5325(dev) && enable) 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 415 VC3_HIGH_8BIT_EN); 416 else 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 418 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 421 } else if (is63xx(dev)) { 422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 425 } else { 426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 429 } 430 431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 432 433 dev->vlan_enabled = enable; 434 } 435 436 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 437 { 438 u32 port_mask = 0; 439 u16 max_size = JMS_MIN_SIZE; 440 441 if (is5325(dev) || is5365(dev)) 442 return -EINVAL; 443 444 if (enable) { 445 port_mask = dev->enabled_ports; 446 max_size = JMS_MAX_SIZE; 447 if (allow_10_100) 448 port_mask |= JPM_10_100_JUMBO_EN; 449 } 450 451 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 452 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 453 } 454 455 static int b53_flush_arl(struct b53_device *dev, u8 mask) 456 { 457 unsigned int i; 458 459 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 460 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 461 462 for (i = 0; i < 10; i++) { 463 u8 fast_age_ctrl; 464 465 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 466 &fast_age_ctrl); 467 468 if (!(fast_age_ctrl & FAST_AGE_DONE)) 469 goto out; 470 471 msleep(1); 472 } 473 474 return -ETIMEDOUT; 475 out: 476 /* Only age dynamic entries (default behavior) */ 477 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 478 return 0; 479 } 480 481 static int b53_fast_age_port(struct b53_device *dev, int port) 482 { 483 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 484 485 return b53_flush_arl(dev, FAST_AGE_PORT); 486 } 487 488 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 489 { 490 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 491 492 return b53_flush_arl(dev, FAST_AGE_VLAN); 493 } 494 495 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 496 { 497 struct b53_device *dev = ds->priv; 498 unsigned int i; 499 u16 pvlan; 500 501 /* Enable the IMP port to be in the same VLAN as the other ports 502 * on a per-port basis such that we only have Port i and IMP in 503 * the same VLAN. 504 */ 505 b53_for_each_port(dev, i) { 506 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 507 pvlan |= BIT(cpu_port); 508 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 509 } 510 } 511 EXPORT_SYMBOL(b53_imp_vlan_setup); 512 513 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 514 bool unicast) 515 { 516 u16 uc; 517 518 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 519 if (unicast) 520 uc |= BIT(port); 521 else 522 uc &= ~BIT(port); 523 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 524 } 525 526 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 527 bool multicast) 528 { 529 u16 mc; 530 531 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 532 if (multicast) 533 mc |= BIT(port); 534 else 535 mc &= ~BIT(port); 536 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 537 538 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 539 if (multicast) 540 mc |= BIT(port); 541 else 542 mc &= ~BIT(port); 543 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 544 } 545 546 static void b53_port_set_learning(struct b53_device *dev, int port, 547 bool learning) 548 { 549 u16 reg; 550 551 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 552 if (learning) 553 reg &= ~BIT(port); 554 else 555 reg |= BIT(port); 556 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 557 } 558 559 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 560 { 561 struct b53_device *dev = ds->priv; 562 unsigned int cpu_port; 563 int ret = 0; 564 u16 pvlan; 565 566 if (!dsa_is_user_port(ds, port)) 567 return 0; 568 569 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 570 571 b53_port_set_ucast_flood(dev, port, true); 572 b53_port_set_mcast_flood(dev, port, true); 573 b53_port_set_learning(dev, port, false); 574 575 if (dev->ops->irq_enable) 576 ret = dev->ops->irq_enable(dev, port); 577 if (ret) 578 return ret; 579 580 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 581 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 582 583 /* Set this port, and only this one to be in the default VLAN, 584 * if member of a bridge, restore its membership prior to 585 * bringing down this port. 586 */ 587 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 588 pvlan &= ~0x1ff; 589 pvlan |= BIT(port); 590 pvlan |= dev->ports[port].vlan_ctl_mask; 591 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 592 593 b53_imp_vlan_setup(ds, cpu_port); 594 595 /* If EEE was enabled, restore it */ 596 if (dev->ports[port].eee.eee_enabled) 597 b53_eee_enable_set(ds, port, true); 598 599 return 0; 600 } 601 EXPORT_SYMBOL(b53_enable_port); 602 603 void b53_disable_port(struct dsa_switch *ds, int port) 604 { 605 struct b53_device *dev = ds->priv; 606 u8 reg; 607 608 /* Disable Tx/Rx for the port */ 609 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 610 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 611 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 612 613 if (dev->ops->irq_disable) 614 dev->ops->irq_disable(dev, port); 615 } 616 EXPORT_SYMBOL(b53_disable_port); 617 618 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 619 { 620 struct b53_device *dev = ds->priv; 621 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 622 u8 hdr_ctl, val; 623 u16 reg; 624 625 /* Resolve which bit controls the Broadcom tag */ 626 switch (port) { 627 case 8: 628 val = BRCM_HDR_P8_EN; 629 break; 630 case 7: 631 val = BRCM_HDR_P7_EN; 632 break; 633 case 5: 634 val = BRCM_HDR_P5_EN; 635 break; 636 default: 637 val = 0; 638 break; 639 } 640 641 /* Enable management mode if tagging is requested */ 642 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 643 if (tag_en) 644 hdr_ctl |= SM_SW_FWD_MODE; 645 else 646 hdr_ctl &= ~SM_SW_FWD_MODE; 647 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 648 649 /* Configure the appropriate IMP port */ 650 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 651 if (port == 8) 652 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 653 else if (port == 5) 654 hdr_ctl |= GC_FRM_MGMT_PORT_M; 655 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 656 657 /* Enable Broadcom tags for IMP port */ 658 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 659 if (tag_en) 660 hdr_ctl |= val; 661 else 662 hdr_ctl &= ~val; 663 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 664 665 /* Registers below are only accessible on newer devices */ 666 if (!is58xx(dev)) 667 return; 668 669 /* Enable reception Broadcom tag for CPU TX (switch RX) to 670 * allow us to tag outgoing frames 671 */ 672 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 673 if (tag_en) 674 reg &= ~BIT(port); 675 else 676 reg |= BIT(port); 677 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 678 679 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 680 * allow delivering frames to the per-port net_devices 681 */ 682 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 683 if (tag_en) 684 reg &= ~BIT(port); 685 else 686 reg |= BIT(port); 687 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 688 } 689 EXPORT_SYMBOL(b53_brcm_hdr_setup); 690 691 static void b53_enable_cpu_port(struct b53_device *dev, int port) 692 { 693 u8 port_ctrl; 694 695 /* BCM5325 CPU port is at 8 */ 696 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 697 port = B53_CPU_PORT; 698 699 port_ctrl = PORT_CTRL_RX_BCST_EN | 700 PORT_CTRL_RX_MCST_EN | 701 PORT_CTRL_RX_UCST_EN; 702 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 703 704 b53_brcm_hdr_setup(dev->ds, port); 705 706 b53_port_set_ucast_flood(dev, port, true); 707 b53_port_set_mcast_flood(dev, port, true); 708 b53_port_set_learning(dev, port, false); 709 } 710 711 static void b53_enable_mib(struct b53_device *dev) 712 { 713 u8 gc; 714 715 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 716 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 717 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 718 } 719 720 static u16 b53_default_pvid(struct b53_device *dev) 721 { 722 if (is5325(dev) || is5365(dev)) 723 return 1; 724 else 725 return 0; 726 } 727 728 int b53_configure_vlan(struct dsa_switch *ds) 729 { 730 struct b53_device *dev = ds->priv; 731 struct b53_vlan vl = { 0 }; 732 struct b53_vlan *v; 733 int i, def_vid; 734 u16 vid; 735 736 def_vid = b53_default_pvid(dev); 737 738 /* clear all vlan entries */ 739 if (is5325(dev) || is5365(dev)) { 740 for (i = def_vid; i < dev->num_vlans; i++) 741 b53_set_vlan_entry(dev, i, &vl); 742 } else { 743 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 744 } 745 746 b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering); 747 748 b53_for_each_port(dev, i) 749 b53_write16(dev, B53_VLAN_PAGE, 750 B53_VLAN_PORT_DEF_TAG(i), def_vid); 751 752 /* Upon initial call we have not set-up any VLANs, but upon 753 * system resume, we need to restore all VLAN entries. 754 */ 755 for (vid = def_vid; vid < dev->num_vlans; vid++) { 756 v = &dev->vlans[vid]; 757 758 if (!v->members) 759 continue; 760 761 b53_set_vlan_entry(dev, vid, v); 762 b53_fast_age_vlan(dev, vid); 763 } 764 765 return 0; 766 } 767 EXPORT_SYMBOL(b53_configure_vlan); 768 769 static void b53_switch_reset_gpio(struct b53_device *dev) 770 { 771 int gpio = dev->reset_gpio; 772 773 if (gpio < 0) 774 return; 775 776 /* Reset sequence: RESET low(50ms)->high(20ms) 777 */ 778 gpio_set_value(gpio, 0); 779 mdelay(50); 780 781 gpio_set_value(gpio, 1); 782 mdelay(20); 783 784 dev->current_page = 0xff; 785 } 786 787 static int b53_switch_reset(struct b53_device *dev) 788 { 789 unsigned int timeout = 1000; 790 u8 mgmt, reg; 791 792 b53_switch_reset_gpio(dev); 793 794 if (is539x(dev)) { 795 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 796 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 797 } 798 799 /* This is specific to 58xx devices here, do not use is58xx() which 800 * covers the larger Starfigther 2 family, including 7445/7278 which 801 * still use this driver as a library and need to perform the reset 802 * earlier. 803 */ 804 if (dev->chip_id == BCM58XX_DEVICE_ID || 805 dev->chip_id == BCM583XX_DEVICE_ID) { 806 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 807 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 808 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 809 810 do { 811 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 812 if (!(reg & SW_RST)) 813 break; 814 815 usleep_range(1000, 2000); 816 } while (timeout-- > 0); 817 818 if (timeout == 0) { 819 dev_err(dev->dev, 820 "Timeout waiting for SW_RST to clear!\n"); 821 return -ETIMEDOUT; 822 } 823 } 824 825 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 826 827 if (!(mgmt & SM_SW_FWD_EN)) { 828 mgmt &= ~SM_SW_FWD_MODE; 829 mgmt |= SM_SW_FWD_EN; 830 831 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 832 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 833 834 if (!(mgmt & SM_SW_FWD_EN)) { 835 dev_err(dev->dev, "Failed to enable switch!\n"); 836 return -EINVAL; 837 } 838 } 839 840 b53_enable_mib(dev); 841 842 return b53_flush_arl(dev, FAST_AGE_STATIC); 843 } 844 845 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 846 { 847 struct b53_device *priv = ds->priv; 848 u16 value = 0; 849 int ret; 850 851 if (priv->ops->phy_read16) 852 ret = priv->ops->phy_read16(priv, addr, reg, &value); 853 else 854 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 855 reg * 2, &value); 856 857 return ret ? ret : value; 858 } 859 860 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 861 { 862 struct b53_device *priv = ds->priv; 863 864 if (priv->ops->phy_write16) 865 return priv->ops->phy_write16(priv, addr, reg, val); 866 867 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 868 } 869 870 static int b53_reset_switch(struct b53_device *priv) 871 { 872 /* reset vlans */ 873 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 874 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 875 876 priv->serdes_lane = B53_INVALID_LANE; 877 878 return b53_switch_reset(priv); 879 } 880 881 static int b53_apply_config(struct b53_device *priv) 882 { 883 /* disable switching */ 884 b53_set_forwarding(priv, 0); 885 886 b53_configure_vlan(priv->ds); 887 888 /* enable switching */ 889 b53_set_forwarding(priv, 1); 890 891 return 0; 892 } 893 894 static void b53_reset_mib(struct b53_device *priv) 895 { 896 u8 gc; 897 898 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 899 900 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 901 msleep(1); 902 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 903 msleep(1); 904 } 905 906 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 907 { 908 if (is5365(dev)) 909 return b53_mibs_65; 910 else if (is63xx(dev)) 911 return b53_mibs_63xx; 912 else if (is58xx(dev)) 913 return b53_mibs_58xx; 914 else 915 return b53_mibs; 916 } 917 918 static unsigned int b53_get_mib_size(struct b53_device *dev) 919 { 920 if (is5365(dev)) 921 return B53_MIBS_65_SIZE; 922 else if (is63xx(dev)) 923 return B53_MIBS_63XX_SIZE; 924 else if (is58xx(dev)) 925 return B53_MIBS_58XX_SIZE; 926 else 927 return B53_MIBS_SIZE; 928 } 929 930 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 931 { 932 /* These ports typically do not have built-in PHYs */ 933 switch (port) { 934 case B53_CPU_PORT_25: 935 case 7: 936 case B53_CPU_PORT: 937 return NULL; 938 } 939 940 return mdiobus_get_phy(ds->slave_mii_bus, port); 941 } 942 943 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 944 uint8_t *data) 945 { 946 struct b53_device *dev = ds->priv; 947 const struct b53_mib_desc *mibs = b53_get_mib(dev); 948 unsigned int mib_size = b53_get_mib_size(dev); 949 struct phy_device *phydev; 950 unsigned int i; 951 952 if (stringset == ETH_SS_STATS) { 953 for (i = 0; i < mib_size; i++) 954 strlcpy(data + i * ETH_GSTRING_LEN, 955 mibs[i].name, ETH_GSTRING_LEN); 956 } else if (stringset == ETH_SS_PHY_STATS) { 957 phydev = b53_get_phy_device(ds, port); 958 if (!phydev) 959 return; 960 961 phy_ethtool_get_strings(phydev, data); 962 } 963 } 964 EXPORT_SYMBOL(b53_get_strings); 965 966 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 967 { 968 struct b53_device *dev = ds->priv; 969 const struct b53_mib_desc *mibs = b53_get_mib(dev); 970 unsigned int mib_size = b53_get_mib_size(dev); 971 const struct b53_mib_desc *s; 972 unsigned int i; 973 u64 val = 0; 974 975 if (is5365(dev) && port == 5) 976 port = 8; 977 978 mutex_lock(&dev->stats_mutex); 979 980 for (i = 0; i < mib_size; i++) { 981 s = &mibs[i]; 982 983 if (s->size == 8) { 984 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 985 } else { 986 u32 val32; 987 988 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 989 &val32); 990 val = val32; 991 } 992 data[i] = (u64)val; 993 } 994 995 mutex_unlock(&dev->stats_mutex); 996 } 997 EXPORT_SYMBOL(b53_get_ethtool_stats); 998 999 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1000 { 1001 struct phy_device *phydev; 1002 1003 phydev = b53_get_phy_device(ds, port); 1004 if (!phydev) 1005 return; 1006 1007 phy_ethtool_get_stats(phydev, NULL, data); 1008 } 1009 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1010 1011 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1012 { 1013 struct b53_device *dev = ds->priv; 1014 struct phy_device *phydev; 1015 1016 if (sset == ETH_SS_STATS) { 1017 return b53_get_mib_size(dev); 1018 } else if (sset == ETH_SS_PHY_STATS) { 1019 phydev = b53_get_phy_device(ds, port); 1020 if (!phydev) 1021 return 0; 1022 1023 return phy_ethtool_get_sset_count(phydev); 1024 } 1025 1026 return 0; 1027 } 1028 EXPORT_SYMBOL(b53_get_sset_count); 1029 1030 enum b53_devlink_resource_id { 1031 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1032 }; 1033 1034 static u64 b53_devlink_vlan_table_get(void *priv) 1035 { 1036 struct b53_device *dev = priv; 1037 struct b53_vlan *vl; 1038 unsigned int i; 1039 u64 count = 0; 1040 1041 for (i = 0; i < dev->num_vlans; i++) { 1042 vl = &dev->vlans[i]; 1043 if (vl->members) 1044 count++; 1045 } 1046 1047 return count; 1048 } 1049 1050 int b53_setup_devlink_resources(struct dsa_switch *ds) 1051 { 1052 struct devlink_resource_size_params size_params; 1053 struct b53_device *dev = ds->priv; 1054 int err; 1055 1056 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1057 dev->num_vlans, 1058 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1059 1060 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1061 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1062 DEVLINK_RESOURCE_ID_PARENT_TOP, 1063 &size_params); 1064 if (err) 1065 goto out; 1066 1067 dsa_devlink_resource_occ_get_register(ds, 1068 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1069 b53_devlink_vlan_table_get, dev); 1070 1071 return 0; 1072 out: 1073 dsa_devlink_resources_unregister(ds); 1074 return err; 1075 } 1076 EXPORT_SYMBOL(b53_setup_devlink_resources); 1077 1078 static int b53_setup(struct dsa_switch *ds) 1079 { 1080 struct b53_device *dev = ds->priv; 1081 unsigned int port; 1082 int ret; 1083 1084 ret = b53_reset_switch(dev); 1085 if (ret) { 1086 dev_err(ds->dev, "failed to reset switch\n"); 1087 return ret; 1088 } 1089 1090 b53_reset_mib(dev); 1091 1092 ret = b53_apply_config(dev); 1093 if (ret) { 1094 dev_err(ds->dev, "failed to apply configuration\n"); 1095 return ret; 1096 } 1097 1098 /* Configure IMP/CPU port, disable all other ports. Enabled 1099 * ports will be configured with .port_enable 1100 */ 1101 for (port = 0; port < dev->num_ports; port++) { 1102 if (dsa_is_cpu_port(ds, port)) 1103 b53_enable_cpu_port(dev, port); 1104 else 1105 b53_disable_port(ds, port); 1106 } 1107 1108 return b53_setup_devlink_resources(ds); 1109 } 1110 1111 static void b53_teardown(struct dsa_switch *ds) 1112 { 1113 dsa_devlink_resources_unregister(ds); 1114 } 1115 1116 static void b53_force_link(struct b53_device *dev, int port, int link) 1117 { 1118 u8 reg, val, off; 1119 1120 /* Override the port settings */ 1121 if (port == dev->cpu_port) { 1122 off = B53_PORT_OVERRIDE_CTRL; 1123 val = PORT_OVERRIDE_EN; 1124 } else { 1125 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1126 val = GMII_PO_EN; 1127 } 1128 1129 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1130 reg |= val; 1131 if (link) 1132 reg |= PORT_OVERRIDE_LINK; 1133 else 1134 reg &= ~PORT_OVERRIDE_LINK; 1135 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1136 } 1137 1138 static void b53_force_port_config(struct b53_device *dev, int port, 1139 int speed, int duplex, 1140 bool tx_pause, bool rx_pause) 1141 { 1142 u8 reg, val, off; 1143 1144 /* Override the port settings */ 1145 if (port == dev->cpu_port) { 1146 off = B53_PORT_OVERRIDE_CTRL; 1147 val = PORT_OVERRIDE_EN; 1148 } else { 1149 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1150 val = GMII_PO_EN; 1151 } 1152 1153 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1154 reg |= val; 1155 if (duplex == DUPLEX_FULL) 1156 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1157 else 1158 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1159 1160 switch (speed) { 1161 case 2000: 1162 reg |= PORT_OVERRIDE_SPEED_2000M; 1163 fallthrough; 1164 case SPEED_1000: 1165 reg |= PORT_OVERRIDE_SPEED_1000M; 1166 break; 1167 case SPEED_100: 1168 reg |= PORT_OVERRIDE_SPEED_100M; 1169 break; 1170 case SPEED_10: 1171 reg |= PORT_OVERRIDE_SPEED_10M; 1172 break; 1173 default: 1174 dev_err(dev->dev, "unknown speed: %d\n", speed); 1175 return; 1176 } 1177 1178 if (rx_pause) 1179 reg |= PORT_OVERRIDE_RX_FLOW; 1180 if (tx_pause) 1181 reg |= PORT_OVERRIDE_TX_FLOW; 1182 1183 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1184 } 1185 1186 static void b53_adjust_link(struct dsa_switch *ds, int port, 1187 struct phy_device *phydev) 1188 { 1189 struct b53_device *dev = ds->priv; 1190 struct ethtool_eee *p = &dev->ports[port].eee; 1191 u8 rgmii_ctrl = 0, reg = 0, off; 1192 bool tx_pause = false; 1193 bool rx_pause = false; 1194 1195 if (!phy_is_pseudo_fixed_link(phydev)) 1196 return; 1197 1198 /* Enable flow control on BCM5301x's CPU port */ 1199 if (is5301x(dev) && port == dev->cpu_port) 1200 tx_pause = rx_pause = true; 1201 1202 if (phydev->pause) { 1203 if (phydev->asym_pause) 1204 tx_pause = true; 1205 rx_pause = true; 1206 } 1207 1208 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, 1209 tx_pause, rx_pause); 1210 b53_force_link(dev, port, phydev->link); 1211 1212 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1213 if (port == 8) 1214 off = B53_RGMII_CTRL_IMP; 1215 else 1216 off = B53_RGMII_CTRL_P(port); 1217 1218 /* Configure the port RGMII clock delay by DLL disabled and 1219 * tx_clk aligned timing (restoring to reset defaults) 1220 */ 1221 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1222 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1223 RGMII_CTRL_TIMING_SEL); 1224 1225 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1226 * sure that we enable the port TX clock internal delay to 1227 * account for this internal delay that is inserted, otherwise 1228 * the switch won't be able to receive correctly. 1229 * 1230 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1231 * any delay neither on transmission nor reception, so the 1232 * BCM53125 must also be configured accordingly to account for 1233 * the lack of delay and introduce 1234 * 1235 * The BCM53125 switch has its RX clock and TX clock control 1236 * swapped, hence the reason why we modify the TX clock path in 1237 * the "RGMII" case 1238 */ 1239 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1240 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1241 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1242 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1243 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1244 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1245 1246 dev_info(ds->dev, "Configured port %d for %s\n", port, 1247 phy_modes(phydev->interface)); 1248 } 1249 1250 /* configure MII port if necessary */ 1251 if (is5325(dev)) { 1252 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1253 ®); 1254 1255 /* reverse mii needs to be enabled */ 1256 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1257 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1258 reg | PORT_OVERRIDE_RV_MII_25); 1259 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1260 ®); 1261 1262 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1263 dev_err(ds->dev, 1264 "Failed to enable reverse MII mode\n"); 1265 return; 1266 } 1267 } 1268 } else if (is5301x(dev)) { 1269 if (port != dev->cpu_port) { 1270 b53_force_port_config(dev, dev->cpu_port, 2000, 1271 DUPLEX_FULL, true, true); 1272 b53_force_link(dev, dev->cpu_port, 1); 1273 } 1274 } 1275 1276 /* Re-negotiate EEE if it was enabled already */ 1277 p->eee_enabled = b53_eee_init(ds, port, phydev); 1278 } 1279 1280 void b53_port_event(struct dsa_switch *ds, int port) 1281 { 1282 struct b53_device *dev = ds->priv; 1283 bool link; 1284 u16 sts; 1285 1286 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1287 link = !!(sts & BIT(port)); 1288 dsa_port_phylink_mac_change(ds, port, link); 1289 } 1290 EXPORT_SYMBOL(b53_port_event); 1291 1292 void b53_phylink_validate(struct dsa_switch *ds, int port, 1293 unsigned long *supported, 1294 struct phylink_link_state *state) 1295 { 1296 struct b53_device *dev = ds->priv; 1297 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1298 1299 if (dev->ops->serdes_phylink_validate) 1300 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1301 1302 /* Allow all the expected bits */ 1303 phylink_set(mask, Autoneg); 1304 phylink_set_port_modes(mask); 1305 phylink_set(mask, Pause); 1306 phylink_set(mask, Asym_Pause); 1307 1308 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1309 * support Gigabit, including Half duplex. 1310 */ 1311 if (state->interface != PHY_INTERFACE_MODE_MII && 1312 state->interface != PHY_INTERFACE_MODE_REVMII && 1313 !phy_interface_mode_is_8023z(state->interface) && 1314 !(is5325(dev) || is5365(dev))) { 1315 phylink_set(mask, 1000baseT_Full); 1316 phylink_set(mask, 1000baseT_Half); 1317 } 1318 1319 if (!phy_interface_mode_is_8023z(state->interface)) { 1320 phylink_set(mask, 10baseT_Half); 1321 phylink_set(mask, 10baseT_Full); 1322 phylink_set(mask, 100baseT_Half); 1323 phylink_set(mask, 100baseT_Full); 1324 } 1325 1326 bitmap_and(supported, supported, mask, 1327 __ETHTOOL_LINK_MODE_MASK_NBITS); 1328 bitmap_and(state->advertising, state->advertising, mask, 1329 __ETHTOOL_LINK_MODE_MASK_NBITS); 1330 1331 phylink_helper_basex_speed(state); 1332 } 1333 EXPORT_SYMBOL(b53_phylink_validate); 1334 1335 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1336 struct phylink_link_state *state) 1337 { 1338 struct b53_device *dev = ds->priv; 1339 int ret = -EOPNOTSUPP; 1340 1341 if ((phy_interface_mode_is_8023z(state->interface) || 1342 state->interface == PHY_INTERFACE_MODE_SGMII) && 1343 dev->ops->serdes_link_state) 1344 ret = dev->ops->serdes_link_state(dev, port, state); 1345 1346 return ret; 1347 } 1348 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1349 1350 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1351 unsigned int mode, 1352 const struct phylink_link_state *state) 1353 { 1354 struct b53_device *dev = ds->priv; 1355 1356 if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED) 1357 return; 1358 1359 if ((phy_interface_mode_is_8023z(state->interface) || 1360 state->interface == PHY_INTERFACE_MODE_SGMII) && 1361 dev->ops->serdes_config) 1362 dev->ops->serdes_config(dev, port, mode, state); 1363 } 1364 EXPORT_SYMBOL(b53_phylink_mac_config); 1365 1366 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1367 { 1368 struct b53_device *dev = ds->priv; 1369 1370 if (dev->ops->serdes_an_restart) 1371 dev->ops->serdes_an_restart(dev, port); 1372 } 1373 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1374 1375 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1376 unsigned int mode, 1377 phy_interface_t interface) 1378 { 1379 struct b53_device *dev = ds->priv; 1380 1381 if (mode == MLO_AN_PHY) 1382 return; 1383 1384 if (mode == MLO_AN_FIXED) { 1385 b53_force_link(dev, port, false); 1386 return; 1387 } 1388 1389 if (phy_interface_mode_is_8023z(interface) && 1390 dev->ops->serdes_link_set) 1391 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1392 } 1393 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1394 1395 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1396 unsigned int mode, 1397 phy_interface_t interface, 1398 struct phy_device *phydev, 1399 int speed, int duplex, 1400 bool tx_pause, bool rx_pause) 1401 { 1402 struct b53_device *dev = ds->priv; 1403 1404 if (mode == MLO_AN_PHY) 1405 return; 1406 1407 if (mode == MLO_AN_FIXED) { 1408 b53_force_port_config(dev, port, speed, duplex, 1409 tx_pause, rx_pause); 1410 b53_force_link(dev, port, true); 1411 return; 1412 } 1413 1414 if (phy_interface_mode_is_8023z(interface) && 1415 dev->ops->serdes_link_set) 1416 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1417 } 1418 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1419 1420 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1421 struct netlink_ext_ack *extack) 1422 { 1423 struct b53_device *dev = ds->priv; 1424 1425 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering); 1426 1427 return 0; 1428 } 1429 EXPORT_SYMBOL(b53_vlan_filtering); 1430 1431 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1432 const struct switchdev_obj_port_vlan *vlan) 1433 { 1434 struct b53_device *dev = ds->priv; 1435 1436 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1437 return -EOPNOTSUPP; 1438 1439 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1440 * receiving VLAN tagged frames at all, we can still allow the port to 1441 * be configured for egress untagged. 1442 */ 1443 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1444 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1445 return -EINVAL; 1446 1447 if (vlan->vid >= dev->num_vlans) 1448 return -ERANGE; 1449 1450 b53_enable_vlan(dev, true, ds->vlan_filtering); 1451 1452 return 0; 1453 } 1454 1455 int b53_vlan_add(struct dsa_switch *ds, int port, 1456 const struct switchdev_obj_port_vlan *vlan, 1457 struct netlink_ext_ack *extack) 1458 { 1459 struct b53_device *dev = ds->priv; 1460 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1461 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1462 struct b53_vlan *vl; 1463 int err; 1464 1465 err = b53_vlan_prepare(ds, port, vlan); 1466 if (err) 1467 return err; 1468 1469 vl = &dev->vlans[vlan->vid]; 1470 1471 b53_get_vlan_entry(dev, vlan->vid, vl); 1472 1473 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1474 untagged = true; 1475 1476 vl->members |= BIT(port); 1477 if (untagged && !dsa_is_cpu_port(ds, port)) 1478 vl->untag |= BIT(port); 1479 else 1480 vl->untag &= ~BIT(port); 1481 1482 b53_set_vlan_entry(dev, vlan->vid, vl); 1483 b53_fast_age_vlan(dev, vlan->vid); 1484 1485 if (pvid && !dsa_is_cpu_port(ds, port)) { 1486 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1487 vlan->vid); 1488 b53_fast_age_vlan(dev, vlan->vid); 1489 } 1490 1491 return 0; 1492 } 1493 EXPORT_SYMBOL(b53_vlan_add); 1494 1495 int b53_vlan_del(struct dsa_switch *ds, int port, 1496 const struct switchdev_obj_port_vlan *vlan) 1497 { 1498 struct b53_device *dev = ds->priv; 1499 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1500 struct b53_vlan *vl; 1501 u16 pvid; 1502 1503 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1504 1505 vl = &dev->vlans[vlan->vid]; 1506 1507 b53_get_vlan_entry(dev, vlan->vid, vl); 1508 1509 vl->members &= ~BIT(port); 1510 1511 if (pvid == vlan->vid) 1512 pvid = b53_default_pvid(dev); 1513 1514 if (untagged && !dsa_is_cpu_port(ds, port)) 1515 vl->untag &= ~(BIT(port)); 1516 1517 b53_set_vlan_entry(dev, vlan->vid, vl); 1518 b53_fast_age_vlan(dev, vlan->vid); 1519 1520 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1521 b53_fast_age_vlan(dev, pvid); 1522 1523 return 0; 1524 } 1525 EXPORT_SYMBOL(b53_vlan_del); 1526 1527 /* Address Resolution Logic routines */ 1528 static int b53_arl_op_wait(struct b53_device *dev) 1529 { 1530 unsigned int timeout = 10; 1531 u8 reg; 1532 1533 do { 1534 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1535 if (!(reg & ARLTBL_START_DONE)) 1536 return 0; 1537 1538 usleep_range(1000, 2000); 1539 } while (timeout--); 1540 1541 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1542 1543 return -ETIMEDOUT; 1544 } 1545 1546 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1547 { 1548 u8 reg; 1549 1550 if (op > ARLTBL_RW) 1551 return -EINVAL; 1552 1553 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1554 reg |= ARLTBL_START_DONE; 1555 if (op) 1556 reg |= ARLTBL_RW; 1557 else 1558 reg &= ~ARLTBL_RW; 1559 if (dev->vlan_enabled) 1560 reg &= ~ARLTBL_IVL_SVL_SELECT; 1561 else 1562 reg |= ARLTBL_IVL_SVL_SELECT; 1563 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1564 1565 return b53_arl_op_wait(dev); 1566 } 1567 1568 static int b53_arl_read(struct b53_device *dev, u64 mac, 1569 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1570 { 1571 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1572 unsigned int i; 1573 int ret; 1574 1575 ret = b53_arl_op_wait(dev); 1576 if (ret) 1577 return ret; 1578 1579 bitmap_zero(free_bins, dev->num_arl_bins); 1580 1581 /* Read the bins */ 1582 for (i = 0; i < dev->num_arl_bins; i++) { 1583 u64 mac_vid; 1584 u32 fwd_entry; 1585 1586 b53_read64(dev, B53_ARLIO_PAGE, 1587 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1588 b53_read32(dev, B53_ARLIO_PAGE, 1589 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1590 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1591 1592 if (!(fwd_entry & ARLTBL_VALID)) { 1593 set_bit(i, free_bins); 1594 continue; 1595 } 1596 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1597 continue; 1598 if (dev->vlan_enabled && 1599 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1600 continue; 1601 *idx = i; 1602 return 0; 1603 } 1604 1605 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0) 1606 return -ENOSPC; 1607 1608 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1609 1610 return -ENOENT; 1611 } 1612 1613 static int b53_arl_op(struct b53_device *dev, int op, int port, 1614 const unsigned char *addr, u16 vid, bool is_valid) 1615 { 1616 struct b53_arl_entry ent; 1617 u32 fwd_entry; 1618 u64 mac, mac_vid = 0; 1619 u8 idx = 0; 1620 int ret; 1621 1622 /* Convert the array into a 64-bit MAC */ 1623 mac = ether_addr_to_u64(addr); 1624 1625 /* Perform a read for the given MAC and VID */ 1626 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1627 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1628 1629 /* Issue a read operation for this MAC */ 1630 ret = b53_arl_rw_op(dev, 1); 1631 if (ret) 1632 return ret; 1633 1634 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1635 1636 /* If this is a read, just finish now */ 1637 if (op) 1638 return ret; 1639 1640 switch (ret) { 1641 case -ETIMEDOUT: 1642 return ret; 1643 case -ENOSPC: 1644 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1645 addr, vid); 1646 return is_valid ? ret : 0; 1647 case -ENOENT: 1648 /* We could not find a matching MAC, so reset to a new entry */ 1649 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1650 addr, vid, idx); 1651 fwd_entry = 0; 1652 break; 1653 default: 1654 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1655 addr, vid, idx); 1656 break; 1657 } 1658 1659 /* For multicast address, the port is a bitmask and the validity 1660 * is determined by having at least one port being still active 1661 */ 1662 if (!is_multicast_ether_addr(addr)) { 1663 ent.port = port; 1664 ent.is_valid = is_valid; 1665 } else { 1666 if (is_valid) 1667 ent.port |= BIT(port); 1668 else 1669 ent.port &= ~BIT(port); 1670 1671 ent.is_valid = !!(ent.port); 1672 } 1673 1674 ent.vid = vid; 1675 ent.is_static = true; 1676 ent.is_age = false; 1677 memcpy(ent.mac, addr, ETH_ALEN); 1678 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1679 1680 b53_write64(dev, B53_ARLIO_PAGE, 1681 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1682 b53_write32(dev, B53_ARLIO_PAGE, 1683 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1684 1685 return b53_arl_rw_op(dev, 0); 1686 } 1687 1688 int b53_fdb_add(struct dsa_switch *ds, int port, 1689 const unsigned char *addr, u16 vid) 1690 { 1691 struct b53_device *priv = ds->priv; 1692 1693 /* 5325 and 5365 require some more massaging, but could 1694 * be supported eventually 1695 */ 1696 if (is5325(priv) || is5365(priv)) 1697 return -EOPNOTSUPP; 1698 1699 return b53_arl_op(priv, 0, port, addr, vid, true); 1700 } 1701 EXPORT_SYMBOL(b53_fdb_add); 1702 1703 int b53_fdb_del(struct dsa_switch *ds, int port, 1704 const unsigned char *addr, u16 vid) 1705 { 1706 struct b53_device *priv = ds->priv; 1707 1708 return b53_arl_op(priv, 0, port, addr, vid, false); 1709 } 1710 EXPORT_SYMBOL(b53_fdb_del); 1711 1712 static int b53_arl_search_wait(struct b53_device *dev) 1713 { 1714 unsigned int timeout = 1000; 1715 u8 reg; 1716 1717 do { 1718 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1719 if (!(reg & ARL_SRCH_STDN)) 1720 return 0; 1721 1722 if (reg & ARL_SRCH_VLID) 1723 return 0; 1724 1725 usleep_range(1000, 2000); 1726 } while (timeout--); 1727 1728 return -ETIMEDOUT; 1729 } 1730 1731 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1732 struct b53_arl_entry *ent) 1733 { 1734 u64 mac_vid; 1735 u32 fwd_entry; 1736 1737 b53_read64(dev, B53_ARLIO_PAGE, 1738 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1739 b53_read32(dev, B53_ARLIO_PAGE, 1740 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1741 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1742 } 1743 1744 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1745 dsa_fdb_dump_cb_t *cb, void *data) 1746 { 1747 if (!ent->is_valid) 1748 return 0; 1749 1750 if (port != ent->port) 1751 return 0; 1752 1753 return cb(ent->mac, ent->vid, ent->is_static, data); 1754 } 1755 1756 int b53_fdb_dump(struct dsa_switch *ds, int port, 1757 dsa_fdb_dump_cb_t *cb, void *data) 1758 { 1759 struct b53_device *priv = ds->priv; 1760 struct b53_arl_entry results[2]; 1761 unsigned int count = 0; 1762 int ret; 1763 u8 reg; 1764 1765 /* Start search operation */ 1766 reg = ARL_SRCH_STDN; 1767 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1768 1769 do { 1770 ret = b53_arl_search_wait(priv); 1771 if (ret) 1772 return ret; 1773 1774 b53_arl_search_rd(priv, 0, &results[0]); 1775 ret = b53_fdb_copy(port, &results[0], cb, data); 1776 if (ret) 1777 return ret; 1778 1779 if (priv->num_arl_bins > 2) { 1780 b53_arl_search_rd(priv, 1, &results[1]); 1781 ret = b53_fdb_copy(port, &results[1], cb, data); 1782 if (ret) 1783 return ret; 1784 1785 if (!results[0].is_valid && !results[1].is_valid) 1786 break; 1787 } 1788 1789 } while (count++ < b53_max_arl_entries(priv) / 2); 1790 1791 return 0; 1792 } 1793 EXPORT_SYMBOL(b53_fdb_dump); 1794 1795 int b53_mdb_add(struct dsa_switch *ds, int port, 1796 const struct switchdev_obj_port_mdb *mdb) 1797 { 1798 struct b53_device *priv = ds->priv; 1799 1800 /* 5325 and 5365 require some more massaging, but could 1801 * be supported eventually 1802 */ 1803 if (is5325(priv) || is5365(priv)) 1804 return -EOPNOTSUPP; 1805 1806 return b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1807 } 1808 EXPORT_SYMBOL(b53_mdb_add); 1809 1810 int b53_mdb_del(struct dsa_switch *ds, int port, 1811 const struct switchdev_obj_port_mdb *mdb) 1812 { 1813 struct b53_device *priv = ds->priv; 1814 int ret; 1815 1816 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1817 if (ret) 1818 dev_err(ds->dev, "failed to delete MDB entry\n"); 1819 1820 return ret; 1821 } 1822 EXPORT_SYMBOL(b53_mdb_del); 1823 1824 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1825 { 1826 struct b53_device *dev = ds->priv; 1827 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1828 u16 pvlan, reg; 1829 unsigned int i; 1830 1831 /* On 7278, port 7 which connects to the ASP should only receive 1832 * traffic from matching CFP rules. 1833 */ 1834 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1835 return -EINVAL; 1836 1837 /* Make this port leave the all VLANs join since we will have proper 1838 * VLAN entries from now on 1839 */ 1840 if (is58xx(dev)) { 1841 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1842 reg &= ~BIT(port); 1843 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1844 reg &= ~BIT(cpu_port); 1845 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1846 } 1847 1848 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1849 1850 b53_for_each_port(dev, i) { 1851 if (dsa_to_port(ds, i)->bridge_dev != br) 1852 continue; 1853 1854 /* Add this local port to the remote port VLAN control 1855 * membership and update the remote port bitmask 1856 */ 1857 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1858 reg |= BIT(port); 1859 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1860 dev->ports[i].vlan_ctl_mask = reg; 1861 1862 pvlan |= BIT(i); 1863 } 1864 1865 /* Configure the local port VLAN control membership to include 1866 * remote ports and update the local port bitmask 1867 */ 1868 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1869 dev->ports[port].vlan_ctl_mask = pvlan; 1870 1871 return 0; 1872 } 1873 EXPORT_SYMBOL(b53_br_join); 1874 1875 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1876 { 1877 struct b53_device *dev = ds->priv; 1878 struct b53_vlan *vl = &dev->vlans[0]; 1879 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1880 unsigned int i; 1881 u16 pvlan, reg, pvid; 1882 1883 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1884 1885 b53_for_each_port(dev, i) { 1886 /* Don't touch the remaining ports */ 1887 if (dsa_to_port(ds, i)->bridge_dev != br) 1888 continue; 1889 1890 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1891 reg &= ~BIT(port); 1892 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1893 dev->ports[port].vlan_ctl_mask = reg; 1894 1895 /* Prevent self removal to preserve isolation */ 1896 if (port != i) 1897 pvlan &= ~BIT(i); 1898 } 1899 1900 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1901 dev->ports[port].vlan_ctl_mask = pvlan; 1902 1903 pvid = b53_default_pvid(dev); 1904 1905 /* Make this port join all VLANs without VLAN entries */ 1906 if (is58xx(dev)) { 1907 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1908 reg |= BIT(port); 1909 if (!(reg & BIT(cpu_port))) 1910 reg |= BIT(cpu_port); 1911 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1912 } else { 1913 b53_get_vlan_entry(dev, pvid, vl); 1914 vl->members |= BIT(port) | BIT(cpu_port); 1915 vl->untag |= BIT(port) | BIT(cpu_port); 1916 b53_set_vlan_entry(dev, pvid, vl); 1917 } 1918 } 1919 EXPORT_SYMBOL(b53_br_leave); 1920 1921 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1922 { 1923 struct b53_device *dev = ds->priv; 1924 u8 hw_state; 1925 u8 reg; 1926 1927 switch (state) { 1928 case BR_STATE_DISABLED: 1929 hw_state = PORT_CTRL_DIS_STATE; 1930 break; 1931 case BR_STATE_LISTENING: 1932 hw_state = PORT_CTRL_LISTEN_STATE; 1933 break; 1934 case BR_STATE_LEARNING: 1935 hw_state = PORT_CTRL_LEARN_STATE; 1936 break; 1937 case BR_STATE_FORWARDING: 1938 hw_state = PORT_CTRL_FWD_STATE; 1939 break; 1940 case BR_STATE_BLOCKING: 1941 hw_state = PORT_CTRL_BLOCK_STATE; 1942 break; 1943 default: 1944 dev_err(ds->dev, "invalid STP state: %d\n", state); 1945 return; 1946 } 1947 1948 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1949 reg &= ~PORT_CTRL_STP_STATE_MASK; 1950 reg |= hw_state; 1951 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1952 } 1953 EXPORT_SYMBOL(b53_br_set_stp_state); 1954 1955 void b53_br_fast_age(struct dsa_switch *ds, int port) 1956 { 1957 struct b53_device *dev = ds->priv; 1958 1959 if (b53_fast_age_port(dev, port)) 1960 dev_err(ds->dev, "fast ageing failed\n"); 1961 } 1962 EXPORT_SYMBOL(b53_br_fast_age); 1963 1964 int b53_br_flags_pre(struct dsa_switch *ds, int port, 1965 struct switchdev_brport_flags flags, 1966 struct netlink_ext_ack *extack) 1967 { 1968 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 1969 return -EINVAL; 1970 1971 return 0; 1972 } 1973 EXPORT_SYMBOL(b53_br_flags_pre); 1974 1975 int b53_br_flags(struct dsa_switch *ds, int port, 1976 struct switchdev_brport_flags flags, 1977 struct netlink_ext_ack *extack) 1978 { 1979 if (flags.mask & BR_FLOOD) 1980 b53_port_set_ucast_flood(ds->priv, port, 1981 !!(flags.val & BR_FLOOD)); 1982 if (flags.mask & BR_MCAST_FLOOD) 1983 b53_port_set_mcast_flood(ds->priv, port, 1984 !!(flags.val & BR_MCAST_FLOOD)); 1985 if (flags.mask & BR_LEARNING) 1986 b53_port_set_learning(ds->priv, port, 1987 !!(flags.val & BR_LEARNING)); 1988 1989 return 0; 1990 } 1991 EXPORT_SYMBOL(b53_br_flags); 1992 1993 int b53_set_mrouter(struct dsa_switch *ds, int port, bool mrouter, 1994 struct netlink_ext_ack *extack) 1995 { 1996 b53_port_set_mcast_flood(ds->priv, port, mrouter); 1997 1998 return 0; 1999 } 2000 EXPORT_SYMBOL(b53_set_mrouter); 2001 2002 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2003 { 2004 /* Broadcom switches will accept enabling Broadcom tags on the 2005 * following ports: 5, 7 and 8, any other port is not supported 2006 */ 2007 switch (port) { 2008 case B53_CPU_PORT_25: 2009 case 7: 2010 case B53_CPU_PORT: 2011 return true; 2012 } 2013 2014 return false; 2015 } 2016 2017 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2018 enum dsa_tag_protocol tag_protocol) 2019 { 2020 bool ret = b53_possible_cpu_port(ds, port); 2021 2022 if (!ret) { 2023 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2024 port); 2025 return ret; 2026 } 2027 2028 switch (tag_protocol) { 2029 case DSA_TAG_PROTO_BRCM: 2030 case DSA_TAG_PROTO_BRCM_PREPEND: 2031 dev_warn(ds->dev, 2032 "Port %d is stacked to Broadcom tag switch\n", port); 2033 ret = false; 2034 break; 2035 default: 2036 ret = true; 2037 break; 2038 } 2039 2040 return ret; 2041 } 2042 2043 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2044 enum dsa_tag_protocol mprot) 2045 { 2046 struct b53_device *dev = ds->priv; 2047 2048 /* Older models (5325, 5365) support a different tag format that we do 2049 * not support in net/dsa/tag_brcm.c yet. 2050 */ 2051 if (is5325(dev) || is5365(dev) || 2052 !b53_can_enable_brcm_tags(ds, port, mprot)) { 2053 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2054 goto out; 2055 } 2056 2057 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2058 * which requires us to use the prepended Broadcom tag type 2059 */ 2060 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2061 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2062 goto out; 2063 } 2064 2065 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2066 out: 2067 return dev->tag_protocol; 2068 } 2069 EXPORT_SYMBOL(b53_get_tag_protocol); 2070 2071 int b53_mirror_add(struct dsa_switch *ds, int port, 2072 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 2073 { 2074 struct b53_device *dev = ds->priv; 2075 u16 reg, loc; 2076 2077 if (ingress) 2078 loc = B53_IG_MIR_CTL; 2079 else 2080 loc = B53_EG_MIR_CTL; 2081 2082 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2083 reg |= BIT(port); 2084 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2085 2086 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2087 reg &= ~CAP_PORT_MASK; 2088 reg |= mirror->to_local_port; 2089 reg |= MIRROR_EN; 2090 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2091 2092 return 0; 2093 } 2094 EXPORT_SYMBOL(b53_mirror_add); 2095 2096 void b53_mirror_del(struct dsa_switch *ds, int port, 2097 struct dsa_mall_mirror_tc_entry *mirror) 2098 { 2099 struct b53_device *dev = ds->priv; 2100 bool loc_disable = false, other_loc_disable = false; 2101 u16 reg, loc; 2102 2103 if (mirror->ingress) 2104 loc = B53_IG_MIR_CTL; 2105 else 2106 loc = B53_EG_MIR_CTL; 2107 2108 /* Update the desired ingress/egress register */ 2109 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2110 reg &= ~BIT(port); 2111 if (!(reg & MIRROR_MASK)) 2112 loc_disable = true; 2113 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2114 2115 /* Now look at the other one to know if we can disable mirroring 2116 * entirely 2117 */ 2118 if (mirror->ingress) 2119 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2120 else 2121 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2122 if (!(reg & MIRROR_MASK)) 2123 other_loc_disable = true; 2124 2125 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2126 /* Both no longer have ports, let's disable mirroring */ 2127 if (loc_disable && other_loc_disable) { 2128 reg &= ~MIRROR_EN; 2129 reg &= ~mirror->to_local_port; 2130 } 2131 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2132 } 2133 EXPORT_SYMBOL(b53_mirror_del); 2134 2135 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 2136 { 2137 struct b53_device *dev = ds->priv; 2138 u16 reg; 2139 2140 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 2141 if (enable) 2142 reg |= BIT(port); 2143 else 2144 reg &= ~BIT(port); 2145 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 2146 } 2147 EXPORT_SYMBOL(b53_eee_enable_set); 2148 2149 2150 /* Returns 0 if EEE was not enabled, or 1 otherwise 2151 */ 2152 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2153 { 2154 int ret; 2155 2156 ret = phy_init_eee(phy, 0); 2157 if (ret) 2158 return 0; 2159 2160 b53_eee_enable_set(ds, port, true); 2161 2162 return 1; 2163 } 2164 EXPORT_SYMBOL(b53_eee_init); 2165 2166 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2167 { 2168 struct b53_device *dev = ds->priv; 2169 struct ethtool_eee *p = &dev->ports[port].eee; 2170 u16 reg; 2171 2172 if (is5325(dev) || is5365(dev)) 2173 return -EOPNOTSUPP; 2174 2175 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 2176 e->eee_enabled = p->eee_enabled; 2177 e->eee_active = !!(reg & BIT(port)); 2178 2179 return 0; 2180 } 2181 EXPORT_SYMBOL(b53_get_mac_eee); 2182 2183 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2184 { 2185 struct b53_device *dev = ds->priv; 2186 struct ethtool_eee *p = &dev->ports[port].eee; 2187 2188 if (is5325(dev) || is5365(dev)) 2189 return -EOPNOTSUPP; 2190 2191 p->eee_enabled = e->eee_enabled; 2192 b53_eee_enable_set(ds, port, e->eee_enabled); 2193 2194 return 0; 2195 } 2196 EXPORT_SYMBOL(b53_set_mac_eee); 2197 2198 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2199 { 2200 struct b53_device *dev = ds->priv; 2201 bool enable_jumbo; 2202 bool allow_10_100; 2203 2204 if (is5325(dev) || is5365(dev)) 2205 return -EOPNOTSUPP; 2206 2207 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2208 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2209 2210 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2211 } 2212 2213 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2214 { 2215 return JMS_MAX_SIZE; 2216 } 2217 2218 static const struct dsa_switch_ops b53_switch_ops = { 2219 .get_tag_protocol = b53_get_tag_protocol, 2220 .setup = b53_setup, 2221 .teardown = b53_teardown, 2222 .get_strings = b53_get_strings, 2223 .get_ethtool_stats = b53_get_ethtool_stats, 2224 .get_sset_count = b53_get_sset_count, 2225 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2226 .phy_read = b53_phy_read16, 2227 .phy_write = b53_phy_write16, 2228 .adjust_link = b53_adjust_link, 2229 .phylink_validate = b53_phylink_validate, 2230 .phylink_mac_link_state = b53_phylink_mac_link_state, 2231 .phylink_mac_config = b53_phylink_mac_config, 2232 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 2233 .phylink_mac_link_down = b53_phylink_mac_link_down, 2234 .phylink_mac_link_up = b53_phylink_mac_link_up, 2235 .port_enable = b53_enable_port, 2236 .port_disable = b53_disable_port, 2237 .get_mac_eee = b53_get_mac_eee, 2238 .set_mac_eee = b53_set_mac_eee, 2239 .port_bridge_join = b53_br_join, 2240 .port_bridge_leave = b53_br_leave, 2241 .port_pre_bridge_flags = b53_br_flags_pre, 2242 .port_bridge_flags = b53_br_flags, 2243 .port_set_mrouter = b53_set_mrouter, 2244 .port_stp_state_set = b53_br_set_stp_state, 2245 .port_fast_age = b53_br_fast_age, 2246 .port_vlan_filtering = b53_vlan_filtering, 2247 .port_vlan_add = b53_vlan_add, 2248 .port_vlan_del = b53_vlan_del, 2249 .port_fdb_dump = b53_fdb_dump, 2250 .port_fdb_add = b53_fdb_add, 2251 .port_fdb_del = b53_fdb_del, 2252 .port_mirror_add = b53_mirror_add, 2253 .port_mirror_del = b53_mirror_del, 2254 .port_mdb_add = b53_mdb_add, 2255 .port_mdb_del = b53_mdb_del, 2256 .port_max_mtu = b53_get_max_mtu, 2257 .port_change_mtu = b53_change_mtu, 2258 }; 2259 2260 struct b53_chip_data { 2261 u32 chip_id; 2262 const char *dev_name; 2263 u16 vlans; 2264 u16 enabled_ports; 2265 u8 cpu_port; 2266 u8 vta_regs[3]; 2267 u8 arl_bins; 2268 u16 arl_buckets; 2269 u8 duplex_reg; 2270 u8 jumbo_pm_reg; 2271 u8 jumbo_size_reg; 2272 }; 2273 2274 #define B53_VTA_REGS \ 2275 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2276 #define B53_VTA_REGS_9798 \ 2277 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2278 #define B53_VTA_REGS_63XX \ 2279 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2280 2281 static const struct b53_chip_data b53_switch_chips[] = { 2282 { 2283 .chip_id = BCM5325_DEVICE_ID, 2284 .dev_name = "BCM5325", 2285 .vlans = 16, 2286 .enabled_ports = 0x1f, 2287 .arl_bins = 2, 2288 .arl_buckets = 1024, 2289 .cpu_port = B53_CPU_PORT_25, 2290 .duplex_reg = B53_DUPLEX_STAT_FE, 2291 }, 2292 { 2293 .chip_id = BCM5365_DEVICE_ID, 2294 .dev_name = "BCM5365", 2295 .vlans = 256, 2296 .enabled_ports = 0x1f, 2297 .arl_bins = 2, 2298 .arl_buckets = 1024, 2299 .cpu_port = B53_CPU_PORT_25, 2300 .duplex_reg = B53_DUPLEX_STAT_FE, 2301 }, 2302 { 2303 .chip_id = BCM5389_DEVICE_ID, 2304 .dev_name = "BCM5389", 2305 .vlans = 4096, 2306 .enabled_ports = 0x1f, 2307 .arl_bins = 4, 2308 .arl_buckets = 1024, 2309 .cpu_port = B53_CPU_PORT, 2310 .vta_regs = B53_VTA_REGS, 2311 .duplex_reg = B53_DUPLEX_STAT_GE, 2312 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2313 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2314 }, 2315 { 2316 .chip_id = BCM5395_DEVICE_ID, 2317 .dev_name = "BCM5395", 2318 .vlans = 4096, 2319 .enabled_ports = 0x1f, 2320 .arl_bins = 4, 2321 .arl_buckets = 1024, 2322 .cpu_port = B53_CPU_PORT, 2323 .vta_regs = B53_VTA_REGS, 2324 .duplex_reg = B53_DUPLEX_STAT_GE, 2325 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2326 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2327 }, 2328 { 2329 .chip_id = BCM5397_DEVICE_ID, 2330 .dev_name = "BCM5397", 2331 .vlans = 4096, 2332 .enabled_ports = 0x1f, 2333 .arl_bins = 4, 2334 .arl_buckets = 1024, 2335 .cpu_port = B53_CPU_PORT, 2336 .vta_regs = B53_VTA_REGS_9798, 2337 .duplex_reg = B53_DUPLEX_STAT_GE, 2338 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2339 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2340 }, 2341 { 2342 .chip_id = BCM5398_DEVICE_ID, 2343 .dev_name = "BCM5398", 2344 .vlans = 4096, 2345 .enabled_ports = 0x7f, 2346 .arl_bins = 4, 2347 .arl_buckets = 1024, 2348 .cpu_port = B53_CPU_PORT, 2349 .vta_regs = B53_VTA_REGS_9798, 2350 .duplex_reg = B53_DUPLEX_STAT_GE, 2351 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2352 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2353 }, 2354 { 2355 .chip_id = BCM53115_DEVICE_ID, 2356 .dev_name = "BCM53115", 2357 .vlans = 4096, 2358 .enabled_ports = 0x1f, 2359 .arl_bins = 4, 2360 .arl_buckets = 1024, 2361 .vta_regs = B53_VTA_REGS, 2362 .cpu_port = B53_CPU_PORT, 2363 .duplex_reg = B53_DUPLEX_STAT_GE, 2364 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2365 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2366 }, 2367 { 2368 .chip_id = BCM53125_DEVICE_ID, 2369 .dev_name = "BCM53125", 2370 .vlans = 4096, 2371 .enabled_ports = 0xff, 2372 .arl_bins = 4, 2373 .arl_buckets = 1024, 2374 .cpu_port = B53_CPU_PORT, 2375 .vta_regs = B53_VTA_REGS, 2376 .duplex_reg = B53_DUPLEX_STAT_GE, 2377 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2378 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2379 }, 2380 { 2381 .chip_id = BCM53128_DEVICE_ID, 2382 .dev_name = "BCM53128", 2383 .vlans = 4096, 2384 .enabled_ports = 0x1ff, 2385 .arl_bins = 4, 2386 .arl_buckets = 1024, 2387 .cpu_port = B53_CPU_PORT, 2388 .vta_regs = B53_VTA_REGS, 2389 .duplex_reg = B53_DUPLEX_STAT_GE, 2390 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2391 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2392 }, 2393 { 2394 .chip_id = BCM63XX_DEVICE_ID, 2395 .dev_name = "BCM63xx", 2396 .vlans = 4096, 2397 .enabled_ports = 0, /* pdata must provide them */ 2398 .arl_bins = 4, 2399 .arl_buckets = 1024, 2400 .cpu_port = B53_CPU_PORT, 2401 .vta_regs = B53_VTA_REGS_63XX, 2402 .duplex_reg = B53_DUPLEX_STAT_63XX, 2403 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2404 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2405 }, 2406 { 2407 .chip_id = BCM53010_DEVICE_ID, 2408 .dev_name = "BCM53010", 2409 .vlans = 4096, 2410 .enabled_ports = 0x1f, 2411 .arl_bins = 4, 2412 .arl_buckets = 1024, 2413 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2414 .vta_regs = B53_VTA_REGS, 2415 .duplex_reg = B53_DUPLEX_STAT_GE, 2416 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2417 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2418 }, 2419 { 2420 .chip_id = BCM53011_DEVICE_ID, 2421 .dev_name = "BCM53011", 2422 .vlans = 4096, 2423 .enabled_ports = 0x1bf, 2424 .arl_bins = 4, 2425 .arl_buckets = 1024, 2426 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2427 .vta_regs = B53_VTA_REGS, 2428 .duplex_reg = B53_DUPLEX_STAT_GE, 2429 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2430 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2431 }, 2432 { 2433 .chip_id = BCM53012_DEVICE_ID, 2434 .dev_name = "BCM53012", 2435 .vlans = 4096, 2436 .enabled_ports = 0x1bf, 2437 .arl_bins = 4, 2438 .arl_buckets = 1024, 2439 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2440 .vta_regs = B53_VTA_REGS, 2441 .duplex_reg = B53_DUPLEX_STAT_GE, 2442 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2443 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2444 }, 2445 { 2446 .chip_id = BCM53018_DEVICE_ID, 2447 .dev_name = "BCM53018", 2448 .vlans = 4096, 2449 .enabled_ports = 0x1f, 2450 .arl_bins = 4, 2451 .arl_buckets = 1024, 2452 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2453 .vta_regs = B53_VTA_REGS, 2454 .duplex_reg = B53_DUPLEX_STAT_GE, 2455 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2456 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2457 }, 2458 { 2459 .chip_id = BCM53019_DEVICE_ID, 2460 .dev_name = "BCM53019", 2461 .vlans = 4096, 2462 .enabled_ports = 0x1f, 2463 .arl_bins = 4, 2464 .arl_buckets = 1024, 2465 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2466 .vta_regs = B53_VTA_REGS, 2467 .duplex_reg = B53_DUPLEX_STAT_GE, 2468 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2469 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2470 }, 2471 { 2472 .chip_id = BCM58XX_DEVICE_ID, 2473 .dev_name = "BCM585xx/586xx/88312", 2474 .vlans = 4096, 2475 .enabled_ports = 0x1ff, 2476 .arl_bins = 4, 2477 .arl_buckets = 1024, 2478 .cpu_port = B53_CPU_PORT, 2479 .vta_regs = B53_VTA_REGS, 2480 .duplex_reg = B53_DUPLEX_STAT_GE, 2481 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2482 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2483 }, 2484 { 2485 .chip_id = BCM583XX_DEVICE_ID, 2486 .dev_name = "BCM583xx/11360", 2487 .vlans = 4096, 2488 .enabled_ports = 0x103, 2489 .arl_bins = 4, 2490 .arl_buckets = 1024, 2491 .cpu_port = B53_CPU_PORT, 2492 .vta_regs = B53_VTA_REGS, 2493 .duplex_reg = B53_DUPLEX_STAT_GE, 2494 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2495 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2496 }, 2497 /* Starfighter 2 */ 2498 { 2499 .chip_id = BCM4908_DEVICE_ID, 2500 .dev_name = "BCM4908", 2501 .vlans = 4096, 2502 .enabled_ports = 0x1bf, 2503 .arl_bins = 4, 2504 .arl_buckets = 256, 2505 .cpu_port = 8, /* TODO: ports 4, 5, 8 */ 2506 .vta_regs = B53_VTA_REGS, 2507 .duplex_reg = B53_DUPLEX_STAT_GE, 2508 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2509 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2510 }, 2511 { 2512 .chip_id = BCM7445_DEVICE_ID, 2513 .dev_name = "BCM7445", 2514 .vlans = 4096, 2515 .enabled_ports = 0x1ff, 2516 .arl_bins = 4, 2517 .arl_buckets = 1024, 2518 .cpu_port = B53_CPU_PORT, 2519 .vta_regs = B53_VTA_REGS, 2520 .duplex_reg = B53_DUPLEX_STAT_GE, 2521 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2522 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2523 }, 2524 { 2525 .chip_id = BCM7278_DEVICE_ID, 2526 .dev_name = "BCM7278", 2527 .vlans = 4096, 2528 .enabled_ports = 0x1ff, 2529 .arl_bins = 4, 2530 .arl_buckets = 256, 2531 .cpu_port = B53_CPU_PORT, 2532 .vta_regs = B53_VTA_REGS, 2533 .duplex_reg = B53_DUPLEX_STAT_GE, 2534 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2535 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2536 }, 2537 }; 2538 2539 static int b53_switch_init(struct b53_device *dev) 2540 { 2541 unsigned int i; 2542 int ret; 2543 2544 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2545 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2546 2547 if (chip->chip_id == dev->chip_id) { 2548 if (!dev->enabled_ports) 2549 dev->enabled_ports = chip->enabled_ports; 2550 dev->name = chip->dev_name; 2551 dev->duplex_reg = chip->duplex_reg; 2552 dev->vta_regs[0] = chip->vta_regs[0]; 2553 dev->vta_regs[1] = chip->vta_regs[1]; 2554 dev->vta_regs[2] = chip->vta_regs[2]; 2555 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2556 dev->cpu_port = chip->cpu_port; 2557 dev->num_vlans = chip->vlans; 2558 dev->num_arl_bins = chip->arl_bins; 2559 dev->num_arl_buckets = chip->arl_buckets; 2560 break; 2561 } 2562 } 2563 2564 /* check which BCM5325x version we have */ 2565 if (is5325(dev)) { 2566 u8 vc4; 2567 2568 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2569 2570 /* check reserved bits */ 2571 switch (vc4 & 3) { 2572 case 1: 2573 /* BCM5325E */ 2574 break; 2575 case 3: 2576 /* BCM5325F - do not use port 4 */ 2577 dev->enabled_ports &= ~BIT(4); 2578 break; 2579 default: 2580 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2581 #ifndef CONFIG_BCM47XX 2582 /* BCM5325M */ 2583 return -EINVAL; 2584 #else 2585 break; 2586 #endif 2587 } 2588 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2589 u64 strap_value; 2590 2591 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2592 /* use second IMP port if GMII is enabled */ 2593 if (strap_value & SV_GMII_CTRL_115) 2594 dev->cpu_port = 5; 2595 } 2596 2597 /* cpu port is always last */ 2598 dev->num_ports = dev->cpu_port + 1; 2599 dev->enabled_ports |= BIT(dev->cpu_port); 2600 2601 /* Include non standard CPU port built-in PHYs to be probed */ 2602 if (is539x(dev) || is531x5(dev)) { 2603 for (i = 0; i < dev->num_ports; i++) { 2604 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2605 !b53_possible_cpu_port(dev->ds, i)) 2606 dev->ds->phys_mii_mask |= BIT(i); 2607 } 2608 } 2609 2610 dev->ports = devm_kcalloc(dev->dev, 2611 dev->num_ports, sizeof(struct b53_port), 2612 GFP_KERNEL); 2613 if (!dev->ports) 2614 return -ENOMEM; 2615 2616 dev->vlans = devm_kcalloc(dev->dev, 2617 dev->num_vlans, sizeof(struct b53_vlan), 2618 GFP_KERNEL); 2619 if (!dev->vlans) 2620 return -ENOMEM; 2621 2622 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2623 if (dev->reset_gpio >= 0) { 2624 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2625 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2626 if (ret) 2627 return ret; 2628 } 2629 2630 return 0; 2631 } 2632 2633 struct b53_device *b53_switch_alloc(struct device *base, 2634 const struct b53_io_ops *ops, 2635 void *priv) 2636 { 2637 struct dsa_switch *ds; 2638 struct b53_device *dev; 2639 2640 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2641 if (!ds) 2642 return NULL; 2643 2644 ds->dev = base; 2645 ds->num_ports = DSA_MAX_PORTS; 2646 2647 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2648 if (!dev) 2649 return NULL; 2650 2651 ds->priv = dev; 2652 dev->dev = base; 2653 2654 dev->ds = ds; 2655 dev->priv = priv; 2656 dev->ops = ops; 2657 ds->ops = &b53_switch_ops; 2658 ds->untag_bridge_pvid = true; 2659 dev->vlan_enabled = true; 2660 /* Let DSA handle the case were multiple bridges span the same switch 2661 * device and different VLAN awareness settings are requested, which 2662 * would be breaking filtering semantics for any of the other bridge 2663 * devices. (not hardware supported) 2664 */ 2665 ds->vlan_filtering_is_global = true; 2666 2667 mutex_init(&dev->reg_mutex); 2668 mutex_init(&dev->stats_mutex); 2669 2670 return dev; 2671 } 2672 EXPORT_SYMBOL(b53_switch_alloc); 2673 2674 int b53_switch_detect(struct b53_device *dev) 2675 { 2676 u32 id32; 2677 u16 tmp; 2678 u8 id8; 2679 int ret; 2680 2681 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2682 if (ret) 2683 return ret; 2684 2685 switch (id8) { 2686 case 0: 2687 /* BCM5325 and BCM5365 do not have this register so reads 2688 * return 0. But the read operation did succeed, so assume this 2689 * is one of them. 2690 * 2691 * Next check if we can write to the 5325's VTA register; for 2692 * 5365 it is read only. 2693 */ 2694 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2695 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2696 2697 if (tmp == 0xf) 2698 dev->chip_id = BCM5325_DEVICE_ID; 2699 else 2700 dev->chip_id = BCM5365_DEVICE_ID; 2701 break; 2702 case BCM5389_DEVICE_ID: 2703 case BCM5395_DEVICE_ID: 2704 case BCM5397_DEVICE_ID: 2705 case BCM5398_DEVICE_ID: 2706 dev->chip_id = id8; 2707 break; 2708 default: 2709 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2710 if (ret) 2711 return ret; 2712 2713 switch (id32) { 2714 case BCM53115_DEVICE_ID: 2715 case BCM53125_DEVICE_ID: 2716 case BCM53128_DEVICE_ID: 2717 case BCM53010_DEVICE_ID: 2718 case BCM53011_DEVICE_ID: 2719 case BCM53012_DEVICE_ID: 2720 case BCM53018_DEVICE_ID: 2721 case BCM53019_DEVICE_ID: 2722 dev->chip_id = id32; 2723 break; 2724 default: 2725 dev_err(dev->dev, 2726 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2727 id8, id32); 2728 return -ENODEV; 2729 } 2730 } 2731 2732 if (dev->chip_id == BCM5325_DEVICE_ID) 2733 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2734 &dev->core_rev); 2735 else 2736 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2737 &dev->core_rev); 2738 } 2739 EXPORT_SYMBOL(b53_switch_detect); 2740 2741 int b53_switch_register(struct b53_device *dev) 2742 { 2743 int ret; 2744 2745 if (dev->pdata) { 2746 dev->chip_id = dev->pdata->chip_id; 2747 dev->enabled_ports = dev->pdata->enabled_ports; 2748 } 2749 2750 if (!dev->chip_id && b53_switch_detect(dev)) 2751 return -EINVAL; 2752 2753 ret = b53_switch_init(dev); 2754 if (ret) 2755 return ret; 2756 2757 dev_info(dev->dev, "found switch: %s, rev %i\n", 2758 dev->name, dev->core_rev); 2759 2760 return dsa_register_switch(dev->ds); 2761 } 2762 EXPORT_SYMBOL(b53_switch_register); 2763 2764 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2765 MODULE_DESCRIPTION("B53 switch library"); 2766 MODULE_LICENSE("Dual BSD/GPL"); 2767