1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/etherdevice.h> 30 #include <linux/if_bridge.h> 31 #include <net/dsa.h> 32 33 #include "b53_regs.h" 34 #include "b53_priv.h" 35 36 struct b53_mib_desc { 37 u8 size; 38 u8 offset; 39 const char *name; 40 }; 41 42 /* BCM5365 MIB counters */ 43 static const struct b53_mib_desc b53_mibs_65[] = { 44 { 8, 0x00, "TxOctets" }, 45 { 4, 0x08, "TxDropPkts" }, 46 { 4, 0x10, "TxBroadcastPkts" }, 47 { 4, 0x14, "TxMulticastPkts" }, 48 { 4, 0x18, "TxUnicastPkts" }, 49 { 4, 0x1c, "TxCollisions" }, 50 { 4, 0x20, "TxSingleCollision" }, 51 { 4, 0x24, "TxMultipleCollision" }, 52 { 4, 0x28, "TxDeferredTransmit" }, 53 { 4, 0x2c, "TxLateCollision" }, 54 { 4, 0x30, "TxExcessiveCollision" }, 55 { 4, 0x38, "TxPausePkts" }, 56 { 8, 0x44, "RxOctets" }, 57 { 4, 0x4c, "RxUndersizePkts" }, 58 { 4, 0x50, "RxPausePkts" }, 59 { 4, 0x54, "Pkts64Octets" }, 60 { 4, 0x58, "Pkts65to127Octets" }, 61 { 4, 0x5c, "Pkts128to255Octets" }, 62 { 4, 0x60, "Pkts256to511Octets" }, 63 { 4, 0x64, "Pkts512to1023Octets" }, 64 { 4, 0x68, "Pkts1024to1522Octets" }, 65 { 4, 0x6c, "RxOversizePkts" }, 66 { 4, 0x70, "RxJabbers" }, 67 { 4, 0x74, "RxAlignmentErrors" }, 68 { 4, 0x78, "RxFCSErrors" }, 69 { 8, 0x7c, "RxGoodOctets" }, 70 { 4, 0x84, "RxDropPkts" }, 71 { 4, 0x88, "RxUnicastPkts" }, 72 { 4, 0x8c, "RxMulticastPkts" }, 73 { 4, 0x90, "RxBroadcastPkts" }, 74 { 4, 0x94, "RxSAChanges" }, 75 { 4, 0x98, "RxFragments" }, 76 }; 77 78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 79 80 /* BCM63xx MIB counters */ 81 static const struct b53_mib_desc b53_mibs_63xx[] = { 82 { 8, 0x00, "TxOctets" }, 83 { 4, 0x08, "TxDropPkts" }, 84 { 4, 0x0c, "TxQoSPkts" }, 85 { 4, 0x10, "TxBroadcastPkts" }, 86 { 4, 0x14, "TxMulticastPkts" }, 87 { 4, 0x18, "TxUnicastPkts" }, 88 { 4, 0x1c, "TxCollisions" }, 89 { 4, 0x20, "TxSingleCollision" }, 90 { 4, 0x24, "TxMultipleCollision" }, 91 { 4, 0x28, "TxDeferredTransmit" }, 92 { 4, 0x2c, "TxLateCollision" }, 93 { 4, 0x30, "TxExcessiveCollision" }, 94 { 4, 0x38, "TxPausePkts" }, 95 { 8, 0x3c, "TxQoSOctets" }, 96 { 8, 0x44, "RxOctets" }, 97 { 4, 0x4c, "RxUndersizePkts" }, 98 { 4, 0x50, "RxPausePkts" }, 99 { 4, 0x54, "Pkts64Octets" }, 100 { 4, 0x58, "Pkts65to127Octets" }, 101 { 4, 0x5c, "Pkts128to255Octets" }, 102 { 4, 0x60, "Pkts256to511Octets" }, 103 { 4, 0x64, "Pkts512to1023Octets" }, 104 { 4, 0x68, "Pkts1024to1522Octets" }, 105 { 4, 0x6c, "RxOversizePkts" }, 106 { 4, 0x70, "RxJabbers" }, 107 { 4, 0x74, "RxAlignmentErrors" }, 108 { 4, 0x78, "RxFCSErrors" }, 109 { 8, 0x7c, "RxGoodOctets" }, 110 { 4, 0x84, "RxDropPkts" }, 111 { 4, 0x88, "RxUnicastPkts" }, 112 { 4, 0x8c, "RxMulticastPkts" }, 113 { 4, 0x90, "RxBroadcastPkts" }, 114 { 4, 0x94, "RxSAChanges" }, 115 { 4, 0x98, "RxFragments" }, 116 { 4, 0xa0, "RxSymbolErrors" }, 117 { 4, 0xa4, "RxQoSPkts" }, 118 { 8, 0xa8, "RxQoSOctets" }, 119 { 4, 0xb0, "Pkts1523to2047Octets" }, 120 { 4, 0xb4, "Pkts2048to4095Octets" }, 121 { 4, 0xb8, "Pkts4096to8191Octets" }, 122 { 4, 0xbc, "Pkts8192to9728Octets" }, 123 { 4, 0xc0, "RxDiscarded" }, 124 }; 125 126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 127 128 /* MIB counters */ 129 static const struct b53_mib_desc b53_mibs[] = { 130 { 8, 0x00, "TxOctets" }, 131 { 4, 0x08, "TxDropPkts" }, 132 { 4, 0x10, "TxBroadcastPkts" }, 133 { 4, 0x14, "TxMulticastPkts" }, 134 { 4, 0x18, "TxUnicastPkts" }, 135 { 4, 0x1c, "TxCollisions" }, 136 { 4, 0x20, "TxSingleCollision" }, 137 { 4, 0x24, "TxMultipleCollision" }, 138 { 4, 0x28, "TxDeferredTransmit" }, 139 { 4, 0x2c, "TxLateCollision" }, 140 { 4, 0x30, "TxExcessiveCollision" }, 141 { 4, 0x38, "TxPausePkts" }, 142 { 8, 0x50, "RxOctets" }, 143 { 4, 0x58, "RxUndersizePkts" }, 144 { 4, 0x5c, "RxPausePkts" }, 145 { 4, 0x60, "Pkts64Octets" }, 146 { 4, 0x64, "Pkts65to127Octets" }, 147 { 4, 0x68, "Pkts128to255Octets" }, 148 { 4, 0x6c, "Pkts256to511Octets" }, 149 { 4, 0x70, "Pkts512to1023Octets" }, 150 { 4, 0x74, "Pkts1024to1522Octets" }, 151 { 4, 0x78, "RxOversizePkts" }, 152 { 4, 0x7c, "RxJabbers" }, 153 { 4, 0x80, "RxAlignmentErrors" }, 154 { 4, 0x84, "RxFCSErrors" }, 155 { 8, 0x88, "RxGoodOctets" }, 156 { 4, 0x90, "RxDropPkts" }, 157 { 4, 0x94, "RxUnicastPkts" }, 158 { 4, 0x98, "RxMulticastPkts" }, 159 { 4, 0x9c, "RxBroadcastPkts" }, 160 { 4, 0xa0, "RxSAChanges" }, 161 { 4, 0xa4, "RxFragments" }, 162 { 4, 0xa8, "RxJumboPkts" }, 163 { 4, 0xac, "RxSymbolErrors" }, 164 { 4, 0xc0, "RxDiscarded" }, 165 }; 166 167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 168 169 static const struct b53_mib_desc b53_mibs_58xx[] = { 170 { 8, 0x00, "TxOctets" }, 171 { 4, 0x08, "TxDropPkts" }, 172 { 4, 0x0c, "TxQPKTQ0" }, 173 { 4, 0x10, "TxBroadcastPkts" }, 174 { 4, 0x14, "TxMulticastPkts" }, 175 { 4, 0x18, "TxUnicastPKts" }, 176 { 4, 0x1c, "TxCollisions" }, 177 { 4, 0x20, "TxSingleCollision" }, 178 { 4, 0x24, "TxMultipleCollision" }, 179 { 4, 0x28, "TxDeferredCollision" }, 180 { 4, 0x2c, "TxLateCollision" }, 181 { 4, 0x30, "TxExcessiveCollision" }, 182 { 4, 0x34, "TxFrameInDisc" }, 183 { 4, 0x38, "TxPausePkts" }, 184 { 4, 0x3c, "TxQPKTQ1" }, 185 { 4, 0x40, "TxQPKTQ2" }, 186 { 4, 0x44, "TxQPKTQ3" }, 187 { 4, 0x48, "TxQPKTQ4" }, 188 { 4, 0x4c, "TxQPKTQ5" }, 189 { 8, 0x50, "RxOctets" }, 190 { 4, 0x58, "RxUndersizePkts" }, 191 { 4, 0x5c, "RxPausePkts" }, 192 { 4, 0x60, "RxPkts64Octets" }, 193 { 4, 0x64, "RxPkts65to127Octets" }, 194 { 4, 0x68, "RxPkts128to255Octets" }, 195 { 4, 0x6c, "RxPkts256to511Octets" }, 196 { 4, 0x70, "RxPkts512to1023Octets" }, 197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 198 { 4, 0x78, "RxOversizePkts" }, 199 { 4, 0x7c, "RxJabbers" }, 200 { 4, 0x80, "RxAlignmentErrors" }, 201 { 4, 0x84, "RxFCSErrors" }, 202 { 8, 0x88, "RxGoodOctets" }, 203 { 4, 0x90, "RxDropPkts" }, 204 { 4, 0x94, "RxUnicastPkts" }, 205 { 4, 0x98, "RxMulticastPkts" }, 206 { 4, 0x9c, "RxBroadcastPkts" }, 207 { 4, 0xa0, "RxSAChanges" }, 208 { 4, 0xa4, "RxFragments" }, 209 { 4, 0xa8, "RxJumboPkt" }, 210 { 4, 0xac, "RxSymblErr" }, 211 { 4, 0xb0, "InRangeErrCount" }, 212 { 4, 0xb4, "OutRangeErrCount" }, 213 { 4, 0xb8, "EEELpiEvent" }, 214 { 4, 0xbc, "EEELpiDuration" }, 215 { 4, 0xc0, "RxDiscard" }, 216 { 4, 0xc8, "TxQPKTQ6" }, 217 { 4, 0xcc, "TxQPKTQ7" }, 218 { 4, 0xd0, "TxPkts64Octets" }, 219 { 4, 0xd4, "TxPkts65to127Octets" }, 220 { 4, 0xd8, "TxPkts128to255Octets" }, 221 { 4, 0xdc, "TxPkts256to511Ocets" }, 222 { 4, 0xe0, "TxPkts512to1023Ocets" }, 223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 224 }; 225 226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 227 228 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 229 { 230 unsigned int i; 231 232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 233 234 for (i = 0; i < 10; i++) { 235 u8 vta; 236 237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 238 if (!(vta & VTA_START_CMD)) 239 return 0; 240 241 usleep_range(100, 200); 242 } 243 244 return -EIO; 245 } 246 247 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 248 struct b53_vlan *vlan) 249 { 250 if (is5325(dev)) { 251 u32 entry = 0; 252 253 if (vlan->members) { 254 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 255 VA_UNTAG_S_25) | vlan->members; 256 if (dev->core_rev >= 3) 257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 258 else 259 entry |= VA_VALID_25; 260 } 261 262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 264 VTA_RW_STATE_WR | VTA_RW_OP_EN); 265 } else if (is5365(dev)) { 266 u16 entry = 0; 267 268 if (vlan->members) 269 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 271 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 274 VTA_RW_STATE_WR | VTA_RW_OP_EN); 275 } else { 276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 278 (vlan->untag << VTE_UNTAG_S) | vlan->members); 279 280 b53_do_vlan_op(dev, VTA_CMD_WRITE); 281 } 282 283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 284 vid, vlan->members, vlan->untag); 285 } 286 287 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 288 struct b53_vlan *vlan) 289 { 290 if (is5325(dev)) { 291 u32 entry = 0; 292 293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 294 VTA_RW_STATE_RD | VTA_RW_OP_EN); 295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 296 297 if (dev->core_rev >= 3) 298 vlan->valid = !!(entry & VA_VALID_25_R4); 299 else 300 vlan->valid = !!(entry & VA_VALID_25); 301 vlan->members = entry & VA_MEMBER_MASK; 302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 303 304 } else if (is5365(dev)) { 305 u16 entry = 0; 306 307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 308 VTA_RW_STATE_WR | VTA_RW_OP_EN); 309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 310 311 vlan->valid = !!(entry & VA_VALID_65); 312 vlan->members = entry & VA_MEMBER_MASK; 313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 314 } else { 315 u32 entry = 0; 316 317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 318 b53_do_vlan_op(dev, VTA_CMD_READ); 319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 320 vlan->members = entry & VTE_MEMBERS; 321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 322 vlan->valid = true; 323 } 324 } 325 326 static void b53_set_forwarding(struct b53_device *dev, int enable) 327 { 328 u8 mgmt; 329 330 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 331 332 if (enable) 333 mgmt |= SM_SW_FWD_EN; 334 else 335 mgmt &= ~SM_SW_FWD_EN; 336 337 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 338 339 /* Include IMP port in dumb forwarding mode 340 */ 341 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 342 mgmt |= B53_MII_DUMB_FWDG_EN; 343 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 344 } 345 346 static void b53_enable_vlan(struct b53_device *dev, bool enable) 347 { 348 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 349 350 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 351 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 352 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 353 354 if (is5325(dev) || is5365(dev)) { 355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 357 } else if (is63xx(dev)) { 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 360 } else { 361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 363 } 364 365 mgmt &= ~SM_SW_FWD_MODE; 366 367 if (enable) { 368 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 369 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 370 vc4 &= ~VC4_ING_VID_CHECK_MASK; 371 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 372 vc5 |= VC5_DROP_VTABLE_MISS; 373 374 if (is5325(dev)) 375 vc0 &= ~VC0_RESERVED_1; 376 377 if (is5325(dev) || is5365(dev)) 378 vc1 |= VC1_RX_MCST_TAG_EN; 379 380 } else { 381 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 382 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 383 vc4 &= ~VC4_ING_VID_CHECK_MASK; 384 vc5 &= ~VC5_DROP_VTABLE_MISS; 385 386 if (is5325(dev) || is5365(dev)) 387 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 388 else 389 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 390 391 if (is5325(dev) || is5365(dev)) 392 vc1 &= ~VC1_RX_MCST_TAG_EN; 393 } 394 395 if (!is5325(dev) && !is5365(dev)) 396 vc5 &= ~VC5_VID_FFF_EN; 397 398 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 400 401 if (is5325(dev) || is5365(dev)) { 402 /* enable the high 8 bit vid check on 5325 */ 403 if (is5325(dev) && enable) 404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 405 VC3_HIGH_8BIT_EN); 406 else 407 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 408 409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 411 } else if (is63xx(dev)) { 412 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 415 } else { 416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 419 } 420 421 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 422 } 423 424 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 425 { 426 u32 port_mask = 0; 427 u16 max_size = JMS_MIN_SIZE; 428 429 if (is5325(dev) || is5365(dev)) 430 return -EINVAL; 431 432 if (enable) { 433 port_mask = dev->enabled_ports; 434 max_size = JMS_MAX_SIZE; 435 if (allow_10_100) 436 port_mask |= JPM_10_100_JUMBO_EN; 437 } 438 439 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 440 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 441 } 442 443 static int b53_flush_arl(struct b53_device *dev, u8 mask) 444 { 445 unsigned int i; 446 447 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 448 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 449 450 for (i = 0; i < 10; i++) { 451 u8 fast_age_ctrl; 452 453 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 454 &fast_age_ctrl); 455 456 if (!(fast_age_ctrl & FAST_AGE_DONE)) 457 goto out; 458 459 msleep(1); 460 } 461 462 return -ETIMEDOUT; 463 out: 464 /* Only age dynamic entries (default behavior) */ 465 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 466 return 0; 467 } 468 469 static int b53_fast_age_port(struct b53_device *dev, int port) 470 { 471 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 472 473 return b53_flush_arl(dev, FAST_AGE_PORT); 474 } 475 476 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 477 { 478 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 479 480 return b53_flush_arl(dev, FAST_AGE_VLAN); 481 } 482 483 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 484 { 485 struct b53_device *dev = ds->priv; 486 unsigned int i; 487 u16 pvlan; 488 489 /* Enable the IMP port to be in the same VLAN as the other ports 490 * on a per-port basis such that we only have Port i and IMP in 491 * the same VLAN. 492 */ 493 b53_for_each_port(dev, i) { 494 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 495 pvlan |= BIT(cpu_port); 496 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 497 } 498 } 499 EXPORT_SYMBOL(b53_imp_vlan_setup); 500 501 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 502 { 503 struct b53_device *dev = ds->priv; 504 unsigned int cpu_port = ds->ports[port].cpu_dp->index; 505 u16 pvlan; 506 507 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 508 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 509 510 /* Set this port, and only this one to be in the default VLAN, 511 * if member of a bridge, restore its membership prior to 512 * bringing down this port. 513 */ 514 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 515 pvlan &= ~0x1ff; 516 pvlan |= BIT(port); 517 pvlan |= dev->ports[port].vlan_ctl_mask; 518 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 519 520 b53_imp_vlan_setup(ds, cpu_port); 521 522 /* If EEE was enabled, restore it */ 523 if (dev->ports[port].eee.eee_enabled) 524 b53_eee_enable_set(ds, port, true); 525 526 return 0; 527 } 528 EXPORT_SYMBOL(b53_enable_port); 529 530 void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 531 { 532 struct b53_device *dev = ds->priv; 533 u8 reg; 534 535 /* Disable Tx/Rx for the port */ 536 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 537 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 538 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 539 } 540 EXPORT_SYMBOL(b53_disable_port); 541 542 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 543 { 544 bool tag_en = !(ds->ops->get_tag_protocol(ds, port) == 545 DSA_TAG_PROTO_NONE); 546 struct b53_device *dev = ds->priv; 547 u8 hdr_ctl, val; 548 u16 reg; 549 550 /* Resolve which bit controls the Broadcom tag */ 551 switch (port) { 552 case 8: 553 val = BRCM_HDR_P8_EN; 554 break; 555 case 7: 556 val = BRCM_HDR_P7_EN; 557 break; 558 case 5: 559 val = BRCM_HDR_P5_EN; 560 break; 561 default: 562 val = 0; 563 break; 564 } 565 566 /* Enable Broadcom tags for IMP port */ 567 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 568 if (tag_en) 569 hdr_ctl |= val; 570 else 571 hdr_ctl &= ~val; 572 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 573 574 /* Registers below are only accessible on newer devices */ 575 if (!is58xx(dev)) 576 return; 577 578 /* Enable reception Broadcom tag for CPU TX (switch RX) to 579 * allow us to tag outgoing frames 580 */ 581 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 582 if (tag_en) 583 reg &= ~BIT(port); 584 else 585 reg |= BIT(port); 586 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 587 588 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 589 * allow delivering frames to the per-port net_devices 590 */ 591 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 592 if (tag_en) 593 reg &= ~BIT(port); 594 else 595 reg |= BIT(port); 596 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 597 } 598 EXPORT_SYMBOL(b53_brcm_hdr_setup); 599 600 static void b53_enable_cpu_port(struct b53_device *dev, int port) 601 { 602 u8 port_ctrl; 603 604 /* BCM5325 CPU port is at 8 */ 605 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 606 port = B53_CPU_PORT; 607 608 port_ctrl = PORT_CTRL_RX_BCST_EN | 609 PORT_CTRL_RX_MCST_EN | 610 PORT_CTRL_RX_UCST_EN; 611 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 612 613 b53_brcm_hdr_setup(dev->ds, port); 614 } 615 616 static void b53_enable_mib(struct b53_device *dev) 617 { 618 u8 gc; 619 620 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 621 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 622 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 623 } 624 625 int b53_configure_vlan(struct dsa_switch *ds) 626 { 627 struct b53_device *dev = ds->priv; 628 struct b53_vlan vl = { 0 }; 629 int i; 630 631 /* clear all vlan entries */ 632 if (is5325(dev) || is5365(dev)) { 633 for (i = 1; i < dev->num_vlans; i++) 634 b53_set_vlan_entry(dev, i, &vl); 635 } else { 636 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 637 } 638 639 b53_enable_vlan(dev, false); 640 641 b53_for_each_port(dev, i) 642 b53_write16(dev, B53_VLAN_PAGE, 643 B53_VLAN_PORT_DEF_TAG(i), 1); 644 645 if (!is5325(dev) && !is5365(dev)) 646 b53_set_jumbo(dev, dev->enable_jumbo, false); 647 648 return 0; 649 } 650 EXPORT_SYMBOL(b53_configure_vlan); 651 652 static void b53_switch_reset_gpio(struct b53_device *dev) 653 { 654 int gpio = dev->reset_gpio; 655 656 if (gpio < 0) 657 return; 658 659 /* Reset sequence: RESET low(50ms)->high(20ms) 660 */ 661 gpio_set_value(gpio, 0); 662 mdelay(50); 663 664 gpio_set_value(gpio, 1); 665 mdelay(20); 666 667 dev->current_page = 0xff; 668 } 669 670 static int b53_switch_reset(struct b53_device *dev) 671 { 672 unsigned int timeout = 1000; 673 u8 mgmt, reg; 674 675 b53_switch_reset_gpio(dev); 676 677 if (is539x(dev)) { 678 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 679 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 680 } 681 682 /* This is specific to 58xx devices here, do not use is58xx() which 683 * covers the larger Starfigther 2 family, including 7445/7278 which 684 * still use this driver as a library and need to perform the reset 685 * earlier. 686 */ 687 if (dev->chip_id == BCM58XX_DEVICE_ID) { 688 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 689 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 690 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 691 692 do { 693 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 694 if (!(reg & SW_RST)) 695 break; 696 697 usleep_range(1000, 2000); 698 } while (timeout-- > 0); 699 700 if (timeout == 0) 701 return -ETIMEDOUT; 702 } 703 704 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 705 706 if (!(mgmt & SM_SW_FWD_EN)) { 707 mgmt &= ~SM_SW_FWD_MODE; 708 mgmt |= SM_SW_FWD_EN; 709 710 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 711 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 712 713 if (!(mgmt & SM_SW_FWD_EN)) { 714 dev_err(dev->dev, "Failed to enable switch!\n"); 715 return -EINVAL; 716 } 717 } 718 719 b53_enable_mib(dev); 720 721 return b53_flush_arl(dev, FAST_AGE_STATIC); 722 } 723 724 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 725 { 726 struct b53_device *priv = ds->priv; 727 u16 value = 0; 728 int ret; 729 730 if (priv->ops->phy_read16) 731 ret = priv->ops->phy_read16(priv, addr, reg, &value); 732 else 733 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 734 reg * 2, &value); 735 736 return ret ? ret : value; 737 } 738 739 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 740 { 741 struct b53_device *priv = ds->priv; 742 743 if (priv->ops->phy_write16) 744 return priv->ops->phy_write16(priv, addr, reg, val); 745 746 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 747 } 748 749 static int b53_reset_switch(struct b53_device *priv) 750 { 751 /* reset vlans */ 752 priv->enable_jumbo = false; 753 754 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 755 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 756 757 return b53_switch_reset(priv); 758 } 759 760 static int b53_apply_config(struct b53_device *priv) 761 { 762 /* disable switching */ 763 b53_set_forwarding(priv, 0); 764 765 b53_configure_vlan(priv->ds); 766 767 /* enable switching */ 768 b53_set_forwarding(priv, 1); 769 770 return 0; 771 } 772 773 static void b53_reset_mib(struct b53_device *priv) 774 { 775 u8 gc; 776 777 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 778 779 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 780 msleep(1); 781 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 782 msleep(1); 783 } 784 785 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 786 { 787 if (is5365(dev)) 788 return b53_mibs_65; 789 else if (is63xx(dev)) 790 return b53_mibs_63xx; 791 else if (is58xx(dev)) 792 return b53_mibs_58xx; 793 else 794 return b53_mibs; 795 } 796 797 static unsigned int b53_get_mib_size(struct b53_device *dev) 798 { 799 if (is5365(dev)) 800 return B53_MIBS_65_SIZE; 801 else if (is63xx(dev)) 802 return B53_MIBS_63XX_SIZE; 803 else if (is58xx(dev)) 804 return B53_MIBS_58XX_SIZE; 805 else 806 return B53_MIBS_SIZE; 807 } 808 809 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 810 { 811 /* These ports typically do not have built-in PHYs */ 812 switch (port) { 813 case B53_CPU_PORT_25: 814 case 7: 815 case B53_CPU_PORT: 816 return NULL; 817 } 818 819 return mdiobus_get_phy(ds->slave_mii_bus, port); 820 } 821 822 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 823 uint8_t *data) 824 { 825 struct b53_device *dev = ds->priv; 826 const struct b53_mib_desc *mibs = b53_get_mib(dev); 827 unsigned int mib_size = b53_get_mib_size(dev); 828 struct phy_device *phydev; 829 unsigned int i; 830 831 if (stringset == ETH_SS_STATS) { 832 for (i = 0; i < mib_size; i++) 833 strlcpy(data + i * ETH_GSTRING_LEN, 834 mibs[i].name, ETH_GSTRING_LEN); 835 } else if (stringset == ETH_SS_PHY_STATS) { 836 phydev = b53_get_phy_device(ds, port); 837 if (!phydev) 838 return; 839 840 phy_ethtool_get_strings(phydev, data); 841 } 842 } 843 EXPORT_SYMBOL(b53_get_strings); 844 845 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 846 { 847 struct b53_device *dev = ds->priv; 848 const struct b53_mib_desc *mibs = b53_get_mib(dev); 849 unsigned int mib_size = b53_get_mib_size(dev); 850 const struct b53_mib_desc *s; 851 unsigned int i; 852 u64 val = 0; 853 854 if (is5365(dev) && port == 5) 855 port = 8; 856 857 mutex_lock(&dev->stats_mutex); 858 859 for (i = 0; i < mib_size; i++) { 860 s = &mibs[i]; 861 862 if (s->size == 8) { 863 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 864 } else { 865 u32 val32; 866 867 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 868 &val32); 869 val = val32; 870 } 871 data[i] = (u64)val; 872 } 873 874 mutex_unlock(&dev->stats_mutex); 875 } 876 EXPORT_SYMBOL(b53_get_ethtool_stats); 877 878 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 879 { 880 struct phy_device *phydev; 881 882 phydev = b53_get_phy_device(ds, port); 883 if (!phydev) 884 return; 885 886 phy_ethtool_get_stats(phydev, NULL, data); 887 } 888 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 889 890 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 891 { 892 struct b53_device *dev = ds->priv; 893 struct phy_device *phydev; 894 895 if (sset == ETH_SS_STATS) { 896 return b53_get_mib_size(dev); 897 } else if (sset == ETH_SS_PHY_STATS) { 898 phydev = b53_get_phy_device(ds, port); 899 if (!phydev) 900 return 0; 901 902 return phy_ethtool_get_sset_count(phydev); 903 } 904 905 return 0; 906 } 907 EXPORT_SYMBOL(b53_get_sset_count); 908 909 static int b53_setup(struct dsa_switch *ds) 910 { 911 struct b53_device *dev = ds->priv; 912 unsigned int port; 913 int ret; 914 915 ret = b53_reset_switch(dev); 916 if (ret) { 917 dev_err(ds->dev, "failed to reset switch\n"); 918 return ret; 919 } 920 921 b53_reset_mib(dev); 922 923 ret = b53_apply_config(dev); 924 if (ret) 925 dev_err(ds->dev, "failed to apply configuration\n"); 926 927 /* Configure IMP/CPU port, disable unused ports. Enabled 928 * ports will be configured with .port_enable 929 */ 930 for (port = 0; port < dev->num_ports; port++) { 931 if (dsa_is_cpu_port(ds, port)) 932 b53_enable_cpu_port(dev, port); 933 else if (dsa_is_unused_port(ds, port)) 934 b53_disable_port(ds, port, NULL); 935 } 936 937 return ret; 938 } 939 940 static void b53_adjust_link(struct dsa_switch *ds, int port, 941 struct phy_device *phydev) 942 { 943 struct b53_device *dev = ds->priv; 944 struct ethtool_eee *p = &dev->ports[port].eee; 945 u8 rgmii_ctrl = 0, reg = 0, off; 946 947 if (!phy_is_pseudo_fixed_link(phydev)) 948 return; 949 950 /* Override the port settings */ 951 if (port == dev->cpu_port) { 952 off = B53_PORT_OVERRIDE_CTRL; 953 reg = PORT_OVERRIDE_EN; 954 } else { 955 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 956 reg = GMII_PO_EN; 957 } 958 959 /* Set the link UP */ 960 if (phydev->link) 961 reg |= PORT_OVERRIDE_LINK; 962 963 if (phydev->duplex == DUPLEX_FULL) 964 reg |= PORT_OVERRIDE_FULL_DUPLEX; 965 966 switch (phydev->speed) { 967 case 2000: 968 reg |= PORT_OVERRIDE_SPEED_2000M; 969 /* fallthrough */ 970 case SPEED_1000: 971 reg |= PORT_OVERRIDE_SPEED_1000M; 972 break; 973 case SPEED_100: 974 reg |= PORT_OVERRIDE_SPEED_100M; 975 break; 976 case SPEED_10: 977 reg |= PORT_OVERRIDE_SPEED_10M; 978 break; 979 default: 980 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed); 981 return; 982 } 983 984 /* Enable flow control on BCM5301x's CPU port */ 985 if (is5301x(dev) && port == dev->cpu_port) 986 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW; 987 988 if (phydev->pause) { 989 if (phydev->asym_pause) 990 reg |= PORT_OVERRIDE_TX_FLOW; 991 reg |= PORT_OVERRIDE_RX_FLOW; 992 } 993 994 b53_write8(dev, B53_CTRL_PAGE, off, reg); 995 996 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 997 if (port == 8) 998 off = B53_RGMII_CTRL_IMP; 999 else 1000 off = B53_RGMII_CTRL_P(port); 1001 1002 /* Configure the port RGMII clock delay by DLL disabled and 1003 * tx_clk aligned timing (restoring to reset defaults) 1004 */ 1005 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1006 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1007 RGMII_CTRL_TIMING_SEL); 1008 1009 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1010 * sure that we enable the port TX clock internal delay to 1011 * account for this internal delay that is inserted, otherwise 1012 * the switch won't be able to receive correctly. 1013 * 1014 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1015 * any delay neither on transmission nor reception, so the 1016 * BCM53125 must also be configured accordingly to account for 1017 * the lack of delay and introduce 1018 * 1019 * The BCM53125 switch has its RX clock and TX clock control 1020 * swapped, hence the reason why we modify the TX clock path in 1021 * the "RGMII" case 1022 */ 1023 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1024 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1025 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1026 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1027 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1028 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1029 1030 dev_info(ds->dev, "Configured port %d for %s\n", port, 1031 phy_modes(phydev->interface)); 1032 } 1033 1034 /* configure MII port if necessary */ 1035 if (is5325(dev)) { 1036 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1037 ®); 1038 1039 /* reverse mii needs to be enabled */ 1040 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1041 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1042 reg | PORT_OVERRIDE_RV_MII_25); 1043 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1044 ®); 1045 1046 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1047 dev_err(ds->dev, 1048 "Failed to enable reverse MII mode\n"); 1049 return; 1050 } 1051 } 1052 } else if (is5301x(dev)) { 1053 if (port != dev->cpu_port) { 1054 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port); 1055 u8 gmii_po; 1056 1057 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po); 1058 gmii_po |= GMII_PO_LINK | 1059 GMII_PO_RX_FLOW | 1060 GMII_PO_TX_FLOW | 1061 GMII_PO_EN | 1062 GMII_PO_SPEED_2000M; 1063 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po); 1064 } 1065 } 1066 1067 /* Re-negotiate EEE if it was enabled already */ 1068 p->eee_enabled = b53_eee_init(ds, port, phydev); 1069 } 1070 1071 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 1072 { 1073 return 0; 1074 } 1075 EXPORT_SYMBOL(b53_vlan_filtering); 1076 1077 int b53_vlan_prepare(struct dsa_switch *ds, int port, 1078 const struct switchdev_obj_port_vlan *vlan) 1079 { 1080 struct b53_device *dev = ds->priv; 1081 1082 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 1083 return -EOPNOTSUPP; 1084 1085 if (vlan->vid_end > dev->num_vlans) 1086 return -ERANGE; 1087 1088 b53_enable_vlan(dev, true); 1089 1090 return 0; 1091 } 1092 EXPORT_SYMBOL(b53_vlan_prepare); 1093 1094 void b53_vlan_add(struct dsa_switch *ds, int port, 1095 const struct switchdev_obj_port_vlan *vlan) 1096 { 1097 struct b53_device *dev = ds->priv; 1098 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1099 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1100 struct b53_vlan *vl; 1101 u16 vid; 1102 1103 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1104 vl = &dev->vlans[vid]; 1105 1106 b53_get_vlan_entry(dev, vid, vl); 1107 1108 vl->members |= BIT(port); 1109 if (untagged) 1110 vl->untag |= BIT(port); 1111 else 1112 vl->untag &= ~BIT(port); 1113 1114 b53_set_vlan_entry(dev, vid, vl); 1115 b53_fast_age_vlan(dev, vid); 1116 } 1117 1118 if (pvid) { 1119 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1120 vlan->vid_end); 1121 b53_fast_age_vlan(dev, vid); 1122 } 1123 } 1124 EXPORT_SYMBOL(b53_vlan_add); 1125 1126 int b53_vlan_del(struct dsa_switch *ds, int port, 1127 const struct switchdev_obj_port_vlan *vlan) 1128 { 1129 struct b53_device *dev = ds->priv; 1130 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1131 struct b53_vlan *vl; 1132 u16 vid; 1133 u16 pvid; 1134 1135 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1136 1137 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1138 vl = &dev->vlans[vid]; 1139 1140 b53_get_vlan_entry(dev, vid, vl); 1141 1142 vl->members &= ~BIT(port); 1143 1144 if (pvid == vid) { 1145 if (is5325(dev) || is5365(dev)) 1146 pvid = 1; 1147 else 1148 pvid = 0; 1149 } 1150 1151 if (untagged) 1152 vl->untag &= ~(BIT(port)); 1153 1154 b53_set_vlan_entry(dev, vid, vl); 1155 b53_fast_age_vlan(dev, vid); 1156 } 1157 1158 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1159 b53_fast_age_vlan(dev, pvid); 1160 1161 return 0; 1162 } 1163 EXPORT_SYMBOL(b53_vlan_del); 1164 1165 /* Address Resolution Logic routines */ 1166 static int b53_arl_op_wait(struct b53_device *dev) 1167 { 1168 unsigned int timeout = 10; 1169 u8 reg; 1170 1171 do { 1172 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1173 if (!(reg & ARLTBL_START_DONE)) 1174 return 0; 1175 1176 usleep_range(1000, 2000); 1177 } while (timeout--); 1178 1179 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1180 1181 return -ETIMEDOUT; 1182 } 1183 1184 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1185 { 1186 u8 reg; 1187 1188 if (op > ARLTBL_RW) 1189 return -EINVAL; 1190 1191 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1192 reg |= ARLTBL_START_DONE; 1193 if (op) 1194 reg |= ARLTBL_RW; 1195 else 1196 reg &= ~ARLTBL_RW; 1197 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1198 1199 return b53_arl_op_wait(dev); 1200 } 1201 1202 static int b53_arl_read(struct b53_device *dev, u64 mac, 1203 u16 vid, struct b53_arl_entry *ent, u8 *idx, 1204 bool is_valid) 1205 { 1206 unsigned int i; 1207 int ret; 1208 1209 ret = b53_arl_op_wait(dev); 1210 if (ret) 1211 return ret; 1212 1213 /* Read the bins */ 1214 for (i = 0; i < dev->num_arl_entries; i++) { 1215 u64 mac_vid; 1216 u32 fwd_entry; 1217 1218 b53_read64(dev, B53_ARLIO_PAGE, 1219 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1220 b53_read32(dev, B53_ARLIO_PAGE, 1221 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1222 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1223 1224 if (!(fwd_entry & ARLTBL_VALID)) 1225 continue; 1226 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1227 continue; 1228 *idx = i; 1229 } 1230 1231 return -ENOENT; 1232 } 1233 1234 static int b53_arl_op(struct b53_device *dev, int op, int port, 1235 const unsigned char *addr, u16 vid, bool is_valid) 1236 { 1237 struct b53_arl_entry ent; 1238 u32 fwd_entry; 1239 u64 mac, mac_vid = 0; 1240 u8 idx = 0; 1241 int ret; 1242 1243 /* Convert the array into a 64-bit MAC */ 1244 mac = ether_addr_to_u64(addr); 1245 1246 /* Perform a read for the given MAC and VID */ 1247 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1248 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1249 1250 /* Issue a read operation for this MAC */ 1251 ret = b53_arl_rw_op(dev, 1); 1252 if (ret) 1253 return ret; 1254 1255 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid); 1256 /* If this is a read, just finish now */ 1257 if (op) 1258 return ret; 1259 1260 /* We could not find a matching MAC, so reset to a new entry */ 1261 if (ret) { 1262 fwd_entry = 0; 1263 idx = 1; 1264 } 1265 1266 memset(&ent, 0, sizeof(ent)); 1267 ent.port = port; 1268 ent.is_valid = is_valid; 1269 ent.vid = vid; 1270 ent.is_static = true; 1271 memcpy(ent.mac, addr, ETH_ALEN); 1272 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1273 1274 b53_write64(dev, B53_ARLIO_PAGE, 1275 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1276 b53_write32(dev, B53_ARLIO_PAGE, 1277 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1278 1279 return b53_arl_rw_op(dev, 0); 1280 } 1281 1282 int b53_fdb_add(struct dsa_switch *ds, int port, 1283 const unsigned char *addr, u16 vid) 1284 { 1285 struct b53_device *priv = ds->priv; 1286 1287 /* 5325 and 5365 require some more massaging, but could 1288 * be supported eventually 1289 */ 1290 if (is5325(priv) || is5365(priv)) 1291 return -EOPNOTSUPP; 1292 1293 return b53_arl_op(priv, 0, port, addr, vid, true); 1294 } 1295 EXPORT_SYMBOL(b53_fdb_add); 1296 1297 int b53_fdb_del(struct dsa_switch *ds, int port, 1298 const unsigned char *addr, u16 vid) 1299 { 1300 struct b53_device *priv = ds->priv; 1301 1302 return b53_arl_op(priv, 0, port, addr, vid, false); 1303 } 1304 EXPORT_SYMBOL(b53_fdb_del); 1305 1306 static int b53_arl_search_wait(struct b53_device *dev) 1307 { 1308 unsigned int timeout = 1000; 1309 u8 reg; 1310 1311 do { 1312 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1313 if (!(reg & ARL_SRCH_STDN)) 1314 return 0; 1315 1316 if (reg & ARL_SRCH_VLID) 1317 return 0; 1318 1319 usleep_range(1000, 2000); 1320 } while (timeout--); 1321 1322 return -ETIMEDOUT; 1323 } 1324 1325 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1326 struct b53_arl_entry *ent) 1327 { 1328 u64 mac_vid; 1329 u32 fwd_entry; 1330 1331 b53_read64(dev, B53_ARLIO_PAGE, 1332 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1333 b53_read32(dev, B53_ARLIO_PAGE, 1334 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1335 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1336 } 1337 1338 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1339 dsa_fdb_dump_cb_t *cb, void *data) 1340 { 1341 if (!ent->is_valid) 1342 return 0; 1343 1344 if (port != ent->port) 1345 return 0; 1346 1347 return cb(ent->mac, ent->vid, ent->is_static, data); 1348 } 1349 1350 int b53_fdb_dump(struct dsa_switch *ds, int port, 1351 dsa_fdb_dump_cb_t *cb, void *data) 1352 { 1353 struct b53_device *priv = ds->priv; 1354 struct b53_arl_entry results[2]; 1355 unsigned int count = 0; 1356 int ret; 1357 u8 reg; 1358 1359 /* Start search operation */ 1360 reg = ARL_SRCH_STDN; 1361 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1362 1363 do { 1364 ret = b53_arl_search_wait(priv); 1365 if (ret) 1366 return ret; 1367 1368 b53_arl_search_rd(priv, 0, &results[0]); 1369 ret = b53_fdb_copy(port, &results[0], cb, data); 1370 if (ret) 1371 return ret; 1372 1373 if (priv->num_arl_entries > 2) { 1374 b53_arl_search_rd(priv, 1, &results[1]); 1375 ret = b53_fdb_copy(port, &results[1], cb, data); 1376 if (ret) 1377 return ret; 1378 1379 if (!results[0].is_valid && !results[1].is_valid) 1380 break; 1381 } 1382 1383 } while (count++ < 1024); 1384 1385 return 0; 1386 } 1387 EXPORT_SYMBOL(b53_fdb_dump); 1388 1389 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1390 { 1391 struct b53_device *dev = ds->priv; 1392 s8 cpu_port = ds->ports[port].cpu_dp->index; 1393 u16 pvlan, reg; 1394 unsigned int i; 1395 1396 /* Make this port leave the all VLANs join since we will have proper 1397 * VLAN entries from now on 1398 */ 1399 if (is58xx(dev)) { 1400 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1401 reg &= ~BIT(port); 1402 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1403 reg &= ~BIT(cpu_port); 1404 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1405 } 1406 1407 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1408 1409 b53_for_each_port(dev, i) { 1410 if (dsa_to_port(ds, i)->bridge_dev != br) 1411 continue; 1412 1413 /* Add this local port to the remote port VLAN control 1414 * membership and update the remote port bitmask 1415 */ 1416 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1417 reg |= BIT(port); 1418 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1419 dev->ports[i].vlan_ctl_mask = reg; 1420 1421 pvlan |= BIT(i); 1422 } 1423 1424 /* Configure the local port VLAN control membership to include 1425 * remote ports and update the local port bitmask 1426 */ 1427 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1428 dev->ports[port].vlan_ctl_mask = pvlan; 1429 1430 return 0; 1431 } 1432 EXPORT_SYMBOL(b53_br_join); 1433 1434 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1435 { 1436 struct b53_device *dev = ds->priv; 1437 struct b53_vlan *vl = &dev->vlans[0]; 1438 s8 cpu_port = ds->ports[port].cpu_dp->index; 1439 unsigned int i; 1440 u16 pvlan, reg, pvid; 1441 1442 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1443 1444 b53_for_each_port(dev, i) { 1445 /* Don't touch the remaining ports */ 1446 if (dsa_to_port(ds, i)->bridge_dev != br) 1447 continue; 1448 1449 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1450 reg &= ~BIT(port); 1451 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1452 dev->ports[port].vlan_ctl_mask = reg; 1453 1454 /* Prevent self removal to preserve isolation */ 1455 if (port != i) 1456 pvlan &= ~BIT(i); 1457 } 1458 1459 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1460 dev->ports[port].vlan_ctl_mask = pvlan; 1461 1462 if (is5325(dev) || is5365(dev)) 1463 pvid = 1; 1464 else 1465 pvid = 0; 1466 1467 /* Make this port join all VLANs without VLAN entries */ 1468 if (is58xx(dev)) { 1469 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1470 reg |= BIT(port); 1471 if (!(reg & BIT(cpu_port))) 1472 reg |= BIT(cpu_port); 1473 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1474 } else { 1475 b53_get_vlan_entry(dev, pvid, vl); 1476 vl->members |= BIT(port) | BIT(cpu_port); 1477 vl->untag |= BIT(port) | BIT(cpu_port); 1478 b53_set_vlan_entry(dev, pvid, vl); 1479 } 1480 } 1481 EXPORT_SYMBOL(b53_br_leave); 1482 1483 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1484 { 1485 struct b53_device *dev = ds->priv; 1486 u8 hw_state; 1487 u8 reg; 1488 1489 switch (state) { 1490 case BR_STATE_DISABLED: 1491 hw_state = PORT_CTRL_DIS_STATE; 1492 break; 1493 case BR_STATE_LISTENING: 1494 hw_state = PORT_CTRL_LISTEN_STATE; 1495 break; 1496 case BR_STATE_LEARNING: 1497 hw_state = PORT_CTRL_LEARN_STATE; 1498 break; 1499 case BR_STATE_FORWARDING: 1500 hw_state = PORT_CTRL_FWD_STATE; 1501 break; 1502 case BR_STATE_BLOCKING: 1503 hw_state = PORT_CTRL_BLOCK_STATE; 1504 break; 1505 default: 1506 dev_err(ds->dev, "invalid STP state: %d\n", state); 1507 return; 1508 } 1509 1510 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1511 reg &= ~PORT_CTRL_STP_STATE_MASK; 1512 reg |= hw_state; 1513 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1514 } 1515 EXPORT_SYMBOL(b53_br_set_stp_state); 1516 1517 void b53_br_fast_age(struct dsa_switch *ds, int port) 1518 { 1519 struct b53_device *dev = ds->priv; 1520 1521 if (b53_fast_age_port(dev, port)) 1522 dev_err(ds->dev, "fast ageing failed\n"); 1523 } 1524 EXPORT_SYMBOL(b53_br_fast_age); 1525 1526 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 1527 { 1528 /* Broadcom switches will accept enabling Broadcom tags on the 1529 * following ports: 5, 7 and 8, any other port is not supported 1530 */ 1531 switch (port) { 1532 case B53_CPU_PORT_25: 1533 case 7: 1534 case B53_CPU_PORT: 1535 return true; 1536 } 1537 1538 return false; 1539 } 1540 1541 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port) 1542 { 1543 bool ret = b53_possible_cpu_port(ds, port); 1544 1545 if (!ret) 1546 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 1547 port); 1548 return ret; 1549 } 1550 1551 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port) 1552 { 1553 struct b53_device *dev = ds->priv; 1554 1555 /* Older models (5325, 5365) support a different tag format that we do 1556 * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed 1557 * mode to be turned on which means we need to specifically manage ARL 1558 * misses on multicast addresses (TBD). 1559 */ 1560 if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) || 1561 !b53_can_enable_brcm_tags(ds, port)) 1562 return DSA_TAG_PROTO_NONE; 1563 1564 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 1565 * which requires us to use the prepended Broadcom tag type 1566 */ 1567 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) 1568 return DSA_TAG_PROTO_BRCM_PREPEND; 1569 1570 return DSA_TAG_PROTO_BRCM; 1571 } 1572 EXPORT_SYMBOL(b53_get_tag_protocol); 1573 1574 int b53_mirror_add(struct dsa_switch *ds, int port, 1575 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1576 { 1577 struct b53_device *dev = ds->priv; 1578 u16 reg, loc; 1579 1580 if (ingress) 1581 loc = B53_IG_MIR_CTL; 1582 else 1583 loc = B53_EG_MIR_CTL; 1584 1585 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1586 reg &= ~MIRROR_MASK; 1587 reg |= BIT(port); 1588 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1589 1590 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1591 reg &= ~CAP_PORT_MASK; 1592 reg |= mirror->to_local_port; 1593 reg |= MIRROR_EN; 1594 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1595 1596 return 0; 1597 } 1598 EXPORT_SYMBOL(b53_mirror_add); 1599 1600 void b53_mirror_del(struct dsa_switch *ds, int port, 1601 struct dsa_mall_mirror_tc_entry *mirror) 1602 { 1603 struct b53_device *dev = ds->priv; 1604 bool loc_disable = false, other_loc_disable = false; 1605 u16 reg, loc; 1606 1607 if (mirror->ingress) 1608 loc = B53_IG_MIR_CTL; 1609 else 1610 loc = B53_EG_MIR_CTL; 1611 1612 /* Update the desired ingress/egress register */ 1613 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1614 reg &= ~BIT(port); 1615 if (!(reg & MIRROR_MASK)) 1616 loc_disable = true; 1617 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1618 1619 /* Now look at the other one to know if we can disable mirroring 1620 * entirely 1621 */ 1622 if (mirror->ingress) 1623 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 1624 else 1625 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 1626 if (!(reg & MIRROR_MASK)) 1627 other_loc_disable = true; 1628 1629 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1630 /* Both no longer have ports, let's disable mirroring */ 1631 if (loc_disable && other_loc_disable) { 1632 reg &= ~MIRROR_EN; 1633 reg &= ~mirror->to_local_port; 1634 } 1635 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1636 } 1637 EXPORT_SYMBOL(b53_mirror_del); 1638 1639 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 1640 { 1641 struct b53_device *dev = ds->priv; 1642 u16 reg; 1643 1644 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 1645 if (enable) 1646 reg |= BIT(port); 1647 else 1648 reg &= ~BIT(port); 1649 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 1650 } 1651 EXPORT_SYMBOL(b53_eee_enable_set); 1652 1653 1654 /* Returns 0 if EEE was not enabled, or 1 otherwise 1655 */ 1656 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 1657 { 1658 int ret; 1659 1660 ret = phy_init_eee(phy, 0); 1661 if (ret) 1662 return 0; 1663 1664 b53_eee_enable_set(ds, port, true); 1665 1666 return 1; 1667 } 1668 EXPORT_SYMBOL(b53_eee_init); 1669 1670 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1671 { 1672 struct b53_device *dev = ds->priv; 1673 struct ethtool_eee *p = &dev->ports[port].eee; 1674 u16 reg; 1675 1676 if (is5325(dev) || is5365(dev)) 1677 return -EOPNOTSUPP; 1678 1679 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 1680 e->eee_enabled = p->eee_enabled; 1681 e->eee_active = !!(reg & BIT(port)); 1682 1683 return 0; 1684 } 1685 EXPORT_SYMBOL(b53_get_mac_eee); 1686 1687 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1688 { 1689 struct b53_device *dev = ds->priv; 1690 struct ethtool_eee *p = &dev->ports[port].eee; 1691 1692 if (is5325(dev) || is5365(dev)) 1693 return -EOPNOTSUPP; 1694 1695 p->eee_enabled = e->eee_enabled; 1696 b53_eee_enable_set(ds, port, e->eee_enabled); 1697 1698 return 0; 1699 } 1700 EXPORT_SYMBOL(b53_set_mac_eee); 1701 1702 static const struct dsa_switch_ops b53_switch_ops = { 1703 .get_tag_protocol = b53_get_tag_protocol, 1704 .setup = b53_setup, 1705 .get_strings = b53_get_strings, 1706 .get_ethtool_stats = b53_get_ethtool_stats, 1707 .get_sset_count = b53_get_sset_count, 1708 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1709 .phy_read = b53_phy_read16, 1710 .phy_write = b53_phy_write16, 1711 .adjust_link = b53_adjust_link, 1712 .port_enable = b53_enable_port, 1713 .port_disable = b53_disable_port, 1714 .get_mac_eee = b53_get_mac_eee, 1715 .set_mac_eee = b53_set_mac_eee, 1716 .port_bridge_join = b53_br_join, 1717 .port_bridge_leave = b53_br_leave, 1718 .port_stp_state_set = b53_br_set_stp_state, 1719 .port_fast_age = b53_br_fast_age, 1720 .port_vlan_filtering = b53_vlan_filtering, 1721 .port_vlan_prepare = b53_vlan_prepare, 1722 .port_vlan_add = b53_vlan_add, 1723 .port_vlan_del = b53_vlan_del, 1724 .port_fdb_dump = b53_fdb_dump, 1725 .port_fdb_add = b53_fdb_add, 1726 .port_fdb_del = b53_fdb_del, 1727 .port_mirror_add = b53_mirror_add, 1728 .port_mirror_del = b53_mirror_del, 1729 }; 1730 1731 struct b53_chip_data { 1732 u32 chip_id; 1733 const char *dev_name; 1734 u16 vlans; 1735 u16 enabled_ports; 1736 u8 cpu_port; 1737 u8 vta_regs[3]; 1738 u8 arl_entries; 1739 u8 duplex_reg; 1740 u8 jumbo_pm_reg; 1741 u8 jumbo_size_reg; 1742 }; 1743 1744 #define B53_VTA_REGS \ 1745 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 1746 #define B53_VTA_REGS_9798 \ 1747 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 1748 #define B53_VTA_REGS_63XX \ 1749 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 1750 1751 static const struct b53_chip_data b53_switch_chips[] = { 1752 { 1753 .chip_id = BCM5325_DEVICE_ID, 1754 .dev_name = "BCM5325", 1755 .vlans = 16, 1756 .enabled_ports = 0x1f, 1757 .arl_entries = 2, 1758 .cpu_port = B53_CPU_PORT_25, 1759 .duplex_reg = B53_DUPLEX_STAT_FE, 1760 }, 1761 { 1762 .chip_id = BCM5365_DEVICE_ID, 1763 .dev_name = "BCM5365", 1764 .vlans = 256, 1765 .enabled_ports = 0x1f, 1766 .arl_entries = 2, 1767 .cpu_port = B53_CPU_PORT_25, 1768 .duplex_reg = B53_DUPLEX_STAT_FE, 1769 }, 1770 { 1771 .chip_id = BCM5395_DEVICE_ID, 1772 .dev_name = "BCM5395", 1773 .vlans = 4096, 1774 .enabled_ports = 0x1f, 1775 .arl_entries = 4, 1776 .cpu_port = B53_CPU_PORT, 1777 .vta_regs = B53_VTA_REGS, 1778 .duplex_reg = B53_DUPLEX_STAT_GE, 1779 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1780 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1781 }, 1782 { 1783 .chip_id = BCM5397_DEVICE_ID, 1784 .dev_name = "BCM5397", 1785 .vlans = 4096, 1786 .enabled_ports = 0x1f, 1787 .arl_entries = 4, 1788 .cpu_port = B53_CPU_PORT, 1789 .vta_regs = B53_VTA_REGS_9798, 1790 .duplex_reg = B53_DUPLEX_STAT_GE, 1791 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1792 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1793 }, 1794 { 1795 .chip_id = BCM5398_DEVICE_ID, 1796 .dev_name = "BCM5398", 1797 .vlans = 4096, 1798 .enabled_ports = 0x7f, 1799 .arl_entries = 4, 1800 .cpu_port = B53_CPU_PORT, 1801 .vta_regs = B53_VTA_REGS_9798, 1802 .duplex_reg = B53_DUPLEX_STAT_GE, 1803 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1804 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1805 }, 1806 { 1807 .chip_id = BCM53115_DEVICE_ID, 1808 .dev_name = "BCM53115", 1809 .vlans = 4096, 1810 .enabled_ports = 0x1f, 1811 .arl_entries = 4, 1812 .vta_regs = B53_VTA_REGS, 1813 .cpu_port = B53_CPU_PORT, 1814 .duplex_reg = B53_DUPLEX_STAT_GE, 1815 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1816 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1817 }, 1818 { 1819 .chip_id = BCM53125_DEVICE_ID, 1820 .dev_name = "BCM53125", 1821 .vlans = 4096, 1822 .enabled_ports = 0xff, 1823 .arl_entries = 4, 1824 .cpu_port = B53_CPU_PORT, 1825 .vta_regs = B53_VTA_REGS, 1826 .duplex_reg = B53_DUPLEX_STAT_GE, 1827 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1828 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1829 }, 1830 { 1831 .chip_id = BCM53128_DEVICE_ID, 1832 .dev_name = "BCM53128", 1833 .vlans = 4096, 1834 .enabled_ports = 0x1ff, 1835 .arl_entries = 4, 1836 .cpu_port = B53_CPU_PORT, 1837 .vta_regs = B53_VTA_REGS, 1838 .duplex_reg = B53_DUPLEX_STAT_GE, 1839 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1840 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1841 }, 1842 { 1843 .chip_id = BCM63XX_DEVICE_ID, 1844 .dev_name = "BCM63xx", 1845 .vlans = 4096, 1846 .enabled_ports = 0, /* pdata must provide them */ 1847 .arl_entries = 4, 1848 .cpu_port = B53_CPU_PORT, 1849 .vta_regs = B53_VTA_REGS_63XX, 1850 .duplex_reg = B53_DUPLEX_STAT_63XX, 1851 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 1852 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 1853 }, 1854 { 1855 .chip_id = BCM53010_DEVICE_ID, 1856 .dev_name = "BCM53010", 1857 .vlans = 4096, 1858 .enabled_ports = 0x1f, 1859 .arl_entries = 4, 1860 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1861 .vta_regs = B53_VTA_REGS, 1862 .duplex_reg = B53_DUPLEX_STAT_GE, 1863 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1864 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1865 }, 1866 { 1867 .chip_id = BCM53011_DEVICE_ID, 1868 .dev_name = "BCM53011", 1869 .vlans = 4096, 1870 .enabled_ports = 0x1bf, 1871 .arl_entries = 4, 1872 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1873 .vta_regs = B53_VTA_REGS, 1874 .duplex_reg = B53_DUPLEX_STAT_GE, 1875 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1876 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1877 }, 1878 { 1879 .chip_id = BCM53012_DEVICE_ID, 1880 .dev_name = "BCM53012", 1881 .vlans = 4096, 1882 .enabled_ports = 0x1bf, 1883 .arl_entries = 4, 1884 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1885 .vta_regs = B53_VTA_REGS, 1886 .duplex_reg = B53_DUPLEX_STAT_GE, 1887 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1888 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1889 }, 1890 { 1891 .chip_id = BCM53018_DEVICE_ID, 1892 .dev_name = "BCM53018", 1893 .vlans = 4096, 1894 .enabled_ports = 0x1f, 1895 .arl_entries = 4, 1896 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1897 .vta_regs = B53_VTA_REGS, 1898 .duplex_reg = B53_DUPLEX_STAT_GE, 1899 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1900 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1901 }, 1902 { 1903 .chip_id = BCM53019_DEVICE_ID, 1904 .dev_name = "BCM53019", 1905 .vlans = 4096, 1906 .enabled_ports = 0x1f, 1907 .arl_entries = 4, 1908 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1909 .vta_regs = B53_VTA_REGS, 1910 .duplex_reg = B53_DUPLEX_STAT_GE, 1911 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1912 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1913 }, 1914 { 1915 .chip_id = BCM58XX_DEVICE_ID, 1916 .dev_name = "BCM585xx/586xx/88312", 1917 .vlans = 4096, 1918 .enabled_ports = 0x1ff, 1919 .arl_entries = 4, 1920 .cpu_port = B53_CPU_PORT, 1921 .vta_regs = B53_VTA_REGS, 1922 .duplex_reg = B53_DUPLEX_STAT_GE, 1923 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1924 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1925 }, 1926 { 1927 .chip_id = BCM7445_DEVICE_ID, 1928 .dev_name = "BCM7445", 1929 .vlans = 4096, 1930 .enabled_ports = 0x1ff, 1931 .arl_entries = 4, 1932 .cpu_port = B53_CPU_PORT, 1933 .vta_regs = B53_VTA_REGS, 1934 .duplex_reg = B53_DUPLEX_STAT_GE, 1935 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1936 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1937 }, 1938 { 1939 .chip_id = BCM7278_DEVICE_ID, 1940 .dev_name = "BCM7278", 1941 .vlans = 4096, 1942 .enabled_ports = 0x1ff, 1943 .arl_entries= 4, 1944 .cpu_port = B53_CPU_PORT, 1945 .vta_regs = B53_VTA_REGS, 1946 .duplex_reg = B53_DUPLEX_STAT_GE, 1947 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1948 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1949 }, 1950 }; 1951 1952 static int b53_switch_init(struct b53_device *dev) 1953 { 1954 unsigned int i; 1955 int ret; 1956 1957 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 1958 const struct b53_chip_data *chip = &b53_switch_chips[i]; 1959 1960 if (chip->chip_id == dev->chip_id) { 1961 if (!dev->enabled_ports) 1962 dev->enabled_ports = chip->enabled_ports; 1963 dev->name = chip->dev_name; 1964 dev->duplex_reg = chip->duplex_reg; 1965 dev->vta_regs[0] = chip->vta_regs[0]; 1966 dev->vta_regs[1] = chip->vta_regs[1]; 1967 dev->vta_regs[2] = chip->vta_regs[2]; 1968 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 1969 dev->cpu_port = chip->cpu_port; 1970 dev->num_vlans = chip->vlans; 1971 dev->num_arl_entries = chip->arl_entries; 1972 break; 1973 } 1974 } 1975 1976 /* check which BCM5325x version we have */ 1977 if (is5325(dev)) { 1978 u8 vc4; 1979 1980 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 1981 1982 /* check reserved bits */ 1983 switch (vc4 & 3) { 1984 case 1: 1985 /* BCM5325E */ 1986 break; 1987 case 3: 1988 /* BCM5325F - do not use port 4 */ 1989 dev->enabled_ports &= ~BIT(4); 1990 break; 1991 default: 1992 /* On the BCM47XX SoCs this is the supported internal switch.*/ 1993 #ifndef CONFIG_BCM47XX 1994 /* BCM5325M */ 1995 return -EINVAL; 1996 #else 1997 break; 1998 #endif 1999 } 2000 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2001 u64 strap_value; 2002 2003 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2004 /* use second IMP port if GMII is enabled */ 2005 if (strap_value & SV_GMII_CTRL_115) 2006 dev->cpu_port = 5; 2007 } 2008 2009 /* cpu port is always last */ 2010 dev->num_ports = dev->cpu_port + 1; 2011 dev->enabled_ports |= BIT(dev->cpu_port); 2012 2013 /* Include non standard CPU port built-in PHYs to be probed */ 2014 if (is539x(dev) || is531x5(dev)) { 2015 for (i = 0; i < dev->num_ports; i++) { 2016 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2017 !b53_possible_cpu_port(dev->ds, i)) 2018 dev->ds->phys_mii_mask |= BIT(i); 2019 } 2020 } 2021 2022 dev->ports = devm_kzalloc(dev->dev, 2023 sizeof(struct b53_port) * dev->num_ports, 2024 GFP_KERNEL); 2025 if (!dev->ports) 2026 return -ENOMEM; 2027 2028 dev->vlans = devm_kzalloc(dev->dev, 2029 sizeof(struct b53_vlan) * dev->num_vlans, 2030 GFP_KERNEL); 2031 if (!dev->vlans) 2032 return -ENOMEM; 2033 2034 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2035 if (dev->reset_gpio >= 0) { 2036 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2037 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2038 if (ret) 2039 return ret; 2040 } 2041 2042 return 0; 2043 } 2044 2045 struct b53_device *b53_switch_alloc(struct device *base, 2046 const struct b53_io_ops *ops, 2047 void *priv) 2048 { 2049 struct dsa_switch *ds; 2050 struct b53_device *dev; 2051 2052 ds = dsa_switch_alloc(base, DSA_MAX_PORTS); 2053 if (!ds) 2054 return NULL; 2055 2056 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2057 if (!dev) 2058 return NULL; 2059 2060 ds->priv = dev; 2061 dev->dev = base; 2062 2063 dev->ds = ds; 2064 dev->priv = priv; 2065 dev->ops = ops; 2066 ds->ops = &b53_switch_ops; 2067 mutex_init(&dev->reg_mutex); 2068 mutex_init(&dev->stats_mutex); 2069 2070 return dev; 2071 } 2072 EXPORT_SYMBOL(b53_switch_alloc); 2073 2074 int b53_switch_detect(struct b53_device *dev) 2075 { 2076 u32 id32; 2077 u16 tmp; 2078 u8 id8; 2079 int ret; 2080 2081 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2082 if (ret) 2083 return ret; 2084 2085 switch (id8) { 2086 case 0: 2087 /* BCM5325 and BCM5365 do not have this register so reads 2088 * return 0. But the read operation did succeed, so assume this 2089 * is one of them. 2090 * 2091 * Next check if we can write to the 5325's VTA register; for 2092 * 5365 it is read only. 2093 */ 2094 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2095 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2096 2097 if (tmp == 0xf) 2098 dev->chip_id = BCM5325_DEVICE_ID; 2099 else 2100 dev->chip_id = BCM5365_DEVICE_ID; 2101 break; 2102 case BCM5395_DEVICE_ID: 2103 case BCM5397_DEVICE_ID: 2104 case BCM5398_DEVICE_ID: 2105 dev->chip_id = id8; 2106 break; 2107 default: 2108 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2109 if (ret) 2110 return ret; 2111 2112 switch (id32) { 2113 case BCM53115_DEVICE_ID: 2114 case BCM53125_DEVICE_ID: 2115 case BCM53128_DEVICE_ID: 2116 case BCM53010_DEVICE_ID: 2117 case BCM53011_DEVICE_ID: 2118 case BCM53012_DEVICE_ID: 2119 case BCM53018_DEVICE_ID: 2120 case BCM53019_DEVICE_ID: 2121 dev->chip_id = id32; 2122 break; 2123 default: 2124 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 2125 id8, id32); 2126 return -ENODEV; 2127 } 2128 } 2129 2130 if (dev->chip_id == BCM5325_DEVICE_ID) 2131 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2132 &dev->core_rev); 2133 else 2134 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2135 &dev->core_rev); 2136 } 2137 EXPORT_SYMBOL(b53_switch_detect); 2138 2139 int b53_switch_register(struct b53_device *dev) 2140 { 2141 int ret; 2142 2143 if (dev->pdata) { 2144 dev->chip_id = dev->pdata->chip_id; 2145 dev->enabled_ports = dev->pdata->enabled_ports; 2146 } 2147 2148 if (!dev->chip_id && b53_switch_detect(dev)) 2149 return -EINVAL; 2150 2151 ret = b53_switch_init(dev); 2152 if (ret) 2153 return ret; 2154 2155 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 2156 2157 return dsa_register_switch(dev->ds); 2158 } 2159 EXPORT_SYMBOL(b53_switch_register); 2160 2161 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2162 MODULE_DESCRIPTION("B53 switch library"); 2163 MODULE_LICENSE("Dual BSD/GPL"); 2164