1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <net/dsa.h> 31 32 #include "b53_regs.h" 33 #include "b53_priv.h" 34 35 struct b53_mib_desc { 36 u8 size; 37 u8 offset; 38 const char *name; 39 }; 40 41 /* BCM5365 MIB counters */ 42 static const struct b53_mib_desc b53_mibs_65[] = { 43 { 8, 0x00, "TxOctets" }, 44 { 4, 0x08, "TxDropPkts" }, 45 { 4, 0x10, "TxBroadcastPkts" }, 46 { 4, 0x14, "TxMulticastPkts" }, 47 { 4, 0x18, "TxUnicastPkts" }, 48 { 4, 0x1c, "TxCollisions" }, 49 { 4, 0x20, "TxSingleCollision" }, 50 { 4, 0x24, "TxMultipleCollision" }, 51 { 4, 0x28, "TxDeferredTransmit" }, 52 { 4, 0x2c, "TxLateCollision" }, 53 { 4, 0x30, "TxExcessiveCollision" }, 54 { 4, 0x38, "TxPausePkts" }, 55 { 8, 0x44, "RxOctets" }, 56 { 4, 0x4c, "RxUndersizePkts" }, 57 { 4, 0x50, "RxPausePkts" }, 58 { 4, 0x54, "Pkts64Octets" }, 59 { 4, 0x58, "Pkts65to127Octets" }, 60 { 4, 0x5c, "Pkts128to255Octets" }, 61 { 4, 0x60, "Pkts256to511Octets" }, 62 { 4, 0x64, "Pkts512to1023Octets" }, 63 { 4, 0x68, "Pkts1024to1522Octets" }, 64 { 4, 0x6c, "RxOversizePkts" }, 65 { 4, 0x70, "RxJabbers" }, 66 { 4, 0x74, "RxAlignmentErrors" }, 67 { 4, 0x78, "RxFCSErrors" }, 68 { 8, 0x7c, "RxGoodOctets" }, 69 { 4, 0x84, "RxDropPkts" }, 70 { 4, 0x88, "RxUnicastPkts" }, 71 { 4, 0x8c, "RxMulticastPkts" }, 72 { 4, 0x90, "RxBroadcastPkts" }, 73 { 4, 0x94, "RxSAChanges" }, 74 { 4, 0x98, "RxFragments" }, 75 }; 76 77 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 78 79 /* BCM63xx MIB counters */ 80 static const struct b53_mib_desc b53_mibs_63xx[] = { 81 { 8, 0x00, "TxOctets" }, 82 { 4, 0x08, "TxDropPkts" }, 83 { 4, 0x0c, "TxQoSPkts" }, 84 { 4, 0x10, "TxBroadcastPkts" }, 85 { 4, 0x14, "TxMulticastPkts" }, 86 { 4, 0x18, "TxUnicastPkts" }, 87 { 4, 0x1c, "TxCollisions" }, 88 { 4, 0x20, "TxSingleCollision" }, 89 { 4, 0x24, "TxMultipleCollision" }, 90 { 4, 0x28, "TxDeferredTransmit" }, 91 { 4, 0x2c, "TxLateCollision" }, 92 { 4, 0x30, "TxExcessiveCollision" }, 93 { 4, 0x38, "TxPausePkts" }, 94 { 8, 0x3c, "TxQoSOctets" }, 95 { 8, 0x44, "RxOctets" }, 96 { 4, 0x4c, "RxUndersizePkts" }, 97 { 4, 0x50, "RxPausePkts" }, 98 { 4, 0x54, "Pkts64Octets" }, 99 { 4, 0x58, "Pkts65to127Octets" }, 100 { 4, 0x5c, "Pkts128to255Octets" }, 101 { 4, 0x60, "Pkts256to511Octets" }, 102 { 4, 0x64, "Pkts512to1023Octets" }, 103 { 4, 0x68, "Pkts1024to1522Octets" }, 104 { 4, 0x6c, "RxOversizePkts" }, 105 { 4, 0x70, "RxJabbers" }, 106 { 4, 0x74, "RxAlignmentErrors" }, 107 { 4, 0x78, "RxFCSErrors" }, 108 { 8, 0x7c, "RxGoodOctets" }, 109 { 4, 0x84, "RxDropPkts" }, 110 { 4, 0x88, "RxUnicastPkts" }, 111 { 4, 0x8c, "RxMulticastPkts" }, 112 { 4, 0x90, "RxBroadcastPkts" }, 113 { 4, 0x94, "RxSAChanges" }, 114 { 4, 0x98, "RxFragments" }, 115 { 4, 0xa0, "RxSymbolErrors" }, 116 { 4, 0xa4, "RxQoSPkts" }, 117 { 8, 0xa8, "RxQoSOctets" }, 118 { 4, 0xb0, "Pkts1523to2047Octets" }, 119 { 4, 0xb4, "Pkts2048to4095Octets" }, 120 { 4, 0xb8, "Pkts4096to8191Octets" }, 121 { 4, 0xbc, "Pkts8192to9728Octets" }, 122 { 4, 0xc0, "RxDiscarded" }, 123 }; 124 125 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 126 127 /* MIB counters */ 128 static const struct b53_mib_desc b53_mibs[] = { 129 { 8, 0x00, "TxOctets" }, 130 { 4, 0x08, "TxDropPkts" }, 131 { 4, 0x10, "TxBroadcastPkts" }, 132 { 4, 0x14, "TxMulticastPkts" }, 133 { 4, 0x18, "TxUnicastPkts" }, 134 { 4, 0x1c, "TxCollisions" }, 135 { 4, 0x20, "TxSingleCollision" }, 136 { 4, 0x24, "TxMultipleCollision" }, 137 { 4, 0x28, "TxDeferredTransmit" }, 138 { 4, 0x2c, "TxLateCollision" }, 139 { 4, 0x30, "TxExcessiveCollision" }, 140 { 4, 0x38, "TxPausePkts" }, 141 { 8, 0x50, "RxOctets" }, 142 { 4, 0x58, "RxUndersizePkts" }, 143 { 4, 0x5c, "RxPausePkts" }, 144 { 4, 0x60, "Pkts64Octets" }, 145 { 4, 0x64, "Pkts65to127Octets" }, 146 { 4, 0x68, "Pkts128to255Octets" }, 147 { 4, 0x6c, "Pkts256to511Octets" }, 148 { 4, 0x70, "Pkts512to1023Octets" }, 149 { 4, 0x74, "Pkts1024to1522Octets" }, 150 { 4, 0x78, "RxOversizePkts" }, 151 { 4, 0x7c, "RxJabbers" }, 152 { 4, 0x80, "RxAlignmentErrors" }, 153 { 4, 0x84, "RxFCSErrors" }, 154 { 8, 0x88, "RxGoodOctets" }, 155 { 4, 0x90, "RxDropPkts" }, 156 { 4, 0x94, "RxUnicastPkts" }, 157 { 4, 0x98, "RxMulticastPkts" }, 158 { 4, 0x9c, "RxBroadcastPkts" }, 159 { 4, 0xa0, "RxSAChanges" }, 160 { 4, 0xa4, "RxFragments" }, 161 { 4, 0xa8, "RxJumboPkts" }, 162 { 4, 0xac, "RxSymbolErrors" }, 163 { 4, 0xc0, "RxDiscarded" }, 164 }; 165 166 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 167 168 static const struct b53_mib_desc b53_mibs_58xx[] = { 169 { 8, 0x00, "TxOctets" }, 170 { 4, 0x08, "TxDropPkts" }, 171 { 4, 0x0c, "TxQPKTQ0" }, 172 { 4, 0x10, "TxBroadcastPkts" }, 173 { 4, 0x14, "TxMulticastPkts" }, 174 { 4, 0x18, "TxUnicastPKts" }, 175 { 4, 0x1c, "TxCollisions" }, 176 { 4, 0x20, "TxSingleCollision" }, 177 { 4, 0x24, "TxMultipleCollision" }, 178 { 4, 0x28, "TxDeferredCollision" }, 179 { 4, 0x2c, "TxLateCollision" }, 180 { 4, 0x30, "TxExcessiveCollision" }, 181 { 4, 0x34, "TxFrameInDisc" }, 182 { 4, 0x38, "TxPausePkts" }, 183 { 4, 0x3c, "TxQPKTQ1" }, 184 { 4, 0x40, "TxQPKTQ2" }, 185 { 4, 0x44, "TxQPKTQ3" }, 186 { 4, 0x48, "TxQPKTQ4" }, 187 { 4, 0x4c, "TxQPKTQ5" }, 188 { 8, 0x50, "RxOctets" }, 189 { 4, 0x58, "RxUndersizePkts" }, 190 { 4, 0x5c, "RxPausePkts" }, 191 { 4, 0x60, "RxPkts64Octets" }, 192 { 4, 0x64, "RxPkts65to127Octets" }, 193 { 4, 0x68, "RxPkts128to255Octets" }, 194 { 4, 0x6c, "RxPkts256to511Octets" }, 195 { 4, 0x70, "RxPkts512to1023Octets" }, 196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 197 { 4, 0x78, "RxOversizePkts" }, 198 { 4, 0x7c, "RxJabbers" }, 199 { 4, 0x80, "RxAlignmentErrors" }, 200 { 4, 0x84, "RxFCSErrors" }, 201 { 8, 0x88, "RxGoodOctets" }, 202 { 4, 0x90, "RxDropPkts" }, 203 { 4, 0x94, "RxUnicastPkts" }, 204 { 4, 0x98, "RxMulticastPkts" }, 205 { 4, 0x9c, "RxBroadcastPkts" }, 206 { 4, 0xa0, "RxSAChanges" }, 207 { 4, 0xa4, "RxFragments" }, 208 { 4, 0xa8, "RxJumboPkt" }, 209 { 4, 0xac, "RxSymblErr" }, 210 { 4, 0xb0, "InRangeErrCount" }, 211 { 4, 0xb4, "OutRangeErrCount" }, 212 { 4, 0xb8, "EEELpiEvent" }, 213 { 4, 0xbc, "EEELpiDuration" }, 214 { 4, 0xc0, "RxDiscard" }, 215 { 4, 0xc8, "TxQPKTQ6" }, 216 { 4, 0xcc, "TxQPKTQ7" }, 217 { 4, 0xd0, "TxPkts64Octets" }, 218 { 4, 0xd4, "TxPkts65to127Octets" }, 219 { 4, 0xd8, "TxPkts128to255Octets" }, 220 { 4, 0xdc, "TxPkts256to511Ocets" }, 221 { 4, 0xe0, "TxPkts512to1023Ocets" }, 222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 223 }; 224 225 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 226 227 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 228 { 229 unsigned int i; 230 231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 232 233 for (i = 0; i < 10; i++) { 234 u8 vta; 235 236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 237 if (!(vta & VTA_START_CMD)) 238 return 0; 239 240 usleep_range(100, 200); 241 } 242 243 return -EIO; 244 } 245 246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 247 struct b53_vlan *vlan) 248 { 249 if (is5325(dev)) { 250 u32 entry = 0; 251 252 if (vlan->members) { 253 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 254 VA_UNTAG_S_25) | vlan->members; 255 if (dev->core_rev >= 3) 256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 257 else 258 entry |= VA_VALID_25; 259 } 260 261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 263 VTA_RW_STATE_WR | VTA_RW_OP_EN); 264 } else if (is5365(dev)) { 265 u16 entry = 0; 266 267 if (vlan->members) 268 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 270 271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 273 VTA_RW_STATE_WR | VTA_RW_OP_EN); 274 } else { 275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 277 (vlan->untag << VTE_UNTAG_S) | vlan->members); 278 279 b53_do_vlan_op(dev, VTA_CMD_WRITE); 280 } 281 282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 283 vid, vlan->members, vlan->untag); 284 } 285 286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 287 struct b53_vlan *vlan) 288 { 289 if (is5325(dev)) { 290 u32 entry = 0; 291 292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 293 VTA_RW_STATE_RD | VTA_RW_OP_EN); 294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 295 296 if (dev->core_rev >= 3) 297 vlan->valid = !!(entry & VA_VALID_25_R4); 298 else 299 vlan->valid = !!(entry & VA_VALID_25); 300 vlan->members = entry & VA_MEMBER_MASK; 301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 302 303 } else if (is5365(dev)) { 304 u16 entry = 0; 305 306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 307 VTA_RW_STATE_WR | VTA_RW_OP_EN); 308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 309 310 vlan->valid = !!(entry & VA_VALID_65); 311 vlan->members = entry & VA_MEMBER_MASK; 312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 313 } else { 314 u32 entry = 0; 315 316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 317 b53_do_vlan_op(dev, VTA_CMD_READ); 318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 319 vlan->members = entry & VTE_MEMBERS; 320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 321 vlan->valid = true; 322 } 323 } 324 325 static void b53_set_forwarding(struct b53_device *dev, int enable) 326 { 327 u8 mgmt; 328 329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 330 331 if (enable) 332 mgmt |= SM_SW_FWD_EN; 333 else 334 mgmt &= ~SM_SW_FWD_EN; 335 336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 337 338 /* Include IMP port in dumb forwarding mode 339 */ 340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 341 mgmt |= B53_MII_DUMB_FWDG_EN; 342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 343 344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 345 * frames should be flooded or not. 346 */ 347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 350 } 351 352 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 353 bool enable_filtering) 354 { 355 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 356 357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 360 361 if (is5325(dev) || is5365(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 364 } else if (is63xx(dev)) { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 367 } else { 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 370 } 371 372 if (enable) { 373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 375 vc4 &= ~VC4_ING_VID_CHECK_MASK; 376 if (enable_filtering) { 377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 378 vc5 |= VC5_DROP_VTABLE_MISS; 379 } else { 380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 381 vc5 &= ~VC5_DROP_VTABLE_MISS; 382 } 383 384 if (is5325(dev)) 385 vc0 &= ~VC0_RESERVED_1; 386 387 if (is5325(dev) || is5365(dev)) 388 vc1 |= VC1_RX_MCST_TAG_EN; 389 390 } else { 391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 393 vc4 &= ~VC4_ING_VID_CHECK_MASK; 394 vc5 &= ~VC5_DROP_VTABLE_MISS; 395 396 if (is5325(dev) || is5365(dev)) 397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 398 else 399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 400 401 if (is5325(dev) || is5365(dev)) 402 vc1 &= ~VC1_RX_MCST_TAG_EN; 403 } 404 405 if (!is5325(dev) && !is5365(dev)) 406 vc5 &= ~VC5_VID_FFF_EN; 407 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 410 411 if (is5325(dev) || is5365(dev)) { 412 /* enable the high 8 bit vid check on 5325 */ 413 if (is5325(dev) && enable) 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 415 VC3_HIGH_8BIT_EN); 416 else 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 418 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 421 } else if (is63xx(dev)) { 422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 425 } else { 426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 429 } 430 431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 432 433 dev->vlan_enabled = enable; 434 435 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 436 port, enable, enable_filtering); 437 } 438 439 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 440 { 441 u32 port_mask = 0; 442 u16 max_size = JMS_MIN_SIZE; 443 444 if (is5325(dev) || is5365(dev)) 445 return -EINVAL; 446 447 if (enable) { 448 port_mask = dev->enabled_ports; 449 max_size = JMS_MAX_SIZE; 450 if (allow_10_100) 451 port_mask |= JPM_10_100_JUMBO_EN; 452 } 453 454 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 455 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 456 } 457 458 static int b53_flush_arl(struct b53_device *dev, u8 mask) 459 { 460 unsigned int i; 461 462 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 463 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 464 465 for (i = 0; i < 10; i++) { 466 u8 fast_age_ctrl; 467 468 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 469 &fast_age_ctrl); 470 471 if (!(fast_age_ctrl & FAST_AGE_DONE)) 472 goto out; 473 474 msleep(1); 475 } 476 477 return -ETIMEDOUT; 478 out: 479 /* Only age dynamic entries (default behavior) */ 480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 481 return 0; 482 } 483 484 static int b53_fast_age_port(struct b53_device *dev, int port) 485 { 486 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 487 488 return b53_flush_arl(dev, FAST_AGE_PORT); 489 } 490 491 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 492 { 493 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 494 495 return b53_flush_arl(dev, FAST_AGE_VLAN); 496 } 497 498 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 499 { 500 struct b53_device *dev = ds->priv; 501 unsigned int i; 502 u16 pvlan; 503 504 /* Enable the IMP port to be in the same VLAN as the other ports 505 * on a per-port basis such that we only have Port i and IMP in 506 * the same VLAN. 507 */ 508 b53_for_each_port(dev, i) { 509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 510 pvlan |= BIT(cpu_port); 511 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 512 } 513 } 514 EXPORT_SYMBOL(b53_imp_vlan_setup); 515 516 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 517 bool unicast) 518 { 519 u16 uc; 520 521 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 522 if (unicast) 523 uc |= BIT(port); 524 else 525 uc &= ~BIT(port); 526 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 527 } 528 529 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 530 bool multicast) 531 { 532 u16 mc; 533 534 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 535 if (multicast) 536 mc |= BIT(port); 537 else 538 mc &= ~BIT(port); 539 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 540 541 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 542 if (multicast) 543 mc |= BIT(port); 544 else 545 mc &= ~BIT(port); 546 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 547 } 548 549 static void b53_port_set_learning(struct b53_device *dev, int port, 550 bool learning) 551 { 552 u16 reg; 553 554 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 555 if (learning) 556 reg &= ~BIT(port); 557 else 558 reg |= BIT(port); 559 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 560 } 561 562 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 563 { 564 struct b53_device *dev = ds->priv; 565 unsigned int cpu_port; 566 int ret = 0; 567 u16 pvlan; 568 569 if (!dsa_is_user_port(ds, port)) 570 return 0; 571 572 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 573 574 b53_port_set_ucast_flood(dev, port, true); 575 b53_port_set_mcast_flood(dev, port, true); 576 b53_port_set_learning(dev, port, false); 577 578 if (dev->ops->irq_enable) 579 ret = dev->ops->irq_enable(dev, port); 580 if (ret) 581 return ret; 582 583 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 584 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 585 586 /* Set this port, and only this one to be in the default VLAN, 587 * if member of a bridge, restore its membership prior to 588 * bringing down this port. 589 */ 590 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 591 pvlan &= ~0x1ff; 592 pvlan |= BIT(port); 593 pvlan |= dev->ports[port].vlan_ctl_mask; 594 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 595 596 b53_imp_vlan_setup(ds, cpu_port); 597 598 /* If EEE was enabled, restore it */ 599 if (dev->ports[port].eee.eee_enabled) 600 b53_eee_enable_set(ds, port, true); 601 602 return 0; 603 } 604 EXPORT_SYMBOL(b53_enable_port); 605 606 void b53_disable_port(struct dsa_switch *ds, int port) 607 { 608 struct b53_device *dev = ds->priv; 609 u8 reg; 610 611 /* Disable Tx/Rx for the port */ 612 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 613 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 614 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 615 616 if (dev->ops->irq_disable) 617 dev->ops->irq_disable(dev, port); 618 } 619 EXPORT_SYMBOL(b53_disable_port); 620 621 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 622 { 623 struct b53_device *dev = ds->priv; 624 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 625 u8 hdr_ctl, val; 626 u16 reg; 627 628 /* Resolve which bit controls the Broadcom tag */ 629 switch (port) { 630 case 8: 631 val = BRCM_HDR_P8_EN; 632 break; 633 case 7: 634 val = BRCM_HDR_P7_EN; 635 break; 636 case 5: 637 val = BRCM_HDR_P5_EN; 638 break; 639 default: 640 val = 0; 641 break; 642 } 643 644 /* Enable management mode if tagging is requested */ 645 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 646 if (tag_en) 647 hdr_ctl |= SM_SW_FWD_MODE; 648 else 649 hdr_ctl &= ~SM_SW_FWD_MODE; 650 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 651 652 /* Configure the appropriate IMP port */ 653 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 654 if (port == 8) 655 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 656 else if (port == 5) 657 hdr_ctl |= GC_FRM_MGMT_PORT_M; 658 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 659 660 /* Enable Broadcom tags for IMP port */ 661 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 662 if (tag_en) 663 hdr_ctl |= val; 664 else 665 hdr_ctl &= ~val; 666 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 667 668 /* Registers below are only accessible on newer devices */ 669 if (!is58xx(dev)) 670 return; 671 672 /* Enable reception Broadcom tag for CPU TX (switch RX) to 673 * allow us to tag outgoing frames 674 */ 675 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 676 if (tag_en) 677 reg &= ~BIT(port); 678 else 679 reg |= BIT(port); 680 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 681 682 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 683 * allow delivering frames to the per-port net_devices 684 */ 685 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 686 if (tag_en) 687 reg &= ~BIT(port); 688 else 689 reg |= BIT(port); 690 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 691 } 692 EXPORT_SYMBOL(b53_brcm_hdr_setup); 693 694 static void b53_enable_cpu_port(struct b53_device *dev, int port) 695 { 696 u8 port_ctrl; 697 698 /* BCM5325 CPU port is at 8 */ 699 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 700 port = B53_CPU_PORT; 701 702 port_ctrl = PORT_CTRL_RX_BCST_EN | 703 PORT_CTRL_RX_MCST_EN | 704 PORT_CTRL_RX_UCST_EN; 705 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 706 707 b53_brcm_hdr_setup(dev->ds, port); 708 709 b53_port_set_ucast_flood(dev, port, true); 710 b53_port_set_mcast_flood(dev, port, true); 711 b53_port_set_learning(dev, port, false); 712 } 713 714 static void b53_enable_mib(struct b53_device *dev) 715 { 716 u8 gc; 717 718 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 719 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 720 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 721 } 722 723 static u16 b53_default_pvid(struct b53_device *dev) 724 { 725 if (is5325(dev) || is5365(dev)) 726 return 1; 727 else 728 return 0; 729 } 730 731 static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) 732 { 733 struct b53_device *dev = ds->priv; 734 735 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); 736 } 737 738 int b53_configure_vlan(struct dsa_switch *ds) 739 { 740 struct b53_device *dev = ds->priv; 741 struct b53_vlan vl = { 0 }; 742 struct b53_vlan *v; 743 int i, def_vid; 744 u16 vid; 745 746 def_vid = b53_default_pvid(dev); 747 748 /* clear all vlan entries */ 749 if (is5325(dev) || is5365(dev)) { 750 for (i = def_vid; i < dev->num_vlans; i++) 751 b53_set_vlan_entry(dev, i, &vl); 752 } else { 753 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 754 } 755 756 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering); 757 758 /* Create an untagged VLAN entry for the default PVID in case 759 * CONFIG_VLAN_8021Q is disabled and there are no calls to 760 * dsa_slave_vlan_rx_add_vid() to create the default VLAN 761 * entry. Do this only when the tagging protocol is not 762 * DSA_TAG_PROTO_NONE 763 */ 764 b53_for_each_port(dev, i) { 765 v = &dev->vlans[def_vid]; 766 v->members |= BIT(i); 767 if (!b53_vlan_port_needs_forced_tagged(ds, i)) 768 v->untag = v->members; 769 b53_write16(dev, B53_VLAN_PAGE, 770 B53_VLAN_PORT_DEF_TAG(i), def_vid); 771 } 772 773 /* Upon initial call we have not set-up any VLANs, but upon 774 * system resume, we need to restore all VLAN entries. 775 */ 776 for (vid = def_vid; vid < dev->num_vlans; vid++) { 777 v = &dev->vlans[vid]; 778 779 if (!v->members) 780 continue; 781 782 b53_set_vlan_entry(dev, vid, v); 783 b53_fast_age_vlan(dev, vid); 784 } 785 786 return 0; 787 } 788 EXPORT_SYMBOL(b53_configure_vlan); 789 790 static void b53_switch_reset_gpio(struct b53_device *dev) 791 { 792 int gpio = dev->reset_gpio; 793 794 if (gpio < 0) 795 return; 796 797 /* Reset sequence: RESET low(50ms)->high(20ms) 798 */ 799 gpio_set_value(gpio, 0); 800 mdelay(50); 801 802 gpio_set_value(gpio, 1); 803 mdelay(20); 804 805 dev->current_page = 0xff; 806 } 807 808 static int b53_switch_reset(struct b53_device *dev) 809 { 810 unsigned int timeout = 1000; 811 u8 mgmt, reg; 812 813 b53_switch_reset_gpio(dev); 814 815 if (is539x(dev)) { 816 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 817 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 818 } 819 820 /* This is specific to 58xx devices here, do not use is58xx() which 821 * covers the larger Starfigther 2 family, including 7445/7278 which 822 * still use this driver as a library and need to perform the reset 823 * earlier. 824 */ 825 if (dev->chip_id == BCM58XX_DEVICE_ID || 826 dev->chip_id == BCM583XX_DEVICE_ID) { 827 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 828 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 829 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 830 831 do { 832 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 833 if (!(reg & SW_RST)) 834 break; 835 836 usleep_range(1000, 2000); 837 } while (timeout-- > 0); 838 839 if (timeout == 0) { 840 dev_err(dev->dev, 841 "Timeout waiting for SW_RST to clear!\n"); 842 return -ETIMEDOUT; 843 } 844 } 845 846 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 847 848 if (!(mgmt & SM_SW_FWD_EN)) { 849 mgmt &= ~SM_SW_FWD_MODE; 850 mgmt |= SM_SW_FWD_EN; 851 852 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 853 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 854 855 if (!(mgmt & SM_SW_FWD_EN)) { 856 dev_err(dev->dev, "Failed to enable switch!\n"); 857 return -EINVAL; 858 } 859 } 860 861 b53_enable_mib(dev); 862 863 return b53_flush_arl(dev, FAST_AGE_STATIC); 864 } 865 866 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 867 { 868 struct b53_device *priv = ds->priv; 869 u16 value = 0; 870 int ret; 871 872 if (priv->ops->phy_read16) 873 ret = priv->ops->phy_read16(priv, addr, reg, &value); 874 else 875 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 876 reg * 2, &value); 877 878 return ret ? ret : value; 879 } 880 881 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 882 { 883 struct b53_device *priv = ds->priv; 884 885 if (priv->ops->phy_write16) 886 return priv->ops->phy_write16(priv, addr, reg, val); 887 888 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 889 } 890 891 static int b53_reset_switch(struct b53_device *priv) 892 { 893 /* reset vlans */ 894 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 895 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 896 897 priv->serdes_lane = B53_INVALID_LANE; 898 899 return b53_switch_reset(priv); 900 } 901 902 static int b53_apply_config(struct b53_device *priv) 903 { 904 /* disable switching */ 905 b53_set_forwarding(priv, 0); 906 907 b53_configure_vlan(priv->ds); 908 909 /* enable switching */ 910 b53_set_forwarding(priv, 1); 911 912 return 0; 913 } 914 915 static void b53_reset_mib(struct b53_device *priv) 916 { 917 u8 gc; 918 919 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 920 921 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 922 msleep(1); 923 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 924 msleep(1); 925 } 926 927 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 928 { 929 if (is5365(dev)) 930 return b53_mibs_65; 931 else if (is63xx(dev)) 932 return b53_mibs_63xx; 933 else if (is58xx(dev)) 934 return b53_mibs_58xx; 935 else 936 return b53_mibs; 937 } 938 939 static unsigned int b53_get_mib_size(struct b53_device *dev) 940 { 941 if (is5365(dev)) 942 return B53_MIBS_65_SIZE; 943 else if (is63xx(dev)) 944 return B53_MIBS_63XX_SIZE; 945 else if (is58xx(dev)) 946 return B53_MIBS_58XX_SIZE; 947 else 948 return B53_MIBS_SIZE; 949 } 950 951 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 952 { 953 /* These ports typically do not have built-in PHYs */ 954 switch (port) { 955 case B53_CPU_PORT_25: 956 case 7: 957 case B53_CPU_PORT: 958 return NULL; 959 } 960 961 return mdiobus_get_phy(ds->slave_mii_bus, port); 962 } 963 964 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 965 uint8_t *data) 966 { 967 struct b53_device *dev = ds->priv; 968 const struct b53_mib_desc *mibs = b53_get_mib(dev); 969 unsigned int mib_size = b53_get_mib_size(dev); 970 struct phy_device *phydev; 971 unsigned int i; 972 973 if (stringset == ETH_SS_STATS) { 974 for (i = 0; i < mib_size; i++) 975 strlcpy(data + i * ETH_GSTRING_LEN, 976 mibs[i].name, ETH_GSTRING_LEN); 977 } else if (stringset == ETH_SS_PHY_STATS) { 978 phydev = b53_get_phy_device(ds, port); 979 if (!phydev) 980 return; 981 982 phy_ethtool_get_strings(phydev, data); 983 } 984 } 985 EXPORT_SYMBOL(b53_get_strings); 986 987 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 988 { 989 struct b53_device *dev = ds->priv; 990 const struct b53_mib_desc *mibs = b53_get_mib(dev); 991 unsigned int mib_size = b53_get_mib_size(dev); 992 const struct b53_mib_desc *s; 993 unsigned int i; 994 u64 val = 0; 995 996 if (is5365(dev) && port == 5) 997 port = 8; 998 999 mutex_lock(&dev->stats_mutex); 1000 1001 for (i = 0; i < mib_size; i++) { 1002 s = &mibs[i]; 1003 1004 if (s->size == 8) { 1005 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 1006 } else { 1007 u32 val32; 1008 1009 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 1010 &val32); 1011 val = val32; 1012 } 1013 data[i] = (u64)val; 1014 } 1015 1016 mutex_unlock(&dev->stats_mutex); 1017 } 1018 EXPORT_SYMBOL(b53_get_ethtool_stats); 1019 1020 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1021 { 1022 struct phy_device *phydev; 1023 1024 phydev = b53_get_phy_device(ds, port); 1025 if (!phydev) 1026 return; 1027 1028 phy_ethtool_get_stats(phydev, NULL, data); 1029 } 1030 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1031 1032 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1033 { 1034 struct b53_device *dev = ds->priv; 1035 struct phy_device *phydev; 1036 1037 if (sset == ETH_SS_STATS) { 1038 return b53_get_mib_size(dev); 1039 } else if (sset == ETH_SS_PHY_STATS) { 1040 phydev = b53_get_phy_device(ds, port); 1041 if (!phydev) 1042 return 0; 1043 1044 return phy_ethtool_get_sset_count(phydev); 1045 } 1046 1047 return 0; 1048 } 1049 EXPORT_SYMBOL(b53_get_sset_count); 1050 1051 enum b53_devlink_resource_id { 1052 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1053 }; 1054 1055 static u64 b53_devlink_vlan_table_get(void *priv) 1056 { 1057 struct b53_device *dev = priv; 1058 struct b53_vlan *vl; 1059 unsigned int i; 1060 u64 count = 0; 1061 1062 for (i = 0; i < dev->num_vlans; i++) { 1063 vl = &dev->vlans[i]; 1064 if (vl->members) 1065 count++; 1066 } 1067 1068 return count; 1069 } 1070 1071 int b53_setup_devlink_resources(struct dsa_switch *ds) 1072 { 1073 struct devlink_resource_size_params size_params; 1074 struct b53_device *dev = ds->priv; 1075 int err; 1076 1077 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1078 dev->num_vlans, 1079 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1080 1081 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1082 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1083 DEVLINK_RESOURCE_ID_PARENT_TOP, 1084 &size_params); 1085 if (err) 1086 goto out; 1087 1088 dsa_devlink_resource_occ_get_register(ds, 1089 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1090 b53_devlink_vlan_table_get, dev); 1091 1092 return 0; 1093 out: 1094 dsa_devlink_resources_unregister(ds); 1095 return err; 1096 } 1097 EXPORT_SYMBOL(b53_setup_devlink_resources); 1098 1099 static int b53_setup(struct dsa_switch *ds) 1100 { 1101 struct b53_device *dev = ds->priv; 1102 unsigned int port; 1103 int ret; 1104 1105 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set 1106 * which forces the CPU port to be tagged in all VLANs. 1107 */ 1108 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; 1109 1110 ret = b53_reset_switch(dev); 1111 if (ret) { 1112 dev_err(ds->dev, "failed to reset switch\n"); 1113 return ret; 1114 } 1115 1116 b53_reset_mib(dev); 1117 1118 ret = b53_apply_config(dev); 1119 if (ret) { 1120 dev_err(ds->dev, "failed to apply configuration\n"); 1121 return ret; 1122 } 1123 1124 /* Configure IMP/CPU port, disable all other ports. Enabled 1125 * ports will be configured with .port_enable 1126 */ 1127 for (port = 0; port < dev->num_ports; port++) { 1128 if (dsa_is_cpu_port(ds, port)) 1129 b53_enable_cpu_port(dev, port); 1130 else 1131 b53_disable_port(ds, port); 1132 } 1133 1134 return b53_setup_devlink_resources(ds); 1135 } 1136 1137 static void b53_teardown(struct dsa_switch *ds) 1138 { 1139 dsa_devlink_resources_unregister(ds); 1140 } 1141 1142 static void b53_force_link(struct b53_device *dev, int port, int link) 1143 { 1144 u8 reg, val, off; 1145 1146 /* Override the port settings */ 1147 if (port == dev->imp_port) { 1148 off = B53_PORT_OVERRIDE_CTRL; 1149 val = PORT_OVERRIDE_EN; 1150 } else { 1151 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1152 val = GMII_PO_EN; 1153 } 1154 1155 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1156 reg |= val; 1157 if (link) 1158 reg |= PORT_OVERRIDE_LINK; 1159 else 1160 reg &= ~PORT_OVERRIDE_LINK; 1161 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1162 } 1163 1164 static void b53_force_port_config(struct b53_device *dev, int port, 1165 int speed, int duplex, 1166 bool tx_pause, bool rx_pause) 1167 { 1168 u8 reg, val, off; 1169 1170 /* Override the port settings */ 1171 if (port == dev->imp_port) { 1172 off = B53_PORT_OVERRIDE_CTRL; 1173 val = PORT_OVERRIDE_EN; 1174 } else { 1175 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1176 val = GMII_PO_EN; 1177 } 1178 1179 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1180 reg |= val; 1181 if (duplex == DUPLEX_FULL) 1182 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1183 else 1184 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1185 1186 switch (speed) { 1187 case 2000: 1188 reg |= PORT_OVERRIDE_SPEED_2000M; 1189 fallthrough; 1190 case SPEED_1000: 1191 reg |= PORT_OVERRIDE_SPEED_1000M; 1192 break; 1193 case SPEED_100: 1194 reg |= PORT_OVERRIDE_SPEED_100M; 1195 break; 1196 case SPEED_10: 1197 reg |= PORT_OVERRIDE_SPEED_10M; 1198 break; 1199 default: 1200 dev_err(dev->dev, "unknown speed: %d\n", speed); 1201 return; 1202 } 1203 1204 if (rx_pause) 1205 reg |= PORT_OVERRIDE_RX_FLOW; 1206 if (tx_pause) 1207 reg |= PORT_OVERRIDE_TX_FLOW; 1208 1209 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1210 } 1211 1212 static void b53_adjust_link(struct dsa_switch *ds, int port, 1213 struct phy_device *phydev) 1214 { 1215 struct b53_device *dev = ds->priv; 1216 struct ethtool_eee *p = &dev->ports[port].eee; 1217 u8 rgmii_ctrl = 0, reg = 0, off; 1218 bool tx_pause = false; 1219 bool rx_pause = false; 1220 1221 if (!phy_is_pseudo_fixed_link(phydev)) 1222 return; 1223 1224 /* Enable flow control on BCM5301x's CPU port */ 1225 if (is5301x(dev) && dsa_is_cpu_port(ds, port)) 1226 tx_pause = rx_pause = true; 1227 1228 if (phydev->pause) { 1229 if (phydev->asym_pause) 1230 tx_pause = true; 1231 rx_pause = true; 1232 } 1233 1234 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, 1235 tx_pause, rx_pause); 1236 b53_force_link(dev, port, phydev->link); 1237 1238 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1239 if (port == dev->imp_port) 1240 off = B53_RGMII_CTRL_IMP; 1241 else 1242 off = B53_RGMII_CTRL_P(port); 1243 1244 /* Configure the port RGMII clock delay by DLL disabled and 1245 * tx_clk aligned timing (restoring to reset defaults) 1246 */ 1247 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1248 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1249 RGMII_CTRL_TIMING_SEL); 1250 1251 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1252 * sure that we enable the port TX clock internal delay to 1253 * account for this internal delay that is inserted, otherwise 1254 * the switch won't be able to receive correctly. 1255 * 1256 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1257 * any delay neither on transmission nor reception, so the 1258 * BCM53125 must also be configured accordingly to account for 1259 * the lack of delay and introduce 1260 * 1261 * The BCM53125 switch has its RX clock and TX clock control 1262 * swapped, hence the reason why we modify the TX clock path in 1263 * the "RGMII" case 1264 */ 1265 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1266 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1267 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1268 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1269 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1270 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1271 1272 dev_info(ds->dev, "Configured port %d for %s\n", port, 1273 phy_modes(phydev->interface)); 1274 } 1275 1276 /* configure MII port if necessary */ 1277 if (is5325(dev)) { 1278 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1279 ®); 1280 1281 /* reverse mii needs to be enabled */ 1282 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1283 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1284 reg | PORT_OVERRIDE_RV_MII_25); 1285 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1286 ®); 1287 1288 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1289 dev_err(ds->dev, 1290 "Failed to enable reverse MII mode\n"); 1291 return; 1292 } 1293 } 1294 } 1295 1296 /* Re-negotiate EEE if it was enabled already */ 1297 p->eee_enabled = b53_eee_init(ds, port, phydev); 1298 } 1299 1300 void b53_port_event(struct dsa_switch *ds, int port) 1301 { 1302 struct b53_device *dev = ds->priv; 1303 bool link; 1304 u16 sts; 1305 1306 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1307 link = !!(sts & BIT(port)); 1308 dsa_port_phylink_mac_change(ds, port, link); 1309 } 1310 EXPORT_SYMBOL(b53_port_event); 1311 1312 void b53_phylink_validate(struct dsa_switch *ds, int port, 1313 unsigned long *supported, 1314 struct phylink_link_state *state) 1315 { 1316 struct b53_device *dev = ds->priv; 1317 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1318 1319 if (dev->ops->serdes_phylink_validate) 1320 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1321 1322 /* Allow all the expected bits */ 1323 phylink_set(mask, Autoneg); 1324 phylink_set_port_modes(mask); 1325 phylink_set(mask, Pause); 1326 phylink_set(mask, Asym_Pause); 1327 1328 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1329 * support Gigabit, including Half duplex. 1330 */ 1331 if (state->interface != PHY_INTERFACE_MODE_MII && 1332 state->interface != PHY_INTERFACE_MODE_REVMII && 1333 !phy_interface_mode_is_8023z(state->interface) && 1334 !(is5325(dev) || is5365(dev))) { 1335 phylink_set(mask, 1000baseT_Full); 1336 phylink_set(mask, 1000baseT_Half); 1337 } 1338 1339 if (!phy_interface_mode_is_8023z(state->interface)) { 1340 phylink_set(mask, 10baseT_Half); 1341 phylink_set(mask, 10baseT_Full); 1342 phylink_set(mask, 100baseT_Half); 1343 phylink_set(mask, 100baseT_Full); 1344 } 1345 1346 linkmode_and(supported, supported, mask); 1347 linkmode_and(state->advertising, state->advertising, mask); 1348 1349 phylink_helper_basex_speed(state); 1350 } 1351 EXPORT_SYMBOL(b53_phylink_validate); 1352 1353 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1354 struct phylink_link_state *state) 1355 { 1356 struct b53_device *dev = ds->priv; 1357 int ret = -EOPNOTSUPP; 1358 1359 if ((phy_interface_mode_is_8023z(state->interface) || 1360 state->interface == PHY_INTERFACE_MODE_SGMII) && 1361 dev->ops->serdes_link_state) 1362 ret = dev->ops->serdes_link_state(dev, port, state); 1363 1364 return ret; 1365 } 1366 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1367 1368 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1369 unsigned int mode, 1370 const struct phylink_link_state *state) 1371 { 1372 struct b53_device *dev = ds->priv; 1373 1374 if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED) 1375 return; 1376 1377 if ((phy_interface_mode_is_8023z(state->interface) || 1378 state->interface == PHY_INTERFACE_MODE_SGMII) && 1379 dev->ops->serdes_config) 1380 dev->ops->serdes_config(dev, port, mode, state); 1381 } 1382 EXPORT_SYMBOL(b53_phylink_mac_config); 1383 1384 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1385 { 1386 struct b53_device *dev = ds->priv; 1387 1388 if (dev->ops->serdes_an_restart) 1389 dev->ops->serdes_an_restart(dev, port); 1390 } 1391 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1392 1393 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1394 unsigned int mode, 1395 phy_interface_t interface) 1396 { 1397 struct b53_device *dev = ds->priv; 1398 1399 if (mode == MLO_AN_PHY) 1400 return; 1401 1402 if (mode == MLO_AN_FIXED) { 1403 b53_force_link(dev, port, false); 1404 return; 1405 } 1406 1407 if (phy_interface_mode_is_8023z(interface) && 1408 dev->ops->serdes_link_set) 1409 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1410 } 1411 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1412 1413 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1414 unsigned int mode, 1415 phy_interface_t interface, 1416 struct phy_device *phydev, 1417 int speed, int duplex, 1418 bool tx_pause, bool rx_pause) 1419 { 1420 struct b53_device *dev = ds->priv; 1421 1422 if (mode == MLO_AN_PHY) 1423 return; 1424 1425 if (mode == MLO_AN_FIXED) { 1426 b53_force_port_config(dev, port, speed, duplex, 1427 tx_pause, rx_pause); 1428 b53_force_link(dev, port, true); 1429 return; 1430 } 1431 1432 if (phy_interface_mode_is_8023z(interface) && 1433 dev->ops->serdes_link_set) 1434 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1435 } 1436 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1437 1438 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1439 struct netlink_ext_ack *extack) 1440 { 1441 struct b53_device *dev = ds->priv; 1442 1443 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering); 1444 1445 return 0; 1446 } 1447 EXPORT_SYMBOL(b53_vlan_filtering); 1448 1449 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1450 const struct switchdev_obj_port_vlan *vlan) 1451 { 1452 struct b53_device *dev = ds->priv; 1453 1454 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1455 return -EOPNOTSUPP; 1456 1457 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1458 * receiving VLAN tagged frames at all, we can still allow the port to 1459 * be configured for egress untagged. 1460 */ 1461 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1462 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1463 return -EINVAL; 1464 1465 if (vlan->vid >= dev->num_vlans) 1466 return -ERANGE; 1467 1468 b53_enable_vlan(dev, port, true, ds->vlan_filtering); 1469 1470 return 0; 1471 } 1472 1473 int b53_vlan_add(struct dsa_switch *ds, int port, 1474 const struct switchdev_obj_port_vlan *vlan, 1475 struct netlink_ext_ack *extack) 1476 { 1477 struct b53_device *dev = ds->priv; 1478 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1479 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1480 struct b53_vlan *vl; 1481 int err; 1482 1483 err = b53_vlan_prepare(ds, port, vlan); 1484 if (err) 1485 return err; 1486 1487 vl = &dev->vlans[vlan->vid]; 1488 1489 b53_get_vlan_entry(dev, vlan->vid, vl); 1490 1491 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1492 untagged = true; 1493 1494 vl->members |= BIT(port); 1495 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1496 vl->untag |= BIT(port); 1497 else 1498 vl->untag &= ~BIT(port); 1499 1500 b53_set_vlan_entry(dev, vlan->vid, vl); 1501 b53_fast_age_vlan(dev, vlan->vid); 1502 1503 if (pvid && !dsa_is_cpu_port(ds, port)) { 1504 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1505 vlan->vid); 1506 b53_fast_age_vlan(dev, vlan->vid); 1507 } 1508 1509 return 0; 1510 } 1511 EXPORT_SYMBOL(b53_vlan_add); 1512 1513 int b53_vlan_del(struct dsa_switch *ds, int port, 1514 const struct switchdev_obj_port_vlan *vlan) 1515 { 1516 struct b53_device *dev = ds->priv; 1517 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1518 struct b53_vlan *vl; 1519 u16 pvid; 1520 1521 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1522 1523 vl = &dev->vlans[vlan->vid]; 1524 1525 b53_get_vlan_entry(dev, vlan->vid, vl); 1526 1527 vl->members &= ~BIT(port); 1528 1529 if (pvid == vlan->vid) 1530 pvid = b53_default_pvid(dev); 1531 1532 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) 1533 vl->untag &= ~(BIT(port)); 1534 1535 b53_set_vlan_entry(dev, vlan->vid, vl); 1536 b53_fast_age_vlan(dev, vlan->vid); 1537 1538 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1539 b53_fast_age_vlan(dev, pvid); 1540 1541 return 0; 1542 } 1543 EXPORT_SYMBOL(b53_vlan_del); 1544 1545 /* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */ 1546 static int b53_arl_op_wait(struct b53_device *dev) 1547 { 1548 unsigned int timeout = 10; 1549 u8 reg; 1550 1551 do { 1552 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1553 if (!(reg & ARLTBL_START_DONE)) 1554 return 0; 1555 1556 usleep_range(1000, 2000); 1557 } while (timeout--); 1558 1559 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1560 1561 return -ETIMEDOUT; 1562 } 1563 1564 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1565 { 1566 u8 reg; 1567 1568 if (op > ARLTBL_RW) 1569 return -EINVAL; 1570 1571 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1572 reg |= ARLTBL_START_DONE; 1573 if (op) 1574 reg |= ARLTBL_RW; 1575 else 1576 reg &= ~ARLTBL_RW; 1577 if (dev->vlan_enabled) 1578 reg &= ~ARLTBL_IVL_SVL_SELECT; 1579 else 1580 reg |= ARLTBL_IVL_SVL_SELECT; 1581 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1582 1583 return b53_arl_op_wait(dev); 1584 } 1585 1586 static int b53_arl_read(struct b53_device *dev, u64 mac, 1587 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1588 { 1589 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1590 unsigned int i; 1591 int ret; 1592 1593 ret = b53_arl_op_wait(dev); 1594 if (ret) 1595 return ret; 1596 1597 bitmap_zero(free_bins, dev->num_arl_bins); 1598 1599 /* Read the bins */ 1600 for (i = 0; i < dev->num_arl_bins; i++) { 1601 u64 mac_vid; 1602 u32 fwd_entry; 1603 1604 b53_read64(dev, B53_ARLIO_PAGE, 1605 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1606 b53_read32(dev, B53_ARLIO_PAGE, 1607 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1608 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1609 1610 if (!(fwd_entry & ARLTBL_VALID)) { 1611 set_bit(i, free_bins); 1612 continue; 1613 } 1614 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1615 continue; 1616 if (dev->vlan_enabled && 1617 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1618 continue; 1619 *idx = i; 1620 return 0; 1621 } 1622 1623 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0) 1624 return -ENOSPC; 1625 1626 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1627 1628 return -ENOENT; 1629 } 1630 1631 static int b53_arl_op(struct b53_device *dev, int op, int port, 1632 const unsigned char *addr, u16 vid, bool is_valid) 1633 { 1634 struct b53_arl_entry ent; 1635 u32 fwd_entry; 1636 u64 mac, mac_vid = 0; 1637 u8 idx = 0; 1638 int ret; 1639 1640 /* Convert the array into a 64-bit MAC */ 1641 mac = ether_addr_to_u64(addr); 1642 1643 /* Perform a read for the given MAC and VID */ 1644 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1645 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1646 1647 /* Issue a read operation for this MAC */ 1648 ret = b53_arl_rw_op(dev, 1); 1649 if (ret) 1650 return ret; 1651 1652 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1653 1654 /* If this is a read, just finish now */ 1655 if (op) 1656 return ret; 1657 1658 switch (ret) { 1659 case -ETIMEDOUT: 1660 return ret; 1661 case -ENOSPC: 1662 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1663 addr, vid); 1664 return is_valid ? ret : 0; 1665 case -ENOENT: 1666 /* We could not find a matching MAC, so reset to a new entry */ 1667 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1668 addr, vid, idx); 1669 fwd_entry = 0; 1670 break; 1671 default: 1672 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1673 addr, vid, idx); 1674 break; 1675 } 1676 1677 /* For multicast address, the port is a bitmask and the validity 1678 * is determined by having at least one port being still active 1679 */ 1680 if (!is_multicast_ether_addr(addr)) { 1681 ent.port = port; 1682 ent.is_valid = is_valid; 1683 } else { 1684 if (is_valid) 1685 ent.port |= BIT(port); 1686 else 1687 ent.port &= ~BIT(port); 1688 1689 ent.is_valid = !!(ent.port); 1690 } 1691 1692 ent.vid = vid; 1693 ent.is_static = true; 1694 ent.is_age = false; 1695 memcpy(ent.mac, addr, ETH_ALEN); 1696 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1697 1698 b53_write64(dev, B53_ARLIO_PAGE, 1699 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1700 b53_write32(dev, B53_ARLIO_PAGE, 1701 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1702 1703 return b53_arl_rw_op(dev, 0); 1704 } 1705 1706 int b53_fdb_add(struct dsa_switch *ds, int port, 1707 const unsigned char *addr, u16 vid) 1708 { 1709 struct b53_device *priv = ds->priv; 1710 int ret; 1711 1712 /* 5325 and 5365 require some more massaging, but could 1713 * be supported eventually 1714 */ 1715 if (is5325(priv) || is5365(priv)) 1716 return -EOPNOTSUPP; 1717 1718 mutex_lock(&priv->arl_mutex); 1719 ret = b53_arl_op(priv, 0, port, addr, vid, true); 1720 mutex_unlock(&priv->arl_mutex); 1721 1722 return ret; 1723 } 1724 EXPORT_SYMBOL(b53_fdb_add); 1725 1726 int b53_fdb_del(struct dsa_switch *ds, int port, 1727 const unsigned char *addr, u16 vid) 1728 { 1729 struct b53_device *priv = ds->priv; 1730 int ret; 1731 1732 mutex_lock(&priv->arl_mutex); 1733 ret = b53_arl_op(priv, 0, port, addr, vid, false); 1734 mutex_unlock(&priv->arl_mutex); 1735 1736 return ret; 1737 } 1738 EXPORT_SYMBOL(b53_fdb_del); 1739 1740 static int b53_arl_search_wait(struct b53_device *dev) 1741 { 1742 unsigned int timeout = 1000; 1743 u8 reg; 1744 1745 do { 1746 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1747 if (!(reg & ARL_SRCH_STDN)) 1748 return 0; 1749 1750 if (reg & ARL_SRCH_VLID) 1751 return 0; 1752 1753 usleep_range(1000, 2000); 1754 } while (timeout--); 1755 1756 return -ETIMEDOUT; 1757 } 1758 1759 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1760 struct b53_arl_entry *ent) 1761 { 1762 u64 mac_vid; 1763 u32 fwd_entry; 1764 1765 b53_read64(dev, B53_ARLIO_PAGE, 1766 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1767 b53_read32(dev, B53_ARLIO_PAGE, 1768 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1769 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1770 } 1771 1772 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1773 dsa_fdb_dump_cb_t *cb, void *data) 1774 { 1775 if (!ent->is_valid) 1776 return 0; 1777 1778 if (port != ent->port) 1779 return 0; 1780 1781 return cb(ent->mac, ent->vid, ent->is_static, data); 1782 } 1783 1784 int b53_fdb_dump(struct dsa_switch *ds, int port, 1785 dsa_fdb_dump_cb_t *cb, void *data) 1786 { 1787 struct b53_device *priv = ds->priv; 1788 struct b53_arl_entry results[2]; 1789 unsigned int count = 0; 1790 int ret; 1791 u8 reg; 1792 1793 mutex_lock(&priv->arl_mutex); 1794 1795 /* Start search operation */ 1796 reg = ARL_SRCH_STDN; 1797 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1798 1799 do { 1800 ret = b53_arl_search_wait(priv); 1801 if (ret) 1802 break; 1803 1804 b53_arl_search_rd(priv, 0, &results[0]); 1805 ret = b53_fdb_copy(port, &results[0], cb, data); 1806 if (ret) 1807 break; 1808 1809 if (priv->num_arl_bins > 2) { 1810 b53_arl_search_rd(priv, 1, &results[1]); 1811 ret = b53_fdb_copy(port, &results[1], cb, data); 1812 if (ret) 1813 break; 1814 1815 if (!results[0].is_valid && !results[1].is_valid) 1816 break; 1817 } 1818 1819 } while (count++ < b53_max_arl_entries(priv) / 2); 1820 1821 mutex_unlock(&priv->arl_mutex); 1822 1823 return 0; 1824 } 1825 EXPORT_SYMBOL(b53_fdb_dump); 1826 1827 int b53_mdb_add(struct dsa_switch *ds, int port, 1828 const struct switchdev_obj_port_mdb *mdb) 1829 { 1830 struct b53_device *priv = ds->priv; 1831 int ret; 1832 1833 /* 5325 and 5365 require some more massaging, but could 1834 * be supported eventually 1835 */ 1836 if (is5325(priv) || is5365(priv)) 1837 return -EOPNOTSUPP; 1838 1839 mutex_lock(&priv->arl_mutex); 1840 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1841 mutex_unlock(&priv->arl_mutex); 1842 1843 return ret; 1844 } 1845 EXPORT_SYMBOL(b53_mdb_add); 1846 1847 int b53_mdb_del(struct dsa_switch *ds, int port, 1848 const struct switchdev_obj_port_mdb *mdb) 1849 { 1850 struct b53_device *priv = ds->priv; 1851 int ret; 1852 1853 mutex_lock(&priv->arl_mutex); 1854 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1855 mutex_unlock(&priv->arl_mutex); 1856 if (ret) 1857 dev_err(ds->dev, "failed to delete MDB entry\n"); 1858 1859 return ret; 1860 } 1861 EXPORT_SYMBOL(b53_mdb_del); 1862 1863 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1864 { 1865 struct b53_device *dev = ds->priv; 1866 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1867 u16 pvlan, reg; 1868 unsigned int i; 1869 1870 /* On 7278, port 7 which connects to the ASP should only receive 1871 * traffic from matching CFP rules. 1872 */ 1873 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1874 return -EINVAL; 1875 1876 /* Make this port leave the all VLANs join since we will have proper 1877 * VLAN entries from now on 1878 */ 1879 if (is58xx(dev)) { 1880 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1881 reg &= ~BIT(port); 1882 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1883 reg &= ~BIT(cpu_port); 1884 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1885 } 1886 1887 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1888 1889 b53_for_each_port(dev, i) { 1890 if (dsa_to_port(ds, i)->bridge_dev != br) 1891 continue; 1892 1893 /* Add this local port to the remote port VLAN control 1894 * membership and update the remote port bitmask 1895 */ 1896 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1897 reg |= BIT(port); 1898 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1899 dev->ports[i].vlan_ctl_mask = reg; 1900 1901 pvlan |= BIT(i); 1902 } 1903 1904 /* Configure the local port VLAN control membership to include 1905 * remote ports and update the local port bitmask 1906 */ 1907 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1908 dev->ports[port].vlan_ctl_mask = pvlan; 1909 1910 return 0; 1911 } 1912 EXPORT_SYMBOL(b53_br_join); 1913 1914 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1915 { 1916 struct b53_device *dev = ds->priv; 1917 struct b53_vlan *vl = &dev->vlans[0]; 1918 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1919 unsigned int i; 1920 u16 pvlan, reg, pvid; 1921 1922 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1923 1924 b53_for_each_port(dev, i) { 1925 /* Don't touch the remaining ports */ 1926 if (dsa_to_port(ds, i)->bridge_dev != br) 1927 continue; 1928 1929 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1930 reg &= ~BIT(port); 1931 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1932 dev->ports[port].vlan_ctl_mask = reg; 1933 1934 /* Prevent self removal to preserve isolation */ 1935 if (port != i) 1936 pvlan &= ~BIT(i); 1937 } 1938 1939 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1940 dev->ports[port].vlan_ctl_mask = pvlan; 1941 1942 pvid = b53_default_pvid(dev); 1943 1944 /* Make this port join all VLANs without VLAN entries */ 1945 if (is58xx(dev)) { 1946 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1947 reg |= BIT(port); 1948 if (!(reg & BIT(cpu_port))) 1949 reg |= BIT(cpu_port); 1950 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1951 } else { 1952 b53_get_vlan_entry(dev, pvid, vl); 1953 vl->members |= BIT(port) | BIT(cpu_port); 1954 vl->untag |= BIT(port) | BIT(cpu_port); 1955 b53_set_vlan_entry(dev, pvid, vl); 1956 } 1957 } 1958 EXPORT_SYMBOL(b53_br_leave); 1959 1960 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1961 { 1962 struct b53_device *dev = ds->priv; 1963 u8 hw_state; 1964 u8 reg; 1965 1966 switch (state) { 1967 case BR_STATE_DISABLED: 1968 hw_state = PORT_CTRL_DIS_STATE; 1969 break; 1970 case BR_STATE_LISTENING: 1971 hw_state = PORT_CTRL_LISTEN_STATE; 1972 break; 1973 case BR_STATE_LEARNING: 1974 hw_state = PORT_CTRL_LEARN_STATE; 1975 break; 1976 case BR_STATE_FORWARDING: 1977 hw_state = PORT_CTRL_FWD_STATE; 1978 break; 1979 case BR_STATE_BLOCKING: 1980 hw_state = PORT_CTRL_BLOCK_STATE; 1981 break; 1982 default: 1983 dev_err(ds->dev, "invalid STP state: %d\n", state); 1984 return; 1985 } 1986 1987 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1988 reg &= ~PORT_CTRL_STP_STATE_MASK; 1989 reg |= hw_state; 1990 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1991 } 1992 EXPORT_SYMBOL(b53_br_set_stp_state); 1993 1994 void b53_br_fast_age(struct dsa_switch *ds, int port) 1995 { 1996 struct b53_device *dev = ds->priv; 1997 1998 if (b53_fast_age_port(dev, port)) 1999 dev_err(ds->dev, "fast ageing failed\n"); 2000 } 2001 EXPORT_SYMBOL(b53_br_fast_age); 2002 2003 int b53_br_flags_pre(struct dsa_switch *ds, int port, 2004 struct switchdev_brport_flags flags, 2005 struct netlink_ext_ack *extack) 2006 { 2007 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 2008 return -EINVAL; 2009 2010 return 0; 2011 } 2012 EXPORT_SYMBOL(b53_br_flags_pre); 2013 2014 int b53_br_flags(struct dsa_switch *ds, int port, 2015 struct switchdev_brport_flags flags, 2016 struct netlink_ext_ack *extack) 2017 { 2018 if (flags.mask & BR_FLOOD) 2019 b53_port_set_ucast_flood(ds->priv, port, 2020 !!(flags.val & BR_FLOOD)); 2021 if (flags.mask & BR_MCAST_FLOOD) 2022 b53_port_set_mcast_flood(ds->priv, port, 2023 !!(flags.val & BR_MCAST_FLOOD)); 2024 if (flags.mask & BR_LEARNING) 2025 b53_port_set_learning(ds->priv, port, 2026 !!(flags.val & BR_LEARNING)); 2027 2028 return 0; 2029 } 2030 EXPORT_SYMBOL(b53_br_flags); 2031 2032 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2033 { 2034 /* Broadcom switches will accept enabling Broadcom tags on the 2035 * following ports: 5, 7 and 8, any other port is not supported 2036 */ 2037 switch (port) { 2038 case B53_CPU_PORT_25: 2039 case 7: 2040 case B53_CPU_PORT: 2041 return true; 2042 } 2043 2044 return false; 2045 } 2046 2047 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2048 enum dsa_tag_protocol tag_protocol) 2049 { 2050 bool ret = b53_possible_cpu_port(ds, port); 2051 2052 if (!ret) { 2053 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2054 port); 2055 return ret; 2056 } 2057 2058 switch (tag_protocol) { 2059 case DSA_TAG_PROTO_BRCM: 2060 case DSA_TAG_PROTO_BRCM_PREPEND: 2061 dev_warn(ds->dev, 2062 "Port %d is stacked to Broadcom tag switch\n", port); 2063 ret = false; 2064 break; 2065 default: 2066 ret = true; 2067 break; 2068 } 2069 2070 return ret; 2071 } 2072 2073 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2074 enum dsa_tag_protocol mprot) 2075 { 2076 struct b53_device *dev = ds->priv; 2077 2078 if (!b53_can_enable_brcm_tags(ds, port, mprot)) { 2079 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2080 goto out; 2081 } 2082 2083 /* Older models require a different 6 byte tag */ 2084 if (is5325(dev) || is5365(dev) || is63xx(dev)) { 2085 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; 2086 goto out; 2087 } 2088 2089 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2090 * which requires us to use the prepended Broadcom tag type 2091 */ 2092 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2093 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2094 goto out; 2095 } 2096 2097 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2098 out: 2099 return dev->tag_protocol; 2100 } 2101 EXPORT_SYMBOL(b53_get_tag_protocol); 2102 2103 int b53_mirror_add(struct dsa_switch *ds, int port, 2104 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 2105 { 2106 struct b53_device *dev = ds->priv; 2107 u16 reg, loc; 2108 2109 if (ingress) 2110 loc = B53_IG_MIR_CTL; 2111 else 2112 loc = B53_EG_MIR_CTL; 2113 2114 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2115 reg |= BIT(port); 2116 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2117 2118 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2119 reg &= ~CAP_PORT_MASK; 2120 reg |= mirror->to_local_port; 2121 reg |= MIRROR_EN; 2122 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2123 2124 return 0; 2125 } 2126 EXPORT_SYMBOL(b53_mirror_add); 2127 2128 void b53_mirror_del(struct dsa_switch *ds, int port, 2129 struct dsa_mall_mirror_tc_entry *mirror) 2130 { 2131 struct b53_device *dev = ds->priv; 2132 bool loc_disable = false, other_loc_disable = false; 2133 u16 reg, loc; 2134 2135 if (mirror->ingress) 2136 loc = B53_IG_MIR_CTL; 2137 else 2138 loc = B53_EG_MIR_CTL; 2139 2140 /* Update the desired ingress/egress register */ 2141 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2142 reg &= ~BIT(port); 2143 if (!(reg & MIRROR_MASK)) 2144 loc_disable = true; 2145 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2146 2147 /* Now look at the other one to know if we can disable mirroring 2148 * entirely 2149 */ 2150 if (mirror->ingress) 2151 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2152 else 2153 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2154 if (!(reg & MIRROR_MASK)) 2155 other_loc_disable = true; 2156 2157 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2158 /* Both no longer have ports, let's disable mirroring */ 2159 if (loc_disable && other_loc_disable) { 2160 reg &= ~MIRROR_EN; 2161 reg &= ~mirror->to_local_port; 2162 } 2163 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2164 } 2165 EXPORT_SYMBOL(b53_mirror_del); 2166 2167 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 2168 { 2169 struct b53_device *dev = ds->priv; 2170 u16 reg; 2171 2172 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 2173 if (enable) 2174 reg |= BIT(port); 2175 else 2176 reg &= ~BIT(port); 2177 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 2178 } 2179 EXPORT_SYMBOL(b53_eee_enable_set); 2180 2181 2182 /* Returns 0 if EEE was not enabled, or 1 otherwise 2183 */ 2184 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2185 { 2186 int ret; 2187 2188 ret = phy_init_eee(phy, 0); 2189 if (ret) 2190 return 0; 2191 2192 b53_eee_enable_set(ds, port, true); 2193 2194 return 1; 2195 } 2196 EXPORT_SYMBOL(b53_eee_init); 2197 2198 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2199 { 2200 struct b53_device *dev = ds->priv; 2201 struct ethtool_eee *p = &dev->ports[port].eee; 2202 u16 reg; 2203 2204 if (is5325(dev) || is5365(dev)) 2205 return -EOPNOTSUPP; 2206 2207 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 2208 e->eee_enabled = p->eee_enabled; 2209 e->eee_active = !!(reg & BIT(port)); 2210 2211 return 0; 2212 } 2213 EXPORT_SYMBOL(b53_get_mac_eee); 2214 2215 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2216 { 2217 struct b53_device *dev = ds->priv; 2218 struct ethtool_eee *p = &dev->ports[port].eee; 2219 2220 if (is5325(dev) || is5365(dev)) 2221 return -EOPNOTSUPP; 2222 2223 p->eee_enabled = e->eee_enabled; 2224 b53_eee_enable_set(ds, port, e->eee_enabled); 2225 2226 return 0; 2227 } 2228 EXPORT_SYMBOL(b53_set_mac_eee); 2229 2230 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2231 { 2232 struct b53_device *dev = ds->priv; 2233 bool enable_jumbo; 2234 bool allow_10_100; 2235 2236 if (is5325(dev) || is5365(dev)) 2237 return -EOPNOTSUPP; 2238 2239 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2240 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2241 2242 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2243 } 2244 2245 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2246 { 2247 return JMS_MAX_SIZE; 2248 } 2249 2250 static const struct dsa_switch_ops b53_switch_ops = { 2251 .get_tag_protocol = b53_get_tag_protocol, 2252 .setup = b53_setup, 2253 .teardown = b53_teardown, 2254 .get_strings = b53_get_strings, 2255 .get_ethtool_stats = b53_get_ethtool_stats, 2256 .get_sset_count = b53_get_sset_count, 2257 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2258 .phy_read = b53_phy_read16, 2259 .phy_write = b53_phy_write16, 2260 .adjust_link = b53_adjust_link, 2261 .phylink_validate = b53_phylink_validate, 2262 .phylink_mac_link_state = b53_phylink_mac_link_state, 2263 .phylink_mac_config = b53_phylink_mac_config, 2264 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 2265 .phylink_mac_link_down = b53_phylink_mac_link_down, 2266 .phylink_mac_link_up = b53_phylink_mac_link_up, 2267 .port_enable = b53_enable_port, 2268 .port_disable = b53_disable_port, 2269 .get_mac_eee = b53_get_mac_eee, 2270 .set_mac_eee = b53_set_mac_eee, 2271 .port_bridge_join = b53_br_join, 2272 .port_bridge_leave = b53_br_leave, 2273 .port_pre_bridge_flags = b53_br_flags_pre, 2274 .port_bridge_flags = b53_br_flags, 2275 .port_stp_state_set = b53_br_set_stp_state, 2276 .port_fast_age = b53_br_fast_age, 2277 .port_vlan_filtering = b53_vlan_filtering, 2278 .port_vlan_add = b53_vlan_add, 2279 .port_vlan_del = b53_vlan_del, 2280 .port_fdb_dump = b53_fdb_dump, 2281 .port_fdb_add = b53_fdb_add, 2282 .port_fdb_del = b53_fdb_del, 2283 .port_mirror_add = b53_mirror_add, 2284 .port_mirror_del = b53_mirror_del, 2285 .port_mdb_add = b53_mdb_add, 2286 .port_mdb_del = b53_mdb_del, 2287 .port_max_mtu = b53_get_max_mtu, 2288 .port_change_mtu = b53_change_mtu, 2289 }; 2290 2291 struct b53_chip_data { 2292 u32 chip_id; 2293 const char *dev_name; 2294 u16 vlans; 2295 u16 enabled_ports; 2296 u8 imp_port; 2297 u8 cpu_port; 2298 u8 vta_regs[3]; 2299 u8 arl_bins; 2300 u16 arl_buckets; 2301 u8 duplex_reg; 2302 u8 jumbo_pm_reg; 2303 u8 jumbo_size_reg; 2304 }; 2305 2306 #define B53_VTA_REGS \ 2307 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2308 #define B53_VTA_REGS_9798 \ 2309 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2310 #define B53_VTA_REGS_63XX \ 2311 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2312 2313 static const struct b53_chip_data b53_switch_chips[] = { 2314 { 2315 .chip_id = BCM5325_DEVICE_ID, 2316 .dev_name = "BCM5325", 2317 .vlans = 16, 2318 .enabled_ports = 0x3f, 2319 .arl_bins = 2, 2320 .arl_buckets = 1024, 2321 .imp_port = 5, 2322 .duplex_reg = B53_DUPLEX_STAT_FE, 2323 }, 2324 { 2325 .chip_id = BCM5365_DEVICE_ID, 2326 .dev_name = "BCM5365", 2327 .vlans = 256, 2328 .enabled_ports = 0x3f, 2329 .arl_bins = 2, 2330 .arl_buckets = 1024, 2331 .imp_port = 5, 2332 .duplex_reg = B53_DUPLEX_STAT_FE, 2333 }, 2334 { 2335 .chip_id = BCM5389_DEVICE_ID, 2336 .dev_name = "BCM5389", 2337 .vlans = 4096, 2338 .enabled_ports = 0x11f, 2339 .arl_bins = 4, 2340 .arl_buckets = 1024, 2341 .imp_port = 8, 2342 .vta_regs = B53_VTA_REGS, 2343 .duplex_reg = B53_DUPLEX_STAT_GE, 2344 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2345 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2346 }, 2347 { 2348 .chip_id = BCM5395_DEVICE_ID, 2349 .dev_name = "BCM5395", 2350 .vlans = 4096, 2351 .enabled_ports = 0x11f, 2352 .arl_bins = 4, 2353 .arl_buckets = 1024, 2354 .imp_port = 8, 2355 .vta_regs = B53_VTA_REGS, 2356 .duplex_reg = B53_DUPLEX_STAT_GE, 2357 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2358 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2359 }, 2360 { 2361 .chip_id = BCM5397_DEVICE_ID, 2362 .dev_name = "BCM5397", 2363 .vlans = 4096, 2364 .enabled_ports = 0x11f, 2365 .arl_bins = 4, 2366 .arl_buckets = 1024, 2367 .imp_port = 8, 2368 .vta_regs = B53_VTA_REGS_9798, 2369 .duplex_reg = B53_DUPLEX_STAT_GE, 2370 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2371 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2372 }, 2373 { 2374 .chip_id = BCM5398_DEVICE_ID, 2375 .dev_name = "BCM5398", 2376 .vlans = 4096, 2377 .enabled_ports = 0x17f, 2378 .arl_bins = 4, 2379 .arl_buckets = 1024, 2380 .imp_port = 8, 2381 .vta_regs = B53_VTA_REGS_9798, 2382 .duplex_reg = B53_DUPLEX_STAT_GE, 2383 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2384 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2385 }, 2386 { 2387 .chip_id = BCM53115_DEVICE_ID, 2388 .dev_name = "BCM53115", 2389 .vlans = 4096, 2390 .enabled_ports = 0x11f, 2391 .arl_bins = 4, 2392 .arl_buckets = 1024, 2393 .vta_regs = B53_VTA_REGS, 2394 .imp_port = 8, 2395 .duplex_reg = B53_DUPLEX_STAT_GE, 2396 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2397 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2398 }, 2399 { 2400 .chip_id = BCM53125_DEVICE_ID, 2401 .dev_name = "BCM53125", 2402 .vlans = 4096, 2403 .enabled_ports = 0x1ff, 2404 .arl_bins = 4, 2405 .arl_buckets = 1024, 2406 .imp_port = 8, 2407 .vta_regs = B53_VTA_REGS, 2408 .duplex_reg = B53_DUPLEX_STAT_GE, 2409 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2410 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2411 }, 2412 { 2413 .chip_id = BCM53128_DEVICE_ID, 2414 .dev_name = "BCM53128", 2415 .vlans = 4096, 2416 .enabled_ports = 0x1ff, 2417 .arl_bins = 4, 2418 .arl_buckets = 1024, 2419 .imp_port = 8, 2420 .vta_regs = B53_VTA_REGS, 2421 .duplex_reg = B53_DUPLEX_STAT_GE, 2422 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2423 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2424 }, 2425 { 2426 .chip_id = BCM63XX_DEVICE_ID, 2427 .dev_name = "BCM63xx", 2428 .vlans = 4096, 2429 .enabled_ports = 0, /* pdata must provide them */ 2430 .arl_bins = 4, 2431 .arl_buckets = 1024, 2432 .imp_port = 8, 2433 .vta_regs = B53_VTA_REGS_63XX, 2434 .duplex_reg = B53_DUPLEX_STAT_63XX, 2435 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2436 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2437 }, 2438 { 2439 .chip_id = BCM53010_DEVICE_ID, 2440 .dev_name = "BCM53010", 2441 .vlans = 4096, 2442 .enabled_ports = 0x1bf, 2443 .arl_bins = 4, 2444 .arl_buckets = 1024, 2445 .imp_port = 8, 2446 .vta_regs = B53_VTA_REGS, 2447 .duplex_reg = B53_DUPLEX_STAT_GE, 2448 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2449 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2450 }, 2451 { 2452 .chip_id = BCM53011_DEVICE_ID, 2453 .dev_name = "BCM53011", 2454 .vlans = 4096, 2455 .enabled_ports = 0x1bf, 2456 .arl_bins = 4, 2457 .arl_buckets = 1024, 2458 .imp_port = 8, 2459 .vta_regs = B53_VTA_REGS, 2460 .duplex_reg = B53_DUPLEX_STAT_GE, 2461 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2462 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2463 }, 2464 { 2465 .chip_id = BCM53012_DEVICE_ID, 2466 .dev_name = "BCM53012", 2467 .vlans = 4096, 2468 .enabled_ports = 0x1bf, 2469 .arl_bins = 4, 2470 .arl_buckets = 1024, 2471 .imp_port = 8, 2472 .vta_regs = B53_VTA_REGS, 2473 .duplex_reg = B53_DUPLEX_STAT_GE, 2474 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2475 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2476 }, 2477 { 2478 .chip_id = BCM53018_DEVICE_ID, 2479 .dev_name = "BCM53018", 2480 .vlans = 4096, 2481 .enabled_ports = 0x1bf, 2482 .arl_bins = 4, 2483 .arl_buckets = 1024, 2484 .imp_port = 8, 2485 .vta_regs = B53_VTA_REGS, 2486 .duplex_reg = B53_DUPLEX_STAT_GE, 2487 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2488 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2489 }, 2490 { 2491 .chip_id = BCM53019_DEVICE_ID, 2492 .dev_name = "BCM53019", 2493 .vlans = 4096, 2494 .enabled_ports = 0x1bf, 2495 .arl_bins = 4, 2496 .arl_buckets = 1024, 2497 .imp_port = 8, 2498 .vta_regs = B53_VTA_REGS, 2499 .duplex_reg = B53_DUPLEX_STAT_GE, 2500 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2501 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2502 }, 2503 { 2504 .chip_id = BCM58XX_DEVICE_ID, 2505 .dev_name = "BCM585xx/586xx/88312", 2506 .vlans = 4096, 2507 .enabled_ports = 0x1ff, 2508 .arl_bins = 4, 2509 .arl_buckets = 1024, 2510 .imp_port = 8, 2511 .vta_regs = B53_VTA_REGS, 2512 .duplex_reg = B53_DUPLEX_STAT_GE, 2513 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2514 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2515 }, 2516 { 2517 .chip_id = BCM583XX_DEVICE_ID, 2518 .dev_name = "BCM583xx/11360", 2519 .vlans = 4096, 2520 .enabled_ports = 0x103, 2521 .arl_bins = 4, 2522 .arl_buckets = 1024, 2523 .imp_port = 8, 2524 .vta_regs = B53_VTA_REGS, 2525 .duplex_reg = B53_DUPLEX_STAT_GE, 2526 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2527 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2528 }, 2529 /* Starfighter 2 */ 2530 { 2531 .chip_id = BCM4908_DEVICE_ID, 2532 .dev_name = "BCM4908", 2533 .vlans = 4096, 2534 .enabled_ports = 0x1bf, 2535 .arl_bins = 4, 2536 .arl_buckets = 256, 2537 .imp_port = 8, 2538 .vta_regs = B53_VTA_REGS, 2539 .duplex_reg = B53_DUPLEX_STAT_GE, 2540 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2541 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2542 }, 2543 { 2544 .chip_id = BCM7445_DEVICE_ID, 2545 .dev_name = "BCM7445", 2546 .vlans = 4096, 2547 .enabled_ports = 0x1ff, 2548 .arl_bins = 4, 2549 .arl_buckets = 1024, 2550 .imp_port = 8, 2551 .vta_regs = B53_VTA_REGS, 2552 .duplex_reg = B53_DUPLEX_STAT_GE, 2553 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2554 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2555 }, 2556 { 2557 .chip_id = BCM7278_DEVICE_ID, 2558 .dev_name = "BCM7278", 2559 .vlans = 4096, 2560 .enabled_ports = 0x1ff, 2561 .arl_bins = 4, 2562 .arl_buckets = 256, 2563 .imp_port = 8, 2564 .vta_regs = B53_VTA_REGS, 2565 .duplex_reg = B53_DUPLEX_STAT_GE, 2566 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2567 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2568 }, 2569 }; 2570 2571 static int b53_switch_init(struct b53_device *dev) 2572 { 2573 unsigned int i; 2574 int ret; 2575 2576 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2577 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2578 2579 if (chip->chip_id == dev->chip_id) { 2580 if (!dev->enabled_ports) 2581 dev->enabled_ports = chip->enabled_ports; 2582 dev->name = chip->dev_name; 2583 dev->duplex_reg = chip->duplex_reg; 2584 dev->vta_regs[0] = chip->vta_regs[0]; 2585 dev->vta_regs[1] = chip->vta_regs[1]; 2586 dev->vta_regs[2] = chip->vta_regs[2]; 2587 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2588 dev->imp_port = chip->imp_port; 2589 dev->num_vlans = chip->vlans; 2590 dev->num_arl_bins = chip->arl_bins; 2591 dev->num_arl_buckets = chip->arl_buckets; 2592 break; 2593 } 2594 } 2595 2596 /* check which BCM5325x version we have */ 2597 if (is5325(dev)) { 2598 u8 vc4; 2599 2600 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2601 2602 /* check reserved bits */ 2603 switch (vc4 & 3) { 2604 case 1: 2605 /* BCM5325E */ 2606 break; 2607 case 3: 2608 /* BCM5325F - do not use port 4 */ 2609 dev->enabled_ports &= ~BIT(4); 2610 break; 2611 default: 2612 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2613 #ifndef CONFIG_BCM47XX 2614 /* BCM5325M */ 2615 return -EINVAL; 2616 #else 2617 break; 2618 #endif 2619 } 2620 } 2621 2622 dev->num_ports = fls(dev->enabled_ports); 2623 2624 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); 2625 2626 /* Include non standard CPU port built-in PHYs to be probed */ 2627 if (is539x(dev) || is531x5(dev)) { 2628 for (i = 0; i < dev->num_ports; i++) { 2629 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2630 !b53_possible_cpu_port(dev->ds, i)) 2631 dev->ds->phys_mii_mask |= BIT(i); 2632 } 2633 } 2634 2635 dev->ports = devm_kcalloc(dev->dev, 2636 dev->num_ports, sizeof(struct b53_port), 2637 GFP_KERNEL); 2638 if (!dev->ports) 2639 return -ENOMEM; 2640 2641 dev->vlans = devm_kcalloc(dev->dev, 2642 dev->num_vlans, sizeof(struct b53_vlan), 2643 GFP_KERNEL); 2644 if (!dev->vlans) 2645 return -ENOMEM; 2646 2647 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2648 if (dev->reset_gpio >= 0) { 2649 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2650 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2651 if (ret) 2652 return ret; 2653 } 2654 2655 return 0; 2656 } 2657 2658 struct b53_device *b53_switch_alloc(struct device *base, 2659 const struct b53_io_ops *ops, 2660 void *priv) 2661 { 2662 struct dsa_switch *ds; 2663 struct b53_device *dev; 2664 2665 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2666 if (!ds) 2667 return NULL; 2668 2669 ds->dev = base; 2670 2671 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2672 if (!dev) 2673 return NULL; 2674 2675 ds->priv = dev; 2676 dev->dev = base; 2677 2678 dev->ds = ds; 2679 dev->priv = priv; 2680 dev->ops = ops; 2681 ds->ops = &b53_switch_ops; 2682 dev->vlan_enabled = true; 2683 /* Let DSA handle the case were multiple bridges span the same switch 2684 * device and different VLAN awareness settings are requested, which 2685 * would be breaking filtering semantics for any of the other bridge 2686 * devices. (not hardware supported) 2687 */ 2688 ds->vlan_filtering_is_global = true; 2689 2690 mutex_init(&dev->reg_mutex); 2691 mutex_init(&dev->stats_mutex); 2692 mutex_init(&dev->arl_mutex); 2693 2694 return dev; 2695 } 2696 EXPORT_SYMBOL(b53_switch_alloc); 2697 2698 int b53_switch_detect(struct b53_device *dev) 2699 { 2700 u32 id32; 2701 u16 tmp; 2702 u8 id8; 2703 int ret; 2704 2705 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2706 if (ret) 2707 return ret; 2708 2709 switch (id8) { 2710 case 0: 2711 /* BCM5325 and BCM5365 do not have this register so reads 2712 * return 0. But the read operation did succeed, so assume this 2713 * is one of them. 2714 * 2715 * Next check if we can write to the 5325's VTA register; for 2716 * 5365 it is read only. 2717 */ 2718 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2719 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2720 2721 if (tmp == 0xf) 2722 dev->chip_id = BCM5325_DEVICE_ID; 2723 else 2724 dev->chip_id = BCM5365_DEVICE_ID; 2725 break; 2726 case BCM5389_DEVICE_ID: 2727 case BCM5395_DEVICE_ID: 2728 case BCM5397_DEVICE_ID: 2729 case BCM5398_DEVICE_ID: 2730 dev->chip_id = id8; 2731 break; 2732 default: 2733 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2734 if (ret) 2735 return ret; 2736 2737 switch (id32) { 2738 case BCM53115_DEVICE_ID: 2739 case BCM53125_DEVICE_ID: 2740 case BCM53128_DEVICE_ID: 2741 case BCM53010_DEVICE_ID: 2742 case BCM53011_DEVICE_ID: 2743 case BCM53012_DEVICE_ID: 2744 case BCM53018_DEVICE_ID: 2745 case BCM53019_DEVICE_ID: 2746 dev->chip_id = id32; 2747 break; 2748 default: 2749 dev_err(dev->dev, 2750 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2751 id8, id32); 2752 return -ENODEV; 2753 } 2754 } 2755 2756 if (dev->chip_id == BCM5325_DEVICE_ID) 2757 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2758 &dev->core_rev); 2759 else 2760 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2761 &dev->core_rev); 2762 } 2763 EXPORT_SYMBOL(b53_switch_detect); 2764 2765 int b53_switch_register(struct b53_device *dev) 2766 { 2767 int ret; 2768 2769 if (dev->pdata) { 2770 dev->chip_id = dev->pdata->chip_id; 2771 dev->enabled_ports = dev->pdata->enabled_ports; 2772 } 2773 2774 if (!dev->chip_id && b53_switch_detect(dev)) 2775 return -EINVAL; 2776 2777 ret = b53_switch_init(dev); 2778 if (ret) 2779 return ret; 2780 2781 dev_info(dev->dev, "found switch: %s, rev %i\n", 2782 dev->name, dev->core_rev); 2783 2784 return dsa_register_switch(dev->ds); 2785 } 2786 EXPORT_SYMBOL(b53_switch_register); 2787 2788 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2789 MODULE_DESCRIPTION("B53 switch library"); 2790 MODULE_LICENSE("Dual BSD/GPL"); 2791