1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if_bridge.h> 32 #include <net/dsa.h> 33 34 #include "b53_regs.h" 35 #include "b53_priv.h" 36 37 struct b53_mib_desc { 38 u8 size; 39 u8 offset; 40 const char *name; 41 }; 42 43 /* BCM5365 MIB counters */ 44 static const struct b53_mib_desc b53_mibs_65[] = { 45 { 8, 0x00, "TxOctets" }, 46 { 4, 0x08, "TxDropPkts" }, 47 { 4, 0x10, "TxBroadcastPkts" }, 48 { 4, 0x14, "TxMulticastPkts" }, 49 { 4, 0x18, "TxUnicastPkts" }, 50 { 4, 0x1c, "TxCollisions" }, 51 { 4, 0x20, "TxSingleCollision" }, 52 { 4, 0x24, "TxMultipleCollision" }, 53 { 4, 0x28, "TxDeferredTransmit" }, 54 { 4, 0x2c, "TxLateCollision" }, 55 { 4, 0x30, "TxExcessiveCollision" }, 56 { 4, 0x38, "TxPausePkts" }, 57 { 8, 0x44, "RxOctets" }, 58 { 4, 0x4c, "RxUndersizePkts" }, 59 { 4, 0x50, "RxPausePkts" }, 60 { 4, 0x54, "Pkts64Octets" }, 61 { 4, 0x58, "Pkts65to127Octets" }, 62 { 4, 0x5c, "Pkts128to255Octets" }, 63 { 4, 0x60, "Pkts256to511Octets" }, 64 { 4, 0x64, "Pkts512to1023Octets" }, 65 { 4, 0x68, "Pkts1024to1522Octets" }, 66 { 4, 0x6c, "RxOversizePkts" }, 67 { 4, 0x70, "RxJabbers" }, 68 { 4, 0x74, "RxAlignmentErrors" }, 69 { 4, 0x78, "RxFCSErrors" }, 70 { 8, 0x7c, "RxGoodOctets" }, 71 { 4, 0x84, "RxDropPkts" }, 72 { 4, 0x88, "RxUnicastPkts" }, 73 { 4, 0x8c, "RxMulticastPkts" }, 74 { 4, 0x90, "RxBroadcastPkts" }, 75 { 4, 0x94, "RxSAChanges" }, 76 { 4, 0x98, "RxFragments" }, 77 }; 78 79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 80 81 /* BCM63xx MIB counters */ 82 static const struct b53_mib_desc b53_mibs_63xx[] = { 83 { 8, 0x00, "TxOctets" }, 84 { 4, 0x08, "TxDropPkts" }, 85 { 4, 0x0c, "TxQoSPkts" }, 86 { 4, 0x10, "TxBroadcastPkts" }, 87 { 4, 0x14, "TxMulticastPkts" }, 88 { 4, 0x18, "TxUnicastPkts" }, 89 { 4, 0x1c, "TxCollisions" }, 90 { 4, 0x20, "TxSingleCollision" }, 91 { 4, 0x24, "TxMultipleCollision" }, 92 { 4, 0x28, "TxDeferredTransmit" }, 93 { 4, 0x2c, "TxLateCollision" }, 94 { 4, 0x30, "TxExcessiveCollision" }, 95 { 4, 0x38, "TxPausePkts" }, 96 { 8, 0x3c, "TxQoSOctets" }, 97 { 8, 0x44, "RxOctets" }, 98 { 4, 0x4c, "RxUndersizePkts" }, 99 { 4, 0x50, "RxPausePkts" }, 100 { 4, 0x54, "Pkts64Octets" }, 101 { 4, 0x58, "Pkts65to127Octets" }, 102 { 4, 0x5c, "Pkts128to255Octets" }, 103 { 4, 0x60, "Pkts256to511Octets" }, 104 { 4, 0x64, "Pkts512to1023Octets" }, 105 { 4, 0x68, "Pkts1024to1522Octets" }, 106 { 4, 0x6c, "RxOversizePkts" }, 107 { 4, 0x70, "RxJabbers" }, 108 { 4, 0x74, "RxAlignmentErrors" }, 109 { 4, 0x78, "RxFCSErrors" }, 110 { 8, 0x7c, "RxGoodOctets" }, 111 { 4, 0x84, "RxDropPkts" }, 112 { 4, 0x88, "RxUnicastPkts" }, 113 { 4, 0x8c, "RxMulticastPkts" }, 114 { 4, 0x90, "RxBroadcastPkts" }, 115 { 4, 0x94, "RxSAChanges" }, 116 { 4, 0x98, "RxFragments" }, 117 { 4, 0xa0, "RxSymbolErrors" }, 118 { 4, 0xa4, "RxQoSPkts" }, 119 { 8, 0xa8, "RxQoSOctets" }, 120 { 4, 0xb0, "Pkts1523to2047Octets" }, 121 { 4, 0xb4, "Pkts2048to4095Octets" }, 122 { 4, 0xb8, "Pkts4096to8191Octets" }, 123 { 4, 0xbc, "Pkts8192to9728Octets" }, 124 { 4, 0xc0, "RxDiscarded" }, 125 }; 126 127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 128 129 /* MIB counters */ 130 static const struct b53_mib_desc b53_mibs[] = { 131 { 8, 0x00, "TxOctets" }, 132 { 4, 0x08, "TxDropPkts" }, 133 { 4, 0x10, "TxBroadcastPkts" }, 134 { 4, 0x14, "TxMulticastPkts" }, 135 { 4, 0x18, "TxUnicastPkts" }, 136 { 4, 0x1c, "TxCollisions" }, 137 { 4, 0x20, "TxSingleCollision" }, 138 { 4, 0x24, "TxMultipleCollision" }, 139 { 4, 0x28, "TxDeferredTransmit" }, 140 { 4, 0x2c, "TxLateCollision" }, 141 { 4, 0x30, "TxExcessiveCollision" }, 142 { 4, 0x38, "TxPausePkts" }, 143 { 8, 0x50, "RxOctets" }, 144 { 4, 0x58, "RxUndersizePkts" }, 145 { 4, 0x5c, "RxPausePkts" }, 146 { 4, 0x60, "Pkts64Octets" }, 147 { 4, 0x64, "Pkts65to127Octets" }, 148 { 4, 0x68, "Pkts128to255Octets" }, 149 { 4, 0x6c, "Pkts256to511Octets" }, 150 { 4, 0x70, "Pkts512to1023Octets" }, 151 { 4, 0x74, "Pkts1024to1522Octets" }, 152 { 4, 0x78, "RxOversizePkts" }, 153 { 4, 0x7c, "RxJabbers" }, 154 { 4, 0x80, "RxAlignmentErrors" }, 155 { 4, 0x84, "RxFCSErrors" }, 156 { 8, 0x88, "RxGoodOctets" }, 157 { 4, 0x90, "RxDropPkts" }, 158 { 4, 0x94, "RxUnicastPkts" }, 159 { 4, 0x98, "RxMulticastPkts" }, 160 { 4, 0x9c, "RxBroadcastPkts" }, 161 { 4, 0xa0, "RxSAChanges" }, 162 { 4, 0xa4, "RxFragments" }, 163 { 4, 0xa8, "RxJumboPkts" }, 164 { 4, 0xac, "RxSymbolErrors" }, 165 { 4, 0xc0, "RxDiscarded" }, 166 }; 167 168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 169 170 static const struct b53_mib_desc b53_mibs_58xx[] = { 171 { 8, 0x00, "TxOctets" }, 172 { 4, 0x08, "TxDropPkts" }, 173 { 4, 0x0c, "TxQPKTQ0" }, 174 { 4, 0x10, "TxBroadcastPkts" }, 175 { 4, 0x14, "TxMulticastPkts" }, 176 { 4, 0x18, "TxUnicastPKts" }, 177 { 4, 0x1c, "TxCollisions" }, 178 { 4, 0x20, "TxSingleCollision" }, 179 { 4, 0x24, "TxMultipleCollision" }, 180 { 4, 0x28, "TxDeferredCollision" }, 181 { 4, 0x2c, "TxLateCollision" }, 182 { 4, 0x30, "TxExcessiveCollision" }, 183 { 4, 0x34, "TxFrameInDisc" }, 184 { 4, 0x38, "TxPausePkts" }, 185 { 4, 0x3c, "TxQPKTQ1" }, 186 { 4, 0x40, "TxQPKTQ2" }, 187 { 4, 0x44, "TxQPKTQ3" }, 188 { 4, 0x48, "TxQPKTQ4" }, 189 { 4, 0x4c, "TxQPKTQ5" }, 190 { 8, 0x50, "RxOctets" }, 191 { 4, 0x58, "RxUndersizePkts" }, 192 { 4, 0x5c, "RxPausePkts" }, 193 { 4, 0x60, "RxPkts64Octets" }, 194 { 4, 0x64, "RxPkts65to127Octets" }, 195 { 4, 0x68, "RxPkts128to255Octets" }, 196 { 4, 0x6c, "RxPkts256to511Octets" }, 197 { 4, 0x70, "RxPkts512to1023Octets" }, 198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 199 { 4, 0x78, "RxOversizePkts" }, 200 { 4, 0x7c, "RxJabbers" }, 201 { 4, 0x80, "RxAlignmentErrors" }, 202 { 4, 0x84, "RxFCSErrors" }, 203 { 8, 0x88, "RxGoodOctets" }, 204 { 4, 0x90, "RxDropPkts" }, 205 { 4, 0x94, "RxUnicastPkts" }, 206 { 4, 0x98, "RxMulticastPkts" }, 207 { 4, 0x9c, "RxBroadcastPkts" }, 208 { 4, 0xa0, "RxSAChanges" }, 209 { 4, 0xa4, "RxFragments" }, 210 { 4, 0xa8, "RxJumboPkt" }, 211 { 4, 0xac, "RxSymblErr" }, 212 { 4, 0xb0, "InRangeErrCount" }, 213 { 4, 0xb4, "OutRangeErrCount" }, 214 { 4, 0xb8, "EEELpiEvent" }, 215 { 4, 0xbc, "EEELpiDuration" }, 216 { 4, 0xc0, "RxDiscard" }, 217 { 4, 0xc8, "TxQPKTQ6" }, 218 { 4, 0xcc, "TxQPKTQ7" }, 219 { 4, 0xd0, "TxPkts64Octets" }, 220 { 4, 0xd4, "TxPkts65to127Octets" }, 221 { 4, 0xd8, "TxPkts128to255Octets" }, 222 { 4, 0xdc, "TxPkts256to511Ocets" }, 223 { 4, 0xe0, "TxPkts512to1023Ocets" }, 224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 225 }; 226 227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 228 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 230 { 231 unsigned int i; 232 233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 234 235 for (i = 0; i < 10; i++) { 236 u8 vta; 237 238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 239 if (!(vta & VTA_START_CMD)) 240 return 0; 241 242 usleep_range(100, 200); 243 } 244 245 return -EIO; 246 } 247 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 249 struct b53_vlan *vlan) 250 { 251 if (is5325(dev)) { 252 u32 entry = 0; 253 254 if (vlan->members) { 255 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 256 VA_UNTAG_S_25) | vlan->members; 257 if (dev->core_rev >= 3) 258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 259 else 260 entry |= VA_VALID_25; 261 } 262 263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 265 VTA_RW_STATE_WR | VTA_RW_OP_EN); 266 } else if (is5365(dev)) { 267 u16 entry = 0; 268 269 if (vlan->members) 270 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 272 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 275 VTA_RW_STATE_WR | VTA_RW_OP_EN); 276 } else { 277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 279 (vlan->untag << VTE_UNTAG_S) | vlan->members); 280 281 b53_do_vlan_op(dev, VTA_CMD_WRITE); 282 } 283 284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 285 vid, vlan->members, vlan->untag); 286 } 287 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 289 struct b53_vlan *vlan) 290 { 291 if (is5325(dev)) { 292 u32 entry = 0; 293 294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 295 VTA_RW_STATE_RD | VTA_RW_OP_EN); 296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 297 298 if (dev->core_rev >= 3) 299 vlan->valid = !!(entry & VA_VALID_25_R4); 300 else 301 vlan->valid = !!(entry & VA_VALID_25); 302 vlan->members = entry & VA_MEMBER_MASK; 303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 304 305 } else if (is5365(dev)) { 306 u16 entry = 0; 307 308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 309 VTA_RW_STATE_WR | VTA_RW_OP_EN); 310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 311 312 vlan->valid = !!(entry & VA_VALID_65); 313 vlan->members = entry & VA_MEMBER_MASK; 314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 315 } else { 316 u32 entry = 0; 317 318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 319 b53_do_vlan_op(dev, VTA_CMD_READ); 320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 321 vlan->members = entry & VTE_MEMBERS; 322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 323 vlan->valid = true; 324 } 325 } 326 327 static void b53_set_forwarding(struct b53_device *dev, int enable) 328 { 329 u8 mgmt; 330 331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 332 333 if (enable) 334 mgmt |= SM_SW_FWD_EN; 335 else 336 mgmt &= ~SM_SW_FWD_EN; 337 338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 339 340 /* Include IMP port in dumb forwarding mode 341 */ 342 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 343 mgmt |= B53_MII_DUMB_FWDG_EN; 344 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 345 } 346 347 static void b53_enable_vlan(struct b53_device *dev, bool enable, 348 bool enable_filtering) 349 { 350 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 351 352 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 353 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 354 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 355 356 if (is5325(dev) || is5365(dev)) { 357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 359 } else if (is63xx(dev)) { 360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 362 } else { 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 364 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 365 } 366 367 mgmt &= ~SM_SW_FWD_MODE; 368 369 if (enable) { 370 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 371 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 372 vc4 &= ~VC4_ING_VID_CHECK_MASK; 373 if (enable_filtering) { 374 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 375 vc5 |= VC5_DROP_VTABLE_MISS; 376 } else { 377 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 378 vc5 &= ~VC5_DROP_VTABLE_MISS; 379 } 380 381 if (is5325(dev)) 382 vc0 &= ~VC0_RESERVED_1; 383 384 if (is5325(dev) || is5365(dev)) 385 vc1 |= VC1_RX_MCST_TAG_EN; 386 387 } else { 388 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 389 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 390 vc4 &= ~VC4_ING_VID_CHECK_MASK; 391 vc5 &= ~VC5_DROP_VTABLE_MISS; 392 393 if (is5325(dev) || is5365(dev)) 394 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 395 else 396 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 397 398 if (is5325(dev) || is5365(dev)) 399 vc1 &= ~VC1_RX_MCST_TAG_EN; 400 } 401 402 if (!is5325(dev) && !is5365(dev)) 403 vc5 &= ~VC5_VID_FFF_EN; 404 405 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 406 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 407 408 if (is5325(dev) || is5365(dev)) { 409 /* enable the high 8 bit vid check on 5325 */ 410 if (is5325(dev) && enable) 411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 412 VC3_HIGH_8BIT_EN); 413 else 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 415 416 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 418 } else if (is63xx(dev)) { 419 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 422 } else { 423 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 425 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 426 } 427 428 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 429 430 dev->vlan_enabled = enable; 431 } 432 433 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 434 { 435 u32 port_mask = 0; 436 u16 max_size = JMS_MIN_SIZE; 437 438 if (is5325(dev) || is5365(dev)) 439 return -EINVAL; 440 441 if (enable) { 442 port_mask = dev->enabled_ports; 443 max_size = JMS_MAX_SIZE; 444 if (allow_10_100) 445 port_mask |= JPM_10_100_JUMBO_EN; 446 } 447 448 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 449 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 450 } 451 452 static int b53_flush_arl(struct b53_device *dev, u8 mask) 453 { 454 unsigned int i; 455 456 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 457 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 458 459 for (i = 0; i < 10; i++) { 460 u8 fast_age_ctrl; 461 462 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 463 &fast_age_ctrl); 464 465 if (!(fast_age_ctrl & FAST_AGE_DONE)) 466 goto out; 467 468 msleep(1); 469 } 470 471 return -ETIMEDOUT; 472 out: 473 /* Only age dynamic entries (default behavior) */ 474 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 475 return 0; 476 } 477 478 static int b53_fast_age_port(struct b53_device *dev, int port) 479 { 480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 481 482 return b53_flush_arl(dev, FAST_AGE_PORT); 483 } 484 485 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 486 { 487 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 488 489 return b53_flush_arl(dev, FAST_AGE_VLAN); 490 } 491 492 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 493 { 494 struct b53_device *dev = ds->priv; 495 unsigned int i; 496 u16 pvlan; 497 498 /* Enable the IMP port to be in the same VLAN as the other ports 499 * on a per-port basis such that we only have Port i and IMP in 500 * the same VLAN. 501 */ 502 b53_for_each_port(dev, i) { 503 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 504 pvlan |= BIT(cpu_port); 505 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 506 } 507 } 508 EXPORT_SYMBOL(b53_imp_vlan_setup); 509 510 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 511 { 512 struct b53_device *dev = ds->priv; 513 unsigned int cpu_port; 514 int ret = 0; 515 u16 pvlan; 516 517 if (!dsa_is_user_port(ds, port)) 518 return 0; 519 520 cpu_port = ds->ports[port].cpu_dp->index; 521 522 if (dev->ops->irq_enable) 523 ret = dev->ops->irq_enable(dev, port); 524 if (ret) 525 return ret; 526 527 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 528 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 529 530 /* Set this port, and only this one to be in the default VLAN, 531 * if member of a bridge, restore its membership prior to 532 * bringing down this port. 533 */ 534 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 535 pvlan &= ~0x1ff; 536 pvlan |= BIT(port); 537 pvlan |= dev->ports[port].vlan_ctl_mask; 538 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 539 540 b53_imp_vlan_setup(ds, cpu_port); 541 542 /* If EEE was enabled, restore it */ 543 if (dev->ports[port].eee.eee_enabled) 544 b53_eee_enable_set(ds, port, true); 545 546 return 0; 547 } 548 EXPORT_SYMBOL(b53_enable_port); 549 550 void b53_disable_port(struct dsa_switch *ds, int port) 551 { 552 struct b53_device *dev = ds->priv; 553 u8 reg; 554 555 /* Disable Tx/Rx for the port */ 556 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 557 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 558 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 559 560 if (dev->ops->irq_disable) 561 dev->ops->irq_disable(dev, port); 562 } 563 EXPORT_SYMBOL(b53_disable_port); 564 565 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 566 { 567 bool tag_en = !(ds->ops->get_tag_protocol(ds, port) == 568 DSA_TAG_PROTO_NONE); 569 struct b53_device *dev = ds->priv; 570 u8 hdr_ctl, val; 571 u16 reg; 572 573 /* Resolve which bit controls the Broadcom tag */ 574 switch (port) { 575 case 8: 576 val = BRCM_HDR_P8_EN; 577 break; 578 case 7: 579 val = BRCM_HDR_P7_EN; 580 break; 581 case 5: 582 val = BRCM_HDR_P5_EN; 583 break; 584 default: 585 val = 0; 586 break; 587 } 588 589 /* Enable Broadcom tags for IMP port */ 590 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 591 if (tag_en) 592 hdr_ctl |= val; 593 else 594 hdr_ctl &= ~val; 595 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 596 597 /* Registers below are only accessible on newer devices */ 598 if (!is58xx(dev)) 599 return; 600 601 /* Enable reception Broadcom tag for CPU TX (switch RX) to 602 * allow us to tag outgoing frames 603 */ 604 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 605 if (tag_en) 606 reg &= ~BIT(port); 607 else 608 reg |= BIT(port); 609 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 610 611 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 612 * allow delivering frames to the per-port net_devices 613 */ 614 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 615 if (tag_en) 616 reg &= ~BIT(port); 617 else 618 reg |= BIT(port); 619 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 620 } 621 EXPORT_SYMBOL(b53_brcm_hdr_setup); 622 623 static void b53_enable_cpu_port(struct b53_device *dev, int port) 624 { 625 u8 port_ctrl; 626 627 /* BCM5325 CPU port is at 8 */ 628 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 629 port = B53_CPU_PORT; 630 631 port_ctrl = PORT_CTRL_RX_BCST_EN | 632 PORT_CTRL_RX_MCST_EN | 633 PORT_CTRL_RX_UCST_EN; 634 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 635 636 b53_brcm_hdr_setup(dev->ds, port); 637 } 638 639 static void b53_enable_mib(struct b53_device *dev) 640 { 641 u8 gc; 642 643 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 644 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 645 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 646 } 647 648 static u16 b53_default_pvid(struct b53_device *dev) 649 { 650 if (is5325(dev) || is5365(dev)) 651 return 1; 652 else 653 return 0; 654 } 655 656 int b53_configure_vlan(struct dsa_switch *ds) 657 { 658 struct b53_device *dev = ds->priv; 659 struct b53_vlan vl = { 0 }; 660 int i, def_vid; 661 662 def_vid = b53_default_pvid(dev); 663 664 /* clear all vlan entries */ 665 if (is5325(dev) || is5365(dev)) { 666 for (i = def_vid; i < dev->num_vlans; i++) 667 b53_set_vlan_entry(dev, i, &vl); 668 } else { 669 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 670 } 671 672 b53_enable_vlan(dev, false, ds->vlan_filtering); 673 674 b53_for_each_port(dev, i) 675 b53_write16(dev, B53_VLAN_PAGE, 676 B53_VLAN_PORT_DEF_TAG(i), def_vid); 677 678 if (!is5325(dev) && !is5365(dev)) 679 b53_set_jumbo(dev, dev->enable_jumbo, false); 680 681 return 0; 682 } 683 EXPORT_SYMBOL(b53_configure_vlan); 684 685 static void b53_switch_reset_gpio(struct b53_device *dev) 686 { 687 int gpio = dev->reset_gpio; 688 689 if (gpio < 0) 690 return; 691 692 /* Reset sequence: RESET low(50ms)->high(20ms) 693 */ 694 gpio_set_value(gpio, 0); 695 mdelay(50); 696 697 gpio_set_value(gpio, 1); 698 mdelay(20); 699 700 dev->current_page = 0xff; 701 } 702 703 static int b53_switch_reset(struct b53_device *dev) 704 { 705 unsigned int timeout = 1000; 706 u8 mgmt, reg; 707 708 b53_switch_reset_gpio(dev); 709 710 if (is539x(dev)) { 711 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 712 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 713 } 714 715 /* This is specific to 58xx devices here, do not use is58xx() which 716 * covers the larger Starfigther 2 family, including 7445/7278 which 717 * still use this driver as a library and need to perform the reset 718 * earlier. 719 */ 720 if (dev->chip_id == BCM58XX_DEVICE_ID || 721 dev->chip_id == BCM583XX_DEVICE_ID) { 722 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 723 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 724 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 725 726 do { 727 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 728 if (!(reg & SW_RST)) 729 break; 730 731 usleep_range(1000, 2000); 732 } while (timeout-- > 0); 733 734 if (timeout == 0) 735 return -ETIMEDOUT; 736 } 737 738 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 739 740 if (!(mgmt & SM_SW_FWD_EN)) { 741 mgmt &= ~SM_SW_FWD_MODE; 742 mgmt |= SM_SW_FWD_EN; 743 744 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 745 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 746 747 if (!(mgmt & SM_SW_FWD_EN)) { 748 dev_err(dev->dev, "Failed to enable switch!\n"); 749 return -EINVAL; 750 } 751 } 752 753 b53_enable_mib(dev); 754 755 return b53_flush_arl(dev, FAST_AGE_STATIC); 756 } 757 758 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 759 { 760 struct b53_device *priv = ds->priv; 761 u16 value = 0; 762 int ret; 763 764 if (priv->ops->phy_read16) 765 ret = priv->ops->phy_read16(priv, addr, reg, &value); 766 else 767 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 768 reg * 2, &value); 769 770 return ret ? ret : value; 771 } 772 773 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 774 { 775 struct b53_device *priv = ds->priv; 776 777 if (priv->ops->phy_write16) 778 return priv->ops->phy_write16(priv, addr, reg, val); 779 780 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 781 } 782 783 static int b53_reset_switch(struct b53_device *priv) 784 { 785 /* reset vlans */ 786 priv->enable_jumbo = false; 787 788 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 789 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 790 791 priv->serdes_lane = B53_INVALID_LANE; 792 793 return b53_switch_reset(priv); 794 } 795 796 static int b53_apply_config(struct b53_device *priv) 797 { 798 /* disable switching */ 799 b53_set_forwarding(priv, 0); 800 801 b53_configure_vlan(priv->ds); 802 803 /* enable switching */ 804 b53_set_forwarding(priv, 1); 805 806 return 0; 807 } 808 809 static void b53_reset_mib(struct b53_device *priv) 810 { 811 u8 gc; 812 813 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 814 815 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 816 msleep(1); 817 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 818 msleep(1); 819 } 820 821 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 822 { 823 if (is5365(dev)) 824 return b53_mibs_65; 825 else if (is63xx(dev)) 826 return b53_mibs_63xx; 827 else if (is58xx(dev)) 828 return b53_mibs_58xx; 829 else 830 return b53_mibs; 831 } 832 833 static unsigned int b53_get_mib_size(struct b53_device *dev) 834 { 835 if (is5365(dev)) 836 return B53_MIBS_65_SIZE; 837 else if (is63xx(dev)) 838 return B53_MIBS_63XX_SIZE; 839 else if (is58xx(dev)) 840 return B53_MIBS_58XX_SIZE; 841 else 842 return B53_MIBS_SIZE; 843 } 844 845 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 846 { 847 /* These ports typically do not have built-in PHYs */ 848 switch (port) { 849 case B53_CPU_PORT_25: 850 case 7: 851 case B53_CPU_PORT: 852 return NULL; 853 } 854 855 return mdiobus_get_phy(ds->slave_mii_bus, port); 856 } 857 858 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 859 uint8_t *data) 860 { 861 struct b53_device *dev = ds->priv; 862 const struct b53_mib_desc *mibs = b53_get_mib(dev); 863 unsigned int mib_size = b53_get_mib_size(dev); 864 struct phy_device *phydev; 865 unsigned int i; 866 867 if (stringset == ETH_SS_STATS) { 868 for (i = 0; i < mib_size; i++) 869 strlcpy(data + i * ETH_GSTRING_LEN, 870 mibs[i].name, ETH_GSTRING_LEN); 871 } else if (stringset == ETH_SS_PHY_STATS) { 872 phydev = b53_get_phy_device(ds, port); 873 if (!phydev) 874 return; 875 876 phy_ethtool_get_strings(phydev, data); 877 } 878 } 879 EXPORT_SYMBOL(b53_get_strings); 880 881 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 882 { 883 struct b53_device *dev = ds->priv; 884 const struct b53_mib_desc *mibs = b53_get_mib(dev); 885 unsigned int mib_size = b53_get_mib_size(dev); 886 const struct b53_mib_desc *s; 887 unsigned int i; 888 u64 val = 0; 889 890 if (is5365(dev) && port == 5) 891 port = 8; 892 893 mutex_lock(&dev->stats_mutex); 894 895 for (i = 0; i < mib_size; i++) { 896 s = &mibs[i]; 897 898 if (s->size == 8) { 899 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 900 } else { 901 u32 val32; 902 903 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 904 &val32); 905 val = val32; 906 } 907 data[i] = (u64)val; 908 } 909 910 mutex_unlock(&dev->stats_mutex); 911 } 912 EXPORT_SYMBOL(b53_get_ethtool_stats); 913 914 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 915 { 916 struct phy_device *phydev; 917 918 phydev = b53_get_phy_device(ds, port); 919 if (!phydev) 920 return; 921 922 phy_ethtool_get_stats(phydev, NULL, data); 923 } 924 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 925 926 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 927 { 928 struct b53_device *dev = ds->priv; 929 struct phy_device *phydev; 930 931 if (sset == ETH_SS_STATS) { 932 return b53_get_mib_size(dev); 933 } else if (sset == ETH_SS_PHY_STATS) { 934 phydev = b53_get_phy_device(ds, port); 935 if (!phydev) 936 return 0; 937 938 return phy_ethtool_get_sset_count(phydev); 939 } 940 941 return 0; 942 } 943 EXPORT_SYMBOL(b53_get_sset_count); 944 945 static int b53_setup(struct dsa_switch *ds) 946 { 947 struct b53_device *dev = ds->priv; 948 unsigned int port; 949 int ret; 950 951 ret = b53_reset_switch(dev); 952 if (ret) { 953 dev_err(ds->dev, "failed to reset switch\n"); 954 return ret; 955 } 956 957 b53_reset_mib(dev); 958 959 ret = b53_apply_config(dev); 960 if (ret) 961 dev_err(ds->dev, "failed to apply configuration\n"); 962 963 /* Configure IMP/CPU port, disable all other ports. Enabled 964 * ports will be configured with .port_enable 965 */ 966 for (port = 0; port < dev->num_ports; port++) { 967 if (dsa_is_cpu_port(ds, port)) 968 b53_enable_cpu_port(dev, port); 969 else 970 b53_disable_port(ds, port); 971 } 972 973 /* Let DSA handle the case were multiple bridges span the same switch 974 * device and different VLAN awareness settings are requested, which 975 * would be breaking filtering semantics for any of the other bridge 976 * devices. (not hardware supported) 977 */ 978 ds->vlan_filtering_is_global = true; 979 980 return ret; 981 } 982 983 static void b53_force_link(struct b53_device *dev, int port, int link) 984 { 985 u8 reg, val, off; 986 987 /* Override the port settings */ 988 if (port == dev->cpu_port) { 989 off = B53_PORT_OVERRIDE_CTRL; 990 val = PORT_OVERRIDE_EN; 991 } else { 992 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 993 val = GMII_PO_EN; 994 } 995 996 b53_read8(dev, B53_CTRL_PAGE, off, ®); 997 reg |= val; 998 if (link) 999 reg |= PORT_OVERRIDE_LINK; 1000 else 1001 reg &= ~PORT_OVERRIDE_LINK; 1002 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1003 } 1004 1005 static void b53_force_port_config(struct b53_device *dev, int port, 1006 int speed, int duplex, int pause) 1007 { 1008 u8 reg, val, off; 1009 1010 /* Override the port settings */ 1011 if (port == dev->cpu_port) { 1012 off = B53_PORT_OVERRIDE_CTRL; 1013 val = PORT_OVERRIDE_EN; 1014 } else { 1015 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1016 val = GMII_PO_EN; 1017 } 1018 1019 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1020 reg |= val; 1021 if (duplex == DUPLEX_FULL) 1022 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1023 else 1024 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1025 1026 switch (speed) { 1027 case 2000: 1028 reg |= PORT_OVERRIDE_SPEED_2000M; 1029 /* fallthrough */ 1030 case SPEED_1000: 1031 reg |= PORT_OVERRIDE_SPEED_1000M; 1032 break; 1033 case SPEED_100: 1034 reg |= PORT_OVERRIDE_SPEED_100M; 1035 break; 1036 case SPEED_10: 1037 reg |= PORT_OVERRIDE_SPEED_10M; 1038 break; 1039 default: 1040 dev_err(dev->dev, "unknown speed: %d\n", speed); 1041 return; 1042 } 1043 1044 if (pause & MLO_PAUSE_RX) 1045 reg |= PORT_OVERRIDE_RX_FLOW; 1046 if (pause & MLO_PAUSE_TX) 1047 reg |= PORT_OVERRIDE_TX_FLOW; 1048 1049 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1050 } 1051 1052 static void b53_adjust_link(struct dsa_switch *ds, int port, 1053 struct phy_device *phydev) 1054 { 1055 struct b53_device *dev = ds->priv; 1056 struct ethtool_eee *p = &dev->ports[port].eee; 1057 u8 rgmii_ctrl = 0, reg = 0, off; 1058 int pause = 0; 1059 1060 if (!phy_is_pseudo_fixed_link(phydev)) 1061 return; 1062 1063 /* Enable flow control on BCM5301x's CPU port */ 1064 if (is5301x(dev) && port == dev->cpu_port) 1065 pause = MLO_PAUSE_TXRX_MASK; 1066 1067 if (phydev->pause) { 1068 if (phydev->asym_pause) 1069 pause |= MLO_PAUSE_TX; 1070 pause |= MLO_PAUSE_RX; 1071 } 1072 1073 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause); 1074 b53_force_link(dev, port, phydev->link); 1075 1076 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1077 if (port == 8) 1078 off = B53_RGMII_CTRL_IMP; 1079 else 1080 off = B53_RGMII_CTRL_P(port); 1081 1082 /* Configure the port RGMII clock delay by DLL disabled and 1083 * tx_clk aligned timing (restoring to reset defaults) 1084 */ 1085 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1086 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1087 RGMII_CTRL_TIMING_SEL); 1088 1089 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1090 * sure that we enable the port TX clock internal delay to 1091 * account for this internal delay that is inserted, otherwise 1092 * the switch won't be able to receive correctly. 1093 * 1094 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1095 * any delay neither on transmission nor reception, so the 1096 * BCM53125 must also be configured accordingly to account for 1097 * the lack of delay and introduce 1098 * 1099 * The BCM53125 switch has its RX clock and TX clock control 1100 * swapped, hence the reason why we modify the TX clock path in 1101 * the "RGMII" case 1102 */ 1103 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1104 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1105 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1106 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1107 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1108 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1109 1110 dev_info(ds->dev, "Configured port %d for %s\n", port, 1111 phy_modes(phydev->interface)); 1112 } 1113 1114 /* configure MII port if necessary */ 1115 if (is5325(dev)) { 1116 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1117 ®); 1118 1119 /* reverse mii needs to be enabled */ 1120 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1121 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1122 reg | PORT_OVERRIDE_RV_MII_25); 1123 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1124 ®); 1125 1126 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1127 dev_err(ds->dev, 1128 "Failed to enable reverse MII mode\n"); 1129 return; 1130 } 1131 } 1132 } else if (is5301x(dev)) { 1133 if (port != dev->cpu_port) { 1134 b53_force_port_config(dev, dev->cpu_port, 2000, 1135 DUPLEX_FULL, MLO_PAUSE_TXRX_MASK); 1136 b53_force_link(dev, dev->cpu_port, 1); 1137 } 1138 } 1139 1140 /* Re-negotiate EEE if it was enabled already */ 1141 p->eee_enabled = b53_eee_init(ds, port, phydev); 1142 } 1143 1144 void b53_port_event(struct dsa_switch *ds, int port) 1145 { 1146 struct b53_device *dev = ds->priv; 1147 bool link; 1148 u16 sts; 1149 1150 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1151 link = !!(sts & BIT(port)); 1152 dsa_port_phylink_mac_change(ds, port, link); 1153 } 1154 EXPORT_SYMBOL(b53_port_event); 1155 1156 void b53_phylink_validate(struct dsa_switch *ds, int port, 1157 unsigned long *supported, 1158 struct phylink_link_state *state) 1159 { 1160 struct b53_device *dev = ds->priv; 1161 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1162 1163 if (dev->ops->serdes_phylink_validate) 1164 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1165 1166 /* Allow all the expected bits */ 1167 phylink_set(mask, Autoneg); 1168 phylink_set_port_modes(mask); 1169 phylink_set(mask, Pause); 1170 phylink_set(mask, Asym_Pause); 1171 1172 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1173 * support Gigabit, including Half duplex. 1174 */ 1175 if (state->interface != PHY_INTERFACE_MODE_MII && 1176 state->interface != PHY_INTERFACE_MODE_REVMII && 1177 !phy_interface_mode_is_8023z(state->interface) && 1178 !(is5325(dev) || is5365(dev))) { 1179 phylink_set(mask, 1000baseT_Full); 1180 phylink_set(mask, 1000baseT_Half); 1181 } 1182 1183 if (!phy_interface_mode_is_8023z(state->interface)) { 1184 phylink_set(mask, 10baseT_Half); 1185 phylink_set(mask, 10baseT_Full); 1186 phylink_set(mask, 100baseT_Half); 1187 phylink_set(mask, 100baseT_Full); 1188 } 1189 1190 bitmap_and(supported, supported, mask, 1191 __ETHTOOL_LINK_MODE_MASK_NBITS); 1192 bitmap_and(state->advertising, state->advertising, mask, 1193 __ETHTOOL_LINK_MODE_MASK_NBITS); 1194 1195 phylink_helper_basex_speed(state); 1196 } 1197 EXPORT_SYMBOL(b53_phylink_validate); 1198 1199 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1200 struct phylink_link_state *state) 1201 { 1202 struct b53_device *dev = ds->priv; 1203 int ret = -EOPNOTSUPP; 1204 1205 if ((phy_interface_mode_is_8023z(state->interface) || 1206 state->interface == PHY_INTERFACE_MODE_SGMII) && 1207 dev->ops->serdes_link_state) 1208 ret = dev->ops->serdes_link_state(dev, port, state); 1209 1210 return ret; 1211 } 1212 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1213 1214 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1215 unsigned int mode, 1216 const struct phylink_link_state *state) 1217 { 1218 struct b53_device *dev = ds->priv; 1219 1220 if (mode == MLO_AN_PHY) 1221 return; 1222 1223 if (mode == MLO_AN_FIXED) { 1224 b53_force_port_config(dev, port, state->speed, 1225 state->duplex, state->pause); 1226 return; 1227 } 1228 1229 if ((phy_interface_mode_is_8023z(state->interface) || 1230 state->interface == PHY_INTERFACE_MODE_SGMII) && 1231 dev->ops->serdes_config) 1232 dev->ops->serdes_config(dev, port, mode, state); 1233 } 1234 EXPORT_SYMBOL(b53_phylink_mac_config); 1235 1236 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1237 { 1238 struct b53_device *dev = ds->priv; 1239 1240 if (dev->ops->serdes_an_restart) 1241 dev->ops->serdes_an_restart(dev, port); 1242 } 1243 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1244 1245 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1246 unsigned int mode, 1247 phy_interface_t interface) 1248 { 1249 struct b53_device *dev = ds->priv; 1250 1251 if (mode == MLO_AN_PHY) 1252 return; 1253 1254 if (mode == MLO_AN_FIXED) { 1255 b53_force_link(dev, port, false); 1256 return; 1257 } 1258 1259 if (phy_interface_mode_is_8023z(interface) && 1260 dev->ops->serdes_link_set) 1261 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1262 } 1263 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1264 1265 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1266 unsigned int mode, 1267 phy_interface_t interface, 1268 struct phy_device *phydev) 1269 { 1270 struct b53_device *dev = ds->priv; 1271 1272 if (mode == MLO_AN_PHY) 1273 return; 1274 1275 if (mode == MLO_AN_FIXED) { 1276 b53_force_link(dev, port, true); 1277 return; 1278 } 1279 1280 if (phy_interface_mode_is_8023z(interface) && 1281 dev->ops->serdes_link_set) 1282 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1283 } 1284 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1285 1286 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 1287 { 1288 struct b53_device *dev = ds->priv; 1289 u16 pvid, new_pvid; 1290 1291 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1292 new_pvid = pvid; 1293 if (!vlan_filtering) { 1294 /* Filtering is currently enabled, use the default PVID since 1295 * the bridge does not expect tagging anymore 1296 */ 1297 dev->ports[port].pvid = pvid; 1298 new_pvid = b53_default_pvid(dev); 1299 } else { 1300 /* Filtering is currently disabled, restore the previous PVID */ 1301 new_pvid = dev->ports[port].pvid; 1302 } 1303 1304 if (pvid != new_pvid) 1305 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1306 new_pvid); 1307 1308 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering); 1309 1310 return 0; 1311 } 1312 EXPORT_SYMBOL(b53_vlan_filtering); 1313 1314 int b53_vlan_prepare(struct dsa_switch *ds, int port, 1315 const struct switchdev_obj_port_vlan *vlan) 1316 { 1317 struct b53_device *dev = ds->priv; 1318 1319 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 1320 return -EOPNOTSUPP; 1321 1322 if (vlan->vid_end > dev->num_vlans) 1323 return -ERANGE; 1324 1325 b53_enable_vlan(dev, true, ds->vlan_filtering); 1326 1327 return 0; 1328 } 1329 EXPORT_SYMBOL(b53_vlan_prepare); 1330 1331 void b53_vlan_add(struct dsa_switch *ds, int port, 1332 const struct switchdev_obj_port_vlan *vlan) 1333 { 1334 struct b53_device *dev = ds->priv; 1335 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1336 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1337 struct b53_vlan *vl; 1338 u16 vid; 1339 1340 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1341 vl = &dev->vlans[vid]; 1342 1343 b53_get_vlan_entry(dev, vid, vl); 1344 1345 vl->members |= BIT(port); 1346 if (untagged && !dsa_is_cpu_port(ds, port)) 1347 vl->untag |= BIT(port); 1348 else 1349 vl->untag &= ~BIT(port); 1350 1351 b53_set_vlan_entry(dev, vid, vl); 1352 b53_fast_age_vlan(dev, vid); 1353 } 1354 1355 if (pvid && !dsa_is_cpu_port(ds, port)) { 1356 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1357 vlan->vid_end); 1358 b53_fast_age_vlan(dev, vid); 1359 } 1360 } 1361 EXPORT_SYMBOL(b53_vlan_add); 1362 1363 int b53_vlan_del(struct dsa_switch *ds, int port, 1364 const struct switchdev_obj_port_vlan *vlan) 1365 { 1366 struct b53_device *dev = ds->priv; 1367 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1368 struct b53_vlan *vl; 1369 u16 vid; 1370 u16 pvid; 1371 1372 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1373 1374 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1375 vl = &dev->vlans[vid]; 1376 1377 b53_get_vlan_entry(dev, vid, vl); 1378 1379 vl->members &= ~BIT(port); 1380 1381 if (pvid == vid) 1382 pvid = b53_default_pvid(dev); 1383 1384 if (untagged && !dsa_is_cpu_port(ds, port)) 1385 vl->untag &= ~(BIT(port)); 1386 1387 b53_set_vlan_entry(dev, vid, vl); 1388 b53_fast_age_vlan(dev, vid); 1389 } 1390 1391 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1392 b53_fast_age_vlan(dev, pvid); 1393 1394 return 0; 1395 } 1396 EXPORT_SYMBOL(b53_vlan_del); 1397 1398 /* Address Resolution Logic routines */ 1399 static int b53_arl_op_wait(struct b53_device *dev) 1400 { 1401 unsigned int timeout = 10; 1402 u8 reg; 1403 1404 do { 1405 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1406 if (!(reg & ARLTBL_START_DONE)) 1407 return 0; 1408 1409 usleep_range(1000, 2000); 1410 } while (timeout--); 1411 1412 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1413 1414 return -ETIMEDOUT; 1415 } 1416 1417 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1418 { 1419 u8 reg; 1420 1421 if (op > ARLTBL_RW) 1422 return -EINVAL; 1423 1424 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1425 reg |= ARLTBL_START_DONE; 1426 if (op) 1427 reg |= ARLTBL_RW; 1428 else 1429 reg &= ~ARLTBL_RW; 1430 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1431 1432 return b53_arl_op_wait(dev); 1433 } 1434 1435 static int b53_arl_read(struct b53_device *dev, u64 mac, 1436 u16 vid, struct b53_arl_entry *ent, u8 *idx, 1437 bool is_valid) 1438 { 1439 unsigned int i; 1440 int ret; 1441 1442 ret = b53_arl_op_wait(dev); 1443 if (ret) 1444 return ret; 1445 1446 /* Read the bins */ 1447 for (i = 0; i < dev->num_arl_entries; i++) { 1448 u64 mac_vid; 1449 u32 fwd_entry; 1450 1451 b53_read64(dev, B53_ARLIO_PAGE, 1452 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1453 b53_read32(dev, B53_ARLIO_PAGE, 1454 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1455 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1456 1457 if (!(fwd_entry & ARLTBL_VALID)) 1458 continue; 1459 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1460 continue; 1461 *idx = i; 1462 } 1463 1464 return -ENOENT; 1465 } 1466 1467 static int b53_arl_op(struct b53_device *dev, int op, int port, 1468 const unsigned char *addr, u16 vid, bool is_valid) 1469 { 1470 struct b53_arl_entry ent; 1471 u32 fwd_entry; 1472 u64 mac, mac_vid = 0; 1473 u8 idx = 0; 1474 int ret; 1475 1476 /* Convert the array into a 64-bit MAC */ 1477 mac = ether_addr_to_u64(addr); 1478 1479 /* Perform a read for the given MAC and VID */ 1480 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1481 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1482 1483 /* Issue a read operation for this MAC */ 1484 ret = b53_arl_rw_op(dev, 1); 1485 if (ret) 1486 return ret; 1487 1488 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid); 1489 /* If this is a read, just finish now */ 1490 if (op) 1491 return ret; 1492 1493 /* We could not find a matching MAC, so reset to a new entry */ 1494 if (ret) { 1495 fwd_entry = 0; 1496 idx = 1; 1497 } 1498 1499 memset(&ent, 0, sizeof(ent)); 1500 ent.port = port; 1501 ent.is_valid = is_valid; 1502 ent.vid = vid; 1503 ent.is_static = true; 1504 memcpy(ent.mac, addr, ETH_ALEN); 1505 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1506 1507 b53_write64(dev, B53_ARLIO_PAGE, 1508 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1509 b53_write32(dev, B53_ARLIO_PAGE, 1510 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1511 1512 return b53_arl_rw_op(dev, 0); 1513 } 1514 1515 int b53_fdb_add(struct dsa_switch *ds, int port, 1516 const unsigned char *addr, u16 vid) 1517 { 1518 struct b53_device *priv = ds->priv; 1519 1520 /* 5325 and 5365 require some more massaging, but could 1521 * be supported eventually 1522 */ 1523 if (is5325(priv) || is5365(priv)) 1524 return -EOPNOTSUPP; 1525 1526 return b53_arl_op(priv, 0, port, addr, vid, true); 1527 } 1528 EXPORT_SYMBOL(b53_fdb_add); 1529 1530 int b53_fdb_del(struct dsa_switch *ds, int port, 1531 const unsigned char *addr, u16 vid) 1532 { 1533 struct b53_device *priv = ds->priv; 1534 1535 return b53_arl_op(priv, 0, port, addr, vid, false); 1536 } 1537 EXPORT_SYMBOL(b53_fdb_del); 1538 1539 static int b53_arl_search_wait(struct b53_device *dev) 1540 { 1541 unsigned int timeout = 1000; 1542 u8 reg; 1543 1544 do { 1545 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1546 if (!(reg & ARL_SRCH_STDN)) 1547 return 0; 1548 1549 if (reg & ARL_SRCH_VLID) 1550 return 0; 1551 1552 usleep_range(1000, 2000); 1553 } while (timeout--); 1554 1555 return -ETIMEDOUT; 1556 } 1557 1558 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1559 struct b53_arl_entry *ent) 1560 { 1561 u64 mac_vid; 1562 u32 fwd_entry; 1563 1564 b53_read64(dev, B53_ARLIO_PAGE, 1565 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1566 b53_read32(dev, B53_ARLIO_PAGE, 1567 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1568 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1569 } 1570 1571 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1572 dsa_fdb_dump_cb_t *cb, void *data) 1573 { 1574 if (!ent->is_valid) 1575 return 0; 1576 1577 if (port != ent->port) 1578 return 0; 1579 1580 return cb(ent->mac, ent->vid, ent->is_static, data); 1581 } 1582 1583 int b53_fdb_dump(struct dsa_switch *ds, int port, 1584 dsa_fdb_dump_cb_t *cb, void *data) 1585 { 1586 struct b53_device *priv = ds->priv; 1587 struct b53_arl_entry results[2]; 1588 unsigned int count = 0; 1589 int ret; 1590 u8 reg; 1591 1592 /* Start search operation */ 1593 reg = ARL_SRCH_STDN; 1594 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1595 1596 do { 1597 ret = b53_arl_search_wait(priv); 1598 if (ret) 1599 return ret; 1600 1601 b53_arl_search_rd(priv, 0, &results[0]); 1602 ret = b53_fdb_copy(port, &results[0], cb, data); 1603 if (ret) 1604 return ret; 1605 1606 if (priv->num_arl_entries > 2) { 1607 b53_arl_search_rd(priv, 1, &results[1]); 1608 ret = b53_fdb_copy(port, &results[1], cb, data); 1609 if (ret) 1610 return ret; 1611 1612 if (!results[0].is_valid && !results[1].is_valid) 1613 break; 1614 } 1615 1616 } while (count++ < 1024); 1617 1618 return 0; 1619 } 1620 EXPORT_SYMBOL(b53_fdb_dump); 1621 1622 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1623 { 1624 struct b53_device *dev = ds->priv; 1625 s8 cpu_port = ds->ports[port].cpu_dp->index; 1626 u16 pvlan, reg; 1627 unsigned int i; 1628 1629 /* Make this port leave the all VLANs join since we will have proper 1630 * VLAN entries from now on 1631 */ 1632 if (is58xx(dev)) { 1633 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1634 reg &= ~BIT(port); 1635 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1636 reg &= ~BIT(cpu_port); 1637 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1638 } 1639 1640 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1641 1642 b53_for_each_port(dev, i) { 1643 if (dsa_to_port(ds, i)->bridge_dev != br) 1644 continue; 1645 1646 /* Add this local port to the remote port VLAN control 1647 * membership and update the remote port bitmask 1648 */ 1649 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1650 reg |= BIT(port); 1651 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1652 dev->ports[i].vlan_ctl_mask = reg; 1653 1654 pvlan |= BIT(i); 1655 } 1656 1657 /* Configure the local port VLAN control membership to include 1658 * remote ports and update the local port bitmask 1659 */ 1660 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1661 dev->ports[port].vlan_ctl_mask = pvlan; 1662 1663 return 0; 1664 } 1665 EXPORT_SYMBOL(b53_br_join); 1666 1667 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1668 { 1669 struct b53_device *dev = ds->priv; 1670 struct b53_vlan *vl = &dev->vlans[0]; 1671 s8 cpu_port = ds->ports[port].cpu_dp->index; 1672 unsigned int i; 1673 u16 pvlan, reg, pvid; 1674 1675 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1676 1677 b53_for_each_port(dev, i) { 1678 /* Don't touch the remaining ports */ 1679 if (dsa_to_port(ds, i)->bridge_dev != br) 1680 continue; 1681 1682 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1683 reg &= ~BIT(port); 1684 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1685 dev->ports[port].vlan_ctl_mask = reg; 1686 1687 /* Prevent self removal to preserve isolation */ 1688 if (port != i) 1689 pvlan &= ~BIT(i); 1690 } 1691 1692 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1693 dev->ports[port].vlan_ctl_mask = pvlan; 1694 1695 pvid = b53_default_pvid(dev); 1696 1697 /* Make this port join all VLANs without VLAN entries */ 1698 if (is58xx(dev)) { 1699 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1700 reg |= BIT(port); 1701 if (!(reg & BIT(cpu_port))) 1702 reg |= BIT(cpu_port); 1703 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1704 } else { 1705 b53_get_vlan_entry(dev, pvid, vl); 1706 vl->members |= BIT(port) | BIT(cpu_port); 1707 vl->untag |= BIT(port) | BIT(cpu_port); 1708 b53_set_vlan_entry(dev, pvid, vl); 1709 } 1710 } 1711 EXPORT_SYMBOL(b53_br_leave); 1712 1713 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1714 { 1715 struct b53_device *dev = ds->priv; 1716 u8 hw_state; 1717 u8 reg; 1718 1719 switch (state) { 1720 case BR_STATE_DISABLED: 1721 hw_state = PORT_CTRL_DIS_STATE; 1722 break; 1723 case BR_STATE_LISTENING: 1724 hw_state = PORT_CTRL_LISTEN_STATE; 1725 break; 1726 case BR_STATE_LEARNING: 1727 hw_state = PORT_CTRL_LEARN_STATE; 1728 break; 1729 case BR_STATE_FORWARDING: 1730 hw_state = PORT_CTRL_FWD_STATE; 1731 break; 1732 case BR_STATE_BLOCKING: 1733 hw_state = PORT_CTRL_BLOCK_STATE; 1734 break; 1735 default: 1736 dev_err(ds->dev, "invalid STP state: %d\n", state); 1737 return; 1738 } 1739 1740 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1741 reg &= ~PORT_CTRL_STP_STATE_MASK; 1742 reg |= hw_state; 1743 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1744 } 1745 EXPORT_SYMBOL(b53_br_set_stp_state); 1746 1747 void b53_br_fast_age(struct dsa_switch *ds, int port) 1748 { 1749 struct b53_device *dev = ds->priv; 1750 1751 if (b53_fast_age_port(dev, port)) 1752 dev_err(ds->dev, "fast ageing failed\n"); 1753 } 1754 EXPORT_SYMBOL(b53_br_fast_age); 1755 1756 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 1757 { 1758 /* Broadcom switches will accept enabling Broadcom tags on the 1759 * following ports: 5, 7 and 8, any other port is not supported 1760 */ 1761 switch (port) { 1762 case B53_CPU_PORT_25: 1763 case 7: 1764 case B53_CPU_PORT: 1765 return true; 1766 } 1767 1768 return false; 1769 } 1770 1771 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port) 1772 { 1773 bool ret = b53_possible_cpu_port(ds, port); 1774 1775 if (!ret) 1776 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 1777 port); 1778 return ret; 1779 } 1780 1781 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port) 1782 { 1783 struct b53_device *dev = ds->priv; 1784 1785 /* Older models (5325, 5365) support a different tag format that we do 1786 * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed 1787 * mode to be turned on which means we need to specifically manage ARL 1788 * misses on multicast addresses (TBD). 1789 */ 1790 if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) || 1791 !b53_can_enable_brcm_tags(ds, port)) 1792 return DSA_TAG_PROTO_NONE; 1793 1794 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 1795 * which requires us to use the prepended Broadcom tag type 1796 */ 1797 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) 1798 return DSA_TAG_PROTO_BRCM_PREPEND; 1799 1800 return DSA_TAG_PROTO_BRCM; 1801 } 1802 EXPORT_SYMBOL(b53_get_tag_protocol); 1803 1804 int b53_mirror_add(struct dsa_switch *ds, int port, 1805 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1806 { 1807 struct b53_device *dev = ds->priv; 1808 u16 reg, loc; 1809 1810 if (ingress) 1811 loc = B53_IG_MIR_CTL; 1812 else 1813 loc = B53_EG_MIR_CTL; 1814 1815 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1816 reg &= ~MIRROR_MASK; 1817 reg |= BIT(port); 1818 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1819 1820 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1821 reg &= ~CAP_PORT_MASK; 1822 reg |= mirror->to_local_port; 1823 reg |= MIRROR_EN; 1824 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1825 1826 return 0; 1827 } 1828 EXPORT_SYMBOL(b53_mirror_add); 1829 1830 void b53_mirror_del(struct dsa_switch *ds, int port, 1831 struct dsa_mall_mirror_tc_entry *mirror) 1832 { 1833 struct b53_device *dev = ds->priv; 1834 bool loc_disable = false, other_loc_disable = false; 1835 u16 reg, loc; 1836 1837 if (mirror->ingress) 1838 loc = B53_IG_MIR_CTL; 1839 else 1840 loc = B53_EG_MIR_CTL; 1841 1842 /* Update the desired ingress/egress register */ 1843 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1844 reg &= ~BIT(port); 1845 if (!(reg & MIRROR_MASK)) 1846 loc_disable = true; 1847 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1848 1849 /* Now look at the other one to know if we can disable mirroring 1850 * entirely 1851 */ 1852 if (mirror->ingress) 1853 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 1854 else 1855 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 1856 if (!(reg & MIRROR_MASK)) 1857 other_loc_disable = true; 1858 1859 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1860 /* Both no longer have ports, let's disable mirroring */ 1861 if (loc_disable && other_loc_disable) { 1862 reg &= ~MIRROR_EN; 1863 reg &= ~mirror->to_local_port; 1864 } 1865 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1866 } 1867 EXPORT_SYMBOL(b53_mirror_del); 1868 1869 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 1870 { 1871 struct b53_device *dev = ds->priv; 1872 u16 reg; 1873 1874 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 1875 if (enable) 1876 reg |= BIT(port); 1877 else 1878 reg &= ~BIT(port); 1879 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 1880 } 1881 EXPORT_SYMBOL(b53_eee_enable_set); 1882 1883 1884 /* Returns 0 if EEE was not enabled, or 1 otherwise 1885 */ 1886 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 1887 { 1888 int ret; 1889 1890 ret = phy_init_eee(phy, 0); 1891 if (ret) 1892 return 0; 1893 1894 b53_eee_enable_set(ds, port, true); 1895 1896 return 1; 1897 } 1898 EXPORT_SYMBOL(b53_eee_init); 1899 1900 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1901 { 1902 struct b53_device *dev = ds->priv; 1903 struct ethtool_eee *p = &dev->ports[port].eee; 1904 u16 reg; 1905 1906 if (is5325(dev) || is5365(dev)) 1907 return -EOPNOTSUPP; 1908 1909 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 1910 e->eee_enabled = p->eee_enabled; 1911 e->eee_active = !!(reg & BIT(port)); 1912 1913 return 0; 1914 } 1915 EXPORT_SYMBOL(b53_get_mac_eee); 1916 1917 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1918 { 1919 struct b53_device *dev = ds->priv; 1920 struct ethtool_eee *p = &dev->ports[port].eee; 1921 1922 if (is5325(dev) || is5365(dev)) 1923 return -EOPNOTSUPP; 1924 1925 p->eee_enabled = e->eee_enabled; 1926 b53_eee_enable_set(ds, port, e->eee_enabled); 1927 1928 return 0; 1929 } 1930 EXPORT_SYMBOL(b53_set_mac_eee); 1931 1932 static const struct dsa_switch_ops b53_switch_ops = { 1933 .get_tag_protocol = b53_get_tag_protocol, 1934 .setup = b53_setup, 1935 .get_strings = b53_get_strings, 1936 .get_ethtool_stats = b53_get_ethtool_stats, 1937 .get_sset_count = b53_get_sset_count, 1938 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1939 .phy_read = b53_phy_read16, 1940 .phy_write = b53_phy_write16, 1941 .adjust_link = b53_adjust_link, 1942 .phylink_validate = b53_phylink_validate, 1943 .phylink_mac_link_state = b53_phylink_mac_link_state, 1944 .phylink_mac_config = b53_phylink_mac_config, 1945 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 1946 .phylink_mac_link_down = b53_phylink_mac_link_down, 1947 .phylink_mac_link_up = b53_phylink_mac_link_up, 1948 .port_enable = b53_enable_port, 1949 .port_disable = b53_disable_port, 1950 .get_mac_eee = b53_get_mac_eee, 1951 .set_mac_eee = b53_set_mac_eee, 1952 .port_bridge_join = b53_br_join, 1953 .port_bridge_leave = b53_br_leave, 1954 .port_stp_state_set = b53_br_set_stp_state, 1955 .port_fast_age = b53_br_fast_age, 1956 .port_vlan_filtering = b53_vlan_filtering, 1957 .port_vlan_prepare = b53_vlan_prepare, 1958 .port_vlan_add = b53_vlan_add, 1959 .port_vlan_del = b53_vlan_del, 1960 .port_fdb_dump = b53_fdb_dump, 1961 .port_fdb_add = b53_fdb_add, 1962 .port_fdb_del = b53_fdb_del, 1963 .port_mirror_add = b53_mirror_add, 1964 .port_mirror_del = b53_mirror_del, 1965 }; 1966 1967 struct b53_chip_data { 1968 u32 chip_id; 1969 const char *dev_name; 1970 u16 vlans; 1971 u16 enabled_ports; 1972 u8 cpu_port; 1973 u8 vta_regs[3]; 1974 u8 arl_entries; 1975 u8 duplex_reg; 1976 u8 jumbo_pm_reg; 1977 u8 jumbo_size_reg; 1978 }; 1979 1980 #define B53_VTA_REGS \ 1981 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 1982 #define B53_VTA_REGS_9798 \ 1983 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 1984 #define B53_VTA_REGS_63XX \ 1985 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 1986 1987 static const struct b53_chip_data b53_switch_chips[] = { 1988 { 1989 .chip_id = BCM5325_DEVICE_ID, 1990 .dev_name = "BCM5325", 1991 .vlans = 16, 1992 .enabled_ports = 0x1f, 1993 .arl_entries = 2, 1994 .cpu_port = B53_CPU_PORT_25, 1995 .duplex_reg = B53_DUPLEX_STAT_FE, 1996 }, 1997 { 1998 .chip_id = BCM5365_DEVICE_ID, 1999 .dev_name = "BCM5365", 2000 .vlans = 256, 2001 .enabled_ports = 0x1f, 2002 .arl_entries = 2, 2003 .cpu_port = B53_CPU_PORT_25, 2004 .duplex_reg = B53_DUPLEX_STAT_FE, 2005 }, 2006 { 2007 .chip_id = BCM5389_DEVICE_ID, 2008 .dev_name = "BCM5389", 2009 .vlans = 4096, 2010 .enabled_ports = 0x1f, 2011 .arl_entries = 4, 2012 .cpu_port = B53_CPU_PORT, 2013 .vta_regs = B53_VTA_REGS, 2014 .duplex_reg = B53_DUPLEX_STAT_GE, 2015 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2016 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2017 }, 2018 { 2019 .chip_id = BCM5395_DEVICE_ID, 2020 .dev_name = "BCM5395", 2021 .vlans = 4096, 2022 .enabled_ports = 0x1f, 2023 .arl_entries = 4, 2024 .cpu_port = B53_CPU_PORT, 2025 .vta_regs = B53_VTA_REGS, 2026 .duplex_reg = B53_DUPLEX_STAT_GE, 2027 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2028 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2029 }, 2030 { 2031 .chip_id = BCM5397_DEVICE_ID, 2032 .dev_name = "BCM5397", 2033 .vlans = 4096, 2034 .enabled_ports = 0x1f, 2035 .arl_entries = 4, 2036 .cpu_port = B53_CPU_PORT, 2037 .vta_regs = B53_VTA_REGS_9798, 2038 .duplex_reg = B53_DUPLEX_STAT_GE, 2039 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2040 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2041 }, 2042 { 2043 .chip_id = BCM5398_DEVICE_ID, 2044 .dev_name = "BCM5398", 2045 .vlans = 4096, 2046 .enabled_ports = 0x7f, 2047 .arl_entries = 4, 2048 .cpu_port = B53_CPU_PORT, 2049 .vta_regs = B53_VTA_REGS_9798, 2050 .duplex_reg = B53_DUPLEX_STAT_GE, 2051 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2052 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2053 }, 2054 { 2055 .chip_id = BCM53115_DEVICE_ID, 2056 .dev_name = "BCM53115", 2057 .vlans = 4096, 2058 .enabled_ports = 0x1f, 2059 .arl_entries = 4, 2060 .vta_regs = B53_VTA_REGS, 2061 .cpu_port = B53_CPU_PORT, 2062 .duplex_reg = B53_DUPLEX_STAT_GE, 2063 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2064 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2065 }, 2066 { 2067 .chip_id = BCM53125_DEVICE_ID, 2068 .dev_name = "BCM53125", 2069 .vlans = 4096, 2070 .enabled_ports = 0xff, 2071 .arl_entries = 4, 2072 .cpu_port = B53_CPU_PORT, 2073 .vta_regs = B53_VTA_REGS, 2074 .duplex_reg = B53_DUPLEX_STAT_GE, 2075 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2076 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2077 }, 2078 { 2079 .chip_id = BCM53128_DEVICE_ID, 2080 .dev_name = "BCM53128", 2081 .vlans = 4096, 2082 .enabled_ports = 0x1ff, 2083 .arl_entries = 4, 2084 .cpu_port = B53_CPU_PORT, 2085 .vta_regs = B53_VTA_REGS, 2086 .duplex_reg = B53_DUPLEX_STAT_GE, 2087 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2088 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2089 }, 2090 { 2091 .chip_id = BCM63XX_DEVICE_ID, 2092 .dev_name = "BCM63xx", 2093 .vlans = 4096, 2094 .enabled_ports = 0, /* pdata must provide them */ 2095 .arl_entries = 4, 2096 .cpu_port = B53_CPU_PORT, 2097 .vta_regs = B53_VTA_REGS_63XX, 2098 .duplex_reg = B53_DUPLEX_STAT_63XX, 2099 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2100 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2101 }, 2102 { 2103 .chip_id = BCM53010_DEVICE_ID, 2104 .dev_name = "BCM53010", 2105 .vlans = 4096, 2106 .enabled_ports = 0x1f, 2107 .arl_entries = 4, 2108 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2109 .vta_regs = B53_VTA_REGS, 2110 .duplex_reg = B53_DUPLEX_STAT_GE, 2111 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2112 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2113 }, 2114 { 2115 .chip_id = BCM53011_DEVICE_ID, 2116 .dev_name = "BCM53011", 2117 .vlans = 4096, 2118 .enabled_ports = 0x1bf, 2119 .arl_entries = 4, 2120 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2121 .vta_regs = B53_VTA_REGS, 2122 .duplex_reg = B53_DUPLEX_STAT_GE, 2123 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2124 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2125 }, 2126 { 2127 .chip_id = BCM53012_DEVICE_ID, 2128 .dev_name = "BCM53012", 2129 .vlans = 4096, 2130 .enabled_ports = 0x1bf, 2131 .arl_entries = 4, 2132 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2133 .vta_regs = B53_VTA_REGS, 2134 .duplex_reg = B53_DUPLEX_STAT_GE, 2135 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2136 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2137 }, 2138 { 2139 .chip_id = BCM53018_DEVICE_ID, 2140 .dev_name = "BCM53018", 2141 .vlans = 4096, 2142 .enabled_ports = 0x1f, 2143 .arl_entries = 4, 2144 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2145 .vta_regs = B53_VTA_REGS, 2146 .duplex_reg = B53_DUPLEX_STAT_GE, 2147 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2148 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2149 }, 2150 { 2151 .chip_id = BCM53019_DEVICE_ID, 2152 .dev_name = "BCM53019", 2153 .vlans = 4096, 2154 .enabled_ports = 0x1f, 2155 .arl_entries = 4, 2156 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2157 .vta_regs = B53_VTA_REGS, 2158 .duplex_reg = B53_DUPLEX_STAT_GE, 2159 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2160 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2161 }, 2162 { 2163 .chip_id = BCM58XX_DEVICE_ID, 2164 .dev_name = "BCM585xx/586xx/88312", 2165 .vlans = 4096, 2166 .enabled_ports = 0x1ff, 2167 .arl_entries = 4, 2168 .cpu_port = B53_CPU_PORT, 2169 .vta_regs = B53_VTA_REGS, 2170 .duplex_reg = B53_DUPLEX_STAT_GE, 2171 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2172 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2173 }, 2174 { 2175 .chip_id = BCM583XX_DEVICE_ID, 2176 .dev_name = "BCM583xx/11360", 2177 .vlans = 4096, 2178 .enabled_ports = 0x103, 2179 .arl_entries = 4, 2180 .cpu_port = B53_CPU_PORT, 2181 .vta_regs = B53_VTA_REGS, 2182 .duplex_reg = B53_DUPLEX_STAT_GE, 2183 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2184 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2185 }, 2186 { 2187 .chip_id = BCM7445_DEVICE_ID, 2188 .dev_name = "BCM7445", 2189 .vlans = 4096, 2190 .enabled_ports = 0x1ff, 2191 .arl_entries = 4, 2192 .cpu_port = B53_CPU_PORT, 2193 .vta_regs = B53_VTA_REGS, 2194 .duplex_reg = B53_DUPLEX_STAT_GE, 2195 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2196 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2197 }, 2198 { 2199 .chip_id = BCM7278_DEVICE_ID, 2200 .dev_name = "BCM7278", 2201 .vlans = 4096, 2202 .enabled_ports = 0x1ff, 2203 .arl_entries= 4, 2204 .cpu_port = B53_CPU_PORT, 2205 .vta_regs = B53_VTA_REGS, 2206 .duplex_reg = B53_DUPLEX_STAT_GE, 2207 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2208 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2209 }, 2210 }; 2211 2212 static int b53_switch_init(struct b53_device *dev) 2213 { 2214 unsigned int i; 2215 int ret; 2216 2217 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2218 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2219 2220 if (chip->chip_id == dev->chip_id) { 2221 if (!dev->enabled_ports) 2222 dev->enabled_ports = chip->enabled_ports; 2223 dev->name = chip->dev_name; 2224 dev->duplex_reg = chip->duplex_reg; 2225 dev->vta_regs[0] = chip->vta_regs[0]; 2226 dev->vta_regs[1] = chip->vta_regs[1]; 2227 dev->vta_regs[2] = chip->vta_regs[2]; 2228 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2229 dev->cpu_port = chip->cpu_port; 2230 dev->num_vlans = chip->vlans; 2231 dev->num_arl_entries = chip->arl_entries; 2232 break; 2233 } 2234 } 2235 2236 /* check which BCM5325x version we have */ 2237 if (is5325(dev)) { 2238 u8 vc4; 2239 2240 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2241 2242 /* check reserved bits */ 2243 switch (vc4 & 3) { 2244 case 1: 2245 /* BCM5325E */ 2246 break; 2247 case 3: 2248 /* BCM5325F - do not use port 4 */ 2249 dev->enabled_ports &= ~BIT(4); 2250 break; 2251 default: 2252 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2253 #ifndef CONFIG_BCM47XX 2254 /* BCM5325M */ 2255 return -EINVAL; 2256 #else 2257 break; 2258 #endif 2259 } 2260 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2261 u64 strap_value; 2262 2263 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2264 /* use second IMP port if GMII is enabled */ 2265 if (strap_value & SV_GMII_CTRL_115) 2266 dev->cpu_port = 5; 2267 } 2268 2269 /* cpu port is always last */ 2270 dev->num_ports = dev->cpu_port + 1; 2271 dev->enabled_ports |= BIT(dev->cpu_port); 2272 2273 /* Include non standard CPU port built-in PHYs to be probed */ 2274 if (is539x(dev) || is531x5(dev)) { 2275 for (i = 0; i < dev->num_ports; i++) { 2276 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2277 !b53_possible_cpu_port(dev->ds, i)) 2278 dev->ds->phys_mii_mask |= BIT(i); 2279 } 2280 } 2281 2282 dev->ports = devm_kcalloc(dev->dev, 2283 dev->num_ports, sizeof(struct b53_port), 2284 GFP_KERNEL); 2285 if (!dev->ports) 2286 return -ENOMEM; 2287 2288 dev->vlans = devm_kcalloc(dev->dev, 2289 dev->num_vlans, sizeof(struct b53_vlan), 2290 GFP_KERNEL); 2291 if (!dev->vlans) 2292 return -ENOMEM; 2293 2294 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2295 if (dev->reset_gpio >= 0) { 2296 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2297 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2298 if (ret) 2299 return ret; 2300 } 2301 2302 return 0; 2303 } 2304 2305 struct b53_device *b53_switch_alloc(struct device *base, 2306 const struct b53_io_ops *ops, 2307 void *priv) 2308 { 2309 struct dsa_switch *ds; 2310 struct b53_device *dev; 2311 2312 ds = dsa_switch_alloc(base, DSA_MAX_PORTS); 2313 if (!ds) 2314 return NULL; 2315 2316 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2317 if (!dev) 2318 return NULL; 2319 2320 ds->priv = dev; 2321 dev->dev = base; 2322 2323 dev->ds = ds; 2324 dev->priv = priv; 2325 dev->ops = ops; 2326 ds->ops = &b53_switch_ops; 2327 mutex_init(&dev->reg_mutex); 2328 mutex_init(&dev->stats_mutex); 2329 2330 return dev; 2331 } 2332 EXPORT_SYMBOL(b53_switch_alloc); 2333 2334 int b53_switch_detect(struct b53_device *dev) 2335 { 2336 u32 id32; 2337 u16 tmp; 2338 u8 id8; 2339 int ret; 2340 2341 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2342 if (ret) 2343 return ret; 2344 2345 switch (id8) { 2346 case 0: 2347 /* BCM5325 and BCM5365 do not have this register so reads 2348 * return 0. But the read operation did succeed, so assume this 2349 * is one of them. 2350 * 2351 * Next check if we can write to the 5325's VTA register; for 2352 * 5365 it is read only. 2353 */ 2354 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2355 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2356 2357 if (tmp == 0xf) 2358 dev->chip_id = BCM5325_DEVICE_ID; 2359 else 2360 dev->chip_id = BCM5365_DEVICE_ID; 2361 break; 2362 case BCM5389_DEVICE_ID: 2363 case BCM5395_DEVICE_ID: 2364 case BCM5397_DEVICE_ID: 2365 case BCM5398_DEVICE_ID: 2366 dev->chip_id = id8; 2367 break; 2368 default: 2369 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2370 if (ret) 2371 return ret; 2372 2373 switch (id32) { 2374 case BCM53115_DEVICE_ID: 2375 case BCM53125_DEVICE_ID: 2376 case BCM53128_DEVICE_ID: 2377 case BCM53010_DEVICE_ID: 2378 case BCM53011_DEVICE_ID: 2379 case BCM53012_DEVICE_ID: 2380 case BCM53018_DEVICE_ID: 2381 case BCM53019_DEVICE_ID: 2382 dev->chip_id = id32; 2383 break; 2384 default: 2385 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 2386 id8, id32); 2387 return -ENODEV; 2388 } 2389 } 2390 2391 if (dev->chip_id == BCM5325_DEVICE_ID) 2392 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2393 &dev->core_rev); 2394 else 2395 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2396 &dev->core_rev); 2397 } 2398 EXPORT_SYMBOL(b53_switch_detect); 2399 2400 int b53_switch_register(struct b53_device *dev) 2401 { 2402 int ret; 2403 2404 if (dev->pdata) { 2405 dev->chip_id = dev->pdata->chip_id; 2406 dev->enabled_ports = dev->pdata->enabled_ports; 2407 } 2408 2409 if (!dev->chip_id && b53_switch_detect(dev)) 2410 return -EINVAL; 2411 2412 ret = b53_switch_init(dev); 2413 if (ret) 2414 return ret; 2415 2416 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 2417 2418 return dsa_register_switch(dev->ds); 2419 } 2420 EXPORT_SYMBOL(b53_switch_register); 2421 2422 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2423 MODULE_DESCRIPTION("B53 switch library"); 2424 MODULE_LICENSE("Dual BSD/GPL"); 2425