1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if_bridge.h> 32 #include <net/dsa.h> 33 34 #include "b53_regs.h" 35 #include "b53_priv.h" 36 37 struct b53_mib_desc { 38 u8 size; 39 u8 offset; 40 const char *name; 41 }; 42 43 /* BCM5365 MIB counters */ 44 static const struct b53_mib_desc b53_mibs_65[] = { 45 { 8, 0x00, "TxOctets" }, 46 { 4, 0x08, "TxDropPkts" }, 47 { 4, 0x10, "TxBroadcastPkts" }, 48 { 4, 0x14, "TxMulticastPkts" }, 49 { 4, 0x18, "TxUnicastPkts" }, 50 { 4, 0x1c, "TxCollisions" }, 51 { 4, 0x20, "TxSingleCollision" }, 52 { 4, 0x24, "TxMultipleCollision" }, 53 { 4, 0x28, "TxDeferredTransmit" }, 54 { 4, 0x2c, "TxLateCollision" }, 55 { 4, 0x30, "TxExcessiveCollision" }, 56 { 4, 0x38, "TxPausePkts" }, 57 { 8, 0x44, "RxOctets" }, 58 { 4, 0x4c, "RxUndersizePkts" }, 59 { 4, 0x50, "RxPausePkts" }, 60 { 4, 0x54, "Pkts64Octets" }, 61 { 4, 0x58, "Pkts65to127Octets" }, 62 { 4, 0x5c, "Pkts128to255Octets" }, 63 { 4, 0x60, "Pkts256to511Octets" }, 64 { 4, 0x64, "Pkts512to1023Octets" }, 65 { 4, 0x68, "Pkts1024to1522Octets" }, 66 { 4, 0x6c, "RxOversizePkts" }, 67 { 4, 0x70, "RxJabbers" }, 68 { 4, 0x74, "RxAlignmentErrors" }, 69 { 4, 0x78, "RxFCSErrors" }, 70 { 8, 0x7c, "RxGoodOctets" }, 71 { 4, 0x84, "RxDropPkts" }, 72 { 4, 0x88, "RxUnicastPkts" }, 73 { 4, 0x8c, "RxMulticastPkts" }, 74 { 4, 0x90, "RxBroadcastPkts" }, 75 { 4, 0x94, "RxSAChanges" }, 76 { 4, 0x98, "RxFragments" }, 77 }; 78 79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 80 81 /* BCM63xx MIB counters */ 82 static const struct b53_mib_desc b53_mibs_63xx[] = { 83 { 8, 0x00, "TxOctets" }, 84 { 4, 0x08, "TxDropPkts" }, 85 { 4, 0x0c, "TxQoSPkts" }, 86 { 4, 0x10, "TxBroadcastPkts" }, 87 { 4, 0x14, "TxMulticastPkts" }, 88 { 4, 0x18, "TxUnicastPkts" }, 89 { 4, 0x1c, "TxCollisions" }, 90 { 4, 0x20, "TxSingleCollision" }, 91 { 4, 0x24, "TxMultipleCollision" }, 92 { 4, 0x28, "TxDeferredTransmit" }, 93 { 4, 0x2c, "TxLateCollision" }, 94 { 4, 0x30, "TxExcessiveCollision" }, 95 { 4, 0x38, "TxPausePkts" }, 96 { 8, 0x3c, "TxQoSOctets" }, 97 { 8, 0x44, "RxOctets" }, 98 { 4, 0x4c, "RxUndersizePkts" }, 99 { 4, 0x50, "RxPausePkts" }, 100 { 4, 0x54, "Pkts64Octets" }, 101 { 4, 0x58, "Pkts65to127Octets" }, 102 { 4, 0x5c, "Pkts128to255Octets" }, 103 { 4, 0x60, "Pkts256to511Octets" }, 104 { 4, 0x64, "Pkts512to1023Octets" }, 105 { 4, 0x68, "Pkts1024to1522Octets" }, 106 { 4, 0x6c, "RxOversizePkts" }, 107 { 4, 0x70, "RxJabbers" }, 108 { 4, 0x74, "RxAlignmentErrors" }, 109 { 4, 0x78, "RxFCSErrors" }, 110 { 8, 0x7c, "RxGoodOctets" }, 111 { 4, 0x84, "RxDropPkts" }, 112 { 4, 0x88, "RxUnicastPkts" }, 113 { 4, 0x8c, "RxMulticastPkts" }, 114 { 4, 0x90, "RxBroadcastPkts" }, 115 { 4, 0x94, "RxSAChanges" }, 116 { 4, 0x98, "RxFragments" }, 117 { 4, 0xa0, "RxSymbolErrors" }, 118 { 4, 0xa4, "RxQoSPkts" }, 119 { 8, 0xa8, "RxQoSOctets" }, 120 { 4, 0xb0, "Pkts1523to2047Octets" }, 121 { 4, 0xb4, "Pkts2048to4095Octets" }, 122 { 4, 0xb8, "Pkts4096to8191Octets" }, 123 { 4, 0xbc, "Pkts8192to9728Octets" }, 124 { 4, 0xc0, "RxDiscarded" }, 125 }; 126 127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 128 129 /* MIB counters */ 130 static const struct b53_mib_desc b53_mibs[] = { 131 { 8, 0x00, "TxOctets" }, 132 { 4, 0x08, "TxDropPkts" }, 133 { 4, 0x10, "TxBroadcastPkts" }, 134 { 4, 0x14, "TxMulticastPkts" }, 135 { 4, 0x18, "TxUnicastPkts" }, 136 { 4, 0x1c, "TxCollisions" }, 137 { 4, 0x20, "TxSingleCollision" }, 138 { 4, 0x24, "TxMultipleCollision" }, 139 { 4, 0x28, "TxDeferredTransmit" }, 140 { 4, 0x2c, "TxLateCollision" }, 141 { 4, 0x30, "TxExcessiveCollision" }, 142 { 4, 0x38, "TxPausePkts" }, 143 { 8, 0x50, "RxOctets" }, 144 { 4, 0x58, "RxUndersizePkts" }, 145 { 4, 0x5c, "RxPausePkts" }, 146 { 4, 0x60, "Pkts64Octets" }, 147 { 4, 0x64, "Pkts65to127Octets" }, 148 { 4, 0x68, "Pkts128to255Octets" }, 149 { 4, 0x6c, "Pkts256to511Octets" }, 150 { 4, 0x70, "Pkts512to1023Octets" }, 151 { 4, 0x74, "Pkts1024to1522Octets" }, 152 { 4, 0x78, "RxOversizePkts" }, 153 { 4, 0x7c, "RxJabbers" }, 154 { 4, 0x80, "RxAlignmentErrors" }, 155 { 4, 0x84, "RxFCSErrors" }, 156 { 8, 0x88, "RxGoodOctets" }, 157 { 4, 0x90, "RxDropPkts" }, 158 { 4, 0x94, "RxUnicastPkts" }, 159 { 4, 0x98, "RxMulticastPkts" }, 160 { 4, 0x9c, "RxBroadcastPkts" }, 161 { 4, 0xa0, "RxSAChanges" }, 162 { 4, 0xa4, "RxFragments" }, 163 { 4, 0xa8, "RxJumboPkts" }, 164 { 4, 0xac, "RxSymbolErrors" }, 165 { 4, 0xc0, "RxDiscarded" }, 166 }; 167 168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 169 170 static const struct b53_mib_desc b53_mibs_58xx[] = { 171 { 8, 0x00, "TxOctets" }, 172 { 4, 0x08, "TxDropPkts" }, 173 { 4, 0x0c, "TxQPKTQ0" }, 174 { 4, 0x10, "TxBroadcastPkts" }, 175 { 4, 0x14, "TxMulticastPkts" }, 176 { 4, 0x18, "TxUnicastPKts" }, 177 { 4, 0x1c, "TxCollisions" }, 178 { 4, 0x20, "TxSingleCollision" }, 179 { 4, 0x24, "TxMultipleCollision" }, 180 { 4, 0x28, "TxDeferredCollision" }, 181 { 4, 0x2c, "TxLateCollision" }, 182 { 4, 0x30, "TxExcessiveCollision" }, 183 { 4, 0x34, "TxFrameInDisc" }, 184 { 4, 0x38, "TxPausePkts" }, 185 { 4, 0x3c, "TxQPKTQ1" }, 186 { 4, 0x40, "TxQPKTQ2" }, 187 { 4, 0x44, "TxQPKTQ3" }, 188 { 4, 0x48, "TxQPKTQ4" }, 189 { 4, 0x4c, "TxQPKTQ5" }, 190 { 8, 0x50, "RxOctets" }, 191 { 4, 0x58, "RxUndersizePkts" }, 192 { 4, 0x5c, "RxPausePkts" }, 193 { 4, 0x60, "RxPkts64Octets" }, 194 { 4, 0x64, "RxPkts65to127Octets" }, 195 { 4, 0x68, "RxPkts128to255Octets" }, 196 { 4, 0x6c, "RxPkts256to511Octets" }, 197 { 4, 0x70, "RxPkts512to1023Octets" }, 198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 199 { 4, 0x78, "RxOversizePkts" }, 200 { 4, 0x7c, "RxJabbers" }, 201 { 4, 0x80, "RxAlignmentErrors" }, 202 { 4, 0x84, "RxFCSErrors" }, 203 { 8, 0x88, "RxGoodOctets" }, 204 { 4, 0x90, "RxDropPkts" }, 205 { 4, 0x94, "RxUnicastPkts" }, 206 { 4, 0x98, "RxMulticastPkts" }, 207 { 4, 0x9c, "RxBroadcastPkts" }, 208 { 4, 0xa0, "RxSAChanges" }, 209 { 4, 0xa4, "RxFragments" }, 210 { 4, 0xa8, "RxJumboPkt" }, 211 { 4, 0xac, "RxSymblErr" }, 212 { 4, 0xb0, "InRangeErrCount" }, 213 { 4, 0xb4, "OutRangeErrCount" }, 214 { 4, 0xb8, "EEELpiEvent" }, 215 { 4, 0xbc, "EEELpiDuration" }, 216 { 4, 0xc0, "RxDiscard" }, 217 { 4, 0xc8, "TxQPKTQ6" }, 218 { 4, 0xcc, "TxQPKTQ7" }, 219 { 4, 0xd0, "TxPkts64Octets" }, 220 { 4, 0xd4, "TxPkts65to127Octets" }, 221 { 4, 0xd8, "TxPkts128to255Octets" }, 222 { 4, 0xdc, "TxPkts256to511Ocets" }, 223 { 4, 0xe0, "TxPkts512to1023Ocets" }, 224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 225 }; 226 227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 228 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 230 { 231 unsigned int i; 232 233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 234 235 for (i = 0; i < 10; i++) { 236 u8 vta; 237 238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 239 if (!(vta & VTA_START_CMD)) 240 return 0; 241 242 usleep_range(100, 200); 243 } 244 245 return -EIO; 246 } 247 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 249 struct b53_vlan *vlan) 250 { 251 if (is5325(dev)) { 252 u32 entry = 0; 253 254 if (vlan->members) { 255 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 256 VA_UNTAG_S_25) | vlan->members; 257 if (dev->core_rev >= 3) 258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 259 else 260 entry |= VA_VALID_25; 261 } 262 263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 265 VTA_RW_STATE_WR | VTA_RW_OP_EN); 266 } else if (is5365(dev)) { 267 u16 entry = 0; 268 269 if (vlan->members) 270 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 272 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 275 VTA_RW_STATE_WR | VTA_RW_OP_EN); 276 } else { 277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 279 (vlan->untag << VTE_UNTAG_S) | vlan->members); 280 281 b53_do_vlan_op(dev, VTA_CMD_WRITE); 282 } 283 284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 285 vid, vlan->members, vlan->untag); 286 } 287 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 289 struct b53_vlan *vlan) 290 { 291 if (is5325(dev)) { 292 u32 entry = 0; 293 294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 295 VTA_RW_STATE_RD | VTA_RW_OP_EN); 296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 297 298 if (dev->core_rev >= 3) 299 vlan->valid = !!(entry & VA_VALID_25_R4); 300 else 301 vlan->valid = !!(entry & VA_VALID_25); 302 vlan->members = entry & VA_MEMBER_MASK; 303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 304 305 } else if (is5365(dev)) { 306 u16 entry = 0; 307 308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 309 VTA_RW_STATE_WR | VTA_RW_OP_EN); 310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 311 312 vlan->valid = !!(entry & VA_VALID_65); 313 vlan->members = entry & VA_MEMBER_MASK; 314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 315 } else { 316 u32 entry = 0; 317 318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 319 b53_do_vlan_op(dev, VTA_CMD_READ); 320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 321 vlan->members = entry & VTE_MEMBERS; 322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 323 vlan->valid = true; 324 } 325 } 326 327 static void b53_set_forwarding(struct b53_device *dev, int enable) 328 { 329 u8 mgmt; 330 331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 332 333 if (enable) 334 mgmt |= SM_SW_FWD_EN; 335 else 336 mgmt &= ~SM_SW_FWD_EN; 337 338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 339 340 /* Include IMP port in dumb forwarding mode 341 */ 342 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 343 mgmt |= B53_MII_DUMB_FWDG_EN; 344 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 345 346 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 347 * frames should be flooded or not. 348 */ 349 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 350 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 351 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 352 } 353 354 static void b53_enable_vlan(struct b53_device *dev, bool enable, 355 bool enable_filtering) 356 { 357 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 358 359 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 362 363 if (is5325(dev) || is5365(dev)) { 364 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 366 } else if (is63xx(dev)) { 367 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 369 } else { 370 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 371 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 372 } 373 374 if (enable) { 375 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 376 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 377 vc4 &= ~VC4_ING_VID_CHECK_MASK; 378 if (enable_filtering) { 379 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 380 vc5 |= VC5_DROP_VTABLE_MISS; 381 } else { 382 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 383 vc5 &= ~VC5_DROP_VTABLE_MISS; 384 } 385 386 if (is5325(dev)) 387 vc0 &= ~VC0_RESERVED_1; 388 389 if (is5325(dev) || is5365(dev)) 390 vc1 |= VC1_RX_MCST_TAG_EN; 391 392 } else { 393 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 394 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 395 vc4 &= ~VC4_ING_VID_CHECK_MASK; 396 vc5 &= ~VC5_DROP_VTABLE_MISS; 397 398 if (is5325(dev) || is5365(dev)) 399 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 400 else 401 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 402 403 if (is5325(dev) || is5365(dev)) 404 vc1 &= ~VC1_RX_MCST_TAG_EN; 405 } 406 407 if (!is5325(dev) && !is5365(dev)) 408 vc5 &= ~VC5_VID_FFF_EN; 409 410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 412 413 if (is5325(dev) || is5365(dev)) { 414 /* enable the high 8 bit vid check on 5325 */ 415 if (is5325(dev) && enable) 416 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 417 VC3_HIGH_8BIT_EN); 418 else 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 420 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 423 } else if (is63xx(dev)) { 424 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 425 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 426 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 427 } else { 428 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 429 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 430 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 431 } 432 433 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 434 435 dev->vlan_enabled = enable; 436 } 437 438 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 439 { 440 u32 port_mask = 0; 441 u16 max_size = JMS_MIN_SIZE; 442 443 if (is5325(dev) || is5365(dev)) 444 return -EINVAL; 445 446 if (enable) { 447 port_mask = dev->enabled_ports; 448 max_size = JMS_MAX_SIZE; 449 if (allow_10_100) 450 port_mask |= JPM_10_100_JUMBO_EN; 451 } 452 453 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 454 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 455 } 456 457 static int b53_flush_arl(struct b53_device *dev, u8 mask) 458 { 459 unsigned int i; 460 461 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 462 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 463 464 for (i = 0; i < 10; i++) { 465 u8 fast_age_ctrl; 466 467 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 468 &fast_age_ctrl); 469 470 if (!(fast_age_ctrl & FAST_AGE_DONE)) 471 goto out; 472 473 msleep(1); 474 } 475 476 return -ETIMEDOUT; 477 out: 478 /* Only age dynamic entries (default behavior) */ 479 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 480 return 0; 481 } 482 483 static int b53_fast_age_port(struct b53_device *dev, int port) 484 { 485 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 486 487 return b53_flush_arl(dev, FAST_AGE_PORT); 488 } 489 490 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 491 { 492 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 493 494 return b53_flush_arl(dev, FAST_AGE_VLAN); 495 } 496 497 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 498 { 499 struct b53_device *dev = ds->priv; 500 unsigned int i; 501 u16 pvlan; 502 503 /* Enable the IMP port to be in the same VLAN as the other ports 504 * on a per-port basis such that we only have Port i and IMP in 505 * the same VLAN. 506 */ 507 b53_for_each_port(dev, i) { 508 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 509 pvlan |= BIT(cpu_port); 510 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 511 } 512 } 513 EXPORT_SYMBOL(b53_imp_vlan_setup); 514 515 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 516 { 517 struct b53_device *dev = ds->priv; 518 unsigned int cpu_port; 519 int ret = 0; 520 u16 pvlan; 521 522 if (!dsa_is_user_port(ds, port)) 523 return 0; 524 525 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 526 527 b53_br_egress_floods(ds, port, true, true); 528 529 if (dev->ops->irq_enable) 530 ret = dev->ops->irq_enable(dev, port); 531 if (ret) 532 return ret; 533 534 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 535 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 536 537 /* Set this port, and only this one to be in the default VLAN, 538 * if member of a bridge, restore its membership prior to 539 * bringing down this port. 540 */ 541 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 542 pvlan &= ~0x1ff; 543 pvlan |= BIT(port); 544 pvlan |= dev->ports[port].vlan_ctl_mask; 545 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 546 547 b53_imp_vlan_setup(ds, cpu_port); 548 549 /* If EEE was enabled, restore it */ 550 if (dev->ports[port].eee.eee_enabled) 551 b53_eee_enable_set(ds, port, true); 552 553 return 0; 554 } 555 EXPORT_SYMBOL(b53_enable_port); 556 557 void b53_disable_port(struct dsa_switch *ds, int port) 558 { 559 struct b53_device *dev = ds->priv; 560 u8 reg; 561 562 /* Disable Tx/Rx for the port */ 563 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 564 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 565 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 566 567 if (dev->ops->irq_disable) 568 dev->ops->irq_disable(dev, port); 569 } 570 EXPORT_SYMBOL(b53_disable_port); 571 572 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 573 { 574 struct b53_device *dev = ds->priv; 575 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 576 u8 hdr_ctl, val; 577 u16 reg; 578 579 /* Resolve which bit controls the Broadcom tag */ 580 switch (port) { 581 case 8: 582 val = BRCM_HDR_P8_EN; 583 break; 584 case 7: 585 val = BRCM_HDR_P7_EN; 586 break; 587 case 5: 588 val = BRCM_HDR_P5_EN; 589 break; 590 default: 591 val = 0; 592 break; 593 } 594 595 /* Enable management mode if tagging is requested */ 596 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 597 if (tag_en) 598 hdr_ctl |= SM_SW_FWD_MODE; 599 else 600 hdr_ctl &= ~SM_SW_FWD_MODE; 601 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 602 603 /* Configure the appropriate IMP port */ 604 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 605 if (port == 8) 606 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 607 else if (port == 5) 608 hdr_ctl |= GC_FRM_MGMT_PORT_M; 609 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 610 611 /* Enable Broadcom tags for IMP port */ 612 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 613 if (tag_en) 614 hdr_ctl |= val; 615 else 616 hdr_ctl &= ~val; 617 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 618 619 /* Registers below are only accessible on newer devices */ 620 if (!is58xx(dev)) 621 return; 622 623 /* Enable reception Broadcom tag for CPU TX (switch RX) to 624 * allow us to tag outgoing frames 625 */ 626 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 627 if (tag_en) 628 reg &= ~BIT(port); 629 else 630 reg |= BIT(port); 631 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 632 633 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 634 * allow delivering frames to the per-port net_devices 635 */ 636 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 637 if (tag_en) 638 reg &= ~BIT(port); 639 else 640 reg |= BIT(port); 641 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 642 } 643 EXPORT_SYMBOL(b53_brcm_hdr_setup); 644 645 static void b53_enable_cpu_port(struct b53_device *dev, int port) 646 { 647 u8 port_ctrl; 648 649 /* BCM5325 CPU port is at 8 */ 650 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 651 port = B53_CPU_PORT; 652 653 port_ctrl = PORT_CTRL_RX_BCST_EN | 654 PORT_CTRL_RX_MCST_EN | 655 PORT_CTRL_RX_UCST_EN; 656 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 657 658 b53_brcm_hdr_setup(dev->ds, port); 659 660 b53_br_egress_floods(dev->ds, port, true, true); 661 } 662 663 static void b53_enable_mib(struct b53_device *dev) 664 { 665 u8 gc; 666 667 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 668 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 669 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 670 } 671 672 static u16 b53_default_pvid(struct b53_device *dev) 673 { 674 if (is5325(dev) || is5365(dev)) 675 return 1; 676 else 677 return 0; 678 } 679 680 int b53_configure_vlan(struct dsa_switch *ds) 681 { 682 struct b53_device *dev = ds->priv; 683 struct b53_vlan vl = { 0 }; 684 struct b53_vlan *v; 685 int i, def_vid; 686 u16 vid; 687 688 def_vid = b53_default_pvid(dev); 689 690 /* clear all vlan entries */ 691 if (is5325(dev) || is5365(dev)) { 692 for (i = def_vid; i < dev->num_vlans; i++) 693 b53_set_vlan_entry(dev, i, &vl); 694 } else { 695 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 696 } 697 698 b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering); 699 700 b53_for_each_port(dev, i) 701 b53_write16(dev, B53_VLAN_PAGE, 702 B53_VLAN_PORT_DEF_TAG(i), def_vid); 703 704 /* Upon initial call we have not set-up any VLANs, but upon 705 * system resume, we need to restore all VLAN entries. 706 */ 707 for (vid = def_vid; vid < dev->num_vlans; vid++) { 708 v = &dev->vlans[vid]; 709 710 if (!v->members) 711 continue; 712 713 b53_set_vlan_entry(dev, vid, v); 714 b53_fast_age_vlan(dev, vid); 715 } 716 717 return 0; 718 } 719 EXPORT_SYMBOL(b53_configure_vlan); 720 721 static void b53_switch_reset_gpio(struct b53_device *dev) 722 { 723 int gpio = dev->reset_gpio; 724 725 if (gpio < 0) 726 return; 727 728 /* Reset sequence: RESET low(50ms)->high(20ms) 729 */ 730 gpio_set_value(gpio, 0); 731 mdelay(50); 732 733 gpio_set_value(gpio, 1); 734 mdelay(20); 735 736 dev->current_page = 0xff; 737 } 738 739 static int b53_switch_reset(struct b53_device *dev) 740 { 741 unsigned int timeout = 1000; 742 u8 mgmt, reg; 743 744 b53_switch_reset_gpio(dev); 745 746 if (is539x(dev)) { 747 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 748 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 749 } 750 751 /* This is specific to 58xx devices here, do not use is58xx() which 752 * covers the larger Starfigther 2 family, including 7445/7278 which 753 * still use this driver as a library and need to perform the reset 754 * earlier. 755 */ 756 if (dev->chip_id == BCM58XX_DEVICE_ID || 757 dev->chip_id == BCM583XX_DEVICE_ID) { 758 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 759 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 760 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 761 762 do { 763 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 764 if (!(reg & SW_RST)) 765 break; 766 767 usleep_range(1000, 2000); 768 } while (timeout-- > 0); 769 770 if (timeout == 0) 771 return -ETIMEDOUT; 772 } 773 774 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 775 776 if (!(mgmt & SM_SW_FWD_EN)) { 777 mgmt &= ~SM_SW_FWD_MODE; 778 mgmt |= SM_SW_FWD_EN; 779 780 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 781 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 782 783 if (!(mgmt & SM_SW_FWD_EN)) { 784 dev_err(dev->dev, "Failed to enable switch!\n"); 785 return -EINVAL; 786 } 787 } 788 789 b53_enable_mib(dev); 790 791 return b53_flush_arl(dev, FAST_AGE_STATIC); 792 } 793 794 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 795 { 796 struct b53_device *priv = ds->priv; 797 u16 value = 0; 798 int ret; 799 800 if (priv->ops->phy_read16) 801 ret = priv->ops->phy_read16(priv, addr, reg, &value); 802 else 803 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 804 reg * 2, &value); 805 806 return ret ? ret : value; 807 } 808 809 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 810 { 811 struct b53_device *priv = ds->priv; 812 813 if (priv->ops->phy_write16) 814 return priv->ops->phy_write16(priv, addr, reg, val); 815 816 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 817 } 818 819 static int b53_reset_switch(struct b53_device *priv) 820 { 821 /* reset vlans */ 822 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 823 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 824 825 priv->serdes_lane = B53_INVALID_LANE; 826 827 return b53_switch_reset(priv); 828 } 829 830 static int b53_apply_config(struct b53_device *priv) 831 { 832 /* disable switching */ 833 b53_set_forwarding(priv, 0); 834 835 b53_configure_vlan(priv->ds); 836 837 /* enable switching */ 838 b53_set_forwarding(priv, 1); 839 840 return 0; 841 } 842 843 static void b53_reset_mib(struct b53_device *priv) 844 { 845 u8 gc; 846 847 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 848 849 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 850 msleep(1); 851 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 852 msleep(1); 853 } 854 855 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 856 { 857 if (is5365(dev)) 858 return b53_mibs_65; 859 else if (is63xx(dev)) 860 return b53_mibs_63xx; 861 else if (is58xx(dev)) 862 return b53_mibs_58xx; 863 else 864 return b53_mibs; 865 } 866 867 static unsigned int b53_get_mib_size(struct b53_device *dev) 868 { 869 if (is5365(dev)) 870 return B53_MIBS_65_SIZE; 871 else if (is63xx(dev)) 872 return B53_MIBS_63XX_SIZE; 873 else if (is58xx(dev)) 874 return B53_MIBS_58XX_SIZE; 875 else 876 return B53_MIBS_SIZE; 877 } 878 879 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 880 { 881 /* These ports typically do not have built-in PHYs */ 882 switch (port) { 883 case B53_CPU_PORT_25: 884 case 7: 885 case B53_CPU_PORT: 886 return NULL; 887 } 888 889 return mdiobus_get_phy(ds->slave_mii_bus, port); 890 } 891 892 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 893 uint8_t *data) 894 { 895 struct b53_device *dev = ds->priv; 896 const struct b53_mib_desc *mibs = b53_get_mib(dev); 897 unsigned int mib_size = b53_get_mib_size(dev); 898 struct phy_device *phydev; 899 unsigned int i; 900 901 if (stringset == ETH_SS_STATS) { 902 for (i = 0; i < mib_size; i++) 903 strlcpy(data + i * ETH_GSTRING_LEN, 904 mibs[i].name, ETH_GSTRING_LEN); 905 } else if (stringset == ETH_SS_PHY_STATS) { 906 phydev = b53_get_phy_device(ds, port); 907 if (!phydev) 908 return; 909 910 phy_ethtool_get_strings(phydev, data); 911 } 912 } 913 EXPORT_SYMBOL(b53_get_strings); 914 915 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 916 { 917 struct b53_device *dev = ds->priv; 918 const struct b53_mib_desc *mibs = b53_get_mib(dev); 919 unsigned int mib_size = b53_get_mib_size(dev); 920 const struct b53_mib_desc *s; 921 unsigned int i; 922 u64 val = 0; 923 924 if (is5365(dev) && port == 5) 925 port = 8; 926 927 mutex_lock(&dev->stats_mutex); 928 929 for (i = 0; i < mib_size; i++) { 930 s = &mibs[i]; 931 932 if (s->size == 8) { 933 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 934 } else { 935 u32 val32; 936 937 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 938 &val32); 939 val = val32; 940 } 941 data[i] = (u64)val; 942 } 943 944 mutex_unlock(&dev->stats_mutex); 945 } 946 EXPORT_SYMBOL(b53_get_ethtool_stats); 947 948 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 949 { 950 struct phy_device *phydev; 951 952 phydev = b53_get_phy_device(ds, port); 953 if (!phydev) 954 return; 955 956 phy_ethtool_get_stats(phydev, NULL, data); 957 } 958 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 959 960 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 961 { 962 struct b53_device *dev = ds->priv; 963 struct phy_device *phydev; 964 965 if (sset == ETH_SS_STATS) { 966 return b53_get_mib_size(dev); 967 } else if (sset == ETH_SS_PHY_STATS) { 968 phydev = b53_get_phy_device(ds, port); 969 if (!phydev) 970 return 0; 971 972 return phy_ethtool_get_sset_count(phydev); 973 } 974 975 return 0; 976 } 977 EXPORT_SYMBOL(b53_get_sset_count); 978 979 static int b53_setup(struct dsa_switch *ds) 980 { 981 struct b53_device *dev = ds->priv; 982 unsigned int port; 983 int ret; 984 985 ret = b53_reset_switch(dev); 986 if (ret) { 987 dev_err(ds->dev, "failed to reset switch\n"); 988 return ret; 989 } 990 991 b53_reset_mib(dev); 992 993 ret = b53_apply_config(dev); 994 if (ret) 995 dev_err(ds->dev, "failed to apply configuration\n"); 996 997 /* Configure IMP/CPU port, disable all other ports. Enabled 998 * ports will be configured with .port_enable 999 */ 1000 for (port = 0; port < dev->num_ports; port++) { 1001 if (dsa_is_cpu_port(ds, port)) 1002 b53_enable_cpu_port(dev, port); 1003 else 1004 b53_disable_port(ds, port); 1005 } 1006 1007 /* Let DSA handle the case were multiple bridges span the same switch 1008 * device and different VLAN awareness settings are requested, which 1009 * would be breaking filtering semantics for any of the other bridge 1010 * devices. (not hardware supported) 1011 */ 1012 ds->vlan_filtering_is_global = true; 1013 1014 return ret; 1015 } 1016 1017 static void b53_force_link(struct b53_device *dev, int port, int link) 1018 { 1019 u8 reg, val, off; 1020 1021 /* Override the port settings */ 1022 if (port == dev->cpu_port) { 1023 off = B53_PORT_OVERRIDE_CTRL; 1024 val = PORT_OVERRIDE_EN; 1025 } else { 1026 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1027 val = GMII_PO_EN; 1028 } 1029 1030 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1031 reg |= val; 1032 if (link) 1033 reg |= PORT_OVERRIDE_LINK; 1034 else 1035 reg &= ~PORT_OVERRIDE_LINK; 1036 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1037 } 1038 1039 static void b53_force_port_config(struct b53_device *dev, int port, 1040 int speed, int duplex, int pause) 1041 { 1042 u8 reg, val, off; 1043 1044 /* Override the port settings */ 1045 if (port == dev->cpu_port) { 1046 off = B53_PORT_OVERRIDE_CTRL; 1047 val = PORT_OVERRIDE_EN; 1048 } else { 1049 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1050 val = GMII_PO_EN; 1051 } 1052 1053 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1054 reg |= val; 1055 if (duplex == DUPLEX_FULL) 1056 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1057 else 1058 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1059 1060 switch (speed) { 1061 case 2000: 1062 reg |= PORT_OVERRIDE_SPEED_2000M; 1063 /* fallthrough */ 1064 case SPEED_1000: 1065 reg |= PORT_OVERRIDE_SPEED_1000M; 1066 break; 1067 case SPEED_100: 1068 reg |= PORT_OVERRIDE_SPEED_100M; 1069 break; 1070 case SPEED_10: 1071 reg |= PORT_OVERRIDE_SPEED_10M; 1072 break; 1073 default: 1074 dev_err(dev->dev, "unknown speed: %d\n", speed); 1075 return; 1076 } 1077 1078 if (pause & MLO_PAUSE_RX) 1079 reg |= PORT_OVERRIDE_RX_FLOW; 1080 if (pause & MLO_PAUSE_TX) 1081 reg |= PORT_OVERRIDE_TX_FLOW; 1082 1083 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1084 } 1085 1086 static void b53_adjust_link(struct dsa_switch *ds, int port, 1087 struct phy_device *phydev) 1088 { 1089 struct b53_device *dev = ds->priv; 1090 struct ethtool_eee *p = &dev->ports[port].eee; 1091 u8 rgmii_ctrl = 0, reg = 0, off; 1092 int pause = 0; 1093 1094 if (!phy_is_pseudo_fixed_link(phydev)) 1095 return; 1096 1097 /* Enable flow control on BCM5301x's CPU port */ 1098 if (is5301x(dev) && port == dev->cpu_port) 1099 pause = MLO_PAUSE_TXRX_MASK; 1100 1101 if (phydev->pause) { 1102 if (phydev->asym_pause) 1103 pause |= MLO_PAUSE_TX; 1104 pause |= MLO_PAUSE_RX; 1105 } 1106 1107 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause); 1108 b53_force_link(dev, port, phydev->link); 1109 1110 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1111 if (port == 8) 1112 off = B53_RGMII_CTRL_IMP; 1113 else 1114 off = B53_RGMII_CTRL_P(port); 1115 1116 /* Configure the port RGMII clock delay by DLL disabled and 1117 * tx_clk aligned timing (restoring to reset defaults) 1118 */ 1119 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1120 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1121 RGMII_CTRL_TIMING_SEL); 1122 1123 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1124 * sure that we enable the port TX clock internal delay to 1125 * account for this internal delay that is inserted, otherwise 1126 * the switch won't be able to receive correctly. 1127 * 1128 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1129 * any delay neither on transmission nor reception, so the 1130 * BCM53125 must also be configured accordingly to account for 1131 * the lack of delay and introduce 1132 * 1133 * The BCM53125 switch has its RX clock and TX clock control 1134 * swapped, hence the reason why we modify the TX clock path in 1135 * the "RGMII" case 1136 */ 1137 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1138 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1139 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1140 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1141 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1142 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1143 1144 dev_info(ds->dev, "Configured port %d for %s\n", port, 1145 phy_modes(phydev->interface)); 1146 } 1147 1148 /* configure MII port if necessary */ 1149 if (is5325(dev)) { 1150 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1151 ®); 1152 1153 /* reverse mii needs to be enabled */ 1154 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1155 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1156 reg | PORT_OVERRIDE_RV_MII_25); 1157 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1158 ®); 1159 1160 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1161 dev_err(ds->dev, 1162 "Failed to enable reverse MII mode\n"); 1163 return; 1164 } 1165 } 1166 } else if (is5301x(dev)) { 1167 if (port != dev->cpu_port) { 1168 b53_force_port_config(dev, dev->cpu_port, 2000, 1169 DUPLEX_FULL, MLO_PAUSE_TXRX_MASK); 1170 b53_force_link(dev, dev->cpu_port, 1); 1171 } 1172 } 1173 1174 /* Re-negotiate EEE if it was enabled already */ 1175 p->eee_enabled = b53_eee_init(ds, port, phydev); 1176 } 1177 1178 void b53_port_event(struct dsa_switch *ds, int port) 1179 { 1180 struct b53_device *dev = ds->priv; 1181 bool link; 1182 u16 sts; 1183 1184 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1185 link = !!(sts & BIT(port)); 1186 dsa_port_phylink_mac_change(ds, port, link); 1187 } 1188 EXPORT_SYMBOL(b53_port_event); 1189 1190 void b53_phylink_validate(struct dsa_switch *ds, int port, 1191 unsigned long *supported, 1192 struct phylink_link_state *state) 1193 { 1194 struct b53_device *dev = ds->priv; 1195 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1196 1197 if (dev->ops->serdes_phylink_validate) 1198 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1199 1200 /* Allow all the expected bits */ 1201 phylink_set(mask, Autoneg); 1202 phylink_set_port_modes(mask); 1203 phylink_set(mask, Pause); 1204 phylink_set(mask, Asym_Pause); 1205 1206 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1207 * support Gigabit, including Half duplex. 1208 */ 1209 if (state->interface != PHY_INTERFACE_MODE_MII && 1210 state->interface != PHY_INTERFACE_MODE_REVMII && 1211 !phy_interface_mode_is_8023z(state->interface) && 1212 !(is5325(dev) || is5365(dev))) { 1213 phylink_set(mask, 1000baseT_Full); 1214 phylink_set(mask, 1000baseT_Half); 1215 } 1216 1217 if (!phy_interface_mode_is_8023z(state->interface)) { 1218 phylink_set(mask, 10baseT_Half); 1219 phylink_set(mask, 10baseT_Full); 1220 phylink_set(mask, 100baseT_Half); 1221 phylink_set(mask, 100baseT_Full); 1222 } 1223 1224 bitmap_and(supported, supported, mask, 1225 __ETHTOOL_LINK_MODE_MASK_NBITS); 1226 bitmap_and(state->advertising, state->advertising, mask, 1227 __ETHTOOL_LINK_MODE_MASK_NBITS); 1228 1229 phylink_helper_basex_speed(state); 1230 } 1231 EXPORT_SYMBOL(b53_phylink_validate); 1232 1233 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1234 struct phylink_link_state *state) 1235 { 1236 struct b53_device *dev = ds->priv; 1237 int ret = -EOPNOTSUPP; 1238 1239 if ((phy_interface_mode_is_8023z(state->interface) || 1240 state->interface == PHY_INTERFACE_MODE_SGMII) && 1241 dev->ops->serdes_link_state) 1242 ret = dev->ops->serdes_link_state(dev, port, state); 1243 1244 return ret; 1245 } 1246 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1247 1248 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1249 unsigned int mode, 1250 const struct phylink_link_state *state) 1251 { 1252 struct b53_device *dev = ds->priv; 1253 1254 if (mode == MLO_AN_PHY) 1255 return; 1256 1257 if (mode == MLO_AN_FIXED) { 1258 b53_force_port_config(dev, port, state->speed, 1259 state->duplex, state->pause); 1260 return; 1261 } 1262 1263 if ((phy_interface_mode_is_8023z(state->interface) || 1264 state->interface == PHY_INTERFACE_MODE_SGMII) && 1265 dev->ops->serdes_config) 1266 dev->ops->serdes_config(dev, port, mode, state); 1267 } 1268 EXPORT_SYMBOL(b53_phylink_mac_config); 1269 1270 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1271 { 1272 struct b53_device *dev = ds->priv; 1273 1274 if (dev->ops->serdes_an_restart) 1275 dev->ops->serdes_an_restart(dev, port); 1276 } 1277 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1278 1279 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1280 unsigned int mode, 1281 phy_interface_t interface) 1282 { 1283 struct b53_device *dev = ds->priv; 1284 1285 if (mode == MLO_AN_PHY) 1286 return; 1287 1288 if (mode == MLO_AN_FIXED) { 1289 b53_force_link(dev, port, false); 1290 return; 1291 } 1292 1293 if (phy_interface_mode_is_8023z(interface) && 1294 dev->ops->serdes_link_set) 1295 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1296 } 1297 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1298 1299 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1300 unsigned int mode, 1301 phy_interface_t interface, 1302 struct phy_device *phydev, 1303 int speed, int duplex, 1304 bool tx_pause, bool rx_pause) 1305 { 1306 struct b53_device *dev = ds->priv; 1307 1308 if (mode == MLO_AN_PHY) 1309 return; 1310 1311 if (mode == MLO_AN_FIXED) { 1312 b53_force_link(dev, port, true); 1313 return; 1314 } 1315 1316 if (phy_interface_mode_is_8023z(interface) && 1317 dev->ops->serdes_link_set) 1318 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1319 } 1320 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1321 1322 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 1323 { 1324 struct b53_device *dev = ds->priv; 1325 u16 pvid, new_pvid; 1326 1327 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1328 new_pvid = pvid; 1329 if (!vlan_filtering) { 1330 /* Filtering is currently enabled, use the default PVID since 1331 * the bridge does not expect tagging anymore 1332 */ 1333 dev->ports[port].pvid = pvid; 1334 new_pvid = b53_default_pvid(dev); 1335 } else { 1336 /* Filtering is currently disabled, restore the previous PVID */ 1337 new_pvid = dev->ports[port].pvid; 1338 } 1339 1340 if (pvid != new_pvid) 1341 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1342 new_pvid); 1343 1344 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering); 1345 1346 return 0; 1347 } 1348 EXPORT_SYMBOL(b53_vlan_filtering); 1349 1350 int b53_vlan_prepare(struct dsa_switch *ds, int port, 1351 const struct switchdev_obj_port_vlan *vlan) 1352 { 1353 struct b53_device *dev = ds->priv; 1354 1355 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 1356 return -EOPNOTSUPP; 1357 1358 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1359 * receiving VLAN tagged frames at all, we can still allow the port to 1360 * be configured for egress untagged. 1361 */ 1362 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1363 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1364 return -EINVAL; 1365 1366 if (vlan->vid_end > dev->num_vlans) 1367 return -ERANGE; 1368 1369 b53_enable_vlan(dev, true, ds->vlan_filtering); 1370 1371 return 0; 1372 } 1373 EXPORT_SYMBOL(b53_vlan_prepare); 1374 1375 void b53_vlan_add(struct dsa_switch *ds, int port, 1376 const struct switchdev_obj_port_vlan *vlan) 1377 { 1378 struct b53_device *dev = ds->priv; 1379 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1380 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1381 struct b53_vlan *vl; 1382 u16 vid; 1383 1384 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1385 vl = &dev->vlans[vid]; 1386 1387 b53_get_vlan_entry(dev, vid, vl); 1388 1389 if (vid == 0 && vid == b53_default_pvid(dev)) 1390 untagged = true; 1391 1392 vl->members |= BIT(port); 1393 if (untagged && !dsa_is_cpu_port(ds, port)) 1394 vl->untag |= BIT(port); 1395 else 1396 vl->untag &= ~BIT(port); 1397 1398 b53_set_vlan_entry(dev, vid, vl); 1399 b53_fast_age_vlan(dev, vid); 1400 } 1401 1402 if (pvid && !dsa_is_cpu_port(ds, port)) { 1403 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1404 vlan->vid_end); 1405 b53_fast_age_vlan(dev, vid); 1406 } 1407 } 1408 EXPORT_SYMBOL(b53_vlan_add); 1409 1410 int b53_vlan_del(struct dsa_switch *ds, int port, 1411 const struct switchdev_obj_port_vlan *vlan) 1412 { 1413 struct b53_device *dev = ds->priv; 1414 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1415 struct b53_vlan *vl; 1416 u16 vid; 1417 u16 pvid; 1418 1419 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1420 1421 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1422 vl = &dev->vlans[vid]; 1423 1424 b53_get_vlan_entry(dev, vid, vl); 1425 1426 vl->members &= ~BIT(port); 1427 1428 if (pvid == vid) 1429 pvid = b53_default_pvid(dev); 1430 1431 if (untagged && !dsa_is_cpu_port(ds, port)) 1432 vl->untag &= ~(BIT(port)); 1433 1434 b53_set_vlan_entry(dev, vid, vl); 1435 b53_fast_age_vlan(dev, vid); 1436 } 1437 1438 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1439 b53_fast_age_vlan(dev, pvid); 1440 1441 return 0; 1442 } 1443 EXPORT_SYMBOL(b53_vlan_del); 1444 1445 /* Address Resolution Logic routines */ 1446 static int b53_arl_op_wait(struct b53_device *dev) 1447 { 1448 unsigned int timeout = 10; 1449 u8 reg; 1450 1451 do { 1452 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1453 if (!(reg & ARLTBL_START_DONE)) 1454 return 0; 1455 1456 usleep_range(1000, 2000); 1457 } while (timeout--); 1458 1459 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1460 1461 return -ETIMEDOUT; 1462 } 1463 1464 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1465 { 1466 u8 reg; 1467 1468 if (op > ARLTBL_RW) 1469 return -EINVAL; 1470 1471 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1472 reg |= ARLTBL_START_DONE; 1473 if (op) 1474 reg |= ARLTBL_RW; 1475 else 1476 reg &= ~ARLTBL_RW; 1477 if (dev->vlan_enabled) 1478 reg &= ~ARLTBL_IVL_SVL_SELECT; 1479 else 1480 reg |= ARLTBL_IVL_SVL_SELECT; 1481 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1482 1483 return b53_arl_op_wait(dev); 1484 } 1485 1486 static int b53_arl_read(struct b53_device *dev, u64 mac, 1487 u16 vid, struct b53_arl_entry *ent, u8 *idx, 1488 bool is_valid) 1489 { 1490 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1491 unsigned int i; 1492 int ret; 1493 1494 ret = b53_arl_op_wait(dev); 1495 if (ret) 1496 return ret; 1497 1498 bitmap_zero(free_bins, dev->num_arl_entries); 1499 1500 /* Read the bins */ 1501 for (i = 0; i < dev->num_arl_entries; i++) { 1502 u64 mac_vid; 1503 u32 fwd_entry; 1504 1505 b53_read64(dev, B53_ARLIO_PAGE, 1506 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1507 b53_read32(dev, B53_ARLIO_PAGE, 1508 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1509 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1510 1511 if (!(fwd_entry & ARLTBL_VALID)) { 1512 set_bit(i, free_bins); 1513 continue; 1514 } 1515 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1516 continue; 1517 if (dev->vlan_enabled && 1518 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1519 continue; 1520 *idx = i; 1521 return 0; 1522 } 1523 1524 if (bitmap_weight(free_bins, dev->num_arl_entries) == 0) 1525 return -ENOSPC; 1526 1527 *idx = find_first_bit(free_bins, dev->num_arl_entries); 1528 1529 return -ENOENT; 1530 } 1531 1532 static int b53_arl_op(struct b53_device *dev, int op, int port, 1533 const unsigned char *addr, u16 vid, bool is_valid) 1534 { 1535 struct b53_arl_entry ent; 1536 u32 fwd_entry; 1537 u64 mac, mac_vid = 0; 1538 u8 idx = 0; 1539 int ret; 1540 1541 /* Convert the array into a 64-bit MAC */ 1542 mac = ether_addr_to_u64(addr); 1543 1544 /* Perform a read for the given MAC and VID */ 1545 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1546 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1547 1548 /* Issue a read operation for this MAC */ 1549 ret = b53_arl_rw_op(dev, 1); 1550 if (ret) 1551 return ret; 1552 1553 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid); 1554 /* If this is a read, just finish now */ 1555 if (op) 1556 return ret; 1557 1558 switch (ret) { 1559 case -ENOSPC: 1560 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1561 addr, vid); 1562 return is_valid ? ret : 0; 1563 case -ENOENT: 1564 /* We could not find a matching MAC, so reset to a new entry */ 1565 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1566 addr, vid, idx); 1567 fwd_entry = 0; 1568 break; 1569 default: 1570 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1571 addr, vid, idx); 1572 break; 1573 } 1574 1575 /* For multicast address, the port is a bitmask and the validity 1576 * is determined by having at least one port being still active 1577 */ 1578 if (!is_multicast_ether_addr(addr)) { 1579 ent.port = port; 1580 ent.is_valid = is_valid; 1581 } else { 1582 if (is_valid) 1583 ent.port |= BIT(port); 1584 else 1585 ent.port &= ~BIT(port); 1586 1587 ent.is_valid = !!(ent.port); 1588 } 1589 1590 ent.vid = vid; 1591 ent.is_static = true; 1592 ent.is_age = false; 1593 memcpy(ent.mac, addr, ETH_ALEN); 1594 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1595 1596 b53_write64(dev, B53_ARLIO_PAGE, 1597 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1598 b53_write32(dev, B53_ARLIO_PAGE, 1599 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1600 1601 return b53_arl_rw_op(dev, 0); 1602 } 1603 1604 int b53_fdb_add(struct dsa_switch *ds, int port, 1605 const unsigned char *addr, u16 vid) 1606 { 1607 struct b53_device *priv = ds->priv; 1608 1609 /* 5325 and 5365 require some more massaging, but could 1610 * be supported eventually 1611 */ 1612 if (is5325(priv) || is5365(priv)) 1613 return -EOPNOTSUPP; 1614 1615 return b53_arl_op(priv, 0, port, addr, vid, true); 1616 } 1617 EXPORT_SYMBOL(b53_fdb_add); 1618 1619 int b53_fdb_del(struct dsa_switch *ds, int port, 1620 const unsigned char *addr, u16 vid) 1621 { 1622 struct b53_device *priv = ds->priv; 1623 1624 return b53_arl_op(priv, 0, port, addr, vid, false); 1625 } 1626 EXPORT_SYMBOL(b53_fdb_del); 1627 1628 static int b53_arl_search_wait(struct b53_device *dev) 1629 { 1630 unsigned int timeout = 1000; 1631 u8 reg; 1632 1633 do { 1634 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1635 if (!(reg & ARL_SRCH_STDN)) 1636 return 0; 1637 1638 if (reg & ARL_SRCH_VLID) 1639 return 0; 1640 1641 usleep_range(1000, 2000); 1642 } while (timeout--); 1643 1644 return -ETIMEDOUT; 1645 } 1646 1647 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1648 struct b53_arl_entry *ent) 1649 { 1650 u64 mac_vid; 1651 u32 fwd_entry; 1652 1653 b53_read64(dev, B53_ARLIO_PAGE, 1654 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1655 b53_read32(dev, B53_ARLIO_PAGE, 1656 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1657 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1658 } 1659 1660 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1661 dsa_fdb_dump_cb_t *cb, void *data) 1662 { 1663 if (!ent->is_valid) 1664 return 0; 1665 1666 if (port != ent->port) 1667 return 0; 1668 1669 return cb(ent->mac, ent->vid, ent->is_static, data); 1670 } 1671 1672 int b53_fdb_dump(struct dsa_switch *ds, int port, 1673 dsa_fdb_dump_cb_t *cb, void *data) 1674 { 1675 struct b53_device *priv = ds->priv; 1676 struct b53_arl_entry results[2]; 1677 unsigned int count = 0; 1678 int ret; 1679 u8 reg; 1680 1681 /* Start search operation */ 1682 reg = ARL_SRCH_STDN; 1683 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1684 1685 do { 1686 ret = b53_arl_search_wait(priv); 1687 if (ret) 1688 return ret; 1689 1690 b53_arl_search_rd(priv, 0, &results[0]); 1691 ret = b53_fdb_copy(port, &results[0], cb, data); 1692 if (ret) 1693 return ret; 1694 1695 if (priv->num_arl_entries > 2) { 1696 b53_arl_search_rd(priv, 1, &results[1]); 1697 ret = b53_fdb_copy(port, &results[1], cb, data); 1698 if (ret) 1699 return ret; 1700 1701 if (!results[0].is_valid && !results[1].is_valid) 1702 break; 1703 } 1704 1705 } while (count++ < 1024); 1706 1707 return 0; 1708 } 1709 EXPORT_SYMBOL(b53_fdb_dump); 1710 1711 int b53_mdb_prepare(struct dsa_switch *ds, int port, 1712 const struct switchdev_obj_port_mdb *mdb) 1713 { 1714 struct b53_device *priv = ds->priv; 1715 1716 /* 5325 and 5365 require some more massaging, but could 1717 * be supported eventually 1718 */ 1719 if (is5325(priv) || is5365(priv)) 1720 return -EOPNOTSUPP; 1721 1722 return 0; 1723 } 1724 EXPORT_SYMBOL(b53_mdb_prepare); 1725 1726 void b53_mdb_add(struct dsa_switch *ds, int port, 1727 const struct switchdev_obj_port_mdb *mdb) 1728 { 1729 struct b53_device *priv = ds->priv; 1730 int ret; 1731 1732 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1733 if (ret) 1734 dev_err(ds->dev, "failed to add MDB entry\n"); 1735 } 1736 EXPORT_SYMBOL(b53_mdb_add); 1737 1738 int b53_mdb_del(struct dsa_switch *ds, int port, 1739 const struct switchdev_obj_port_mdb *mdb) 1740 { 1741 struct b53_device *priv = ds->priv; 1742 int ret; 1743 1744 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1745 if (ret) 1746 dev_err(ds->dev, "failed to delete MDB entry\n"); 1747 1748 return ret; 1749 } 1750 EXPORT_SYMBOL(b53_mdb_del); 1751 1752 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1753 { 1754 struct b53_device *dev = ds->priv; 1755 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1756 u16 pvlan, reg; 1757 unsigned int i; 1758 1759 /* On 7278, port 7 which connects to the ASP should only receive 1760 * traffic from matching CFP rules. 1761 */ 1762 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1763 return -EINVAL; 1764 1765 /* Make this port leave the all VLANs join since we will have proper 1766 * VLAN entries from now on 1767 */ 1768 if (is58xx(dev)) { 1769 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1770 reg &= ~BIT(port); 1771 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1772 reg &= ~BIT(cpu_port); 1773 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1774 } 1775 1776 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1777 1778 b53_for_each_port(dev, i) { 1779 if (dsa_to_port(ds, i)->bridge_dev != br) 1780 continue; 1781 1782 /* Add this local port to the remote port VLAN control 1783 * membership and update the remote port bitmask 1784 */ 1785 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1786 reg |= BIT(port); 1787 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1788 dev->ports[i].vlan_ctl_mask = reg; 1789 1790 pvlan |= BIT(i); 1791 } 1792 1793 /* Configure the local port VLAN control membership to include 1794 * remote ports and update the local port bitmask 1795 */ 1796 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1797 dev->ports[port].vlan_ctl_mask = pvlan; 1798 1799 return 0; 1800 } 1801 EXPORT_SYMBOL(b53_br_join); 1802 1803 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1804 { 1805 struct b53_device *dev = ds->priv; 1806 struct b53_vlan *vl = &dev->vlans[0]; 1807 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1808 unsigned int i; 1809 u16 pvlan, reg, pvid; 1810 1811 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1812 1813 b53_for_each_port(dev, i) { 1814 /* Don't touch the remaining ports */ 1815 if (dsa_to_port(ds, i)->bridge_dev != br) 1816 continue; 1817 1818 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1819 reg &= ~BIT(port); 1820 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1821 dev->ports[port].vlan_ctl_mask = reg; 1822 1823 /* Prevent self removal to preserve isolation */ 1824 if (port != i) 1825 pvlan &= ~BIT(i); 1826 } 1827 1828 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1829 dev->ports[port].vlan_ctl_mask = pvlan; 1830 1831 pvid = b53_default_pvid(dev); 1832 1833 /* Make this port join all VLANs without VLAN entries */ 1834 if (is58xx(dev)) { 1835 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1836 reg |= BIT(port); 1837 if (!(reg & BIT(cpu_port))) 1838 reg |= BIT(cpu_port); 1839 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1840 } else { 1841 b53_get_vlan_entry(dev, pvid, vl); 1842 vl->members |= BIT(port) | BIT(cpu_port); 1843 vl->untag |= BIT(port) | BIT(cpu_port); 1844 b53_set_vlan_entry(dev, pvid, vl); 1845 } 1846 } 1847 EXPORT_SYMBOL(b53_br_leave); 1848 1849 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1850 { 1851 struct b53_device *dev = ds->priv; 1852 u8 hw_state; 1853 u8 reg; 1854 1855 switch (state) { 1856 case BR_STATE_DISABLED: 1857 hw_state = PORT_CTRL_DIS_STATE; 1858 break; 1859 case BR_STATE_LISTENING: 1860 hw_state = PORT_CTRL_LISTEN_STATE; 1861 break; 1862 case BR_STATE_LEARNING: 1863 hw_state = PORT_CTRL_LEARN_STATE; 1864 break; 1865 case BR_STATE_FORWARDING: 1866 hw_state = PORT_CTRL_FWD_STATE; 1867 break; 1868 case BR_STATE_BLOCKING: 1869 hw_state = PORT_CTRL_BLOCK_STATE; 1870 break; 1871 default: 1872 dev_err(ds->dev, "invalid STP state: %d\n", state); 1873 return; 1874 } 1875 1876 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1877 reg &= ~PORT_CTRL_STP_STATE_MASK; 1878 reg |= hw_state; 1879 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1880 } 1881 EXPORT_SYMBOL(b53_br_set_stp_state); 1882 1883 void b53_br_fast_age(struct dsa_switch *ds, int port) 1884 { 1885 struct b53_device *dev = ds->priv; 1886 1887 if (b53_fast_age_port(dev, port)) 1888 dev_err(ds->dev, "fast ageing failed\n"); 1889 } 1890 EXPORT_SYMBOL(b53_br_fast_age); 1891 1892 int b53_br_egress_floods(struct dsa_switch *ds, int port, 1893 bool unicast, bool multicast) 1894 { 1895 struct b53_device *dev = ds->priv; 1896 u16 uc, mc; 1897 1898 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 1899 if (unicast) 1900 uc |= BIT(port); 1901 else 1902 uc &= ~BIT(port); 1903 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 1904 1905 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 1906 if (multicast) 1907 mc |= BIT(port); 1908 else 1909 mc &= ~BIT(port); 1910 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 1911 1912 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 1913 if (multicast) 1914 mc |= BIT(port); 1915 else 1916 mc &= ~BIT(port); 1917 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 1918 1919 return 0; 1920 1921 } 1922 EXPORT_SYMBOL(b53_br_egress_floods); 1923 1924 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 1925 { 1926 /* Broadcom switches will accept enabling Broadcom tags on the 1927 * following ports: 5, 7 and 8, any other port is not supported 1928 */ 1929 switch (port) { 1930 case B53_CPU_PORT_25: 1931 case 7: 1932 case B53_CPU_PORT: 1933 return true; 1934 } 1935 1936 return false; 1937 } 1938 1939 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 1940 enum dsa_tag_protocol tag_protocol) 1941 { 1942 bool ret = b53_possible_cpu_port(ds, port); 1943 1944 if (!ret) { 1945 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 1946 port); 1947 return ret; 1948 } 1949 1950 switch (tag_protocol) { 1951 case DSA_TAG_PROTO_BRCM: 1952 case DSA_TAG_PROTO_BRCM_PREPEND: 1953 dev_warn(ds->dev, 1954 "Port %d is stacked to Broadcom tag switch\n", port); 1955 ret = false; 1956 break; 1957 default: 1958 ret = true; 1959 break; 1960 } 1961 1962 return ret; 1963 } 1964 1965 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 1966 enum dsa_tag_protocol mprot) 1967 { 1968 struct b53_device *dev = ds->priv; 1969 1970 /* Older models (5325, 5365) support a different tag format that we do 1971 * not support in net/dsa/tag_brcm.c yet. 1972 */ 1973 if (is5325(dev) || is5365(dev) || 1974 !b53_can_enable_brcm_tags(ds, port, mprot)) { 1975 dev->tag_protocol = DSA_TAG_PROTO_NONE; 1976 goto out; 1977 } 1978 1979 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 1980 * which requires us to use the prepended Broadcom tag type 1981 */ 1982 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 1983 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 1984 goto out; 1985 } 1986 1987 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 1988 out: 1989 return dev->tag_protocol; 1990 } 1991 EXPORT_SYMBOL(b53_get_tag_protocol); 1992 1993 int b53_mirror_add(struct dsa_switch *ds, int port, 1994 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1995 { 1996 struct b53_device *dev = ds->priv; 1997 u16 reg, loc; 1998 1999 if (ingress) 2000 loc = B53_IG_MIR_CTL; 2001 else 2002 loc = B53_EG_MIR_CTL; 2003 2004 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2005 reg |= BIT(port); 2006 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2007 2008 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2009 reg &= ~CAP_PORT_MASK; 2010 reg |= mirror->to_local_port; 2011 reg |= MIRROR_EN; 2012 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2013 2014 return 0; 2015 } 2016 EXPORT_SYMBOL(b53_mirror_add); 2017 2018 void b53_mirror_del(struct dsa_switch *ds, int port, 2019 struct dsa_mall_mirror_tc_entry *mirror) 2020 { 2021 struct b53_device *dev = ds->priv; 2022 bool loc_disable = false, other_loc_disable = false; 2023 u16 reg, loc; 2024 2025 if (mirror->ingress) 2026 loc = B53_IG_MIR_CTL; 2027 else 2028 loc = B53_EG_MIR_CTL; 2029 2030 /* Update the desired ingress/egress register */ 2031 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2032 reg &= ~BIT(port); 2033 if (!(reg & MIRROR_MASK)) 2034 loc_disable = true; 2035 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2036 2037 /* Now look at the other one to know if we can disable mirroring 2038 * entirely 2039 */ 2040 if (mirror->ingress) 2041 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2042 else 2043 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2044 if (!(reg & MIRROR_MASK)) 2045 other_loc_disable = true; 2046 2047 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2048 /* Both no longer have ports, let's disable mirroring */ 2049 if (loc_disable && other_loc_disable) { 2050 reg &= ~MIRROR_EN; 2051 reg &= ~mirror->to_local_port; 2052 } 2053 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2054 } 2055 EXPORT_SYMBOL(b53_mirror_del); 2056 2057 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 2058 { 2059 struct b53_device *dev = ds->priv; 2060 u16 reg; 2061 2062 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 2063 if (enable) 2064 reg |= BIT(port); 2065 else 2066 reg &= ~BIT(port); 2067 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 2068 } 2069 EXPORT_SYMBOL(b53_eee_enable_set); 2070 2071 2072 /* Returns 0 if EEE was not enabled, or 1 otherwise 2073 */ 2074 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2075 { 2076 int ret; 2077 2078 ret = phy_init_eee(phy, 0); 2079 if (ret) 2080 return 0; 2081 2082 b53_eee_enable_set(ds, port, true); 2083 2084 return 1; 2085 } 2086 EXPORT_SYMBOL(b53_eee_init); 2087 2088 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2089 { 2090 struct b53_device *dev = ds->priv; 2091 struct ethtool_eee *p = &dev->ports[port].eee; 2092 u16 reg; 2093 2094 if (is5325(dev) || is5365(dev)) 2095 return -EOPNOTSUPP; 2096 2097 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 2098 e->eee_enabled = p->eee_enabled; 2099 e->eee_active = !!(reg & BIT(port)); 2100 2101 return 0; 2102 } 2103 EXPORT_SYMBOL(b53_get_mac_eee); 2104 2105 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2106 { 2107 struct b53_device *dev = ds->priv; 2108 struct ethtool_eee *p = &dev->ports[port].eee; 2109 2110 if (is5325(dev) || is5365(dev)) 2111 return -EOPNOTSUPP; 2112 2113 p->eee_enabled = e->eee_enabled; 2114 b53_eee_enable_set(ds, port, e->eee_enabled); 2115 2116 return 0; 2117 } 2118 EXPORT_SYMBOL(b53_set_mac_eee); 2119 2120 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2121 { 2122 struct b53_device *dev = ds->priv; 2123 bool enable_jumbo; 2124 bool allow_10_100; 2125 2126 if (is5325(dev) || is5365(dev)) 2127 return -EOPNOTSUPP; 2128 2129 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2130 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2131 2132 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2133 } 2134 2135 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2136 { 2137 return JMS_MAX_SIZE; 2138 } 2139 2140 static const struct dsa_switch_ops b53_switch_ops = { 2141 .get_tag_protocol = b53_get_tag_protocol, 2142 .setup = b53_setup, 2143 .get_strings = b53_get_strings, 2144 .get_ethtool_stats = b53_get_ethtool_stats, 2145 .get_sset_count = b53_get_sset_count, 2146 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2147 .phy_read = b53_phy_read16, 2148 .phy_write = b53_phy_write16, 2149 .adjust_link = b53_adjust_link, 2150 .phylink_validate = b53_phylink_validate, 2151 .phylink_mac_link_state = b53_phylink_mac_link_state, 2152 .phylink_mac_config = b53_phylink_mac_config, 2153 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 2154 .phylink_mac_link_down = b53_phylink_mac_link_down, 2155 .phylink_mac_link_up = b53_phylink_mac_link_up, 2156 .port_enable = b53_enable_port, 2157 .port_disable = b53_disable_port, 2158 .get_mac_eee = b53_get_mac_eee, 2159 .set_mac_eee = b53_set_mac_eee, 2160 .port_bridge_join = b53_br_join, 2161 .port_bridge_leave = b53_br_leave, 2162 .port_stp_state_set = b53_br_set_stp_state, 2163 .port_fast_age = b53_br_fast_age, 2164 .port_egress_floods = b53_br_egress_floods, 2165 .port_vlan_filtering = b53_vlan_filtering, 2166 .port_vlan_prepare = b53_vlan_prepare, 2167 .port_vlan_add = b53_vlan_add, 2168 .port_vlan_del = b53_vlan_del, 2169 .port_fdb_dump = b53_fdb_dump, 2170 .port_fdb_add = b53_fdb_add, 2171 .port_fdb_del = b53_fdb_del, 2172 .port_mirror_add = b53_mirror_add, 2173 .port_mirror_del = b53_mirror_del, 2174 .port_mdb_prepare = b53_mdb_prepare, 2175 .port_mdb_add = b53_mdb_add, 2176 .port_mdb_del = b53_mdb_del, 2177 .port_max_mtu = b53_get_max_mtu, 2178 .port_change_mtu = b53_change_mtu, 2179 }; 2180 2181 struct b53_chip_data { 2182 u32 chip_id; 2183 const char *dev_name; 2184 u16 vlans; 2185 u16 enabled_ports; 2186 u8 cpu_port; 2187 u8 vta_regs[3]; 2188 u8 arl_entries; 2189 u8 duplex_reg; 2190 u8 jumbo_pm_reg; 2191 u8 jumbo_size_reg; 2192 }; 2193 2194 #define B53_VTA_REGS \ 2195 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2196 #define B53_VTA_REGS_9798 \ 2197 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2198 #define B53_VTA_REGS_63XX \ 2199 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2200 2201 static const struct b53_chip_data b53_switch_chips[] = { 2202 { 2203 .chip_id = BCM5325_DEVICE_ID, 2204 .dev_name = "BCM5325", 2205 .vlans = 16, 2206 .enabled_ports = 0x1f, 2207 .arl_entries = 2, 2208 .cpu_port = B53_CPU_PORT_25, 2209 .duplex_reg = B53_DUPLEX_STAT_FE, 2210 }, 2211 { 2212 .chip_id = BCM5365_DEVICE_ID, 2213 .dev_name = "BCM5365", 2214 .vlans = 256, 2215 .enabled_ports = 0x1f, 2216 .arl_entries = 2, 2217 .cpu_port = B53_CPU_PORT_25, 2218 .duplex_reg = B53_DUPLEX_STAT_FE, 2219 }, 2220 { 2221 .chip_id = BCM5389_DEVICE_ID, 2222 .dev_name = "BCM5389", 2223 .vlans = 4096, 2224 .enabled_ports = 0x1f, 2225 .arl_entries = 4, 2226 .cpu_port = B53_CPU_PORT, 2227 .vta_regs = B53_VTA_REGS, 2228 .duplex_reg = B53_DUPLEX_STAT_GE, 2229 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2230 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2231 }, 2232 { 2233 .chip_id = BCM5395_DEVICE_ID, 2234 .dev_name = "BCM5395", 2235 .vlans = 4096, 2236 .enabled_ports = 0x1f, 2237 .arl_entries = 4, 2238 .cpu_port = B53_CPU_PORT, 2239 .vta_regs = B53_VTA_REGS, 2240 .duplex_reg = B53_DUPLEX_STAT_GE, 2241 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2242 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2243 }, 2244 { 2245 .chip_id = BCM5397_DEVICE_ID, 2246 .dev_name = "BCM5397", 2247 .vlans = 4096, 2248 .enabled_ports = 0x1f, 2249 .arl_entries = 4, 2250 .cpu_port = B53_CPU_PORT, 2251 .vta_regs = B53_VTA_REGS_9798, 2252 .duplex_reg = B53_DUPLEX_STAT_GE, 2253 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2254 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2255 }, 2256 { 2257 .chip_id = BCM5398_DEVICE_ID, 2258 .dev_name = "BCM5398", 2259 .vlans = 4096, 2260 .enabled_ports = 0x7f, 2261 .arl_entries = 4, 2262 .cpu_port = B53_CPU_PORT, 2263 .vta_regs = B53_VTA_REGS_9798, 2264 .duplex_reg = B53_DUPLEX_STAT_GE, 2265 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2266 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2267 }, 2268 { 2269 .chip_id = BCM53115_DEVICE_ID, 2270 .dev_name = "BCM53115", 2271 .vlans = 4096, 2272 .enabled_ports = 0x1f, 2273 .arl_entries = 4, 2274 .vta_regs = B53_VTA_REGS, 2275 .cpu_port = B53_CPU_PORT, 2276 .duplex_reg = B53_DUPLEX_STAT_GE, 2277 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2278 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2279 }, 2280 { 2281 .chip_id = BCM53125_DEVICE_ID, 2282 .dev_name = "BCM53125", 2283 .vlans = 4096, 2284 .enabled_ports = 0xff, 2285 .arl_entries = 4, 2286 .cpu_port = B53_CPU_PORT, 2287 .vta_regs = B53_VTA_REGS, 2288 .duplex_reg = B53_DUPLEX_STAT_GE, 2289 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2290 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2291 }, 2292 { 2293 .chip_id = BCM53128_DEVICE_ID, 2294 .dev_name = "BCM53128", 2295 .vlans = 4096, 2296 .enabled_ports = 0x1ff, 2297 .arl_entries = 4, 2298 .cpu_port = B53_CPU_PORT, 2299 .vta_regs = B53_VTA_REGS, 2300 .duplex_reg = B53_DUPLEX_STAT_GE, 2301 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2302 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2303 }, 2304 { 2305 .chip_id = BCM63XX_DEVICE_ID, 2306 .dev_name = "BCM63xx", 2307 .vlans = 4096, 2308 .enabled_ports = 0, /* pdata must provide them */ 2309 .arl_entries = 4, 2310 .cpu_port = B53_CPU_PORT, 2311 .vta_regs = B53_VTA_REGS_63XX, 2312 .duplex_reg = B53_DUPLEX_STAT_63XX, 2313 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2314 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2315 }, 2316 { 2317 .chip_id = BCM53010_DEVICE_ID, 2318 .dev_name = "BCM53010", 2319 .vlans = 4096, 2320 .enabled_ports = 0x1f, 2321 .arl_entries = 4, 2322 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2323 .vta_regs = B53_VTA_REGS, 2324 .duplex_reg = B53_DUPLEX_STAT_GE, 2325 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2326 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2327 }, 2328 { 2329 .chip_id = BCM53011_DEVICE_ID, 2330 .dev_name = "BCM53011", 2331 .vlans = 4096, 2332 .enabled_ports = 0x1bf, 2333 .arl_entries = 4, 2334 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2335 .vta_regs = B53_VTA_REGS, 2336 .duplex_reg = B53_DUPLEX_STAT_GE, 2337 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2338 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2339 }, 2340 { 2341 .chip_id = BCM53012_DEVICE_ID, 2342 .dev_name = "BCM53012", 2343 .vlans = 4096, 2344 .enabled_ports = 0x1bf, 2345 .arl_entries = 4, 2346 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2347 .vta_regs = B53_VTA_REGS, 2348 .duplex_reg = B53_DUPLEX_STAT_GE, 2349 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2350 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2351 }, 2352 { 2353 .chip_id = BCM53018_DEVICE_ID, 2354 .dev_name = "BCM53018", 2355 .vlans = 4096, 2356 .enabled_ports = 0x1f, 2357 .arl_entries = 4, 2358 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2359 .vta_regs = B53_VTA_REGS, 2360 .duplex_reg = B53_DUPLEX_STAT_GE, 2361 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2362 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2363 }, 2364 { 2365 .chip_id = BCM53019_DEVICE_ID, 2366 .dev_name = "BCM53019", 2367 .vlans = 4096, 2368 .enabled_ports = 0x1f, 2369 .arl_entries = 4, 2370 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2371 .vta_regs = B53_VTA_REGS, 2372 .duplex_reg = B53_DUPLEX_STAT_GE, 2373 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2374 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2375 }, 2376 { 2377 .chip_id = BCM58XX_DEVICE_ID, 2378 .dev_name = "BCM585xx/586xx/88312", 2379 .vlans = 4096, 2380 .enabled_ports = 0x1ff, 2381 .arl_entries = 4, 2382 .cpu_port = B53_CPU_PORT, 2383 .vta_regs = B53_VTA_REGS, 2384 .duplex_reg = B53_DUPLEX_STAT_GE, 2385 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2386 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2387 }, 2388 { 2389 .chip_id = BCM583XX_DEVICE_ID, 2390 .dev_name = "BCM583xx/11360", 2391 .vlans = 4096, 2392 .enabled_ports = 0x103, 2393 .arl_entries = 4, 2394 .cpu_port = B53_CPU_PORT, 2395 .vta_regs = B53_VTA_REGS, 2396 .duplex_reg = B53_DUPLEX_STAT_GE, 2397 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2398 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2399 }, 2400 { 2401 .chip_id = BCM7445_DEVICE_ID, 2402 .dev_name = "BCM7445", 2403 .vlans = 4096, 2404 .enabled_ports = 0x1ff, 2405 .arl_entries = 4, 2406 .cpu_port = B53_CPU_PORT, 2407 .vta_regs = B53_VTA_REGS, 2408 .duplex_reg = B53_DUPLEX_STAT_GE, 2409 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2410 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2411 }, 2412 { 2413 .chip_id = BCM7278_DEVICE_ID, 2414 .dev_name = "BCM7278", 2415 .vlans = 4096, 2416 .enabled_ports = 0x1ff, 2417 .arl_entries= 4, 2418 .cpu_port = B53_CPU_PORT, 2419 .vta_regs = B53_VTA_REGS, 2420 .duplex_reg = B53_DUPLEX_STAT_GE, 2421 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2422 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2423 }, 2424 }; 2425 2426 static int b53_switch_init(struct b53_device *dev) 2427 { 2428 unsigned int i; 2429 int ret; 2430 2431 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2432 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2433 2434 if (chip->chip_id == dev->chip_id) { 2435 if (!dev->enabled_ports) 2436 dev->enabled_ports = chip->enabled_ports; 2437 dev->name = chip->dev_name; 2438 dev->duplex_reg = chip->duplex_reg; 2439 dev->vta_regs[0] = chip->vta_regs[0]; 2440 dev->vta_regs[1] = chip->vta_regs[1]; 2441 dev->vta_regs[2] = chip->vta_regs[2]; 2442 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2443 dev->cpu_port = chip->cpu_port; 2444 dev->num_vlans = chip->vlans; 2445 dev->num_arl_entries = chip->arl_entries; 2446 break; 2447 } 2448 } 2449 2450 /* check which BCM5325x version we have */ 2451 if (is5325(dev)) { 2452 u8 vc4; 2453 2454 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2455 2456 /* check reserved bits */ 2457 switch (vc4 & 3) { 2458 case 1: 2459 /* BCM5325E */ 2460 break; 2461 case 3: 2462 /* BCM5325F - do not use port 4 */ 2463 dev->enabled_ports &= ~BIT(4); 2464 break; 2465 default: 2466 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2467 #ifndef CONFIG_BCM47XX 2468 /* BCM5325M */ 2469 return -EINVAL; 2470 #else 2471 break; 2472 #endif 2473 } 2474 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2475 u64 strap_value; 2476 2477 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2478 /* use second IMP port if GMII is enabled */ 2479 if (strap_value & SV_GMII_CTRL_115) 2480 dev->cpu_port = 5; 2481 } 2482 2483 /* cpu port is always last */ 2484 dev->num_ports = dev->cpu_port + 1; 2485 dev->enabled_ports |= BIT(dev->cpu_port); 2486 2487 /* Include non standard CPU port built-in PHYs to be probed */ 2488 if (is539x(dev) || is531x5(dev)) { 2489 for (i = 0; i < dev->num_ports; i++) { 2490 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2491 !b53_possible_cpu_port(dev->ds, i)) 2492 dev->ds->phys_mii_mask |= BIT(i); 2493 } 2494 } 2495 2496 dev->ports = devm_kcalloc(dev->dev, 2497 dev->num_ports, sizeof(struct b53_port), 2498 GFP_KERNEL); 2499 if (!dev->ports) 2500 return -ENOMEM; 2501 2502 dev->vlans = devm_kcalloc(dev->dev, 2503 dev->num_vlans, sizeof(struct b53_vlan), 2504 GFP_KERNEL); 2505 if (!dev->vlans) 2506 return -ENOMEM; 2507 2508 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2509 if (dev->reset_gpio >= 0) { 2510 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2511 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2512 if (ret) 2513 return ret; 2514 } 2515 2516 return 0; 2517 } 2518 2519 struct b53_device *b53_switch_alloc(struct device *base, 2520 const struct b53_io_ops *ops, 2521 void *priv) 2522 { 2523 struct dsa_switch *ds; 2524 struct b53_device *dev; 2525 2526 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2527 if (!ds) 2528 return NULL; 2529 2530 ds->dev = base; 2531 ds->num_ports = DSA_MAX_PORTS; 2532 2533 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2534 if (!dev) 2535 return NULL; 2536 2537 ds->priv = dev; 2538 dev->dev = base; 2539 2540 dev->ds = ds; 2541 dev->priv = priv; 2542 dev->ops = ops; 2543 ds->ops = &b53_switch_ops; 2544 mutex_init(&dev->reg_mutex); 2545 mutex_init(&dev->stats_mutex); 2546 2547 return dev; 2548 } 2549 EXPORT_SYMBOL(b53_switch_alloc); 2550 2551 int b53_switch_detect(struct b53_device *dev) 2552 { 2553 u32 id32; 2554 u16 tmp; 2555 u8 id8; 2556 int ret; 2557 2558 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2559 if (ret) 2560 return ret; 2561 2562 switch (id8) { 2563 case 0: 2564 /* BCM5325 and BCM5365 do not have this register so reads 2565 * return 0. But the read operation did succeed, so assume this 2566 * is one of them. 2567 * 2568 * Next check if we can write to the 5325's VTA register; for 2569 * 5365 it is read only. 2570 */ 2571 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2572 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2573 2574 if (tmp == 0xf) 2575 dev->chip_id = BCM5325_DEVICE_ID; 2576 else 2577 dev->chip_id = BCM5365_DEVICE_ID; 2578 break; 2579 case BCM5389_DEVICE_ID: 2580 case BCM5395_DEVICE_ID: 2581 case BCM5397_DEVICE_ID: 2582 case BCM5398_DEVICE_ID: 2583 dev->chip_id = id8; 2584 break; 2585 default: 2586 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2587 if (ret) 2588 return ret; 2589 2590 switch (id32) { 2591 case BCM53115_DEVICE_ID: 2592 case BCM53125_DEVICE_ID: 2593 case BCM53128_DEVICE_ID: 2594 case BCM53010_DEVICE_ID: 2595 case BCM53011_DEVICE_ID: 2596 case BCM53012_DEVICE_ID: 2597 case BCM53018_DEVICE_ID: 2598 case BCM53019_DEVICE_ID: 2599 dev->chip_id = id32; 2600 break; 2601 default: 2602 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 2603 id8, id32); 2604 return -ENODEV; 2605 } 2606 } 2607 2608 if (dev->chip_id == BCM5325_DEVICE_ID) 2609 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2610 &dev->core_rev); 2611 else 2612 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2613 &dev->core_rev); 2614 } 2615 EXPORT_SYMBOL(b53_switch_detect); 2616 2617 int b53_switch_register(struct b53_device *dev) 2618 { 2619 int ret; 2620 2621 if (dev->pdata) { 2622 dev->chip_id = dev->pdata->chip_id; 2623 dev->enabled_ports = dev->pdata->enabled_ports; 2624 } 2625 2626 if (!dev->chip_id && b53_switch_detect(dev)) 2627 return -EINVAL; 2628 2629 ret = b53_switch_init(dev); 2630 if (ret) 2631 return ret; 2632 2633 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 2634 2635 return dsa_register_switch(dev->ds); 2636 } 2637 EXPORT_SYMBOL(b53_switch_register); 2638 2639 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2640 MODULE_DESCRIPTION("B53 switch library"); 2641 MODULE_LICENSE("Dual BSD/GPL"); 2642