1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/export.h> 22 #include <linux/gpio.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/b53.h> 26 #include <linux/phy.h> 27 #include <linux/phylink.h> 28 #include <linux/etherdevice.h> 29 #include <linux/if_bridge.h> 30 #include <net/dsa.h> 31 32 #include "b53_regs.h" 33 #include "b53_priv.h" 34 35 struct b53_mib_desc { 36 u8 size; 37 u8 offset; 38 const char *name; 39 }; 40 41 /* BCM5365 MIB counters */ 42 static const struct b53_mib_desc b53_mibs_65[] = { 43 { 8, 0x00, "TxOctets" }, 44 { 4, 0x08, "TxDropPkts" }, 45 { 4, 0x10, "TxBroadcastPkts" }, 46 { 4, 0x14, "TxMulticastPkts" }, 47 { 4, 0x18, "TxUnicastPkts" }, 48 { 4, 0x1c, "TxCollisions" }, 49 { 4, 0x20, "TxSingleCollision" }, 50 { 4, 0x24, "TxMultipleCollision" }, 51 { 4, 0x28, "TxDeferredTransmit" }, 52 { 4, 0x2c, "TxLateCollision" }, 53 { 4, 0x30, "TxExcessiveCollision" }, 54 { 4, 0x38, "TxPausePkts" }, 55 { 8, 0x44, "RxOctets" }, 56 { 4, 0x4c, "RxUndersizePkts" }, 57 { 4, 0x50, "RxPausePkts" }, 58 { 4, 0x54, "Pkts64Octets" }, 59 { 4, 0x58, "Pkts65to127Octets" }, 60 { 4, 0x5c, "Pkts128to255Octets" }, 61 { 4, 0x60, "Pkts256to511Octets" }, 62 { 4, 0x64, "Pkts512to1023Octets" }, 63 { 4, 0x68, "Pkts1024to1522Octets" }, 64 { 4, 0x6c, "RxOversizePkts" }, 65 { 4, 0x70, "RxJabbers" }, 66 { 4, 0x74, "RxAlignmentErrors" }, 67 { 4, 0x78, "RxFCSErrors" }, 68 { 8, 0x7c, "RxGoodOctets" }, 69 { 4, 0x84, "RxDropPkts" }, 70 { 4, 0x88, "RxUnicastPkts" }, 71 { 4, 0x8c, "RxMulticastPkts" }, 72 { 4, 0x90, "RxBroadcastPkts" }, 73 { 4, 0x94, "RxSAChanges" }, 74 { 4, 0x98, "RxFragments" }, 75 }; 76 77 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 78 79 /* BCM63xx MIB counters */ 80 static const struct b53_mib_desc b53_mibs_63xx[] = { 81 { 8, 0x00, "TxOctets" }, 82 { 4, 0x08, "TxDropPkts" }, 83 { 4, 0x0c, "TxQoSPkts" }, 84 { 4, 0x10, "TxBroadcastPkts" }, 85 { 4, 0x14, "TxMulticastPkts" }, 86 { 4, 0x18, "TxUnicastPkts" }, 87 { 4, 0x1c, "TxCollisions" }, 88 { 4, 0x20, "TxSingleCollision" }, 89 { 4, 0x24, "TxMultipleCollision" }, 90 { 4, 0x28, "TxDeferredTransmit" }, 91 { 4, 0x2c, "TxLateCollision" }, 92 { 4, 0x30, "TxExcessiveCollision" }, 93 { 4, 0x38, "TxPausePkts" }, 94 { 8, 0x3c, "TxQoSOctets" }, 95 { 8, 0x44, "RxOctets" }, 96 { 4, 0x4c, "RxUndersizePkts" }, 97 { 4, 0x50, "RxPausePkts" }, 98 { 4, 0x54, "Pkts64Octets" }, 99 { 4, 0x58, "Pkts65to127Octets" }, 100 { 4, 0x5c, "Pkts128to255Octets" }, 101 { 4, 0x60, "Pkts256to511Octets" }, 102 { 4, 0x64, "Pkts512to1023Octets" }, 103 { 4, 0x68, "Pkts1024to1522Octets" }, 104 { 4, 0x6c, "RxOversizePkts" }, 105 { 4, 0x70, "RxJabbers" }, 106 { 4, 0x74, "RxAlignmentErrors" }, 107 { 4, 0x78, "RxFCSErrors" }, 108 { 8, 0x7c, "RxGoodOctets" }, 109 { 4, 0x84, "RxDropPkts" }, 110 { 4, 0x88, "RxUnicastPkts" }, 111 { 4, 0x8c, "RxMulticastPkts" }, 112 { 4, 0x90, "RxBroadcastPkts" }, 113 { 4, 0x94, "RxSAChanges" }, 114 { 4, 0x98, "RxFragments" }, 115 { 4, 0xa0, "RxSymbolErrors" }, 116 { 4, 0xa4, "RxQoSPkts" }, 117 { 8, 0xa8, "RxQoSOctets" }, 118 { 4, 0xb0, "Pkts1523to2047Octets" }, 119 { 4, 0xb4, "Pkts2048to4095Octets" }, 120 { 4, 0xb8, "Pkts4096to8191Octets" }, 121 { 4, 0xbc, "Pkts8192to9728Octets" }, 122 { 4, 0xc0, "RxDiscarded" }, 123 }; 124 125 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 126 127 /* MIB counters */ 128 static const struct b53_mib_desc b53_mibs[] = { 129 { 8, 0x00, "TxOctets" }, 130 { 4, 0x08, "TxDropPkts" }, 131 { 4, 0x10, "TxBroadcastPkts" }, 132 { 4, 0x14, "TxMulticastPkts" }, 133 { 4, 0x18, "TxUnicastPkts" }, 134 { 4, 0x1c, "TxCollisions" }, 135 { 4, 0x20, "TxSingleCollision" }, 136 { 4, 0x24, "TxMultipleCollision" }, 137 { 4, 0x28, "TxDeferredTransmit" }, 138 { 4, 0x2c, "TxLateCollision" }, 139 { 4, 0x30, "TxExcessiveCollision" }, 140 { 4, 0x38, "TxPausePkts" }, 141 { 8, 0x50, "RxOctets" }, 142 { 4, 0x58, "RxUndersizePkts" }, 143 { 4, 0x5c, "RxPausePkts" }, 144 { 4, 0x60, "Pkts64Octets" }, 145 { 4, 0x64, "Pkts65to127Octets" }, 146 { 4, 0x68, "Pkts128to255Octets" }, 147 { 4, 0x6c, "Pkts256to511Octets" }, 148 { 4, 0x70, "Pkts512to1023Octets" }, 149 { 4, 0x74, "Pkts1024to1522Octets" }, 150 { 4, 0x78, "RxOversizePkts" }, 151 { 4, 0x7c, "RxJabbers" }, 152 { 4, 0x80, "RxAlignmentErrors" }, 153 { 4, 0x84, "RxFCSErrors" }, 154 { 8, 0x88, "RxGoodOctets" }, 155 { 4, 0x90, "RxDropPkts" }, 156 { 4, 0x94, "RxUnicastPkts" }, 157 { 4, 0x98, "RxMulticastPkts" }, 158 { 4, 0x9c, "RxBroadcastPkts" }, 159 { 4, 0xa0, "RxSAChanges" }, 160 { 4, 0xa4, "RxFragments" }, 161 { 4, 0xa8, "RxJumboPkts" }, 162 { 4, 0xac, "RxSymbolErrors" }, 163 { 4, 0xc0, "RxDiscarded" }, 164 }; 165 166 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 167 168 static const struct b53_mib_desc b53_mibs_58xx[] = { 169 { 8, 0x00, "TxOctets" }, 170 { 4, 0x08, "TxDropPkts" }, 171 { 4, 0x0c, "TxQPKTQ0" }, 172 { 4, 0x10, "TxBroadcastPkts" }, 173 { 4, 0x14, "TxMulticastPkts" }, 174 { 4, 0x18, "TxUnicastPKts" }, 175 { 4, 0x1c, "TxCollisions" }, 176 { 4, 0x20, "TxSingleCollision" }, 177 { 4, 0x24, "TxMultipleCollision" }, 178 { 4, 0x28, "TxDeferredCollision" }, 179 { 4, 0x2c, "TxLateCollision" }, 180 { 4, 0x30, "TxExcessiveCollision" }, 181 { 4, 0x34, "TxFrameInDisc" }, 182 { 4, 0x38, "TxPausePkts" }, 183 { 4, 0x3c, "TxQPKTQ1" }, 184 { 4, 0x40, "TxQPKTQ2" }, 185 { 4, 0x44, "TxQPKTQ3" }, 186 { 4, 0x48, "TxQPKTQ4" }, 187 { 4, 0x4c, "TxQPKTQ5" }, 188 { 8, 0x50, "RxOctets" }, 189 { 4, 0x58, "RxUndersizePkts" }, 190 { 4, 0x5c, "RxPausePkts" }, 191 { 4, 0x60, "RxPkts64Octets" }, 192 { 4, 0x64, "RxPkts65to127Octets" }, 193 { 4, 0x68, "RxPkts128to255Octets" }, 194 { 4, 0x6c, "RxPkts256to511Octets" }, 195 { 4, 0x70, "RxPkts512to1023Octets" }, 196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 197 { 4, 0x78, "RxOversizePkts" }, 198 { 4, 0x7c, "RxJabbers" }, 199 { 4, 0x80, "RxAlignmentErrors" }, 200 { 4, 0x84, "RxFCSErrors" }, 201 { 8, 0x88, "RxGoodOctets" }, 202 { 4, 0x90, "RxDropPkts" }, 203 { 4, 0x94, "RxUnicastPkts" }, 204 { 4, 0x98, "RxMulticastPkts" }, 205 { 4, 0x9c, "RxBroadcastPkts" }, 206 { 4, 0xa0, "RxSAChanges" }, 207 { 4, 0xa4, "RxFragments" }, 208 { 4, 0xa8, "RxJumboPkt" }, 209 { 4, 0xac, "RxSymblErr" }, 210 { 4, 0xb0, "InRangeErrCount" }, 211 { 4, 0xb4, "OutRangeErrCount" }, 212 { 4, 0xb8, "EEELpiEvent" }, 213 { 4, 0xbc, "EEELpiDuration" }, 214 { 4, 0xc0, "RxDiscard" }, 215 { 4, 0xc8, "TxQPKTQ6" }, 216 { 4, 0xcc, "TxQPKTQ7" }, 217 { 4, 0xd0, "TxPkts64Octets" }, 218 { 4, 0xd4, "TxPkts65to127Octets" }, 219 { 4, 0xd8, "TxPkts128to255Octets" }, 220 { 4, 0xdc, "TxPkts256to511Ocets" }, 221 { 4, 0xe0, "TxPkts512to1023Ocets" }, 222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 223 }; 224 225 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 226 227 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 228 { 229 unsigned int i; 230 231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 232 233 for (i = 0; i < 10; i++) { 234 u8 vta; 235 236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 237 if (!(vta & VTA_START_CMD)) 238 return 0; 239 240 usleep_range(100, 200); 241 } 242 243 return -EIO; 244 } 245 246 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 247 struct b53_vlan *vlan) 248 { 249 if (is5325(dev)) { 250 u32 entry = 0; 251 252 if (vlan->members) { 253 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 254 VA_UNTAG_S_25) | vlan->members; 255 if (dev->core_rev >= 3) 256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 257 else 258 entry |= VA_VALID_25; 259 } 260 261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 263 VTA_RW_STATE_WR | VTA_RW_OP_EN); 264 } else if (is5365(dev)) { 265 u16 entry = 0; 266 267 if (vlan->members) 268 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 270 271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 273 VTA_RW_STATE_WR | VTA_RW_OP_EN); 274 } else { 275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 277 (vlan->untag << VTE_UNTAG_S) | vlan->members); 278 279 b53_do_vlan_op(dev, VTA_CMD_WRITE); 280 } 281 282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 283 vid, vlan->members, vlan->untag); 284 } 285 286 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 287 struct b53_vlan *vlan) 288 { 289 if (is5325(dev)) { 290 u32 entry = 0; 291 292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 293 VTA_RW_STATE_RD | VTA_RW_OP_EN); 294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 295 296 if (dev->core_rev >= 3) 297 vlan->valid = !!(entry & VA_VALID_25_R4); 298 else 299 vlan->valid = !!(entry & VA_VALID_25); 300 vlan->members = entry & VA_MEMBER_MASK; 301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 302 303 } else if (is5365(dev)) { 304 u16 entry = 0; 305 306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 307 VTA_RW_STATE_WR | VTA_RW_OP_EN); 308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 309 310 vlan->valid = !!(entry & VA_VALID_65); 311 vlan->members = entry & VA_MEMBER_MASK; 312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 313 } else { 314 u32 entry = 0; 315 316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 317 b53_do_vlan_op(dev, VTA_CMD_READ); 318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 319 vlan->members = entry & VTE_MEMBERS; 320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 321 vlan->valid = true; 322 } 323 } 324 325 static void b53_set_forwarding(struct b53_device *dev, int enable) 326 { 327 u8 mgmt; 328 329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 330 331 if (enable) 332 mgmt |= SM_SW_FWD_EN; 333 else 334 mgmt &= ~SM_SW_FWD_EN; 335 336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 337 338 /* Include IMP port in dumb forwarding mode 339 */ 340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 341 mgmt |= B53_MII_DUMB_FWDG_EN; 342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 343 344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether 345 * frames should be flooded or not. 346 */ 347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); 348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; 349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); 350 } 351 352 static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, 353 bool enable_filtering) 354 { 355 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 356 357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 360 361 if (is5325(dev) || is5365(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 364 } else if (is63xx(dev)) { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 367 } else { 368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 370 } 371 372 if (enable) { 373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 375 vc4 &= ~VC4_ING_VID_CHECK_MASK; 376 if (enable_filtering) { 377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 378 vc5 |= VC5_DROP_VTABLE_MISS; 379 } else { 380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 381 vc5 &= ~VC5_DROP_VTABLE_MISS; 382 } 383 384 if (is5325(dev)) 385 vc0 &= ~VC0_RESERVED_1; 386 387 if (is5325(dev) || is5365(dev)) 388 vc1 |= VC1_RX_MCST_TAG_EN; 389 390 } else { 391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 393 vc4 &= ~VC4_ING_VID_CHECK_MASK; 394 vc5 &= ~VC5_DROP_VTABLE_MISS; 395 396 if (is5325(dev) || is5365(dev)) 397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 398 else 399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 400 401 if (is5325(dev) || is5365(dev)) 402 vc1 &= ~VC1_RX_MCST_TAG_EN; 403 } 404 405 if (!is5325(dev) && !is5365(dev)) 406 vc5 &= ~VC5_VID_FFF_EN; 407 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 410 411 if (is5325(dev) || is5365(dev)) { 412 /* enable the high 8 bit vid check on 5325 */ 413 if (is5325(dev) && enable) 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 415 VC3_HIGH_8BIT_EN); 416 else 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 418 419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 421 } else if (is63xx(dev)) { 422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 425 } else { 426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 429 } 430 431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 432 433 dev->vlan_enabled = enable; 434 435 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", 436 port, enable, enable_filtering); 437 } 438 439 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 440 { 441 u32 port_mask = 0; 442 u16 max_size = JMS_MIN_SIZE; 443 444 if (is5325(dev) || is5365(dev)) 445 return -EINVAL; 446 447 if (enable) { 448 port_mask = dev->enabled_ports; 449 max_size = JMS_MAX_SIZE; 450 if (allow_10_100) 451 port_mask |= JPM_10_100_JUMBO_EN; 452 } 453 454 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 455 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 456 } 457 458 static int b53_flush_arl(struct b53_device *dev, u8 mask) 459 { 460 unsigned int i; 461 462 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 463 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 464 465 for (i = 0; i < 10; i++) { 466 u8 fast_age_ctrl; 467 468 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 469 &fast_age_ctrl); 470 471 if (!(fast_age_ctrl & FAST_AGE_DONE)) 472 goto out; 473 474 msleep(1); 475 } 476 477 return -ETIMEDOUT; 478 out: 479 /* Only age dynamic entries (default behavior) */ 480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 481 return 0; 482 } 483 484 static int b53_fast_age_port(struct b53_device *dev, int port) 485 { 486 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 487 488 return b53_flush_arl(dev, FAST_AGE_PORT); 489 } 490 491 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 492 { 493 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 494 495 return b53_flush_arl(dev, FAST_AGE_VLAN); 496 } 497 498 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 499 { 500 struct b53_device *dev = ds->priv; 501 unsigned int i; 502 u16 pvlan; 503 504 /* Enable the IMP port to be in the same VLAN as the other ports 505 * on a per-port basis such that we only have Port i and IMP in 506 * the same VLAN. 507 */ 508 b53_for_each_port(dev, i) { 509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 510 pvlan |= BIT(cpu_port); 511 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 512 } 513 } 514 EXPORT_SYMBOL(b53_imp_vlan_setup); 515 516 static void b53_port_set_ucast_flood(struct b53_device *dev, int port, 517 bool unicast) 518 { 519 u16 uc; 520 521 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc); 522 if (unicast) 523 uc |= BIT(port); 524 else 525 uc &= ~BIT(port); 526 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc); 527 } 528 529 static void b53_port_set_mcast_flood(struct b53_device *dev, int port, 530 bool multicast) 531 { 532 u16 mc; 533 534 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc); 535 if (multicast) 536 mc |= BIT(port); 537 else 538 mc &= ~BIT(port); 539 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc); 540 541 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc); 542 if (multicast) 543 mc |= BIT(port); 544 else 545 mc &= ~BIT(port); 546 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc); 547 } 548 549 static void b53_port_set_learning(struct b53_device *dev, int port, 550 bool learning) 551 { 552 u16 reg; 553 554 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®); 555 if (learning) 556 reg &= ~BIT(port); 557 else 558 reg |= BIT(port); 559 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg); 560 } 561 562 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 563 { 564 struct b53_device *dev = ds->priv; 565 unsigned int cpu_port; 566 int ret = 0; 567 u16 pvlan; 568 569 if (!dsa_is_user_port(ds, port)) 570 return 0; 571 572 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 573 574 b53_port_set_ucast_flood(dev, port, true); 575 b53_port_set_mcast_flood(dev, port, true); 576 b53_port_set_learning(dev, port, false); 577 578 if (dev->ops->irq_enable) 579 ret = dev->ops->irq_enable(dev, port); 580 if (ret) 581 return ret; 582 583 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 584 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 585 586 /* Set this port, and only this one to be in the default VLAN, 587 * if member of a bridge, restore its membership prior to 588 * bringing down this port. 589 */ 590 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 591 pvlan &= ~0x1ff; 592 pvlan |= BIT(port); 593 pvlan |= dev->ports[port].vlan_ctl_mask; 594 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 595 596 b53_imp_vlan_setup(ds, cpu_port); 597 598 /* If EEE was enabled, restore it */ 599 if (dev->ports[port].eee.eee_enabled) 600 b53_eee_enable_set(ds, port, true); 601 602 return 0; 603 } 604 EXPORT_SYMBOL(b53_enable_port); 605 606 void b53_disable_port(struct dsa_switch *ds, int port) 607 { 608 struct b53_device *dev = ds->priv; 609 u8 reg; 610 611 /* Disable Tx/Rx for the port */ 612 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 613 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 614 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 615 616 if (dev->ops->irq_disable) 617 dev->ops->irq_disable(dev, port); 618 } 619 EXPORT_SYMBOL(b53_disable_port); 620 621 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 622 { 623 struct b53_device *dev = ds->priv; 624 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE); 625 u8 hdr_ctl, val; 626 u16 reg; 627 628 /* Resolve which bit controls the Broadcom tag */ 629 switch (port) { 630 case 8: 631 val = BRCM_HDR_P8_EN; 632 break; 633 case 7: 634 val = BRCM_HDR_P7_EN; 635 break; 636 case 5: 637 val = BRCM_HDR_P5_EN; 638 break; 639 default: 640 val = 0; 641 break; 642 } 643 644 /* Enable management mode if tagging is requested */ 645 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl); 646 if (tag_en) 647 hdr_ctl |= SM_SW_FWD_MODE; 648 else 649 hdr_ctl &= ~SM_SW_FWD_MODE; 650 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl); 651 652 /* Configure the appropriate IMP port */ 653 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl); 654 if (port == 8) 655 hdr_ctl |= GC_FRM_MGMT_PORT_MII; 656 else if (port == 5) 657 hdr_ctl |= GC_FRM_MGMT_PORT_M; 658 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl); 659 660 /* Enable Broadcom tags for IMP port */ 661 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 662 if (tag_en) 663 hdr_ctl |= val; 664 else 665 hdr_ctl &= ~val; 666 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 667 668 /* Registers below are only accessible on newer devices */ 669 if (!is58xx(dev)) 670 return; 671 672 /* Enable reception Broadcom tag for CPU TX (switch RX) to 673 * allow us to tag outgoing frames 674 */ 675 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 676 if (tag_en) 677 reg &= ~BIT(port); 678 else 679 reg |= BIT(port); 680 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 681 682 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 683 * allow delivering frames to the per-port net_devices 684 */ 685 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 686 if (tag_en) 687 reg &= ~BIT(port); 688 else 689 reg |= BIT(port); 690 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 691 } 692 EXPORT_SYMBOL(b53_brcm_hdr_setup); 693 694 static void b53_enable_cpu_port(struct b53_device *dev, int port) 695 { 696 u8 port_ctrl; 697 698 /* BCM5325 CPU port is at 8 */ 699 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 700 port = B53_CPU_PORT; 701 702 port_ctrl = PORT_CTRL_RX_BCST_EN | 703 PORT_CTRL_RX_MCST_EN | 704 PORT_CTRL_RX_UCST_EN; 705 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 706 707 b53_brcm_hdr_setup(dev->ds, port); 708 709 b53_port_set_ucast_flood(dev, port, true); 710 b53_port_set_mcast_flood(dev, port, true); 711 b53_port_set_learning(dev, port, false); 712 } 713 714 static void b53_enable_mib(struct b53_device *dev) 715 { 716 u8 gc; 717 718 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 719 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 720 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 721 } 722 723 static u16 b53_default_pvid(struct b53_device *dev) 724 { 725 if (is5325(dev) || is5365(dev)) 726 return 1; 727 else 728 return 0; 729 } 730 731 int b53_configure_vlan(struct dsa_switch *ds) 732 { 733 struct b53_device *dev = ds->priv; 734 struct b53_vlan vl = { 0 }; 735 struct b53_vlan *v; 736 int i, def_vid; 737 u16 vid; 738 739 def_vid = b53_default_pvid(dev); 740 741 /* clear all vlan entries */ 742 if (is5325(dev) || is5365(dev)) { 743 for (i = def_vid; i < dev->num_vlans; i++) 744 b53_set_vlan_entry(dev, i, &vl); 745 } else { 746 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 747 } 748 749 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering); 750 751 b53_for_each_port(dev, i) 752 b53_write16(dev, B53_VLAN_PAGE, 753 B53_VLAN_PORT_DEF_TAG(i), def_vid); 754 755 /* Upon initial call we have not set-up any VLANs, but upon 756 * system resume, we need to restore all VLAN entries. 757 */ 758 for (vid = def_vid; vid < dev->num_vlans; vid++) { 759 v = &dev->vlans[vid]; 760 761 if (!v->members) 762 continue; 763 764 b53_set_vlan_entry(dev, vid, v); 765 b53_fast_age_vlan(dev, vid); 766 } 767 768 return 0; 769 } 770 EXPORT_SYMBOL(b53_configure_vlan); 771 772 static void b53_switch_reset_gpio(struct b53_device *dev) 773 { 774 int gpio = dev->reset_gpio; 775 776 if (gpio < 0) 777 return; 778 779 /* Reset sequence: RESET low(50ms)->high(20ms) 780 */ 781 gpio_set_value(gpio, 0); 782 mdelay(50); 783 784 gpio_set_value(gpio, 1); 785 mdelay(20); 786 787 dev->current_page = 0xff; 788 } 789 790 static int b53_switch_reset(struct b53_device *dev) 791 { 792 unsigned int timeout = 1000; 793 u8 mgmt, reg; 794 795 b53_switch_reset_gpio(dev); 796 797 if (is539x(dev)) { 798 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 799 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 800 } 801 802 /* This is specific to 58xx devices here, do not use is58xx() which 803 * covers the larger Starfigther 2 family, including 7445/7278 which 804 * still use this driver as a library and need to perform the reset 805 * earlier. 806 */ 807 if (dev->chip_id == BCM58XX_DEVICE_ID || 808 dev->chip_id == BCM583XX_DEVICE_ID) { 809 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 810 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 811 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 812 813 do { 814 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 815 if (!(reg & SW_RST)) 816 break; 817 818 usleep_range(1000, 2000); 819 } while (timeout-- > 0); 820 821 if (timeout == 0) { 822 dev_err(dev->dev, 823 "Timeout waiting for SW_RST to clear!\n"); 824 return -ETIMEDOUT; 825 } 826 } 827 828 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 829 830 if (!(mgmt & SM_SW_FWD_EN)) { 831 mgmt &= ~SM_SW_FWD_MODE; 832 mgmt |= SM_SW_FWD_EN; 833 834 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 835 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 836 837 if (!(mgmt & SM_SW_FWD_EN)) { 838 dev_err(dev->dev, "Failed to enable switch!\n"); 839 return -EINVAL; 840 } 841 } 842 843 b53_enable_mib(dev); 844 845 return b53_flush_arl(dev, FAST_AGE_STATIC); 846 } 847 848 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 849 { 850 struct b53_device *priv = ds->priv; 851 u16 value = 0; 852 int ret; 853 854 if (priv->ops->phy_read16) 855 ret = priv->ops->phy_read16(priv, addr, reg, &value); 856 else 857 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 858 reg * 2, &value); 859 860 return ret ? ret : value; 861 } 862 863 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 864 { 865 struct b53_device *priv = ds->priv; 866 867 if (priv->ops->phy_write16) 868 return priv->ops->phy_write16(priv, addr, reg, val); 869 870 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 871 } 872 873 static int b53_reset_switch(struct b53_device *priv) 874 { 875 /* reset vlans */ 876 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 877 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 878 879 priv->serdes_lane = B53_INVALID_LANE; 880 881 return b53_switch_reset(priv); 882 } 883 884 static int b53_apply_config(struct b53_device *priv) 885 { 886 /* disable switching */ 887 b53_set_forwarding(priv, 0); 888 889 b53_configure_vlan(priv->ds); 890 891 /* enable switching */ 892 b53_set_forwarding(priv, 1); 893 894 return 0; 895 } 896 897 static void b53_reset_mib(struct b53_device *priv) 898 { 899 u8 gc; 900 901 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 902 903 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 904 msleep(1); 905 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 906 msleep(1); 907 } 908 909 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 910 { 911 if (is5365(dev)) 912 return b53_mibs_65; 913 else if (is63xx(dev)) 914 return b53_mibs_63xx; 915 else if (is58xx(dev)) 916 return b53_mibs_58xx; 917 else 918 return b53_mibs; 919 } 920 921 static unsigned int b53_get_mib_size(struct b53_device *dev) 922 { 923 if (is5365(dev)) 924 return B53_MIBS_65_SIZE; 925 else if (is63xx(dev)) 926 return B53_MIBS_63XX_SIZE; 927 else if (is58xx(dev)) 928 return B53_MIBS_58XX_SIZE; 929 else 930 return B53_MIBS_SIZE; 931 } 932 933 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 934 { 935 /* These ports typically do not have built-in PHYs */ 936 switch (port) { 937 case B53_CPU_PORT_25: 938 case 7: 939 case B53_CPU_PORT: 940 return NULL; 941 } 942 943 return mdiobus_get_phy(ds->slave_mii_bus, port); 944 } 945 946 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 947 uint8_t *data) 948 { 949 struct b53_device *dev = ds->priv; 950 const struct b53_mib_desc *mibs = b53_get_mib(dev); 951 unsigned int mib_size = b53_get_mib_size(dev); 952 struct phy_device *phydev; 953 unsigned int i; 954 955 if (stringset == ETH_SS_STATS) { 956 for (i = 0; i < mib_size; i++) 957 strlcpy(data + i * ETH_GSTRING_LEN, 958 mibs[i].name, ETH_GSTRING_LEN); 959 } else if (stringset == ETH_SS_PHY_STATS) { 960 phydev = b53_get_phy_device(ds, port); 961 if (!phydev) 962 return; 963 964 phy_ethtool_get_strings(phydev, data); 965 } 966 } 967 EXPORT_SYMBOL(b53_get_strings); 968 969 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 970 { 971 struct b53_device *dev = ds->priv; 972 const struct b53_mib_desc *mibs = b53_get_mib(dev); 973 unsigned int mib_size = b53_get_mib_size(dev); 974 const struct b53_mib_desc *s; 975 unsigned int i; 976 u64 val = 0; 977 978 if (is5365(dev) && port == 5) 979 port = 8; 980 981 mutex_lock(&dev->stats_mutex); 982 983 for (i = 0; i < mib_size; i++) { 984 s = &mibs[i]; 985 986 if (s->size == 8) { 987 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 988 } else { 989 u32 val32; 990 991 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 992 &val32); 993 val = val32; 994 } 995 data[i] = (u64)val; 996 } 997 998 mutex_unlock(&dev->stats_mutex); 999 } 1000 EXPORT_SYMBOL(b53_get_ethtool_stats); 1001 1002 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 1003 { 1004 struct phy_device *phydev; 1005 1006 phydev = b53_get_phy_device(ds, port); 1007 if (!phydev) 1008 return; 1009 1010 phy_ethtool_get_stats(phydev, NULL, data); 1011 } 1012 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 1013 1014 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 1015 { 1016 struct b53_device *dev = ds->priv; 1017 struct phy_device *phydev; 1018 1019 if (sset == ETH_SS_STATS) { 1020 return b53_get_mib_size(dev); 1021 } else if (sset == ETH_SS_PHY_STATS) { 1022 phydev = b53_get_phy_device(ds, port); 1023 if (!phydev) 1024 return 0; 1025 1026 return phy_ethtool_get_sset_count(phydev); 1027 } 1028 1029 return 0; 1030 } 1031 EXPORT_SYMBOL(b53_get_sset_count); 1032 1033 enum b53_devlink_resource_id { 1034 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1035 }; 1036 1037 static u64 b53_devlink_vlan_table_get(void *priv) 1038 { 1039 struct b53_device *dev = priv; 1040 struct b53_vlan *vl; 1041 unsigned int i; 1042 u64 count = 0; 1043 1044 for (i = 0; i < dev->num_vlans; i++) { 1045 vl = &dev->vlans[i]; 1046 if (vl->members) 1047 count++; 1048 } 1049 1050 return count; 1051 } 1052 1053 int b53_setup_devlink_resources(struct dsa_switch *ds) 1054 { 1055 struct devlink_resource_size_params size_params; 1056 struct b53_device *dev = ds->priv; 1057 int err; 1058 1059 devlink_resource_size_params_init(&size_params, dev->num_vlans, 1060 dev->num_vlans, 1061 1, DEVLINK_RESOURCE_UNIT_ENTRY); 1062 1063 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans, 1064 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1065 DEVLINK_RESOURCE_ID_PARENT_TOP, 1066 &size_params); 1067 if (err) 1068 goto out; 1069 1070 dsa_devlink_resource_occ_get_register(ds, 1071 B53_DEVLINK_PARAM_ID_VLAN_TABLE, 1072 b53_devlink_vlan_table_get, dev); 1073 1074 return 0; 1075 out: 1076 dsa_devlink_resources_unregister(ds); 1077 return err; 1078 } 1079 EXPORT_SYMBOL(b53_setup_devlink_resources); 1080 1081 static int b53_setup(struct dsa_switch *ds) 1082 { 1083 struct b53_device *dev = ds->priv; 1084 unsigned int port; 1085 int ret; 1086 1087 ret = b53_reset_switch(dev); 1088 if (ret) { 1089 dev_err(ds->dev, "failed to reset switch\n"); 1090 return ret; 1091 } 1092 1093 b53_reset_mib(dev); 1094 1095 ret = b53_apply_config(dev); 1096 if (ret) { 1097 dev_err(ds->dev, "failed to apply configuration\n"); 1098 return ret; 1099 } 1100 1101 /* Configure IMP/CPU port, disable all other ports. Enabled 1102 * ports will be configured with .port_enable 1103 */ 1104 for (port = 0; port < dev->num_ports; port++) { 1105 if (dsa_is_cpu_port(ds, port)) 1106 b53_enable_cpu_port(dev, port); 1107 else 1108 b53_disable_port(ds, port); 1109 } 1110 1111 /* Let DSA handle the case were multiple bridges span the same switch 1112 * device and different VLAN awareness settings are requested, which 1113 * would be breaking filtering semantics for any of the other bridge 1114 * devices. (not hardware supported) 1115 */ 1116 ds->vlan_filtering_is_global = true; 1117 1118 return b53_setup_devlink_resources(ds); 1119 } 1120 1121 static void b53_teardown(struct dsa_switch *ds) 1122 { 1123 dsa_devlink_resources_unregister(ds); 1124 } 1125 1126 static void b53_force_link(struct b53_device *dev, int port, int link) 1127 { 1128 u8 reg, val, off; 1129 1130 /* Override the port settings */ 1131 if (port == dev->cpu_port) { 1132 off = B53_PORT_OVERRIDE_CTRL; 1133 val = PORT_OVERRIDE_EN; 1134 } else { 1135 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1136 val = GMII_PO_EN; 1137 } 1138 1139 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1140 reg |= val; 1141 if (link) 1142 reg |= PORT_OVERRIDE_LINK; 1143 else 1144 reg &= ~PORT_OVERRIDE_LINK; 1145 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1146 } 1147 1148 static void b53_force_port_config(struct b53_device *dev, int port, 1149 int speed, int duplex, 1150 bool tx_pause, bool rx_pause) 1151 { 1152 u8 reg, val, off; 1153 1154 /* Override the port settings */ 1155 if (port == dev->cpu_port) { 1156 off = B53_PORT_OVERRIDE_CTRL; 1157 val = PORT_OVERRIDE_EN; 1158 } else { 1159 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1160 val = GMII_PO_EN; 1161 } 1162 1163 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1164 reg |= val; 1165 if (duplex == DUPLEX_FULL) 1166 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1167 else 1168 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1169 1170 switch (speed) { 1171 case 2000: 1172 reg |= PORT_OVERRIDE_SPEED_2000M; 1173 fallthrough; 1174 case SPEED_1000: 1175 reg |= PORT_OVERRIDE_SPEED_1000M; 1176 break; 1177 case SPEED_100: 1178 reg |= PORT_OVERRIDE_SPEED_100M; 1179 break; 1180 case SPEED_10: 1181 reg |= PORT_OVERRIDE_SPEED_10M; 1182 break; 1183 default: 1184 dev_err(dev->dev, "unknown speed: %d\n", speed); 1185 return; 1186 } 1187 1188 if (rx_pause) 1189 reg |= PORT_OVERRIDE_RX_FLOW; 1190 if (tx_pause) 1191 reg |= PORT_OVERRIDE_TX_FLOW; 1192 1193 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1194 } 1195 1196 static void b53_adjust_link(struct dsa_switch *ds, int port, 1197 struct phy_device *phydev) 1198 { 1199 struct b53_device *dev = ds->priv; 1200 struct ethtool_eee *p = &dev->ports[port].eee; 1201 u8 rgmii_ctrl = 0, reg = 0, off; 1202 bool tx_pause = false; 1203 bool rx_pause = false; 1204 1205 if (!phy_is_pseudo_fixed_link(phydev)) 1206 return; 1207 1208 /* Enable flow control on BCM5301x's CPU port */ 1209 if (is5301x(dev) && port == dev->cpu_port) 1210 tx_pause = rx_pause = true; 1211 1212 if (phydev->pause) { 1213 if (phydev->asym_pause) 1214 tx_pause = true; 1215 rx_pause = true; 1216 } 1217 1218 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, 1219 tx_pause, rx_pause); 1220 b53_force_link(dev, port, phydev->link); 1221 1222 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1223 if (port == 8) 1224 off = B53_RGMII_CTRL_IMP; 1225 else 1226 off = B53_RGMII_CTRL_P(port); 1227 1228 /* Configure the port RGMII clock delay by DLL disabled and 1229 * tx_clk aligned timing (restoring to reset defaults) 1230 */ 1231 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1232 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1233 RGMII_CTRL_TIMING_SEL); 1234 1235 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1236 * sure that we enable the port TX clock internal delay to 1237 * account for this internal delay that is inserted, otherwise 1238 * the switch won't be able to receive correctly. 1239 * 1240 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1241 * any delay neither on transmission nor reception, so the 1242 * BCM53125 must also be configured accordingly to account for 1243 * the lack of delay and introduce 1244 * 1245 * The BCM53125 switch has its RX clock and TX clock control 1246 * swapped, hence the reason why we modify the TX clock path in 1247 * the "RGMII" case 1248 */ 1249 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1250 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1251 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1252 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1253 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1254 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1255 1256 dev_info(ds->dev, "Configured port %d for %s\n", port, 1257 phy_modes(phydev->interface)); 1258 } 1259 1260 /* configure MII port if necessary */ 1261 if (is5325(dev)) { 1262 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1263 ®); 1264 1265 /* reverse mii needs to be enabled */ 1266 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1267 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1268 reg | PORT_OVERRIDE_RV_MII_25); 1269 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1270 ®); 1271 1272 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1273 dev_err(ds->dev, 1274 "Failed to enable reverse MII mode\n"); 1275 return; 1276 } 1277 } 1278 } else if (is5301x(dev)) { 1279 if (port != dev->cpu_port) { 1280 b53_force_port_config(dev, dev->cpu_port, 2000, 1281 DUPLEX_FULL, true, true); 1282 b53_force_link(dev, dev->cpu_port, 1); 1283 } 1284 } 1285 1286 /* Re-negotiate EEE if it was enabled already */ 1287 p->eee_enabled = b53_eee_init(ds, port, phydev); 1288 } 1289 1290 void b53_port_event(struct dsa_switch *ds, int port) 1291 { 1292 struct b53_device *dev = ds->priv; 1293 bool link; 1294 u16 sts; 1295 1296 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1297 link = !!(sts & BIT(port)); 1298 dsa_port_phylink_mac_change(ds, port, link); 1299 } 1300 EXPORT_SYMBOL(b53_port_event); 1301 1302 void b53_phylink_validate(struct dsa_switch *ds, int port, 1303 unsigned long *supported, 1304 struct phylink_link_state *state) 1305 { 1306 struct b53_device *dev = ds->priv; 1307 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1308 1309 if (dev->ops->serdes_phylink_validate) 1310 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1311 1312 /* Allow all the expected bits */ 1313 phylink_set(mask, Autoneg); 1314 phylink_set_port_modes(mask); 1315 phylink_set(mask, Pause); 1316 phylink_set(mask, Asym_Pause); 1317 1318 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1319 * support Gigabit, including Half duplex. 1320 */ 1321 if (state->interface != PHY_INTERFACE_MODE_MII && 1322 state->interface != PHY_INTERFACE_MODE_REVMII && 1323 !phy_interface_mode_is_8023z(state->interface) && 1324 !(is5325(dev) || is5365(dev))) { 1325 phylink_set(mask, 1000baseT_Full); 1326 phylink_set(mask, 1000baseT_Half); 1327 } 1328 1329 if (!phy_interface_mode_is_8023z(state->interface)) { 1330 phylink_set(mask, 10baseT_Half); 1331 phylink_set(mask, 10baseT_Full); 1332 phylink_set(mask, 100baseT_Half); 1333 phylink_set(mask, 100baseT_Full); 1334 } 1335 1336 bitmap_and(supported, supported, mask, 1337 __ETHTOOL_LINK_MODE_MASK_NBITS); 1338 bitmap_and(state->advertising, state->advertising, mask, 1339 __ETHTOOL_LINK_MODE_MASK_NBITS); 1340 1341 phylink_helper_basex_speed(state); 1342 } 1343 EXPORT_SYMBOL(b53_phylink_validate); 1344 1345 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1346 struct phylink_link_state *state) 1347 { 1348 struct b53_device *dev = ds->priv; 1349 int ret = -EOPNOTSUPP; 1350 1351 if ((phy_interface_mode_is_8023z(state->interface) || 1352 state->interface == PHY_INTERFACE_MODE_SGMII) && 1353 dev->ops->serdes_link_state) 1354 ret = dev->ops->serdes_link_state(dev, port, state); 1355 1356 return ret; 1357 } 1358 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1359 1360 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1361 unsigned int mode, 1362 const struct phylink_link_state *state) 1363 { 1364 struct b53_device *dev = ds->priv; 1365 1366 if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED) 1367 return; 1368 1369 if ((phy_interface_mode_is_8023z(state->interface) || 1370 state->interface == PHY_INTERFACE_MODE_SGMII) && 1371 dev->ops->serdes_config) 1372 dev->ops->serdes_config(dev, port, mode, state); 1373 } 1374 EXPORT_SYMBOL(b53_phylink_mac_config); 1375 1376 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1377 { 1378 struct b53_device *dev = ds->priv; 1379 1380 if (dev->ops->serdes_an_restart) 1381 dev->ops->serdes_an_restart(dev, port); 1382 } 1383 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1384 1385 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1386 unsigned int mode, 1387 phy_interface_t interface) 1388 { 1389 struct b53_device *dev = ds->priv; 1390 1391 if (mode == MLO_AN_PHY) 1392 return; 1393 1394 if (mode == MLO_AN_FIXED) { 1395 b53_force_link(dev, port, false); 1396 return; 1397 } 1398 1399 if (phy_interface_mode_is_8023z(interface) && 1400 dev->ops->serdes_link_set) 1401 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1402 } 1403 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1404 1405 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1406 unsigned int mode, 1407 phy_interface_t interface, 1408 struct phy_device *phydev, 1409 int speed, int duplex, 1410 bool tx_pause, bool rx_pause) 1411 { 1412 struct b53_device *dev = ds->priv; 1413 1414 if (mode == MLO_AN_PHY) 1415 return; 1416 1417 if (mode == MLO_AN_FIXED) { 1418 b53_force_port_config(dev, port, speed, duplex, 1419 tx_pause, rx_pause); 1420 b53_force_link(dev, port, true); 1421 return; 1422 } 1423 1424 if (phy_interface_mode_is_8023z(interface) && 1425 dev->ops->serdes_link_set) 1426 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1427 } 1428 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1429 1430 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1431 struct netlink_ext_ack *extack) 1432 { 1433 struct b53_device *dev = ds->priv; 1434 1435 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering); 1436 1437 return 0; 1438 } 1439 EXPORT_SYMBOL(b53_vlan_filtering); 1440 1441 static int b53_vlan_prepare(struct dsa_switch *ds, int port, 1442 const struct switchdev_obj_port_vlan *vlan) 1443 { 1444 struct b53_device *dev = ds->priv; 1445 1446 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0) 1447 return -EOPNOTSUPP; 1448 1449 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of 1450 * receiving VLAN tagged frames at all, we can still allow the port to 1451 * be configured for egress untagged. 1452 */ 1453 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 && 1454 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)) 1455 return -EINVAL; 1456 1457 if (vlan->vid >= dev->num_vlans) 1458 return -ERANGE; 1459 1460 b53_enable_vlan(dev, port, true, ds->vlan_filtering); 1461 1462 return 0; 1463 } 1464 1465 int b53_vlan_add(struct dsa_switch *ds, int port, 1466 const struct switchdev_obj_port_vlan *vlan, 1467 struct netlink_ext_ack *extack) 1468 { 1469 struct b53_device *dev = ds->priv; 1470 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1471 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1472 struct b53_vlan *vl; 1473 int err; 1474 1475 err = b53_vlan_prepare(ds, port, vlan); 1476 if (err) 1477 return err; 1478 1479 vl = &dev->vlans[vlan->vid]; 1480 1481 b53_get_vlan_entry(dev, vlan->vid, vl); 1482 1483 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev)) 1484 untagged = true; 1485 1486 vl->members |= BIT(port); 1487 if (untagged && !dsa_is_cpu_port(ds, port)) 1488 vl->untag |= BIT(port); 1489 else 1490 vl->untag &= ~BIT(port); 1491 1492 b53_set_vlan_entry(dev, vlan->vid, vl); 1493 b53_fast_age_vlan(dev, vlan->vid); 1494 1495 if (pvid && !dsa_is_cpu_port(ds, port)) { 1496 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1497 vlan->vid); 1498 b53_fast_age_vlan(dev, vlan->vid); 1499 } 1500 1501 return 0; 1502 } 1503 EXPORT_SYMBOL(b53_vlan_add); 1504 1505 int b53_vlan_del(struct dsa_switch *ds, int port, 1506 const struct switchdev_obj_port_vlan *vlan) 1507 { 1508 struct b53_device *dev = ds->priv; 1509 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1510 struct b53_vlan *vl; 1511 u16 pvid; 1512 1513 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1514 1515 vl = &dev->vlans[vlan->vid]; 1516 1517 b53_get_vlan_entry(dev, vlan->vid, vl); 1518 1519 vl->members &= ~BIT(port); 1520 1521 if (pvid == vlan->vid) 1522 pvid = b53_default_pvid(dev); 1523 1524 if (untagged && !dsa_is_cpu_port(ds, port)) 1525 vl->untag &= ~(BIT(port)); 1526 1527 b53_set_vlan_entry(dev, vlan->vid, vl); 1528 b53_fast_age_vlan(dev, vlan->vid); 1529 1530 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1531 b53_fast_age_vlan(dev, pvid); 1532 1533 return 0; 1534 } 1535 EXPORT_SYMBOL(b53_vlan_del); 1536 1537 /* Address Resolution Logic routines */ 1538 static int b53_arl_op_wait(struct b53_device *dev) 1539 { 1540 unsigned int timeout = 10; 1541 u8 reg; 1542 1543 do { 1544 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1545 if (!(reg & ARLTBL_START_DONE)) 1546 return 0; 1547 1548 usleep_range(1000, 2000); 1549 } while (timeout--); 1550 1551 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1552 1553 return -ETIMEDOUT; 1554 } 1555 1556 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1557 { 1558 u8 reg; 1559 1560 if (op > ARLTBL_RW) 1561 return -EINVAL; 1562 1563 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1564 reg |= ARLTBL_START_DONE; 1565 if (op) 1566 reg |= ARLTBL_RW; 1567 else 1568 reg &= ~ARLTBL_RW; 1569 if (dev->vlan_enabled) 1570 reg &= ~ARLTBL_IVL_SVL_SELECT; 1571 else 1572 reg |= ARLTBL_IVL_SVL_SELECT; 1573 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1574 1575 return b53_arl_op_wait(dev); 1576 } 1577 1578 static int b53_arl_read(struct b53_device *dev, u64 mac, 1579 u16 vid, struct b53_arl_entry *ent, u8 *idx) 1580 { 1581 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES); 1582 unsigned int i; 1583 int ret; 1584 1585 ret = b53_arl_op_wait(dev); 1586 if (ret) 1587 return ret; 1588 1589 bitmap_zero(free_bins, dev->num_arl_bins); 1590 1591 /* Read the bins */ 1592 for (i = 0; i < dev->num_arl_bins; i++) { 1593 u64 mac_vid; 1594 u32 fwd_entry; 1595 1596 b53_read64(dev, B53_ARLIO_PAGE, 1597 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1598 b53_read32(dev, B53_ARLIO_PAGE, 1599 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1600 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1601 1602 if (!(fwd_entry & ARLTBL_VALID)) { 1603 set_bit(i, free_bins); 1604 continue; 1605 } 1606 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1607 continue; 1608 if (dev->vlan_enabled && 1609 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid) 1610 continue; 1611 *idx = i; 1612 return 0; 1613 } 1614 1615 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0) 1616 return -ENOSPC; 1617 1618 *idx = find_first_bit(free_bins, dev->num_arl_bins); 1619 1620 return -ENOENT; 1621 } 1622 1623 static int b53_arl_op(struct b53_device *dev, int op, int port, 1624 const unsigned char *addr, u16 vid, bool is_valid) 1625 { 1626 struct b53_arl_entry ent; 1627 u32 fwd_entry; 1628 u64 mac, mac_vid = 0; 1629 u8 idx = 0; 1630 int ret; 1631 1632 /* Convert the array into a 64-bit MAC */ 1633 mac = ether_addr_to_u64(addr); 1634 1635 /* Perform a read for the given MAC and VID */ 1636 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1637 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1638 1639 /* Issue a read operation for this MAC */ 1640 ret = b53_arl_rw_op(dev, 1); 1641 if (ret) 1642 return ret; 1643 1644 ret = b53_arl_read(dev, mac, vid, &ent, &idx); 1645 1646 /* If this is a read, just finish now */ 1647 if (op) 1648 return ret; 1649 1650 switch (ret) { 1651 case -ETIMEDOUT: 1652 return ret; 1653 case -ENOSPC: 1654 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n", 1655 addr, vid); 1656 return is_valid ? ret : 0; 1657 case -ENOENT: 1658 /* We could not find a matching MAC, so reset to a new entry */ 1659 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n", 1660 addr, vid, idx); 1661 fwd_entry = 0; 1662 break; 1663 default: 1664 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n", 1665 addr, vid, idx); 1666 break; 1667 } 1668 1669 /* For multicast address, the port is a bitmask and the validity 1670 * is determined by having at least one port being still active 1671 */ 1672 if (!is_multicast_ether_addr(addr)) { 1673 ent.port = port; 1674 ent.is_valid = is_valid; 1675 } else { 1676 if (is_valid) 1677 ent.port |= BIT(port); 1678 else 1679 ent.port &= ~BIT(port); 1680 1681 ent.is_valid = !!(ent.port); 1682 } 1683 1684 ent.vid = vid; 1685 ent.is_static = true; 1686 ent.is_age = false; 1687 memcpy(ent.mac, addr, ETH_ALEN); 1688 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1689 1690 b53_write64(dev, B53_ARLIO_PAGE, 1691 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1692 b53_write32(dev, B53_ARLIO_PAGE, 1693 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1694 1695 return b53_arl_rw_op(dev, 0); 1696 } 1697 1698 int b53_fdb_add(struct dsa_switch *ds, int port, 1699 const unsigned char *addr, u16 vid) 1700 { 1701 struct b53_device *priv = ds->priv; 1702 1703 /* 5325 and 5365 require some more massaging, but could 1704 * be supported eventually 1705 */ 1706 if (is5325(priv) || is5365(priv)) 1707 return -EOPNOTSUPP; 1708 1709 return b53_arl_op(priv, 0, port, addr, vid, true); 1710 } 1711 EXPORT_SYMBOL(b53_fdb_add); 1712 1713 int b53_fdb_del(struct dsa_switch *ds, int port, 1714 const unsigned char *addr, u16 vid) 1715 { 1716 struct b53_device *priv = ds->priv; 1717 1718 return b53_arl_op(priv, 0, port, addr, vid, false); 1719 } 1720 EXPORT_SYMBOL(b53_fdb_del); 1721 1722 static int b53_arl_search_wait(struct b53_device *dev) 1723 { 1724 unsigned int timeout = 1000; 1725 u8 reg; 1726 1727 do { 1728 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1729 if (!(reg & ARL_SRCH_STDN)) 1730 return 0; 1731 1732 if (reg & ARL_SRCH_VLID) 1733 return 0; 1734 1735 usleep_range(1000, 2000); 1736 } while (timeout--); 1737 1738 return -ETIMEDOUT; 1739 } 1740 1741 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1742 struct b53_arl_entry *ent) 1743 { 1744 u64 mac_vid; 1745 u32 fwd_entry; 1746 1747 b53_read64(dev, B53_ARLIO_PAGE, 1748 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1749 b53_read32(dev, B53_ARLIO_PAGE, 1750 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1751 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1752 } 1753 1754 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1755 dsa_fdb_dump_cb_t *cb, void *data) 1756 { 1757 if (!ent->is_valid) 1758 return 0; 1759 1760 if (port != ent->port) 1761 return 0; 1762 1763 return cb(ent->mac, ent->vid, ent->is_static, data); 1764 } 1765 1766 int b53_fdb_dump(struct dsa_switch *ds, int port, 1767 dsa_fdb_dump_cb_t *cb, void *data) 1768 { 1769 struct b53_device *priv = ds->priv; 1770 struct b53_arl_entry results[2]; 1771 unsigned int count = 0; 1772 int ret; 1773 u8 reg; 1774 1775 /* Start search operation */ 1776 reg = ARL_SRCH_STDN; 1777 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1778 1779 do { 1780 ret = b53_arl_search_wait(priv); 1781 if (ret) 1782 return ret; 1783 1784 b53_arl_search_rd(priv, 0, &results[0]); 1785 ret = b53_fdb_copy(port, &results[0], cb, data); 1786 if (ret) 1787 return ret; 1788 1789 if (priv->num_arl_bins > 2) { 1790 b53_arl_search_rd(priv, 1, &results[1]); 1791 ret = b53_fdb_copy(port, &results[1], cb, data); 1792 if (ret) 1793 return ret; 1794 1795 if (!results[0].is_valid && !results[1].is_valid) 1796 break; 1797 } 1798 1799 } while (count++ < b53_max_arl_entries(priv) / 2); 1800 1801 return 0; 1802 } 1803 EXPORT_SYMBOL(b53_fdb_dump); 1804 1805 int b53_mdb_add(struct dsa_switch *ds, int port, 1806 const struct switchdev_obj_port_mdb *mdb) 1807 { 1808 struct b53_device *priv = ds->priv; 1809 1810 /* 5325 and 5365 require some more massaging, but could 1811 * be supported eventually 1812 */ 1813 if (is5325(priv) || is5365(priv)) 1814 return -EOPNOTSUPP; 1815 1816 return b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true); 1817 } 1818 EXPORT_SYMBOL(b53_mdb_add); 1819 1820 int b53_mdb_del(struct dsa_switch *ds, int port, 1821 const struct switchdev_obj_port_mdb *mdb) 1822 { 1823 struct b53_device *priv = ds->priv; 1824 int ret; 1825 1826 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false); 1827 if (ret) 1828 dev_err(ds->dev, "failed to delete MDB entry\n"); 1829 1830 return ret; 1831 } 1832 EXPORT_SYMBOL(b53_mdb_del); 1833 1834 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1835 { 1836 struct b53_device *dev = ds->priv; 1837 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1838 u16 pvlan, reg; 1839 unsigned int i; 1840 1841 /* On 7278, port 7 which connects to the ASP should only receive 1842 * traffic from matching CFP rules. 1843 */ 1844 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7) 1845 return -EINVAL; 1846 1847 /* Make this port leave the all VLANs join since we will have proper 1848 * VLAN entries from now on 1849 */ 1850 if (is58xx(dev)) { 1851 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1852 reg &= ~BIT(port); 1853 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1854 reg &= ~BIT(cpu_port); 1855 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1856 } 1857 1858 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1859 1860 b53_for_each_port(dev, i) { 1861 if (dsa_to_port(ds, i)->bridge_dev != br) 1862 continue; 1863 1864 /* Add this local port to the remote port VLAN control 1865 * membership and update the remote port bitmask 1866 */ 1867 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1868 reg |= BIT(port); 1869 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1870 dev->ports[i].vlan_ctl_mask = reg; 1871 1872 pvlan |= BIT(i); 1873 } 1874 1875 /* Configure the local port VLAN control membership to include 1876 * remote ports and update the local port bitmask 1877 */ 1878 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1879 dev->ports[port].vlan_ctl_mask = pvlan; 1880 1881 return 0; 1882 } 1883 EXPORT_SYMBOL(b53_br_join); 1884 1885 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1886 { 1887 struct b53_device *dev = ds->priv; 1888 struct b53_vlan *vl = &dev->vlans[0]; 1889 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 1890 unsigned int i; 1891 u16 pvlan, reg, pvid; 1892 1893 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1894 1895 b53_for_each_port(dev, i) { 1896 /* Don't touch the remaining ports */ 1897 if (dsa_to_port(ds, i)->bridge_dev != br) 1898 continue; 1899 1900 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1901 reg &= ~BIT(port); 1902 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1903 dev->ports[port].vlan_ctl_mask = reg; 1904 1905 /* Prevent self removal to preserve isolation */ 1906 if (port != i) 1907 pvlan &= ~BIT(i); 1908 } 1909 1910 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1911 dev->ports[port].vlan_ctl_mask = pvlan; 1912 1913 pvid = b53_default_pvid(dev); 1914 1915 /* Make this port join all VLANs without VLAN entries */ 1916 if (is58xx(dev)) { 1917 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1918 reg |= BIT(port); 1919 if (!(reg & BIT(cpu_port))) 1920 reg |= BIT(cpu_port); 1921 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1922 } else { 1923 b53_get_vlan_entry(dev, pvid, vl); 1924 vl->members |= BIT(port) | BIT(cpu_port); 1925 vl->untag |= BIT(port) | BIT(cpu_port); 1926 b53_set_vlan_entry(dev, pvid, vl); 1927 } 1928 } 1929 EXPORT_SYMBOL(b53_br_leave); 1930 1931 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1932 { 1933 struct b53_device *dev = ds->priv; 1934 u8 hw_state; 1935 u8 reg; 1936 1937 switch (state) { 1938 case BR_STATE_DISABLED: 1939 hw_state = PORT_CTRL_DIS_STATE; 1940 break; 1941 case BR_STATE_LISTENING: 1942 hw_state = PORT_CTRL_LISTEN_STATE; 1943 break; 1944 case BR_STATE_LEARNING: 1945 hw_state = PORT_CTRL_LEARN_STATE; 1946 break; 1947 case BR_STATE_FORWARDING: 1948 hw_state = PORT_CTRL_FWD_STATE; 1949 break; 1950 case BR_STATE_BLOCKING: 1951 hw_state = PORT_CTRL_BLOCK_STATE; 1952 break; 1953 default: 1954 dev_err(ds->dev, "invalid STP state: %d\n", state); 1955 return; 1956 } 1957 1958 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1959 reg &= ~PORT_CTRL_STP_STATE_MASK; 1960 reg |= hw_state; 1961 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1962 } 1963 EXPORT_SYMBOL(b53_br_set_stp_state); 1964 1965 void b53_br_fast_age(struct dsa_switch *ds, int port) 1966 { 1967 struct b53_device *dev = ds->priv; 1968 1969 if (b53_fast_age_port(dev, port)) 1970 dev_err(ds->dev, "fast ageing failed\n"); 1971 } 1972 EXPORT_SYMBOL(b53_br_fast_age); 1973 1974 int b53_br_flags_pre(struct dsa_switch *ds, int port, 1975 struct switchdev_brport_flags flags, 1976 struct netlink_ext_ack *extack) 1977 { 1978 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING)) 1979 return -EINVAL; 1980 1981 return 0; 1982 } 1983 EXPORT_SYMBOL(b53_br_flags_pre); 1984 1985 int b53_br_flags(struct dsa_switch *ds, int port, 1986 struct switchdev_brport_flags flags, 1987 struct netlink_ext_ack *extack) 1988 { 1989 if (flags.mask & BR_FLOOD) 1990 b53_port_set_ucast_flood(ds->priv, port, 1991 !!(flags.val & BR_FLOOD)); 1992 if (flags.mask & BR_MCAST_FLOOD) 1993 b53_port_set_mcast_flood(ds->priv, port, 1994 !!(flags.val & BR_MCAST_FLOOD)); 1995 if (flags.mask & BR_LEARNING) 1996 b53_port_set_learning(ds->priv, port, 1997 !!(flags.val & BR_LEARNING)); 1998 1999 return 0; 2000 } 2001 EXPORT_SYMBOL(b53_br_flags); 2002 2003 int b53_set_mrouter(struct dsa_switch *ds, int port, bool mrouter, 2004 struct netlink_ext_ack *extack) 2005 { 2006 b53_port_set_mcast_flood(ds->priv, port, mrouter); 2007 2008 return 0; 2009 } 2010 EXPORT_SYMBOL(b53_set_mrouter); 2011 2012 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 2013 { 2014 /* Broadcom switches will accept enabling Broadcom tags on the 2015 * following ports: 5, 7 and 8, any other port is not supported 2016 */ 2017 switch (port) { 2018 case B53_CPU_PORT_25: 2019 case 7: 2020 case B53_CPU_PORT: 2021 return true; 2022 } 2023 2024 return false; 2025 } 2026 2027 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port, 2028 enum dsa_tag_protocol tag_protocol) 2029 { 2030 bool ret = b53_possible_cpu_port(ds, port); 2031 2032 if (!ret) { 2033 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 2034 port); 2035 return ret; 2036 } 2037 2038 switch (tag_protocol) { 2039 case DSA_TAG_PROTO_BRCM: 2040 case DSA_TAG_PROTO_BRCM_PREPEND: 2041 dev_warn(ds->dev, 2042 "Port %d is stacked to Broadcom tag switch\n", port); 2043 ret = false; 2044 break; 2045 default: 2046 ret = true; 2047 break; 2048 } 2049 2050 return ret; 2051 } 2052 2053 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port, 2054 enum dsa_tag_protocol mprot) 2055 { 2056 struct b53_device *dev = ds->priv; 2057 2058 /* Older models (5325, 5365) support a different tag format that we do 2059 * not support in net/dsa/tag_brcm.c yet. 2060 */ 2061 if (is5325(dev) || is5365(dev) || 2062 !b53_can_enable_brcm_tags(ds, port, mprot)) { 2063 dev->tag_protocol = DSA_TAG_PROTO_NONE; 2064 goto out; 2065 } 2066 2067 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 2068 * which requires us to use the prepended Broadcom tag type 2069 */ 2070 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) { 2071 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND; 2072 goto out; 2073 } 2074 2075 dev->tag_protocol = DSA_TAG_PROTO_BRCM; 2076 out: 2077 return dev->tag_protocol; 2078 } 2079 EXPORT_SYMBOL(b53_get_tag_protocol); 2080 2081 int b53_mirror_add(struct dsa_switch *ds, int port, 2082 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 2083 { 2084 struct b53_device *dev = ds->priv; 2085 u16 reg, loc; 2086 2087 if (ingress) 2088 loc = B53_IG_MIR_CTL; 2089 else 2090 loc = B53_EG_MIR_CTL; 2091 2092 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2093 reg |= BIT(port); 2094 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2095 2096 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2097 reg &= ~CAP_PORT_MASK; 2098 reg |= mirror->to_local_port; 2099 reg |= MIRROR_EN; 2100 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2101 2102 return 0; 2103 } 2104 EXPORT_SYMBOL(b53_mirror_add); 2105 2106 void b53_mirror_del(struct dsa_switch *ds, int port, 2107 struct dsa_mall_mirror_tc_entry *mirror) 2108 { 2109 struct b53_device *dev = ds->priv; 2110 bool loc_disable = false, other_loc_disable = false; 2111 u16 reg, loc; 2112 2113 if (mirror->ingress) 2114 loc = B53_IG_MIR_CTL; 2115 else 2116 loc = B53_EG_MIR_CTL; 2117 2118 /* Update the desired ingress/egress register */ 2119 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 2120 reg &= ~BIT(port); 2121 if (!(reg & MIRROR_MASK)) 2122 loc_disable = true; 2123 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 2124 2125 /* Now look at the other one to know if we can disable mirroring 2126 * entirely 2127 */ 2128 if (mirror->ingress) 2129 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 2130 else 2131 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 2132 if (!(reg & MIRROR_MASK)) 2133 other_loc_disable = true; 2134 2135 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 2136 /* Both no longer have ports, let's disable mirroring */ 2137 if (loc_disable && other_loc_disable) { 2138 reg &= ~MIRROR_EN; 2139 reg &= ~mirror->to_local_port; 2140 } 2141 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 2142 } 2143 EXPORT_SYMBOL(b53_mirror_del); 2144 2145 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 2146 { 2147 struct b53_device *dev = ds->priv; 2148 u16 reg; 2149 2150 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 2151 if (enable) 2152 reg |= BIT(port); 2153 else 2154 reg &= ~BIT(port); 2155 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 2156 } 2157 EXPORT_SYMBOL(b53_eee_enable_set); 2158 2159 2160 /* Returns 0 if EEE was not enabled, or 1 otherwise 2161 */ 2162 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 2163 { 2164 int ret; 2165 2166 ret = phy_init_eee(phy, 0); 2167 if (ret) 2168 return 0; 2169 2170 b53_eee_enable_set(ds, port, true); 2171 2172 return 1; 2173 } 2174 EXPORT_SYMBOL(b53_eee_init); 2175 2176 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2177 { 2178 struct b53_device *dev = ds->priv; 2179 struct ethtool_eee *p = &dev->ports[port].eee; 2180 u16 reg; 2181 2182 if (is5325(dev) || is5365(dev)) 2183 return -EOPNOTSUPP; 2184 2185 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 2186 e->eee_enabled = p->eee_enabled; 2187 e->eee_active = !!(reg & BIT(port)); 2188 2189 return 0; 2190 } 2191 EXPORT_SYMBOL(b53_get_mac_eee); 2192 2193 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 2194 { 2195 struct b53_device *dev = ds->priv; 2196 struct ethtool_eee *p = &dev->ports[port].eee; 2197 2198 if (is5325(dev) || is5365(dev)) 2199 return -EOPNOTSUPP; 2200 2201 p->eee_enabled = e->eee_enabled; 2202 b53_eee_enable_set(ds, port, e->eee_enabled); 2203 2204 return 0; 2205 } 2206 EXPORT_SYMBOL(b53_set_mac_eee); 2207 2208 static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu) 2209 { 2210 struct b53_device *dev = ds->priv; 2211 bool enable_jumbo; 2212 bool allow_10_100; 2213 2214 if (is5325(dev) || is5365(dev)) 2215 return -EOPNOTSUPP; 2216 2217 enable_jumbo = (mtu >= JMS_MIN_SIZE); 2218 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID); 2219 2220 return b53_set_jumbo(dev, enable_jumbo, allow_10_100); 2221 } 2222 2223 static int b53_get_max_mtu(struct dsa_switch *ds, int port) 2224 { 2225 return JMS_MAX_SIZE; 2226 } 2227 2228 static const struct dsa_switch_ops b53_switch_ops = { 2229 .get_tag_protocol = b53_get_tag_protocol, 2230 .setup = b53_setup, 2231 .teardown = b53_teardown, 2232 .get_strings = b53_get_strings, 2233 .get_ethtool_stats = b53_get_ethtool_stats, 2234 .get_sset_count = b53_get_sset_count, 2235 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 2236 .phy_read = b53_phy_read16, 2237 .phy_write = b53_phy_write16, 2238 .adjust_link = b53_adjust_link, 2239 .phylink_validate = b53_phylink_validate, 2240 .phylink_mac_link_state = b53_phylink_mac_link_state, 2241 .phylink_mac_config = b53_phylink_mac_config, 2242 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 2243 .phylink_mac_link_down = b53_phylink_mac_link_down, 2244 .phylink_mac_link_up = b53_phylink_mac_link_up, 2245 .port_enable = b53_enable_port, 2246 .port_disable = b53_disable_port, 2247 .get_mac_eee = b53_get_mac_eee, 2248 .set_mac_eee = b53_set_mac_eee, 2249 .port_bridge_join = b53_br_join, 2250 .port_bridge_leave = b53_br_leave, 2251 .port_pre_bridge_flags = b53_br_flags_pre, 2252 .port_bridge_flags = b53_br_flags, 2253 .port_set_mrouter = b53_set_mrouter, 2254 .port_stp_state_set = b53_br_set_stp_state, 2255 .port_fast_age = b53_br_fast_age, 2256 .port_vlan_filtering = b53_vlan_filtering, 2257 .port_vlan_add = b53_vlan_add, 2258 .port_vlan_del = b53_vlan_del, 2259 .port_fdb_dump = b53_fdb_dump, 2260 .port_fdb_add = b53_fdb_add, 2261 .port_fdb_del = b53_fdb_del, 2262 .port_mirror_add = b53_mirror_add, 2263 .port_mirror_del = b53_mirror_del, 2264 .port_mdb_add = b53_mdb_add, 2265 .port_mdb_del = b53_mdb_del, 2266 .port_max_mtu = b53_get_max_mtu, 2267 .port_change_mtu = b53_change_mtu, 2268 }; 2269 2270 struct b53_chip_data { 2271 u32 chip_id; 2272 const char *dev_name; 2273 u16 vlans; 2274 u16 enabled_ports; 2275 u8 cpu_port; 2276 u8 vta_regs[3]; 2277 u8 arl_bins; 2278 u16 arl_buckets; 2279 u8 duplex_reg; 2280 u8 jumbo_pm_reg; 2281 u8 jumbo_size_reg; 2282 }; 2283 2284 #define B53_VTA_REGS \ 2285 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 2286 #define B53_VTA_REGS_9798 \ 2287 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 2288 #define B53_VTA_REGS_63XX \ 2289 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 2290 2291 static const struct b53_chip_data b53_switch_chips[] = { 2292 { 2293 .chip_id = BCM5325_DEVICE_ID, 2294 .dev_name = "BCM5325", 2295 .vlans = 16, 2296 .enabled_ports = 0x1f, 2297 .arl_bins = 2, 2298 .arl_buckets = 1024, 2299 .cpu_port = B53_CPU_PORT_25, 2300 .duplex_reg = B53_DUPLEX_STAT_FE, 2301 }, 2302 { 2303 .chip_id = BCM5365_DEVICE_ID, 2304 .dev_name = "BCM5365", 2305 .vlans = 256, 2306 .enabled_ports = 0x1f, 2307 .arl_bins = 2, 2308 .arl_buckets = 1024, 2309 .cpu_port = B53_CPU_PORT_25, 2310 .duplex_reg = B53_DUPLEX_STAT_FE, 2311 }, 2312 { 2313 .chip_id = BCM5389_DEVICE_ID, 2314 .dev_name = "BCM5389", 2315 .vlans = 4096, 2316 .enabled_ports = 0x1f, 2317 .arl_bins = 4, 2318 .arl_buckets = 1024, 2319 .cpu_port = B53_CPU_PORT, 2320 .vta_regs = B53_VTA_REGS, 2321 .duplex_reg = B53_DUPLEX_STAT_GE, 2322 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2323 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2324 }, 2325 { 2326 .chip_id = BCM5395_DEVICE_ID, 2327 .dev_name = "BCM5395", 2328 .vlans = 4096, 2329 .enabled_ports = 0x1f, 2330 .arl_bins = 4, 2331 .arl_buckets = 1024, 2332 .cpu_port = B53_CPU_PORT, 2333 .vta_regs = B53_VTA_REGS, 2334 .duplex_reg = B53_DUPLEX_STAT_GE, 2335 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2336 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2337 }, 2338 { 2339 .chip_id = BCM5397_DEVICE_ID, 2340 .dev_name = "BCM5397", 2341 .vlans = 4096, 2342 .enabled_ports = 0x1f, 2343 .arl_bins = 4, 2344 .arl_buckets = 1024, 2345 .cpu_port = B53_CPU_PORT, 2346 .vta_regs = B53_VTA_REGS_9798, 2347 .duplex_reg = B53_DUPLEX_STAT_GE, 2348 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2349 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2350 }, 2351 { 2352 .chip_id = BCM5398_DEVICE_ID, 2353 .dev_name = "BCM5398", 2354 .vlans = 4096, 2355 .enabled_ports = 0x7f, 2356 .arl_bins = 4, 2357 .arl_buckets = 1024, 2358 .cpu_port = B53_CPU_PORT, 2359 .vta_regs = B53_VTA_REGS_9798, 2360 .duplex_reg = B53_DUPLEX_STAT_GE, 2361 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2362 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2363 }, 2364 { 2365 .chip_id = BCM53115_DEVICE_ID, 2366 .dev_name = "BCM53115", 2367 .vlans = 4096, 2368 .enabled_ports = 0x1f, 2369 .arl_bins = 4, 2370 .arl_buckets = 1024, 2371 .vta_regs = B53_VTA_REGS, 2372 .cpu_port = B53_CPU_PORT, 2373 .duplex_reg = B53_DUPLEX_STAT_GE, 2374 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2375 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2376 }, 2377 { 2378 .chip_id = BCM53125_DEVICE_ID, 2379 .dev_name = "BCM53125", 2380 .vlans = 4096, 2381 .enabled_ports = 0xff, 2382 .arl_bins = 4, 2383 .arl_buckets = 1024, 2384 .cpu_port = B53_CPU_PORT, 2385 .vta_regs = B53_VTA_REGS, 2386 .duplex_reg = B53_DUPLEX_STAT_GE, 2387 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2388 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2389 }, 2390 { 2391 .chip_id = BCM53128_DEVICE_ID, 2392 .dev_name = "BCM53128", 2393 .vlans = 4096, 2394 .enabled_ports = 0x1ff, 2395 .arl_bins = 4, 2396 .arl_buckets = 1024, 2397 .cpu_port = B53_CPU_PORT, 2398 .vta_regs = B53_VTA_REGS, 2399 .duplex_reg = B53_DUPLEX_STAT_GE, 2400 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2401 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2402 }, 2403 { 2404 .chip_id = BCM63XX_DEVICE_ID, 2405 .dev_name = "BCM63xx", 2406 .vlans = 4096, 2407 .enabled_ports = 0, /* pdata must provide them */ 2408 .arl_bins = 4, 2409 .arl_buckets = 1024, 2410 .cpu_port = B53_CPU_PORT, 2411 .vta_regs = B53_VTA_REGS_63XX, 2412 .duplex_reg = B53_DUPLEX_STAT_63XX, 2413 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2414 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2415 }, 2416 { 2417 .chip_id = BCM53010_DEVICE_ID, 2418 .dev_name = "BCM53010", 2419 .vlans = 4096, 2420 .enabled_ports = 0x1f, 2421 .arl_bins = 4, 2422 .arl_buckets = 1024, 2423 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2424 .vta_regs = B53_VTA_REGS, 2425 .duplex_reg = B53_DUPLEX_STAT_GE, 2426 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2427 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2428 }, 2429 { 2430 .chip_id = BCM53011_DEVICE_ID, 2431 .dev_name = "BCM53011", 2432 .vlans = 4096, 2433 .enabled_ports = 0x1bf, 2434 .arl_bins = 4, 2435 .arl_buckets = 1024, 2436 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2437 .vta_regs = B53_VTA_REGS, 2438 .duplex_reg = B53_DUPLEX_STAT_GE, 2439 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2440 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2441 }, 2442 { 2443 .chip_id = BCM53012_DEVICE_ID, 2444 .dev_name = "BCM53012", 2445 .vlans = 4096, 2446 .enabled_ports = 0x1bf, 2447 .arl_bins = 4, 2448 .arl_buckets = 1024, 2449 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2450 .vta_regs = B53_VTA_REGS, 2451 .duplex_reg = B53_DUPLEX_STAT_GE, 2452 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2453 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2454 }, 2455 { 2456 .chip_id = BCM53018_DEVICE_ID, 2457 .dev_name = "BCM53018", 2458 .vlans = 4096, 2459 .enabled_ports = 0x1f, 2460 .arl_bins = 4, 2461 .arl_buckets = 1024, 2462 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2463 .vta_regs = B53_VTA_REGS, 2464 .duplex_reg = B53_DUPLEX_STAT_GE, 2465 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2466 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2467 }, 2468 { 2469 .chip_id = BCM53019_DEVICE_ID, 2470 .dev_name = "BCM53019", 2471 .vlans = 4096, 2472 .enabled_ports = 0x1f, 2473 .arl_bins = 4, 2474 .arl_buckets = 1024, 2475 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2476 .vta_regs = B53_VTA_REGS, 2477 .duplex_reg = B53_DUPLEX_STAT_GE, 2478 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2479 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2480 }, 2481 { 2482 .chip_id = BCM58XX_DEVICE_ID, 2483 .dev_name = "BCM585xx/586xx/88312", 2484 .vlans = 4096, 2485 .enabled_ports = 0x1ff, 2486 .arl_bins = 4, 2487 .arl_buckets = 1024, 2488 .cpu_port = B53_CPU_PORT, 2489 .vta_regs = B53_VTA_REGS, 2490 .duplex_reg = B53_DUPLEX_STAT_GE, 2491 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2492 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2493 }, 2494 { 2495 .chip_id = BCM583XX_DEVICE_ID, 2496 .dev_name = "BCM583xx/11360", 2497 .vlans = 4096, 2498 .enabled_ports = 0x103, 2499 .arl_bins = 4, 2500 .arl_buckets = 1024, 2501 .cpu_port = B53_CPU_PORT, 2502 .vta_regs = B53_VTA_REGS, 2503 .duplex_reg = B53_DUPLEX_STAT_GE, 2504 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2505 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2506 }, 2507 /* Starfighter 2 */ 2508 { 2509 .chip_id = BCM4908_DEVICE_ID, 2510 .dev_name = "BCM4908", 2511 .vlans = 4096, 2512 .enabled_ports = 0x1bf, 2513 .arl_bins = 4, 2514 .arl_buckets = 256, 2515 .cpu_port = 8, /* TODO: ports 4, 5, 8 */ 2516 .vta_regs = B53_VTA_REGS, 2517 .duplex_reg = B53_DUPLEX_STAT_GE, 2518 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2519 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2520 }, 2521 { 2522 .chip_id = BCM7445_DEVICE_ID, 2523 .dev_name = "BCM7445", 2524 .vlans = 4096, 2525 .enabled_ports = 0x1ff, 2526 .arl_bins = 4, 2527 .arl_buckets = 1024, 2528 .cpu_port = B53_CPU_PORT, 2529 .vta_regs = B53_VTA_REGS, 2530 .duplex_reg = B53_DUPLEX_STAT_GE, 2531 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2532 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2533 }, 2534 { 2535 .chip_id = BCM7278_DEVICE_ID, 2536 .dev_name = "BCM7278", 2537 .vlans = 4096, 2538 .enabled_ports = 0x1ff, 2539 .arl_bins = 4, 2540 .arl_buckets = 256, 2541 .cpu_port = B53_CPU_PORT, 2542 .vta_regs = B53_VTA_REGS, 2543 .duplex_reg = B53_DUPLEX_STAT_GE, 2544 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2545 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2546 }, 2547 }; 2548 2549 static int b53_switch_init(struct b53_device *dev) 2550 { 2551 unsigned int i; 2552 int ret; 2553 2554 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2555 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2556 2557 if (chip->chip_id == dev->chip_id) { 2558 if (!dev->enabled_ports) 2559 dev->enabled_ports = chip->enabled_ports; 2560 dev->name = chip->dev_name; 2561 dev->duplex_reg = chip->duplex_reg; 2562 dev->vta_regs[0] = chip->vta_regs[0]; 2563 dev->vta_regs[1] = chip->vta_regs[1]; 2564 dev->vta_regs[2] = chip->vta_regs[2]; 2565 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2566 dev->cpu_port = chip->cpu_port; 2567 dev->num_vlans = chip->vlans; 2568 dev->num_arl_bins = chip->arl_bins; 2569 dev->num_arl_buckets = chip->arl_buckets; 2570 break; 2571 } 2572 } 2573 2574 /* check which BCM5325x version we have */ 2575 if (is5325(dev)) { 2576 u8 vc4; 2577 2578 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2579 2580 /* check reserved bits */ 2581 switch (vc4 & 3) { 2582 case 1: 2583 /* BCM5325E */ 2584 break; 2585 case 3: 2586 /* BCM5325F - do not use port 4 */ 2587 dev->enabled_ports &= ~BIT(4); 2588 break; 2589 default: 2590 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2591 #ifndef CONFIG_BCM47XX 2592 /* BCM5325M */ 2593 return -EINVAL; 2594 #else 2595 break; 2596 #endif 2597 } 2598 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2599 u64 strap_value; 2600 2601 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2602 /* use second IMP port if GMII is enabled */ 2603 if (strap_value & SV_GMII_CTRL_115) 2604 dev->cpu_port = 5; 2605 } 2606 2607 /* cpu port is always last */ 2608 dev->num_ports = dev->cpu_port + 1; 2609 dev->enabled_ports |= BIT(dev->cpu_port); 2610 2611 /* Include non standard CPU port built-in PHYs to be probed */ 2612 if (is539x(dev) || is531x5(dev)) { 2613 for (i = 0; i < dev->num_ports; i++) { 2614 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2615 !b53_possible_cpu_port(dev->ds, i)) 2616 dev->ds->phys_mii_mask |= BIT(i); 2617 } 2618 } 2619 2620 dev->ports = devm_kcalloc(dev->dev, 2621 dev->num_ports, sizeof(struct b53_port), 2622 GFP_KERNEL); 2623 if (!dev->ports) 2624 return -ENOMEM; 2625 2626 dev->vlans = devm_kcalloc(dev->dev, 2627 dev->num_vlans, sizeof(struct b53_vlan), 2628 GFP_KERNEL); 2629 if (!dev->vlans) 2630 return -ENOMEM; 2631 2632 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2633 if (dev->reset_gpio >= 0) { 2634 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2635 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2636 if (ret) 2637 return ret; 2638 } 2639 2640 return 0; 2641 } 2642 2643 struct b53_device *b53_switch_alloc(struct device *base, 2644 const struct b53_io_ops *ops, 2645 void *priv) 2646 { 2647 struct dsa_switch *ds; 2648 struct b53_device *dev; 2649 2650 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2651 if (!ds) 2652 return NULL; 2653 2654 ds->dev = base; 2655 ds->num_ports = DSA_MAX_PORTS; 2656 2657 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2658 if (!dev) 2659 return NULL; 2660 2661 ds->priv = dev; 2662 dev->dev = base; 2663 2664 dev->ds = ds; 2665 dev->priv = priv; 2666 dev->ops = ops; 2667 ds->ops = &b53_switch_ops; 2668 ds->untag_bridge_pvid = true; 2669 dev->vlan_enabled = true; 2670 mutex_init(&dev->reg_mutex); 2671 mutex_init(&dev->stats_mutex); 2672 2673 return dev; 2674 } 2675 EXPORT_SYMBOL(b53_switch_alloc); 2676 2677 int b53_switch_detect(struct b53_device *dev) 2678 { 2679 u32 id32; 2680 u16 tmp; 2681 u8 id8; 2682 int ret; 2683 2684 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2685 if (ret) 2686 return ret; 2687 2688 switch (id8) { 2689 case 0: 2690 /* BCM5325 and BCM5365 do not have this register so reads 2691 * return 0. But the read operation did succeed, so assume this 2692 * is one of them. 2693 * 2694 * Next check if we can write to the 5325's VTA register; for 2695 * 5365 it is read only. 2696 */ 2697 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2698 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2699 2700 if (tmp == 0xf) 2701 dev->chip_id = BCM5325_DEVICE_ID; 2702 else 2703 dev->chip_id = BCM5365_DEVICE_ID; 2704 break; 2705 case BCM5389_DEVICE_ID: 2706 case BCM5395_DEVICE_ID: 2707 case BCM5397_DEVICE_ID: 2708 case BCM5398_DEVICE_ID: 2709 dev->chip_id = id8; 2710 break; 2711 default: 2712 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2713 if (ret) 2714 return ret; 2715 2716 switch (id32) { 2717 case BCM53115_DEVICE_ID: 2718 case BCM53125_DEVICE_ID: 2719 case BCM53128_DEVICE_ID: 2720 case BCM53010_DEVICE_ID: 2721 case BCM53011_DEVICE_ID: 2722 case BCM53012_DEVICE_ID: 2723 case BCM53018_DEVICE_ID: 2724 case BCM53019_DEVICE_ID: 2725 dev->chip_id = id32; 2726 break; 2727 default: 2728 dev_err(dev->dev, 2729 "unsupported switch detected (BCM53%02x/BCM%x)\n", 2730 id8, id32); 2731 return -ENODEV; 2732 } 2733 } 2734 2735 if (dev->chip_id == BCM5325_DEVICE_ID) 2736 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2737 &dev->core_rev); 2738 else 2739 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2740 &dev->core_rev); 2741 } 2742 EXPORT_SYMBOL(b53_switch_detect); 2743 2744 int b53_switch_register(struct b53_device *dev) 2745 { 2746 int ret; 2747 2748 if (dev->pdata) { 2749 dev->chip_id = dev->pdata->chip_id; 2750 dev->enabled_ports = dev->pdata->enabled_ports; 2751 } 2752 2753 if (!dev->chip_id && b53_switch_detect(dev)) 2754 return -EINVAL; 2755 2756 ret = b53_switch_init(dev); 2757 if (ret) 2758 return ret; 2759 2760 dev_info(dev->dev, "found switch: %s, rev %i\n", 2761 dev->name, dev->core_rev); 2762 2763 return dsa_register_switch(dev->ds); 2764 } 2765 EXPORT_SYMBOL(b53_switch_register); 2766 2767 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2768 MODULE_DESCRIPTION("B53 switch library"); 2769 MODULE_LICENSE("Dual BSD/GPL"); 2770