1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/etherdevice.h> 30 #include <linux/if_bridge.h> 31 #include <net/dsa.h> 32 33 #include "b53_regs.h" 34 #include "b53_priv.h" 35 36 struct b53_mib_desc { 37 u8 size; 38 u8 offset; 39 const char *name; 40 }; 41 42 /* BCM5365 MIB counters */ 43 static const struct b53_mib_desc b53_mibs_65[] = { 44 { 8, 0x00, "TxOctets" }, 45 { 4, 0x08, "TxDropPkts" }, 46 { 4, 0x10, "TxBroadcastPkts" }, 47 { 4, 0x14, "TxMulticastPkts" }, 48 { 4, 0x18, "TxUnicastPkts" }, 49 { 4, 0x1c, "TxCollisions" }, 50 { 4, 0x20, "TxSingleCollision" }, 51 { 4, 0x24, "TxMultipleCollision" }, 52 { 4, 0x28, "TxDeferredTransmit" }, 53 { 4, 0x2c, "TxLateCollision" }, 54 { 4, 0x30, "TxExcessiveCollision" }, 55 { 4, 0x38, "TxPausePkts" }, 56 { 8, 0x44, "RxOctets" }, 57 { 4, 0x4c, "RxUndersizePkts" }, 58 { 4, 0x50, "RxPausePkts" }, 59 { 4, 0x54, "Pkts64Octets" }, 60 { 4, 0x58, "Pkts65to127Octets" }, 61 { 4, 0x5c, "Pkts128to255Octets" }, 62 { 4, 0x60, "Pkts256to511Octets" }, 63 { 4, 0x64, "Pkts512to1023Octets" }, 64 { 4, 0x68, "Pkts1024to1522Octets" }, 65 { 4, 0x6c, "RxOversizePkts" }, 66 { 4, 0x70, "RxJabbers" }, 67 { 4, 0x74, "RxAlignmentErrors" }, 68 { 4, 0x78, "RxFCSErrors" }, 69 { 8, 0x7c, "RxGoodOctets" }, 70 { 4, 0x84, "RxDropPkts" }, 71 { 4, 0x88, "RxUnicastPkts" }, 72 { 4, 0x8c, "RxMulticastPkts" }, 73 { 4, 0x90, "RxBroadcastPkts" }, 74 { 4, 0x94, "RxSAChanges" }, 75 { 4, 0x98, "RxFragments" }, 76 }; 77 78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 79 80 /* BCM63xx MIB counters */ 81 static const struct b53_mib_desc b53_mibs_63xx[] = { 82 { 8, 0x00, "TxOctets" }, 83 { 4, 0x08, "TxDropPkts" }, 84 { 4, 0x0c, "TxQoSPkts" }, 85 { 4, 0x10, "TxBroadcastPkts" }, 86 { 4, 0x14, "TxMulticastPkts" }, 87 { 4, 0x18, "TxUnicastPkts" }, 88 { 4, 0x1c, "TxCollisions" }, 89 { 4, 0x20, "TxSingleCollision" }, 90 { 4, 0x24, "TxMultipleCollision" }, 91 { 4, 0x28, "TxDeferredTransmit" }, 92 { 4, 0x2c, "TxLateCollision" }, 93 { 4, 0x30, "TxExcessiveCollision" }, 94 { 4, 0x38, "TxPausePkts" }, 95 { 8, 0x3c, "TxQoSOctets" }, 96 { 8, 0x44, "RxOctets" }, 97 { 4, 0x4c, "RxUndersizePkts" }, 98 { 4, 0x50, "RxPausePkts" }, 99 { 4, 0x54, "Pkts64Octets" }, 100 { 4, 0x58, "Pkts65to127Octets" }, 101 { 4, 0x5c, "Pkts128to255Octets" }, 102 { 4, 0x60, "Pkts256to511Octets" }, 103 { 4, 0x64, "Pkts512to1023Octets" }, 104 { 4, 0x68, "Pkts1024to1522Octets" }, 105 { 4, 0x6c, "RxOversizePkts" }, 106 { 4, 0x70, "RxJabbers" }, 107 { 4, 0x74, "RxAlignmentErrors" }, 108 { 4, 0x78, "RxFCSErrors" }, 109 { 8, 0x7c, "RxGoodOctets" }, 110 { 4, 0x84, "RxDropPkts" }, 111 { 4, 0x88, "RxUnicastPkts" }, 112 { 4, 0x8c, "RxMulticastPkts" }, 113 { 4, 0x90, "RxBroadcastPkts" }, 114 { 4, 0x94, "RxSAChanges" }, 115 { 4, 0x98, "RxFragments" }, 116 { 4, 0xa0, "RxSymbolErrors" }, 117 { 4, 0xa4, "RxQoSPkts" }, 118 { 8, 0xa8, "RxQoSOctets" }, 119 { 4, 0xb0, "Pkts1523to2047Octets" }, 120 { 4, 0xb4, "Pkts2048to4095Octets" }, 121 { 4, 0xb8, "Pkts4096to8191Octets" }, 122 { 4, 0xbc, "Pkts8192to9728Octets" }, 123 { 4, 0xc0, "RxDiscarded" }, 124 }; 125 126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 127 128 /* MIB counters */ 129 static const struct b53_mib_desc b53_mibs[] = { 130 { 8, 0x00, "TxOctets" }, 131 { 4, 0x08, "TxDropPkts" }, 132 { 4, 0x10, "TxBroadcastPkts" }, 133 { 4, 0x14, "TxMulticastPkts" }, 134 { 4, 0x18, "TxUnicastPkts" }, 135 { 4, 0x1c, "TxCollisions" }, 136 { 4, 0x20, "TxSingleCollision" }, 137 { 4, 0x24, "TxMultipleCollision" }, 138 { 4, 0x28, "TxDeferredTransmit" }, 139 { 4, 0x2c, "TxLateCollision" }, 140 { 4, 0x30, "TxExcessiveCollision" }, 141 { 4, 0x38, "TxPausePkts" }, 142 { 8, 0x50, "RxOctets" }, 143 { 4, 0x58, "RxUndersizePkts" }, 144 { 4, 0x5c, "RxPausePkts" }, 145 { 4, 0x60, "Pkts64Octets" }, 146 { 4, 0x64, "Pkts65to127Octets" }, 147 { 4, 0x68, "Pkts128to255Octets" }, 148 { 4, 0x6c, "Pkts256to511Octets" }, 149 { 4, 0x70, "Pkts512to1023Octets" }, 150 { 4, 0x74, "Pkts1024to1522Octets" }, 151 { 4, 0x78, "RxOversizePkts" }, 152 { 4, 0x7c, "RxJabbers" }, 153 { 4, 0x80, "RxAlignmentErrors" }, 154 { 4, 0x84, "RxFCSErrors" }, 155 { 8, 0x88, "RxGoodOctets" }, 156 { 4, 0x90, "RxDropPkts" }, 157 { 4, 0x94, "RxUnicastPkts" }, 158 { 4, 0x98, "RxMulticastPkts" }, 159 { 4, 0x9c, "RxBroadcastPkts" }, 160 { 4, 0xa0, "RxSAChanges" }, 161 { 4, 0xa4, "RxFragments" }, 162 { 4, 0xa8, "RxJumboPkts" }, 163 { 4, 0xac, "RxSymbolErrors" }, 164 { 4, 0xc0, "RxDiscarded" }, 165 }; 166 167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 168 169 static const struct b53_mib_desc b53_mibs_58xx[] = { 170 { 8, 0x00, "TxOctets" }, 171 { 4, 0x08, "TxDropPkts" }, 172 { 4, 0x0c, "TxQPKTQ0" }, 173 { 4, 0x10, "TxBroadcastPkts" }, 174 { 4, 0x14, "TxMulticastPkts" }, 175 { 4, 0x18, "TxUnicastPKts" }, 176 { 4, 0x1c, "TxCollisions" }, 177 { 4, 0x20, "TxSingleCollision" }, 178 { 4, 0x24, "TxMultipleCollision" }, 179 { 4, 0x28, "TxDeferredCollision" }, 180 { 4, 0x2c, "TxLateCollision" }, 181 { 4, 0x30, "TxExcessiveCollision" }, 182 { 4, 0x34, "TxFrameInDisc" }, 183 { 4, 0x38, "TxPausePkts" }, 184 { 4, 0x3c, "TxQPKTQ1" }, 185 { 4, 0x40, "TxQPKTQ2" }, 186 { 4, 0x44, "TxQPKTQ3" }, 187 { 4, 0x48, "TxQPKTQ4" }, 188 { 4, 0x4c, "TxQPKTQ5" }, 189 { 8, 0x50, "RxOctets" }, 190 { 4, 0x58, "RxUndersizePkts" }, 191 { 4, 0x5c, "RxPausePkts" }, 192 { 4, 0x60, "RxPkts64Octets" }, 193 { 4, 0x64, "RxPkts65to127Octets" }, 194 { 4, 0x68, "RxPkts128to255Octets" }, 195 { 4, 0x6c, "RxPkts256to511Octets" }, 196 { 4, 0x70, "RxPkts512to1023Octets" }, 197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 198 { 4, 0x78, "RxOversizePkts" }, 199 { 4, 0x7c, "RxJabbers" }, 200 { 4, 0x80, "RxAlignmentErrors" }, 201 { 4, 0x84, "RxFCSErrors" }, 202 { 8, 0x88, "RxGoodOctets" }, 203 { 4, 0x90, "RxDropPkts" }, 204 { 4, 0x94, "RxUnicastPkts" }, 205 { 4, 0x98, "RxMulticastPkts" }, 206 { 4, 0x9c, "RxBroadcastPkts" }, 207 { 4, 0xa0, "RxSAChanges" }, 208 { 4, 0xa4, "RxFragments" }, 209 { 4, 0xa8, "RxJumboPkt" }, 210 { 4, 0xac, "RxSymblErr" }, 211 { 4, 0xb0, "InRangeErrCount" }, 212 { 4, 0xb4, "OutRangeErrCount" }, 213 { 4, 0xb8, "EEELpiEvent" }, 214 { 4, 0xbc, "EEELpiDuration" }, 215 { 4, 0xc0, "RxDiscard" }, 216 { 4, 0xc8, "TxQPKTQ6" }, 217 { 4, 0xcc, "TxQPKTQ7" }, 218 { 4, 0xd0, "TxPkts64Octets" }, 219 { 4, 0xd4, "TxPkts65to127Octets" }, 220 { 4, 0xd8, "TxPkts128to255Octets" }, 221 { 4, 0xdc, "TxPkts256to511Ocets" }, 222 { 4, 0xe0, "TxPkts512to1023Ocets" }, 223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 224 }; 225 226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 227 228 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 229 { 230 unsigned int i; 231 232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 233 234 for (i = 0; i < 10; i++) { 235 u8 vta; 236 237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 238 if (!(vta & VTA_START_CMD)) 239 return 0; 240 241 usleep_range(100, 200); 242 } 243 244 return -EIO; 245 } 246 247 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 248 struct b53_vlan *vlan) 249 { 250 if (is5325(dev)) { 251 u32 entry = 0; 252 253 if (vlan->members) { 254 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 255 VA_UNTAG_S_25) | vlan->members; 256 if (dev->core_rev >= 3) 257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 258 else 259 entry |= VA_VALID_25; 260 } 261 262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 264 VTA_RW_STATE_WR | VTA_RW_OP_EN); 265 } else if (is5365(dev)) { 266 u16 entry = 0; 267 268 if (vlan->members) 269 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 271 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 274 VTA_RW_STATE_WR | VTA_RW_OP_EN); 275 } else { 276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 278 (vlan->untag << VTE_UNTAG_S) | vlan->members); 279 280 b53_do_vlan_op(dev, VTA_CMD_WRITE); 281 } 282 283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 284 vid, vlan->members, vlan->untag); 285 } 286 287 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 288 struct b53_vlan *vlan) 289 { 290 if (is5325(dev)) { 291 u32 entry = 0; 292 293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 294 VTA_RW_STATE_RD | VTA_RW_OP_EN); 295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 296 297 if (dev->core_rev >= 3) 298 vlan->valid = !!(entry & VA_VALID_25_R4); 299 else 300 vlan->valid = !!(entry & VA_VALID_25); 301 vlan->members = entry & VA_MEMBER_MASK; 302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 303 304 } else if (is5365(dev)) { 305 u16 entry = 0; 306 307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 308 VTA_RW_STATE_WR | VTA_RW_OP_EN); 309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 310 311 vlan->valid = !!(entry & VA_VALID_65); 312 vlan->members = entry & VA_MEMBER_MASK; 313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 314 } else { 315 u32 entry = 0; 316 317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 318 b53_do_vlan_op(dev, VTA_CMD_READ); 319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 320 vlan->members = entry & VTE_MEMBERS; 321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 322 vlan->valid = true; 323 } 324 } 325 326 static void b53_set_forwarding(struct b53_device *dev, int enable) 327 { 328 struct dsa_switch *ds = dev->ds; 329 u8 mgmt; 330 331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 332 333 if (enable) 334 mgmt |= SM_SW_FWD_EN; 335 else 336 mgmt &= ~SM_SW_FWD_EN; 337 338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 339 340 /* Include IMP port in dumb forwarding mode when no tagging protocol is 341 * set 342 */ 343 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) { 344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 345 mgmt |= B53_MII_DUMB_FWDG_EN; 346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 347 } 348 } 349 350 static void b53_enable_vlan(struct b53_device *dev, bool enable) 351 { 352 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 353 354 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 357 358 if (is5325(dev) || is5365(dev)) { 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 361 } else if (is63xx(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 364 } else { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 367 } 368 369 mgmt &= ~SM_SW_FWD_MODE; 370 371 if (enable) { 372 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 373 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 374 vc4 &= ~VC4_ING_VID_CHECK_MASK; 375 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 376 vc5 |= VC5_DROP_VTABLE_MISS; 377 378 if (is5325(dev)) 379 vc0 &= ~VC0_RESERVED_1; 380 381 if (is5325(dev) || is5365(dev)) 382 vc1 |= VC1_RX_MCST_TAG_EN; 383 384 } else { 385 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 386 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 387 vc4 &= ~VC4_ING_VID_CHECK_MASK; 388 vc5 &= ~VC5_DROP_VTABLE_MISS; 389 390 if (is5325(dev) || is5365(dev)) 391 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 392 else 393 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 394 395 if (is5325(dev) || is5365(dev)) 396 vc1 &= ~VC1_RX_MCST_TAG_EN; 397 } 398 399 if (!is5325(dev) && !is5365(dev)) 400 vc5 &= ~VC5_VID_FFF_EN; 401 402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 404 405 if (is5325(dev) || is5365(dev)) { 406 /* enable the high 8 bit vid check on 5325 */ 407 if (is5325(dev) && enable) 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 409 VC3_HIGH_8BIT_EN); 410 else 411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 412 413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 415 } else if (is63xx(dev)) { 416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 419 } else { 420 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 423 } 424 425 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 426 } 427 428 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 429 { 430 u32 port_mask = 0; 431 u16 max_size = JMS_MIN_SIZE; 432 433 if (is5325(dev) || is5365(dev)) 434 return -EINVAL; 435 436 if (enable) { 437 port_mask = dev->enabled_ports; 438 max_size = JMS_MAX_SIZE; 439 if (allow_10_100) 440 port_mask |= JPM_10_100_JUMBO_EN; 441 } 442 443 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 444 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 445 } 446 447 static int b53_flush_arl(struct b53_device *dev, u8 mask) 448 { 449 unsigned int i; 450 451 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 452 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 453 454 for (i = 0; i < 10; i++) { 455 u8 fast_age_ctrl; 456 457 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 458 &fast_age_ctrl); 459 460 if (!(fast_age_ctrl & FAST_AGE_DONE)) 461 goto out; 462 463 msleep(1); 464 } 465 466 return -ETIMEDOUT; 467 out: 468 /* Only age dynamic entries (default behavior) */ 469 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 470 return 0; 471 } 472 473 static int b53_fast_age_port(struct b53_device *dev, int port) 474 { 475 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 476 477 return b53_flush_arl(dev, FAST_AGE_PORT); 478 } 479 480 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 481 { 482 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 483 484 return b53_flush_arl(dev, FAST_AGE_VLAN); 485 } 486 487 static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 488 { 489 struct b53_device *dev = ds->priv; 490 unsigned int i; 491 u16 pvlan; 492 493 /* Enable the IMP port to be in the same VLAN as the other ports 494 * on a per-port basis such that we only have Port i and IMP in 495 * the same VLAN. 496 */ 497 b53_for_each_port(dev, i) { 498 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 499 pvlan |= BIT(cpu_port); 500 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 501 } 502 } 503 504 static int b53_enable_port(struct dsa_switch *ds, int port, 505 struct phy_device *phy) 506 { 507 struct b53_device *dev = ds->priv; 508 unsigned int cpu_port = dev->cpu_port; 509 u16 pvlan; 510 511 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 512 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 513 514 /* Set this port, and only this one to be in the default VLAN, 515 * if member of a bridge, restore its membership prior to 516 * bringing down this port. 517 */ 518 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 519 pvlan &= ~0x1ff; 520 pvlan |= BIT(port); 521 pvlan |= dev->ports[port].vlan_ctl_mask; 522 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 523 524 b53_imp_vlan_setup(ds, cpu_port); 525 526 return 0; 527 } 528 529 static void b53_disable_port(struct dsa_switch *ds, int port, 530 struct phy_device *phy) 531 { 532 struct b53_device *dev = ds->priv; 533 u8 reg; 534 535 /* Disable Tx/Rx for the port */ 536 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 537 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 538 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 539 } 540 541 static void b53_enable_cpu_port(struct b53_device *dev) 542 { 543 unsigned int cpu_port = dev->cpu_port; 544 u8 port_ctrl; 545 546 /* BCM5325 CPU port is at 8 */ 547 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25) 548 cpu_port = B53_CPU_PORT; 549 550 port_ctrl = PORT_CTRL_RX_BCST_EN | 551 PORT_CTRL_RX_MCST_EN | 552 PORT_CTRL_RX_UCST_EN; 553 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl); 554 } 555 556 static void b53_enable_mib(struct b53_device *dev) 557 { 558 u8 gc; 559 560 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 561 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 562 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 563 } 564 565 static int b53_configure_vlan(struct b53_device *dev) 566 { 567 struct b53_vlan vl = { 0 }; 568 int i; 569 570 /* clear all vlan entries */ 571 if (is5325(dev) || is5365(dev)) { 572 for (i = 1; i < dev->num_vlans; i++) 573 b53_set_vlan_entry(dev, i, &vl); 574 } else { 575 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 576 } 577 578 b53_enable_vlan(dev, false); 579 580 b53_for_each_port(dev, i) 581 b53_write16(dev, B53_VLAN_PAGE, 582 B53_VLAN_PORT_DEF_TAG(i), 1); 583 584 if (!is5325(dev) && !is5365(dev)) 585 b53_set_jumbo(dev, dev->enable_jumbo, false); 586 587 return 0; 588 } 589 590 static void b53_switch_reset_gpio(struct b53_device *dev) 591 { 592 int gpio = dev->reset_gpio; 593 594 if (gpio < 0) 595 return; 596 597 /* Reset sequence: RESET low(50ms)->high(20ms) 598 */ 599 gpio_set_value(gpio, 0); 600 mdelay(50); 601 602 gpio_set_value(gpio, 1); 603 mdelay(20); 604 605 dev->current_page = 0xff; 606 } 607 608 static int b53_switch_reset(struct b53_device *dev) 609 { 610 unsigned int timeout = 1000; 611 u8 mgmt, reg; 612 613 b53_switch_reset_gpio(dev); 614 615 if (is539x(dev)) { 616 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 617 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 618 } 619 620 /* This is specific to 58xx devices here, do not use is58xx() which 621 * covers the larger Starfigther 2 family, including 7445/7278 which 622 * still use this driver as a library and need to perform the reset 623 * earlier. 624 */ 625 if (dev->chip_id == BCM58XX_DEVICE_ID) { 626 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 627 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 628 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 629 630 do { 631 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 632 if (!(reg & SW_RST)) 633 break; 634 635 usleep_range(1000, 2000); 636 } while (timeout-- > 0); 637 638 if (timeout == 0) 639 return -ETIMEDOUT; 640 } 641 642 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 643 644 if (!(mgmt & SM_SW_FWD_EN)) { 645 mgmt &= ~SM_SW_FWD_MODE; 646 mgmt |= SM_SW_FWD_EN; 647 648 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 649 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 650 651 if (!(mgmt & SM_SW_FWD_EN)) { 652 dev_err(dev->dev, "Failed to enable switch!\n"); 653 return -EINVAL; 654 } 655 } 656 657 b53_enable_mib(dev); 658 659 return b53_flush_arl(dev, FAST_AGE_STATIC); 660 } 661 662 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 663 { 664 struct b53_device *priv = ds->priv; 665 u16 value = 0; 666 int ret; 667 668 if (priv->ops->phy_read16) 669 ret = priv->ops->phy_read16(priv, addr, reg, &value); 670 else 671 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 672 reg * 2, &value); 673 674 return ret ? ret : value; 675 } 676 677 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 678 { 679 struct b53_device *priv = ds->priv; 680 681 if (priv->ops->phy_write16) 682 return priv->ops->phy_write16(priv, addr, reg, val); 683 684 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 685 } 686 687 static int b53_reset_switch(struct b53_device *priv) 688 { 689 /* reset vlans */ 690 priv->enable_jumbo = false; 691 692 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 693 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 694 695 return b53_switch_reset(priv); 696 } 697 698 static int b53_apply_config(struct b53_device *priv) 699 { 700 /* disable switching */ 701 b53_set_forwarding(priv, 0); 702 703 b53_configure_vlan(priv); 704 705 /* enable switching */ 706 b53_set_forwarding(priv, 1); 707 708 return 0; 709 } 710 711 static void b53_reset_mib(struct b53_device *priv) 712 { 713 u8 gc; 714 715 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 716 717 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 718 msleep(1); 719 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 720 msleep(1); 721 } 722 723 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 724 { 725 if (is5365(dev)) 726 return b53_mibs_65; 727 else if (is63xx(dev)) 728 return b53_mibs_63xx; 729 else if (is58xx(dev)) 730 return b53_mibs_58xx; 731 else 732 return b53_mibs; 733 } 734 735 static unsigned int b53_get_mib_size(struct b53_device *dev) 736 { 737 if (is5365(dev)) 738 return B53_MIBS_65_SIZE; 739 else if (is63xx(dev)) 740 return B53_MIBS_63XX_SIZE; 741 else if (is58xx(dev)) 742 return B53_MIBS_58XX_SIZE; 743 else 744 return B53_MIBS_SIZE; 745 } 746 747 void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data) 748 { 749 struct b53_device *dev = ds->priv; 750 const struct b53_mib_desc *mibs = b53_get_mib(dev); 751 unsigned int mib_size = b53_get_mib_size(dev); 752 unsigned int i; 753 754 for (i = 0; i < mib_size; i++) 755 memcpy(data + i * ETH_GSTRING_LEN, 756 mibs[i].name, ETH_GSTRING_LEN); 757 } 758 EXPORT_SYMBOL(b53_get_strings); 759 760 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 761 { 762 struct b53_device *dev = ds->priv; 763 const struct b53_mib_desc *mibs = b53_get_mib(dev); 764 unsigned int mib_size = b53_get_mib_size(dev); 765 const struct b53_mib_desc *s; 766 unsigned int i; 767 u64 val = 0; 768 769 if (is5365(dev) && port == 5) 770 port = 8; 771 772 mutex_lock(&dev->stats_mutex); 773 774 for (i = 0; i < mib_size; i++) { 775 s = &mibs[i]; 776 777 if (s->size == 8) { 778 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 779 } else { 780 u32 val32; 781 782 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 783 &val32); 784 val = val32; 785 } 786 data[i] = (u64)val; 787 } 788 789 mutex_unlock(&dev->stats_mutex); 790 } 791 EXPORT_SYMBOL(b53_get_ethtool_stats); 792 793 int b53_get_sset_count(struct dsa_switch *ds) 794 { 795 struct b53_device *dev = ds->priv; 796 797 return b53_get_mib_size(dev); 798 } 799 EXPORT_SYMBOL(b53_get_sset_count); 800 801 static int b53_setup(struct dsa_switch *ds) 802 { 803 struct b53_device *dev = ds->priv; 804 unsigned int port; 805 int ret; 806 807 ret = b53_reset_switch(dev); 808 if (ret) { 809 dev_err(ds->dev, "failed to reset switch\n"); 810 return ret; 811 } 812 813 b53_reset_mib(dev); 814 815 ret = b53_apply_config(dev); 816 if (ret) 817 dev_err(ds->dev, "failed to apply configuration\n"); 818 819 for (port = 0; port < dev->num_ports; port++) { 820 if (BIT(port) & ds->enabled_port_mask) 821 b53_enable_port(ds, port, NULL); 822 else if (dsa_is_cpu_port(ds, port)) 823 b53_enable_cpu_port(dev); 824 else 825 b53_disable_port(ds, port, NULL); 826 } 827 828 return ret; 829 } 830 831 static void b53_adjust_link(struct dsa_switch *ds, int port, 832 struct phy_device *phydev) 833 { 834 struct b53_device *dev = ds->priv; 835 u8 rgmii_ctrl = 0, reg = 0, off; 836 837 if (!phy_is_pseudo_fixed_link(phydev)) 838 return; 839 840 /* Override the port settings */ 841 if (port == dev->cpu_port) { 842 off = B53_PORT_OVERRIDE_CTRL; 843 reg = PORT_OVERRIDE_EN; 844 } else { 845 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 846 reg = GMII_PO_EN; 847 } 848 849 /* Set the link UP */ 850 if (phydev->link) 851 reg |= PORT_OVERRIDE_LINK; 852 853 if (phydev->duplex == DUPLEX_FULL) 854 reg |= PORT_OVERRIDE_FULL_DUPLEX; 855 856 switch (phydev->speed) { 857 case 2000: 858 reg |= PORT_OVERRIDE_SPEED_2000M; 859 /* fallthrough */ 860 case SPEED_1000: 861 reg |= PORT_OVERRIDE_SPEED_1000M; 862 break; 863 case SPEED_100: 864 reg |= PORT_OVERRIDE_SPEED_100M; 865 break; 866 case SPEED_10: 867 reg |= PORT_OVERRIDE_SPEED_10M; 868 break; 869 default: 870 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed); 871 return; 872 } 873 874 /* Enable flow control on BCM5301x's CPU port */ 875 if (is5301x(dev) && port == dev->cpu_port) 876 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW; 877 878 if (phydev->pause) { 879 if (phydev->asym_pause) 880 reg |= PORT_OVERRIDE_TX_FLOW; 881 reg |= PORT_OVERRIDE_RX_FLOW; 882 } 883 884 b53_write8(dev, B53_CTRL_PAGE, off, reg); 885 886 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 887 if (port == 8) 888 off = B53_RGMII_CTRL_IMP; 889 else 890 off = B53_RGMII_CTRL_P(port); 891 892 /* Configure the port RGMII clock delay by DLL disabled and 893 * tx_clk aligned timing (restoring to reset defaults) 894 */ 895 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 896 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 897 RGMII_CTRL_TIMING_SEL); 898 899 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 900 * sure that we enable the port TX clock internal delay to 901 * account for this internal delay that is inserted, otherwise 902 * the switch won't be able to receive correctly. 903 * 904 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 905 * any delay neither on transmission nor reception, so the 906 * BCM53125 must also be configured accordingly to account for 907 * the lack of delay and introduce 908 * 909 * The BCM53125 switch has its RX clock and TX clock control 910 * swapped, hence the reason why we modify the TX clock path in 911 * the "RGMII" case 912 */ 913 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 914 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 915 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 916 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 917 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 918 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 919 920 dev_info(ds->dev, "Configured port %d for %s\n", port, 921 phy_modes(phydev->interface)); 922 } 923 924 /* configure MII port if necessary */ 925 if (is5325(dev)) { 926 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 927 ®); 928 929 /* reverse mii needs to be enabled */ 930 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 931 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 932 reg | PORT_OVERRIDE_RV_MII_25); 933 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 934 ®); 935 936 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 937 dev_err(ds->dev, 938 "Failed to enable reverse MII mode\n"); 939 return; 940 } 941 } 942 } else if (is5301x(dev)) { 943 if (port != dev->cpu_port) { 944 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port); 945 u8 gmii_po; 946 947 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po); 948 gmii_po |= GMII_PO_LINK | 949 GMII_PO_RX_FLOW | 950 GMII_PO_TX_FLOW | 951 GMII_PO_EN | 952 GMII_PO_SPEED_2000M; 953 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po); 954 } 955 } 956 } 957 958 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 959 { 960 return 0; 961 } 962 EXPORT_SYMBOL(b53_vlan_filtering); 963 964 int b53_vlan_prepare(struct dsa_switch *ds, int port, 965 const struct switchdev_obj_port_vlan *vlan, 966 struct switchdev_trans *trans) 967 { 968 struct b53_device *dev = ds->priv; 969 970 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 971 return -EOPNOTSUPP; 972 973 if (vlan->vid_end > dev->num_vlans) 974 return -ERANGE; 975 976 b53_enable_vlan(dev, true); 977 978 return 0; 979 } 980 EXPORT_SYMBOL(b53_vlan_prepare); 981 982 void b53_vlan_add(struct dsa_switch *ds, int port, 983 const struct switchdev_obj_port_vlan *vlan, 984 struct switchdev_trans *trans) 985 { 986 struct b53_device *dev = ds->priv; 987 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 988 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 989 unsigned int cpu_port = dev->cpu_port; 990 struct b53_vlan *vl; 991 u16 vid; 992 993 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 994 vl = &dev->vlans[vid]; 995 996 b53_get_vlan_entry(dev, vid, vl); 997 998 vl->members |= BIT(port) | BIT(cpu_port); 999 if (untagged) 1000 vl->untag |= BIT(port); 1001 else 1002 vl->untag &= ~BIT(port); 1003 vl->untag &= ~BIT(cpu_port); 1004 1005 b53_set_vlan_entry(dev, vid, vl); 1006 b53_fast_age_vlan(dev, vid); 1007 } 1008 1009 if (pvid) { 1010 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1011 vlan->vid_end); 1012 b53_fast_age_vlan(dev, vid); 1013 } 1014 } 1015 EXPORT_SYMBOL(b53_vlan_add); 1016 1017 int b53_vlan_del(struct dsa_switch *ds, int port, 1018 const struct switchdev_obj_port_vlan *vlan) 1019 { 1020 struct b53_device *dev = ds->priv; 1021 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1022 struct b53_vlan *vl; 1023 u16 vid; 1024 u16 pvid; 1025 1026 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1027 1028 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1029 vl = &dev->vlans[vid]; 1030 1031 b53_get_vlan_entry(dev, vid, vl); 1032 1033 vl->members &= ~BIT(port); 1034 1035 if (pvid == vid) { 1036 if (is5325(dev) || is5365(dev)) 1037 pvid = 1; 1038 else 1039 pvid = 0; 1040 } 1041 1042 if (untagged) 1043 vl->untag &= ~(BIT(port)); 1044 1045 b53_set_vlan_entry(dev, vid, vl); 1046 b53_fast_age_vlan(dev, vid); 1047 } 1048 1049 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1050 b53_fast_age_vlan(dev, pvid); 1051 1052 return 0; 1053 } 1054 EXPORT_SYMBOL(b53_vlan_del); 1055 1056 /* Address Resolution Logic routines */ 1057 static int b53_arl_op_wait(struct b53_device *dev) 1058 { 1059 unsigned int timeout = 10; 1060 u8 reg; 1061 1062 do { 1063 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1064 if (!(reg & ARLTBL_START_DONE)) 1065 return 0; 1066 1067 usleep_range(1000, 2000); 1068 } while (timeout--); 1069 1070 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1071 1072 return -ETIMEDOUT; 1073 } 1074 1075 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1076 { 1077 u8 reg; 1078 1079 if (op > ARLTBL_RW) 1080 return -EINVAL; 1081 1082 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1083 reg |= ARLTBL_START_DONE; 1084 if (op) 1085 reg |= ARLTBL_RW; 1086 else 1087 reg &= ~ARLTBL_RW; 1088 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1089 1090 return b53_arl_op_wait(dev); 1091 } 1092 1093 static int b53_arl_read(struct b53_device *dev, u64 mac, 1094 u16 vid, struct b53_arl_entry *ent, u8 *idx, 1095 bool is_valid) 1096 { 1097 unsigned int i; 1098 int ret; 1099 1100 ret = b53_arl_op_wait(dev); 1101 if (ret) 1102 return ret; 1103 1104 /* Read the bins */ 1105 for (i = 0; i < dev->num_arl_entries; i++) { 1106 u64 mac_vid; 1107 u32 fwd_entry; 1108 1109 b53_read64(dev, B53_ARLIO_PAGE, 1110 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1111 b53_read32(dev, B53_ARLIO_PAGE, 1112 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1113 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1114 1115 if (!(fwd_entry & ARLTBL_VALID)) 1116 continue; 1117 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1118 continue; 1119 *idx = i; 1120 } 1121 1122 return -ENOENT; 1123 } 1124 1125 static int b53_arl_op(struct b53_device *dev, int op, int port, 1126 const unsigned char *addr, u16 vid, bool is_valid) 1127 { 1128 struct b53_arl_entry ent; 1129 u32 fwd_entry; 1130 u64 mac, mac_vid = 0; 1131 u8 idx = 0; 1132 int ret; 1133 1134 /* Convert the array into a 64-bit MAC */ 1135 mac = ether_addr_to_u64(addr); 1136 1137 /* Perform a read for the given MAC and VID */ 1138 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1139 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1140 1141 /* Issue a read operation for this MAC */ 1142 ret = b53_arl_rw_op(dev, 1); 1143 if (ret) 1144 return ret; 1145 1146 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid); 1147 /* If this is a read, just finish now */ 1148 if (op) 1149 return ret; 1150 1151 /* We could not find a matching MAC, so reset to a new entry */ 1152 if (ret) { 1153 fwd_entry = 0; 1154 idx = 1; 1155 } 1156 1157 memset(&ent, 0, sizeof(ent)); 1158 ent.port = port; 1159 ent.is_valid = is_valid; 1160 ent.vid = vid; 1161 ent.is_static = true; 1162 memcpy(ent.mac, addr, ETH_ALEN); 1163 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1164 1165 b53_write64(dev, B53_ARLIO_PAGE, 1166 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1167 b53_write32(dev, B53_ARLIO_PAGE, 1168 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1169 1170 return b53_arl_rw_op(dev, 0); 1171 } 1172 1173 int b53_fdb_add(struct dsa_switch *ds, int port, 1174 const unsigned char *addr, u16 vid) 1175 { 1176 struct b53_device *priv = ds->priv; 1177 1178 /* 5325 and 5365 require some more massaging, but could 1179 * be supported eventually 1180 */ 1181 if (is5325(priv) || is5365(priv)) 1182 return -EOPNOTSUPP; 1183 1184 return b53_arl_op(priv, 0, port, addr, vid, true); 1185 } 1186 EXPORT_SYMBOL(b53_fdb_add); 1187 1188 int b53_fdb_del(struct dsa_switch *ds, int port, 1189 const unsigned char *addr, u16 vid) 1190 { 1191 struct b53_device *priv = ds->priv; 1192 1193 return b53_arl_op(priv, 0, port, addr, vid, false); 1194 } 1195 EXPORT_SYMBOL(b53_fdb_del); 1196 1197 static int b53_arl_search_wait(struct b53_device *dev) 1198 { 1199 unsigned int timeout = 1000; 1200 u8 reg; 1201 1202 do { 1203 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1204 if (!(reg & ARL_SRCH_STDN)) 1205 return 0; 1206 1207 if (reg & ARL_SRCH_VLID) 1208 return 0; 1209 1210 usleep_range(1000, 2000); 1211 } while (timeout--); 1212 1213 return -ETIMEDOUT; 1214 } 1215 1216 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1217 struct b53_arl_entry *ent) 1218 { 1219 u64 mac_vid; 1220 u32 fwd_entry; 1221 1222 b53_read64(dev, B53_ARLIO_PAGE, 1223 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1224 b53_read32(dev, B53_ARLIO_PAGE, 1225 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1226 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1227 } 1228 1229 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1230 dsa_fdb_dump_cb_t *cb, void *data) 1231 { 1232 if (!ent->is_valid) 1233 return 0; 1234 1235 if (port != ent->port) 1236 return 0; 1237 1238 return cb(ent->mac, ent->vid, ent->is_static, data); 1239 } 1240 1241 int b53_fdb_dump(struct dsa_switch *ds, int port, 1242 dsa_fdb_dump_cb_t *cb, void *data) 1243 { 1244 struct b53_device *priv = ds->priv; 1245 struct b53_arl_entry results[2]; 1246 unsigned int count = 0; 1247 int ret; 1248 u8 reg; 1249 1250 /* Start search operation */ 1251 reg = ARL_SRCH_STDN; 1252 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1253 1254 do { 1255 ret = b53_arl_search_wait(priv); 1256 if (ret) 1257 return ret; 1258 1259 b53_arl_search_rd(priv, 0, &results[0]); 1260 ret = b53_fdb_copy(port, &results[0], cb, data); 1261 if (ret) 1262 return ret; 1263 1264 if (priv->num_arl_entries > 2) { 1265 b53_arl_search_rd(priv, 1, &results[1]); 1266 ret = b53_fdb_copy(port, &results[1], cb, data); 1267 if (ret) 1268 return ret; 1269 1270 if (!results[0].is_valid && !results[1].is_valid) 1271 break; 1272 } 1273 1274 } while (count++ < 1024); 1275 1276 return 0; 1277 } 1278 EXPORT_SYMBOL(b53_fdb_dump); 1279 1280 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1281 { 1282 struct b53_device *dev = ds->priv; 1283 s8 cpu_port = ds->dst->cpu_dp->index; 1284 u16 pvlan, reg; 1285 unsigned int i; 1286 1287 /* Make this port leave the all VLANs join since we will have proper 1288 * VLAN entries from now on 1289 */ 1290 if (is58xx(dev)) { 1291 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1292 reg &= ~BIT(port); 1293 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1294 reg &= ~BIT(cpu_port); 1295 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1296 } 1297 1298 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1299 1300 b53_for_each_port(dev, i) { 1301 if (ds->ports[i].bridge_dev != br) 1302 continue; 1303 1304 /* Add this local port to the remote port VLAN control 1305 * membership and update the remote port bitmask 1306 */ 1307 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1308 reg |= BIT(port); 1309 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1310 dev->ports[i].vlan_ctl_mask = reg; 1311 1312 pvlan |= BIT(i); 1313 } 1314 1315 /* Configure the local port VLAN control membership to include 1316 * remote ports and update the local port bitmask 1317 */ 1318 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1319 dev->ports[port].vlan_ctl_mask = pvlan; 1320 1321 return 0; 1322 } 1323 EXPORT_SYMBOL(b53_br_join); 1324 1325 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1326 { 1327 struct b53_device *dev = ds->priv; 1328 struct b53_vlan *vl = &dev->vlans[0]; 1329 s8 cpu_port = ds->dst->cpu_dp->index; 1330 unsigned int i; 1331 u16 pvlan, reg, pvid; 1332 1333 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1334 1335 b53_for_each_port(dev, i) { 1336 /* Don't touch the remaining ports */ 1337 if (ds->ports[i].bridge_dev != br) 1338 continue; 1339 1340 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1341 reg &= ~BIT(port); 1342 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1343 dev->ports[port].vlan_ctl_mask = reg; 1344 1345 /* Prevent self removal to preserve isolation */ 1346 if (port != i) 1347 pvlan &= ~BIT(i); 1348 } 1349 1350 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1351 dev->ports[port].vlan_ctl_mask = pvlan; 1352 1353 if (is5325(dev) || is5365(dev)) 1354 pvid = 1; 1355 else 1356 pvid = 0; 1357 1358 /* Make this port join all VLANs without VLAN entries */ 1359 if (is58xx(dev)) { 1360 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1361 reg |= BIT(port); 1362 if (!(reg & BIT(cpu_port))) 1363 reg |= BIT(cpu_port); 1364 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1365 } else { 1366 b53_get_vlan_entry(dev, pvid, vl); 1367 vl->members |= BIT(port) | BIT(dev->cpu_port); 1368 vl->untag |= BIT(port) | BIT(dev->cpu_port); 1369 b53_set_vlan_entry(dev, pvid, vl); 1370 } 1371 } 1372 EXPORT_SYMBOL(b53_br_leave); 1373 1374 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1375 { 1376 struct b53_device *dev = ds->priv; 1377 u8 hw_state; 1378 u8 reg; 1379 1380 switch (state) { 1381 case BR_STATE_DISABLED: 1382 hw_state = PORT_CTRL_DIS_STATE; 1383 break; 1384 case BR_STATE_LISTENING: 1385 hw_state = PORT_CTRL_LISTEN_STATE; 1386 break; 1387 case BR_STATE_LEARNING: 1388 hw_state = PORT_CTRL_LEARN_STATE; 1389 break; 1390 case BR_STATE_FORWARDING: 1391 hw_state = PORT_CTRL_FWD_STATE; 1392 break; 1393 case BR_STATE_BLOCKING: 1394 hw_state = PORT_CTRL_BLOCK_STATE; 1395 break; 1396 default: 1397 dev_err(ds->dev, "invalid STP state: %d\n", state); 1398 return; 1399 } 1400 1401 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1402 reg &= ~PORT_CTRL_STP_STATE_MASK; 1403 reg |= hw_state; 1404 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1405 } 1406 EXPORT_SYMBOL(b53_br_set_stp_state); 1407 1408 void b53_br_fast_age(struct dsa_switch *ds, int port) 1409 { 1410 struct b53_device *dev = ds->priv; 1411 1412 if (b53_fast_age_port(dev, port)) 1413 dev_err(ds->dev, "fast ageing failed\n"); 1414 } 1415 EXPORT_SYMBOL(b53_br_fast_age); 1416 1417 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds) 1418 { 1419 return DSA_TAG_PROTO_NONE; 1420 } 1421 1422 int b53_mirror_add(struct dsa_switch *ds, int port, 1423 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1424 { 1425 struct b53_device *dev = ds->priv; 1426 u16 reg, loc; 1427 1428 if (ingress) 1429 loc = B53_IG_MIR_CTL; 1430 else 1431 loc = B53_EG_MIR_CTL; 1432 1433 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1434 reg &= ~MIRROR_MASK; 1435 reg |= BIT(port); 1436 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1437 1438 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1439 reg &= ~CAP_PORT_MASK; 1440 reg |= mirror->to_local_port; 1441 reg |= MIRROR_EN; 1442 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1443 1444 return 0; 1445 } 1446 EXPORT_SYMBOL(b53_mirror_add); 1447 1448 void b53_mirror_del(struct dsa_switch *ds, int port, 1449 struct dsa_mall_mirror_tc_entry *mirror) 1450 { 1451 struct b53_device *dev = ds->priv; 1452 bool loc_disable = false, other_loc_disable = false; 1453 u16 reg, loc; 1454 1455 if (mirror->ingress) 1456 loc = B53_IG_MIR_CTL; 1457 else 1458 loc = B53_EG_MIR_CTL; 1459 1460 /* Update the desired ingress/egress register */ 1461 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1462 reg &= ~BIT(port); 1463 if (!(reg & MIRROR_MASK)) 1464 loc_disable = true; 1465 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1466 1467 /* Now look at the other one to know if we can disable mirroring 1468 * entirely 1469 */ 1470 if (mirror->ingress) 1471 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 1472 else 1473 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 1474 if (!(reg & MIRROR_MASK)) 1475 other_loc_disable = true; 1476 1477 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1478 /* Both no longer have ports, let's disable mirroring */ 1479 if (loc_disable && other_loc_disable) { 1480 reg &= ~MIRROR_EN; 1481 reg &= ~mirror->to_local_port; 1482 } 1483 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1484 } 1485 EXPORT_SYMBOL(b53_mirror_del); 1486 1487 static const struct dsa_switch_ops b53_switch_ops = { 1488 .get_tag_protocol = b53_get_tag_protocol, 1489 .setup = b53_setup, 1490 .get_strings = b53_get_strings, 1491 .get_ethtool_stats = b53_get_ethtool_stats, 1492 .get_sset_count = b53_get_sset_count, 1493 .phy_read = b53_phy_read16, 1494 .phy_write = b53_phy_write16, 1495 .adjust_link = b53_adjust_link, 1496 .port_enable = b53_enable_port, 1497 .port_disable = b53_disable_port, 1498 .port_bridge_join = b53_br_join, 1499 .port_bridge_leave = b53_br_leave, 1500 .port_stp_state_set = b53_br_set_stp_state, 1501 .port_fast_age = b53_br_fast_age, 1502 .port_vlan_filtering = b53_vlan_filtering, 1503 .port_vlan_prepare = b53_vlan_prepare, 1504 .port_vlan_add = b53_vlan_add, 1505 .port_vlan_del = b53_vlan_del, 1506 .port_fdb_dump = b53_fdb_dump, 1507 .port_fdb_add = b53_fdb_add, 1508 .port_fdb_del = b53_fdb_del, 1509 .port_mirror_add = b53_mirror_add, 1510 .port_mirror_del = b53_mirror_del, 1511 }; 1512 1513 struct b53_chip_data { 1514 u32 chip_id; 1515 const char *dev_name; 1516 u16 vlans; 1517 u16 enabled_ports; 1518 u8 cpu_port; 1519 u8 vta_regs[3]; 1520 u8 arl_entries; 1521 u8 duplex_reg; 1522 u8 jumbo_pm_reg; 1523 u8 jumbo_size_reg; 1524 }; 1525 1526 #define B53_VTA_REGS \ 1527 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 1528 #define B53_VTA_REGS_9798 \ 1529 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 1530 #define B53_VTA_REGS_63XX \ 1531 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 1532 1533 static const struct b53_chip_data b53_switch_chips[] = { 1534 { 1535 .chip_id = BCM5325_DEVICE_ID, 1536 .dev_name = "BCM5325", 1537 .vlans = 16, 1538 .enabled_ports = 0x1f, 1539 .arl_entries = 2, 1540 .cpu_port = B53_CPU_PORT_25, 1541 .duplex_reg = B53_DUPLEX_STAT_FE, 1542 }, 1543 { 1544 .chip_id = BCM5365_DEVICE_ID, 1545 .dev_name = "BCM5365", 1546 .vlans = 256, 1547 .enabled_ports = 0x1f, 1548 .arl_entries = 2, 1549 .cpu_port = B53_CPU_PORT_25, 1550 .duplex_reg = B53_DUPLEX_STAT_FE, 1551 }, 1552 { 1553 .chip_id = BCM5395_DEVICE_ID, 1554 .dev_name = "BCM5395", 1555 .vlans = 4096, 1556 .enabled_ports = 0x1f, 1557 .arl_entries = 4, 1558 .cpu_port = B53_CPU_PORT, 1559 .vta_regs = B53_VTA_REGS, 1560 .duplex_reg = B53_DUPLEX_STAT_GE, 1561 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1562 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1563 }, 1564 { 1565 .chip_id = BCM5397_DEVICE_ID, 1566 .dev_name = "BCM5397", 1567 .vlans = 4096, 1568 .enabled_ports = 0x1f, 1569 .arl_entries = 4, 1570 .cpu_port = B53_CPU_PORT, 1571 .vta_regs = B53_VTA_REGS_9798, 1572 .duplex_reg = B53_DUPLEX_STAT_GE, 1573 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1574 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1575 }, 1576 { 1577 .chip_id = BCM5398_DEVICE_ID, 1578 .dev_name = "BCM5398", 1579 .vlans = 4096, 1580 .enabled_ports = 0x7f, 1581 .arl_entries = 4, 1582 .cpu_port = B53_CPU_PORT, 1583 .vta_regs = B53_VTA_REGS_9798, 1584 .duplex_reg = B53_DUPLEX_STAT_GE, 1585 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1586 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1587 }, 1588 { 1589 .chip_id = BCM53115_DEVICE_ID, 1590 .dev_name = "BCM53115", 1591 .vlans = 4096, 1592 .enabled_ports = 0x1f, 1593 .arl_entries = 4, 1594 .vta_regs = B53_VTA_REGS, 1595 .cpu_port = B53_CPU_PORT, 1596 .duplex_reg = B53_DUPLEX_STAT_GE, 1597 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1598 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1599 }, 1600 { 1601 .chip_id = BCM53125_DEVICE_ID, 1602 .dev_name = "BCM53125", 1603 .vlans = 4096, 1604 .enabled_ports = 0xff, 1605 .arl_entries = 4, 1606 .cpu_port = B53_CPU_PORT, 1607 .vta_regs = B53_VTA_REGS, 1608 .duplex_reg = B53_DUPLEX_STAT_GE, 1609 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1610 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1611 }, 1612 { 1613 .chip_id = BCM53128_DEVICE_ID, 1614 .dev_name = "BCM53128", 1615 .vlans = 4096, 1616 .enabled_ports = 0x1ff, 1617 .arl_entries = 4, 1618 .cpu_port = B53_CPU_PORT, 1619 .vta_regs = B53_VTA_REGS, 1620 .duplex_reg = B53_DUPLEX_STAT_GE, 1621 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1622 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1623 }, 1624 { 1625 .chip_id = BCM63XX_DEVICE_ID, 1626 .dev_name = "BCM63xx", 1627 .vlans = 4096, 1628 .enabled_ports = 0, /* pdata must provide them */ 1629 .arl_entries = 4, 1630 .cpu_port = B53_CPU_PORT, 1631 .vta_regs = B53_VTA_REGS_63XX, 1632 .duplex_reg = B53_DUPLEX_STAT_63XX, 1633 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 1634 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 1635 }, 1636 { 1637 .chip_id = BCM53010_DEVICE_ID, 1638 .dev_name = "BCM53010", 1639 .vlans = 4096, 1640 .enabled_ports = 0x1f, 1641 .arl_entries = 4, 1642 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1643 .vta_regs = B53_VTA_REGS, 1644 .duplex_reg = B53_DUPLEX_STAT_GE, 1645 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1646 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1647 }, 1648 { 1649 .chip_id = BCM53011_DEVICE_ID, 1650 .dev_name = "BCM53011", 1651 .vlans = 4096, 1652 .enabled_ports = 0x1bf, 1653 .arl_entries = 4, 1654 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1655 .vta_regs = B53_VTA_REGS, 1656 .duplex_reg = B53_DUPLEX_STAT_GE, 1657 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1658 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1659 }, 1660 { 1661 .chip_id = BCM53012_DEVICE_ID, 1662 .dev_name = "BCM53012", 1663 .vlans = 4096, 1664 .enabled_ports = 0x1bf, 1665 .arl_entries = 4, 1666 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1667 .vta_regs = B53_VTA_REGS, 1668 .duplex_reg = B53_DUPLEX_STAT_GE, 1669 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1670 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1671 }, 1672 { 1673 .chip_id = BCM53018_DEVICE_ID, 1674 .dev_name = "BCM53018", 1675 .vlans = 4096, 1676 .enabled_ports = 0x1f, 1677 .arl_entries = 4, 1678 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1679 .vta_regs = B53_VTA_REGS, 1680 .duplex_reg = B53_DUPLEX_STAT_GE, 1681 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1682 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1683 }, 1684 { 1685 .chip_id = BCM53019_DEVICE_ID, 1686 .dev_name = "BCM53019", 1687 .vlans = 4096, 1688 .enabled_ports = 0x1f, 1689 .arl_entries = 4, 1690 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1691 .vta_regs = B53_VTA_REGS, 1692 .duplex_reg = B53_DUPLEX_STAT_GE, 1693 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1694 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1695 }, 1696 { 1697 .chip_id = BCM58XX_DEVICE_ID, 1698 .dev_name = "BCM585xx/586xx/88312", 1699 .vlans = 4096, 1700 .enabled_ports = 0x1ff, 1701 .arl_entries = 4, 1702 .cpu_port = B53_CPU_PORT, 1703 .vta_regs = B53_VTA_REGS, 1704 .duplex_reg = B53_DUPLEX_STAT_GE, 1705 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1706 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1707 }, 1708 { 1709 .chip_id = BCM7445_DEVICE_ID, 1710 .dev_name = "BCM7445", 1711 .vlans = 4096, 1712 .enabled_ports = 0x1ff, 1713 .arl_entries = 4, 1714 .cpu_port = B53_CPU_PORT, 1715 .vta_regs = B53_VTA_REGS, 1716 .duplex_reg = B53_DUPLEX_STAT_GE, 1717 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1718 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1719 }, 1720 { 1721 .chip_id = BCM7278_DEVICE_ID, 1722 .dev_name = "BCM7278", 1723 .vlans = 4096, 1724 .enabled_ports = 0x1ff, 1725 .arl_entries= 4, 1726 .cpu_port = B53_CPU_PORT, 1727 .vta_regs = B53_VTA_REGS, 1728 .duplex_reg = B53_DUPLEX_STAT_GE, 1729 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1730 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1731 }, 1732 }; 1733 1734 static int b53_switch_init(struct b53_device *dev) 1735 { 1736 unsigned int i; 1737 int ret; 1738 1739 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 1740 const struct b53_chip_data *chip = &b53_switch_chips[i]; 1741 1742 if (chip->chip_id == dev->chip_id) { 1743 if (!dev->enabled_ports) 1744 dev->enabled_ports = chip->enabled_ports; 1745 dev->name = chip->dev_name; 1746 dev->duplex_reg = chip->duplex_reg; 1747 dev->vta_regs[0] = chip->vta_regs[0]; 1748 dev->vta_regs[1] = chip->vta_regs[1]; 1749 dev->vta_regs[2] = chip->vta_regs[2]; 1750 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 1751 dev->cpu_port = chip->cpu_port; 1752 dev->num_vlans = chip->vlans; 1753 dev->num_arl_entries = chip->arl_entries; 1754 break; 1755 } 1756 } 1757 1758 /* check which BCM5325x version we have */ 1759 if (is5325(dev)) { 1760 u8 vc4; 1761 1762 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 1763 1764 /* check reserved bits */ 1765 switch (vc4 & 3) { 1766 case 1: 1767 /* BCM5325E */ 1768 break; 1769 case 3: 1770 /* BCM5325F - do not use port 4 */ 1771 dev->enabled_ports &= ~BIT(4); 1772 break; 1773 default: 1774 /* On the BCM47XX SoCs this is the supported internal switch.*/ 1775 #ifndef CONFIG_BCM47XX 1776 /* BCM5325M */ 1777 return -EINVAL; 1778 #else 1779 break; 1780 #endif 1781 } 1782 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 1783 u64 strap_value; 1784 1785 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 1786 /* use second IMP port if GMII is enabled */ 1787 if (strap_value & SV_GMII_CTRL_115) 1788 dev->cpu_port = 5; 1789 } 1790 1791 /* cpu port is always last */ 1792 dev->num_ports = dev->cpu_port + 1; 1793 dev->enabled_ports |= BIT(dev->cpu_port); 1794 1795 dev->ports = devm_kzalloc(dev->dev, 1796 sizeof(struct b53_port) * dev->num_ports, 1797 GFP_KERNEL); 1798 if (!dev->ports) 1799 return -ENOMEM; 1800 1801 dev->vlans = devm_kzalloc(dev->dev, 1802 sizeof(struct b53_vlan) * dev->num_vlans, 1803 GFP_KERNEL); 1804 if (!dev->vlans) 1805 return -ENOMEM; 1806 1807 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 1808 if (dev->reset_gpio >= 0) { 1809 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 1810 GPIOF_OUT_INIT_HIGH, "robo_reset"); 1811 if (ret) 1812 return ret; 1813 } 1814 1815 return 0; 1816 } 1817 1818 struct b53_device *b53_switch_alloc(struct device *base, 1819 const struct b53_io_ops *ops, 1820 void *priv) 1821 { 1822 struct dsa_switch *ds; 1823 struct b53_device *dev; 1824 1825 ds = dsa_switch_alloc(base, DSA_MAX_PORTS); 1826 if (!ds) 1827 return NULL; 1828 1829 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 1830 if (!dev) 1831 return NULL; 1832 1833 ds->priv = dev; 1834 dev->dev = base; 1835 1836 dev->ds = ds; 1837 dev->priv = priv; 1838 dev->ops = ops; 1839 ds->ops = &b53_switch_ops; 1840 mutex_init(&dev->reg_mutex); 1841 mutex_init(&dev->stats_mutex); 1842 1843 return dev; 1844 } 1845 EXPORT_SYMBOL(b53_switch_alloc); 1846 1847 int b53_switch_detect(struct b53_device *dev) 1848 { 1849 u32 id32; 1850 u16 tmp; 1851 u8 id8; 1852 int ret; 1853 1854 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 1855 if (ret) 1856 return ret; 1857 1858 switch (id8) { 1859 case 0: 1860 /* BCM5325 and BCM5365 do not have this register so reads 1861 * return 0. But the read operation did succeed, so assume this 1862 * is one of them. 1863 * 1864 * Next check if we can write to the 5325's VTA register; for 1865 * 5365 it is read only. 1866 */ 1867 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 1868 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 1869 1870 if (tmp == 0xf) 1871 dev->chip_id = BCM5325_DEVICE_ID; 1872 else 1873 dev->chip_id = BCM5365_DEVICE_ID; 1874 break; 1875 case BCM5395_DEVICE_ID: 1876 case BCM5397_DEVICE_ID: 1877 case BCM5398_DEVICE_ID: 1878 dev->chip_id = id8; 1879 break; 1880 default: 1881 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 1882 if (ret) 1883 return ret; 1884 1885 switch (id32) { 1886 case BCM53115_DEVICE_ID: 1887 case BCM53125_DEVICE_ID: 1888 case BCM53128_DEVICE_ID: 1889 case BCM53010_DEVICE_ID: 1890 case BCM53011_DEVICE_ID: 1891 case BCM53012_DEVICE_ID: 1892 case BCM53018_DEVICE_ID: 1893 case BCM53019_DEVICE_ID: 1894 dev->chip_id = id32; 1895 break; 1896 default: 1897 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 1898 id8, id32); 1899 return -ENODEV; 1900 } 1901 } 1902 1903 if (dev->chip_id == BCM5325_DEVICE_ID) 1904 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 1905 &dev->core_rev); 1906 else 1907 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 1908 &dev->core_rev); 1909 } 1910 EXPORT_SYMBOL(b53_switch_detect); 1911 1912 int b53_switch_register(struct b53_device *dev) 1913 { 1914 int ret; 1915 1916 if (dev->pdata) { 1917 dev->chip_id = dev->pdata->chip_id; 1918 dev->enabled_ports = dev->pdata->enabled_ports; 1919 } 1920 1921 if (!dev->chip_id && b53_switch_detect(dev)) 1922 return -EINVAL; 1923 1924 ret = b53_switch_init(dev); 1925 if (ret) 1926 return ret; 1927 1928 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 1929 1930 return dsa_register_switch(dev->ds); 1931 } 1932 EXPORT_SYMBOL(b53_switch_register); 1933 1934 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 1935 MODULE_DESCRIPTION("B53 switch library"); 1936 MODULE_LICENSE("Dual BSD/GPL"); 1937