1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/etherdevice.h> 30 #include <linux/if_bridge.h> 31 #include <net/dsa.h> 32 33 #include "b53_regs.h" 34 #include "b53_priv.h" 35 36 struct b53_mib_desc { 37 u8 size; 38 u8 offset; 39 const char *name; 40 }; 41 42 /* BCM5365 MIB counters */ 43 static const struct b53_mib_desc b53_mibs_65[] = { 44 { 8, 0x00, "TxOctets" }, 45 { 4, 0x08, "TxDropPkts" }, 46 { 4, 0x10, "TxBroadcastPkts" }, 47 { 4, 0x14, "TxMulticastPkts" }, 48 { 4, 0x18, "TxUnicastPkts" }, 49 { 4, 0x1c, "TxCollisions" }, 50 { 4, 0x20, "TxSingleCollision" }, 51 { 4, 0x24, "TxMultipleCollision" }, 52 { 4, 0x28, "TxDeferredTransmit" }, 53 { 4, 0x2c, "TxLateCollision" }, 54 { 4, 0x30, "TxExcessiveCollision" }, 55 { 4, 0x38, "TxPausePkts" }, 56 { 8, 0x44, "RxOctets" }, 57 { 4, 0x4c, "RxUndersizePkts" }, 58 { 4, 0x50, "RxPausePkts" }, 59 { 4, 0x54, "Pkts64Octets" }, 60 { 4, 0x58, "Pkts65to127Octets" }, 61 { 4, 0x5c, "Pkts128to255Octets" }, 62 { 4, 0x60, "Pkts256to511Octets" }, 63 { 4, 0x64, "Pkts512to1023Octets" }, 64 { 4, 0x68, "Pkts1024to1522Octets" }, 65 { 4, 0x6c, "RxOversizePkts" }, 66 { 4, 0x70, "RxJabbers" }, 67 { 4, 0x74, "RxAlignmentErrors" }, 68 { 4, 0x78, "RxFCSErrors" }, 69 { 8, 0x7c, "RxGoodOctets" }, 70 { 4, 0x84, "RxDropPkts" }, 71 { 4, 0x88, "RxUnicastPkts" }, 72 { 4, 0x8c, "RxMulticastPkts" }, 73 { 4, 0x90, "RxBroadcastPkts" }, 74 { 4, 0x94, "RxSAChanges" }, 75 { 4, 0x98, "RxFragments" }, 76 }; 77 78 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 79 80 /* BCM63xx MIB counters */ 81 static const struct b53_mib_desc b53_mibs_63xx[] = { 82 { 8, 0x00, "TxOctets" }, 83 { 4, 0x08, "TxDropPkts" }, 84 { 4, 0x0c, "TxQoSPkts" }, 85 { 4, 0x10, "TxBroadcastPkts" }, 86 { 4, 0x14, "TxMulticastPkts" }, 87 { 4, 0x18, "TxUnicastPkts" }, 88 { 4, 0x1c, "TxCollisions" }, 89 { 4, 0x20, "TxSingleCollision" }, 90 { 4, 0x24, "TxMultipleCollision" }, 91 { 4, 0x28, "TxDeferredTransmit" }, 92 { 4, 0x2c, "TxLateCollision" }, 93 { 4, 0x30, "TxExcessiveCollision" }, 94 { 4, 0x38, "TxPausePkts" }, 95 { 8, 0x3c, "TxQoSOctets" }, 96 { 8, 0x44, "RxOctets" }, 97 { 4, 0x4c, "RxUndersizePkts" }, 98 { 4, 0x50, "RxPausePkts" }, 99 { 4, 0x54, "Pkts64Octets" }, 100 { 4, 0x58, "Pkts65to127Octets" }, 101 { 4, 0x5c, "Pkts128to255Octets" }, 102 { 4, 0x60, "Pkts256to511Octets" }, 103 { 4, 0x64, "Pkts512to1023Octets" }, 104 { 4, 0x68, "Pkts1024to1522Octets" }, 105 { 4, 0x6c, "RxOversizePkts" }, 106 { 4, 0x70, "RxJabbers" }, 107 { 4, 0x74, "RxAlignmentErrors" }, 108 { 4, 0x78, "RxFCSErrors" }, 109 { 8, 0x7c, "RxGoodOctets" }, 110 { 4, 0x84, "RxDropPkts" }, 111 { 4, 0x88, "RxUnicastPkts" }, 112 { 4, 0x8c, "RxMulticastPkts" }, 113 { 4, 0x90, "RxBroadcastPkts" }, 114 { 4, 0x94, "RxSAChanges" }, 115 { 4, 0x98, "RxFragments" }, 116 { 4, 0xa0, "RxSymbolErrors" }, 117 { 4, 0xa4, "RxQoSPkts" }, 118 { 8, 0xa8, "RxQoSOctets" }, 119 { 4, 0xb0, "Pkts1523to2047Octets" }, 120 { 4, 0xb4, "Pkts2048to4095Octets" }, 121 { 4, 0xb8, "Pkts4096to8191Octets" }, 122 { 4, 0xbc, "Pkts8192to9728Octets" }, 123 { 4, 0xc0, "RxDiscarded" }, 124 }; 125 126 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 127 128 /* MIB counters */ 129 static const struct b53_mib_desc b53_mibs[] = { 130 { 8, 0x00, "TxOctets" }, 131 { 4, 0x08, "TxDropPkts" }, 132 { 4, 0x10, "TxBroadcastPkts" }, 133 { 4, 0x14, "TxMulticastPkts" }, 134 { 4, 0x18, "TxUnicastPkts" }, 135 { 4, 0x1c, "TxCollisions" }, 136 { 4, 0x20, "TxSingleCollision" }, 137 { 4, 0x24, "TxMultipleCollision" }, 138 { 4, 0x28, "TxDeferredTransmit" }, 139 { 4, 0x2c, "TxLateCollision" }, 140 { 4, 0x30, "TxExcessiveCollision" }, 141 { 4, 0x38, "TxPausePkts" }, 142 { 8, 0x50, "RxOctets" }, 143 { 4, 0x58, "RxUndersizePkts" }, 144 { 4, 0x5c, "RxPausePkts" }, 145 { 4, 0x60, "Pkts64Octets" }, 146 { 4, 0x64, "Pkts65to127Octets" }, 147 { 4, 0x68, "Pkts128to255Octets" }, 148 { 4, 0x6c, "Pkts256to511Octets" }, 149 { 4, 0x70, "Pkts512to1023Octets" }, 150 { 4, 0x74, "Pkts1024to1522Octets" }, 151 { 4, 0x78, "RxOversizePkts" }, 152 { 4, 0x7c, "RxJabbers" }, 153 { 4, 0x80, "RxAlignmentErrors" }, 154 { 4, 0x84, "RxFCSErrors" }, 155 { 8, 0x88, "RxGoodOctets" }, 156 { 4, 0x90, "RxDropPkts" }, 157 { 4, 0x94, "RxUnicastPkts" }, 158 { 4, 0x98, "RxMulticastPkts" }, 159 { 4, 0x9c, "RxBroadcastPkts" }, 160 { 4, 0xa0, "RxSAChanges" }, 161 { 4, 0xa4, "RxFragments" }, 162 { 4, 0xa8, "RxJumboPkts" }, 163 { 4, 0xac, "RxSymbolErrors" }, 164 { 4, 0xc0, "RxDiscarded" }, 165 }; 166 167 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 168 169 static const struct b53_mib_desc b53_mibs_58xx[] = { 170 { 8, 0x00, "TxOctets" }, 171 { 4, 0x08, "TxDropPkts" }, 172 { 4, 0x0c, "TxQPKTQ0" }, 173 { 4, 0x10, "TxBroadcastPkts" }, 174 { 4, 0x14, "TxMulticastPkts" }, 175 { 4, 0x18, "TxUnicastPKts" }, 176 { 4, 0x1c, "TxCollisions" }, 177 { 4, 0x20, "TxSingleCollision" }, 178 { 4, 0x24, "TxMultipleCollision" }, 179 { 4, 0x28, "TxDeferredCollision" }, 180 { 4, 0x2c, "TxLateCollision" }, 181 { 4, 0x30, "TxExcessiveCollision" }, 182 { 4, 0x34, "TxFrameInDisc" }, 183 { 4, 0x38, "TxPausePkts" }, 184 { 4, 0x3c, "TxQPKTQ1" }, 185 { 4, 0x40, "TxQPKTQ2" }, 186 { 4, 0x44, "TxQPKTQ3" }, 187 { 4, 0x48, "TxQPKTQ4" }, 188 { 4, 0x4c, "TxQPKTQ5" }, 189 { 8, 0x50, "RxOctets" }, 190 { 4, 0x58, "RxUndersizePkts" }, 191 { 4, 0x5c, "RxPausePkts" }, 192 { 4, 0x60, "RxPkts64Octets" }, 193 { 4, 0x64, "RxPkts65to127Octets" }, 194 { 4, 0x68, "RxPkts128to255Octets" }, 195 { 4, 0x6c, "RxPkts256to511Octets" }, 196 { 4, 0x70, "RxPkts512to1023Octets" }, 197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 198 { 4, 0x78, "RxOversizePkts" }, 199 { 4, 0x7c, "RxJabbers" }, 200 { 4, 0x80, "RxAlignmentErrors" }, 201 { 4, 0x84, "RxFCSErrors" }, 202 { 8, 0x88, "RxGoodOctets" }, 203 { 4, 0x90, "RxDropPkts" }, 204 { 4, 0x94, "RxUnicastPkts" }, 205 { 4, 0x98, "RxMulticastPkts" }, 206 { 4, 0x9c, "RxBroadcastPkts" }, 207 { 4, 0xa0, "RxSAChanges" }, 208 { 4, 0xa4, "RxFragments" }, 209 { 4, 0xa8, "RxJumboPkt" }, 210 { 4, 0xac, "RxSymblErr" }, 211 { 4, 0xb0, "InRangeErrCount" }, 212 { 4, 0xb4, "OutRangeErrCount" }, 213 { 4, 0xb8, "EEELpiEvent" }, 214 { 4, 0xbc, "EEELpiDuration" }, 215 { 4, 0xc0, "RxDiscard" }, 216 { 4, 0xc8, "TxQPKTQ6" }, 217 { 4, 0xcc, "TxQPKTQ7" }, 218 { 4, 0xd0, "TxPkts64Octets" }, 219 { 4, 0xd4, "TxPkts65to127Octets" }, 220 { 4, 0xd8, "TxPkts128to255Octets" }, 221 { 4, 0xdc, "TxPkts256to511Ocets" }, 222 { 4, 0xe0, "TxPkts512to1023Ocets" }, 223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 224 }; 225 226 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 227 228 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 229 { 230 unsigned int i; 231 232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 233 234 for (i = 0; i < 10; i++) { 235 u8 vta; 236 237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 238 if (!(vta & VTA_START_CMD)) 239 return 0; 240 241 usleep_range(100, 200); 242 } 243 244 return -EIO; 245 } 246 247 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 248 struct b53_vlan *vlan) 249 { 250 if (is5325(dev)) { 251 u32 entry = 0; 252 253 if (vlan->members) { 254 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 255 VA_UNTAG_S_25) | vlan->members; 256 if (dev->core_rev >= 3) 257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 258 else 259 entry |= VA_VALID_25; 260 } 261 262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 264 VTA_RW_STATE_WR | VTA_RW_OP_EN); 265 } else if (is5365(dev)) { 266 u16 entry = 0; 267 268 if (vlan->members) 269 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 271 272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 274 VTA_RW_STATE_WR | VTA_RW_OP_EN); 275 } else { 276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 278 (vlan->untag << VTE_UNTAG_S) | vlan->members); 279 280 b53_do_vlan_op(dev, VTA_CMD_WRITE); 281 } 282 283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 284 vid, vlan->members, vlan->untag); 285 } 286 287 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 288 struct b53_vlan *vlan) 289 { 290 if (is5325(dev)) { 291 u32 entry = 0; 292 293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 294 VTA_RW_STATE_RD | VTA_RW_OP_EN); 295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 296 297 if (dev->core_rev >= 3) 298 vlan->valid = !!(entry & VA_VALID_25_R4); 299 else 300 vlan->valid = !!(entry & VA_VALID_25); 301 vlan->members = entry & VA_MEMBER_MASK; 302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 303 304 } else if (is5365(dev)) { 305 u16 entry = 0; 306 307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 308 VTA_RW_STATE_WR | VTA_RW_OP_EN); 309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 310 311 vlan->valid = !!(entry & VA_VALID_65); 312 vlan->members = entry & VA_MEMBER_MASK; 313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 314 } else { 315 u32 entry = 0; 316 317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 318 b53_do_vlan_op(dev, VTA_CMD_READ); 319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 320 vlan->members = entry & VTE_MEMBERS; 321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 322 vlan->valid = true; 323 } 324 } 325 326 static void b53_set_forwarding(struct b53_device *dev, int enable) 327 { 328 struct dsa_switch *ds = dev->ds; 329 u8 mgmt; 330 331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 332 333 if (enable) 334 mgmt |= SM_SW_FWD_EN; 335 else 336 mgmt &= ~SM_SW_FWD_EN; 337 338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 339 340 /* Include IMP port in dumb forwarding mode when no tagging protocol is 341 * set 342 */ 343 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) { 344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 345 mgmt |= B53_MII_DUMB_FWDG_EN; 346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 347 } 348 } 349 350 static void b53_enable_vlan(struct b53_device *dev, bool enable) 351 { 352 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 353 354 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 357 358 if (is5325(dev) || is5365(dev)) { 359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 361 } else if (is63xx(dev)) { 362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 364 } else { 365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 367 } 368 369 mgmt &= ~SM_SW_FWD_MODE; 370 371 if (enable) { 372 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 373 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 374 vc4 &= ~VC4_ING_VID_CHECK_MASK; 375 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 376 vc5 |= VC5_DROP_VTABLE_MISS; 377 378 if (is5325(dev)) 379 vc0 &= ~VC0_RESERVED_1; 380 381 if (is5325(dev) || is5365(dev)) 382 vc1 |= VC1_RX_MCST_TAG_EN; 383 384 } else { 385 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 386 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 387 vc4 &= ~VC4_ING_VID_CHECK_MASK; 388 vc5 &= ~VC5_DROP_VTABLE_MISS; 389 390 if (is5325(dev) || is5365(dev)) 391 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 392 else 393 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 394 395 if (is5325(dev) || is5365(dev)) 396 vc1 &= ~VC1_RX_MCST_TAG_EN; 397 } 398 399 if (!is5325(dev) && !is5365(dev)) 400 vc5 &= ~VC5_VID_FFF_EN; 401 402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 404 405 if (is5325(dev) || is5365(dev)) { 406 /* enable the high 8 bit vid check on 5325 */ 407 if (is5325(dev) && enable) 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 409 VC3_HIGH_8BIT_EN); 410 else 411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 412 413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 415 } else if (is63xx(dev)) { 416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 419 } else { 420 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 423 } 424 425 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 426 } 427 428 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 429 { 430 u32 port_mask = 0; 431 u16 max_size = JMS_MIN_SIZE; 432 433 if (is5325(dev) || is5365(dev)) 434 return -EINVAL; 435 436 if (enable) { 437 port_mask = dev->enabled_ports; 438 max_size = JMS_MAX_SIZE; 439 if (allow_10_100) 440 port_mask |= JPM_10_100_JUMBO_EN; 441 } 442 443 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 444 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 445 } 446 447 static int b53_flush_arl(struct b53_device *dev, u8 mask) 448 { 449 unsigned int i; 450 451 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 452 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 453 454 for (i = 0; i < 10; i++) { 455 u8 fast_age_ctrl; 456 457 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 458 &fast_age_ctrl); 459 460 if (!(fast_age_ctrl & FAST_AGE_DONE)) 461 goto out; 462 463 msleep(1); 464 } 465 466 return -ETIMEDOUT; 467 out: 468 /* Only age dynamic entries (default behavior) */ 469 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 470 return 0; 471 } 472 473 static int b53_fast_age_port(struct b53_device *dev, int port) 474 { 475 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 476 477 return b53_flush_arl(dev, FAST_AGE_PORT); 478 } 479 480 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 481 { 482 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 483 484 return b53_flush_arl(dev, FAST_AGE_VLAN); 485 } 486 487 static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 488 { 489 struct b53_device *dev = ds->priv; 490 unsigned int i; 491 u16 pvlan; 492 493 /* Enable the IMP port to be in the same VLAN as the other ports 494 * on a per-port basis such that we only have Port i and IMP in 495 * the same VLAN. 496 */ 497 b53_for_each_port(dev, i) { 498 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 499 pvlan |= BIT(cpu_port); 500 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 501 } 502 } 503 504 static int b53_enable_port(struct dsa_switch *ds, int port, 505 struct phy_device *phy) 506 { 507 struct b53_device *dev = ds->priv; 508 unsigned int cpu_port = dev->cpu_port; 509 u16 pvlan; 510 511 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 512 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 513 514 /* Set this port, and only this one to be in the default VLAN, 515 * if member of a bridge, restore its membership prior to 516 * bringing down this port. 517 */ 518 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 519 pvlan &= ~0x1ff; 520 pvlan |= BIT(port); 521 pvlan |= dev->ports[port].vlan_ctl_mask; 522 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 523 524 b53_imp_vlan_setup(ds, cpu_port); 525 526 return 0; 527 } 528 529 static void b53_disable_port(struct dsa_switch *ds, int port, 530 struct phy_device *phy) 531 { 532 struct b53_device *dev = ds->priv; 533 u8 reg; 534 535 /* Disable Tx/Rx for the port */ 536 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 537 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 538 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 539 } 540 541 static void b53_enable_cpu_port(struct b53_device *dev) 542 { 543 unsigned int cpu_port = dev->cpu_port; 544 u8 port_ctrl; 545 546 /* BCM5325 CPU port is at 8 */ 547 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25) 548 cpu_port = B53_CPU_PORT; 549 550 port_ctrl = PORT_CTRL_RX_BCST_EN | 551 PORT_CTRL_RX_MCST_EN | 552 PORT_CTRL_RX_UCST_EN; 553 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl); 554 } 555 556 static void b53_enable_mib(struct b53_device *dev) 557 { 558 u8 gc; 559 560 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 561 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 562 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 563 } 564 565 static int b53_configure_vlan(struct b53_device *dev) 566 { 567 struct b53_vlan vl = { 0 }; 568 int i; 569 570 /* clear all vlan entries */ 571 if (is5325(dev) || is5365(dev)) { 572 for (i = 1; i < dev->num_vlans; i++) 573 b53_set_vlan_entry(dev, i, &vl); 574 } else { 575 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 576 } 577 578 b53_enable_vlan(dev, false); 579 580 b53_for_each_port(dev, i) 581 b53_write16(dev, B53_VLAN_PAGE, 582 B53_VLAN_PORT_DEF_TAG(i), 1); 583 584 if (!is5325(dev) && !is5365(dev)) 585 b53_set_jumbo(dev, dev->enable_jumbo, false); 586 587 return 0; 588 } 589 590 static void b53_switch_reset_gpio(struct b53_device *dev) 591 { 592 int gpio = dev->reset_gpio; 593 594 if (gpio < 0) 595 return; 596 597 /* Reset sequence: RESET low(50ms)->high(20ms) 598 */ 599 gpio_set_value(gpio, 0); 600 mdelay(50); 601 602 gpio_set_value(gpio, 1); 603 mdelay(20); 604 605 dev->current_page = 0xff; 606 } 607 608 static int b53_switch_reset(struct b53_device *dev) 609 { 610 unsigned int timeout = 1000; 611 u8 mgmt, reg; 612 613 b53_switch_reset_gpio(dev); 614 615 if (is539x(dev)) { 616 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 617 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 618 } 619 620 /* This is specific to 58xx devices here, do not use is58xx() which 621 * covers the larger Starfigther 2 family, including 7445/7278 which 622 * still use this driver as a library and need to perform the reset 623 * earlier. 624 */ 625 if (dev->chip_id == BCM58XX_DEVICE_ID) { 626 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 627 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 628 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 629 630 do { 631 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 632 if (!(reg & SW_RST)) 633 break; 634 635 usleep_range(1000, 2000); 636 } while (timeout-- > 0); 637 638 if (timeout == 0) 639 return -ETIMEDOUT; 640 } 641 642 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 643 644 if (!(mgmt & SM_SW_FWD_EN)) { 645 mgmt &= ~SM_SW_FWD_MODE; 646 mgmt |= SM_SW_FWD_EN; 647 648 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 649 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 650 651 if (!(mgmt & SM_SW_FWD_EN)) { 652 dev_err(dev->dev, "Failed to enable switch!\n"); 653 return -EINVAL; 654 } 655 } 656 657 b53_enable_mib(dev); 658 659 return b53_flush_arl(dev, FAST_AGE_STATIC); 660 } 661 662 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 663 { 664 struct b53_device *priv = ds->priv; 665 u16 value = 0; 666 int ret; 667 668 if (priv->ops->phy_read16) 669 ret = priv->ops->phy_read16(priv, addr, reg, &value); 670 else 671 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 672 reg * 2, &value); 673 674 return ret ? ret : value; 675 } 676 677 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 678 { 679 struct b53_device *priv = ds->priv; 680 681 if (priv->ops->phy_write16) 682 return priv->ops->phy_write16(priv, addr, reg, val); 683 684 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 685 } 686 687 static int b53_reset_switch(struct b53_device *priv) 688 { 689 /* reset vlans */ 690 priv->enable_jumbo = false; 691 692 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 693 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 694 695 return b53_switch_reset(priv); 696 } 697 698 static int b53_apply_config(struct b53_device *priv) 699 { 700 /* disable switching */ 701 b53_set_forwarding(priv, 0); 702 703 b53_configure_vlan(priv); 704 705 /* enable switching */ 706 b53_set_forwarding(priv, 1); 707 708 return 0; 709 } 710 711 static void b53_reset_mib(struct b53_device *priv) 712 { 713 u8 gc; 714 715 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 716 717 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 718 msleep(1); 719 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 720 msleep(1); 721 } 722 723 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 724 { 725 if (is5365(dev)) 726 return b53_mibs_65; 727 else if (is63xx(dev)) 728 return b53_mibs_63xx; 729 else if (is58xx(dev)) 730 return b53_mibs_58xx; 731 else 732 return b53_mibs; 733 } 734 735 static unsigned int b53_get_mib_size(struct b53_device *dev) 736 { 737 if (is5365(dev)) 738 return B53_MIBS_65_SIZE; 739 else if (is63xx(dev)) 740 return B53_MIBS_63XX_SIZE; 741 else if (is58xx(dev)) 742 return B53_MIBS_58XX_SIZE; 743 else 744 return B53_MIBS_SIZE; 745 } 746 747 void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data) 748 { 749 struct b53_device *dev = ds->priv; 750 const struct b53_mib_desc *mibs = b53_get_mib(dev); 751 unsigned int mib_size = b53_get_mib_size(dev); 752 unsigned int i; 753 754 for (i = 0; i < mib_size; i++) 755 memcpy(data + i * ETH_GSTRING_LEN, 756 mibs[i].name, ETH_GSTRING_LEN); 757 } 758 EXPORT_SYMBOL(b53_get_strings); 759 760 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 761 { 762 struct b53_device *dev = ds->priv; 763 const struct b53_mib_desc *mibs = b53_get_mib(dev); 764 unsigned int mib_size = b53_get_mib_size(dev); 765 const struct b53_mib_desc *s; 766 unsigned int i; 767 u64 val = 0; 768 769 if (is5365(dev) && port == 5) 770 port = 8; 771 772 mutex_lock(&dev->stats_mutex); 773 774 for (i = 0; i < mib_size; i++) { 775 s = &mibs[i]; 776 777 if (s->size == 8) { 778 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 779 } else { 780 u32 val32; 781 782 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 783 &val32); 784 val = val32; 785 } 786 data[i] = (u64)val; 787 } 788 789 mutex_unlock(&dev->stats_mutex); 790 } 791 EXPORT_SYMBOL(b53_get_ethtool_stats); 792 793 int b53_get_sset_count(struct dsa_switch *ds) 794 { 795 struct b53_device *dev = ds->priv; 796 797 return b53_get_mib_size(dev); 798 } 799 EXPORT_SYMBOL(b53_get_sset_count); 800 801 static int b53_setup(struct dsa_switch *ds) 802 { 803 struct b53_device *dev = ds->priv; 804 unsigned int port; 805 int ret; 806 807 ret = b53_reset_switch(dev); 808 if (ret) { 809 dev_err(ds->dev, "failed to reset switch\n"); 810 return ret; 811 } 812 813 b53_reset_mib(dev); 814 815 ret = b53_apply_config(dev); 816 if (ret) 817 dev_err(ds->dev, "failed to apply configuration\n"); 818 819 for (port = 0; port < dev->num_ports; port++) { 820 if (BIT(port) & ds->enabled_port_mask) 821 b53_enable_port(ds, port, NULL); 822 else if (dsa_is_cpu_port(ds, port)) 823 b53_enable_cpu_port(dev); 824 else 825 b53_disable_port(ds, port, NULL); 826 } 827 828 return ret; 829 } 830 831 static void b53_adjust_link(struct dsa_switch *ds, int port, 832 struct phy_device *phydev) 833 { 834 struct b53_device *dev = ds->priv; 835 u8 rgmii_ctrl = 0, reg = 0, off; 836 837 if (!phy_is_pseudo_fixed_link(phydev)) 838 return; 839 840 /* Override the port settings */ 841 if (port == dev->cpu_port) { 842 off = B53_PORT_OVERRIDE_CTRL; 843 reg = PORT_OVERRIDE_EN; 844 } else { 845 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 846 reg = GMII_PO_EN; 847 } 848 849 /* Set the link UP */ 850 if (phydev->link) 851 reg |= PORT_OVERRIDE_LINK; 852 853 if (phydev->duplex == DUPLEX_FULL) 854 reg |= PORT_OVERRIDE_FULL_DUPLEX; 855 856 switch (phydev->speed) { 857 case 2000: 858 reg |= PORT_OVERRIDE_SPEED_2000M; 859 /* fallthrough */ 860 case SPEED_1000: 861 reg |= PORT_OVERRIDE_SPEED_1000M; 862 break; 863 case SPEED_100: 864 reg |= PORT_OVERRIDE_SPEED_100M; 865 break; 866 case SPEED_10: 867 reg |= PORT_OVERRIDE_SPEED_10M; 868 break; 869 default: 870 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed); 871 return; 872 } 873 874 /* Enable flow control on BCM5301x's CPU port */ 875 if (is5301x(dev) && port == dev->cpu_port) 876 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW; 877 878 if (phydev->pause) { 879 if (phydev->asym_pause) 880 reg |= PORT_OVERRIDE_TX_FLOW; 881 reg |= PORT_OVERRIDE_RX_FLOW; 882 } 883 884 b53_write8(dev, B53_CTRL_PAGE, off, reg); 885 886 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 887 if (port == 8) 888 off = B53_RGMII_CTRL_IMP; 889 else 890 off = B53_RGMII_CTRL_P(port); 891 892 /* Configure the port RGMII clock delay by DLL disabled and 893 * tx_clk aligned timing (restoring to reset defaults) 894 */ 895 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 896 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 897 RGMII_CTRL_TIMING_SEL); 898 899 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 900 * sure that we enable the port TX clock internal delay to 901 * account for this internal delay that is inserted, otherwise 902 * the switch won't be able to receive correctly. 903 * 904 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 905 * any delay neither on transmission nor reception, so the 906 * BCM53125 must also be configured accordingly to account for 907 * the lack of delay and introduce 908 * 909 * The BCM53125 switch has its RX clock and TX clock control 910 * swapped, hence the reason why we modify the TX clock path in 911 * the "RGMII" case 912 */ 913 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 914 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 915 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 916 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 917 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 918 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 919 920 dev_info(ds->dev, "Configured port %d for %s\n", port, 921 phy_modes(phydev->interface)); 922 } 923 924 /* configure MII port if necessary */ 925 if (is5325(dev)) { 926 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 927 ®); 928 929 /* reverse mii needs to be enabled */ 930 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 931 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 932 reg | PORT_OVERRIDE_RV_MII_25); 933 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 934 ®); 935 936 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 937 dev_err(ds->dev, 938 "Failed to enable reverse MII mode\n"); 939 return; 940 } 941 } 942 } else if (is5301x(dev)) { 943 if (port != dev->cpu_port) { 944 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port); 945 u8 gmii_po; 946 947 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po); 948 gmii_po |= GMII_PO_LINK | 949 GMII_PO_RX_FLOW | 950 GMII_PO_TX_FLOW | 951 GMII_PO_EN | 952 GMII_PO_SPEED_2000M; 953 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po); 954 } 955 } 956 } 957 958 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 959 { 960 return 0; 961 } 962 EXPORT_SYMBOL(b53_vlan_filtering); 963 964 int b53_vlan_prepare(struct dsa_switch *ds, int port, 965 const struct switchdev_obj_port_vlan *vlan, 966 struct switchdev_trans *trans) 967 { 968 struct b53_device *dev = ds->priv; 969 970 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 971 return -EOPNOTSUPP; 972 973 if (vlan->vid_end > dev->num_vlans) 974 return -ERANGE; 975 976 b53_enable_vlan(dev, true); 977 978 return 0; 979 } 980 EXPORT_SYMBOL(b53_vlan_prepare); 981 982 void b53_vlan_add(struct dsa_switch *ds, int port, 983 const struct switchdev_obj_port_vlan *vlan, 984 struct switchdev_trans *trans) 985 { 986 struct b53_device *dev = ds->priv; 987 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 988 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 989 unsigned int cpu_port = dev->cpu_port; 990 struct b53_vlan *vl; 991 u16 vid; 992 993 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 994 vl = &dev->vlans[vid]; 995 996 b53_get_vlan_entry(dev, vid, vl); 997 998 vl->members |= BIT(port) | BIT(cpu_port); 999 if (untagged) 1000 vl->untag |= BIT(port); 1001 else 1002 vl->untag &= ~BIT(port); 1003 vl->untag &= ~BIT(cpu_port); 1004 1005 b53_set_vlan_entry(dev, vid, vl); 1006 b53_fast_age_vlan(dev, vid); 1007 } 1008 1009 if (pvid) { 1010 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1011 vlan->vid_end); 1012 b53_fast_age_vlan(dev, vid); 1013 } 1014 } 1015 EXPORT_SYMBOL(b53_vlan_add); 1016 1017 int b53_vlan_del(struct dsa_switch *ds, int port, 1018 const struct switchdev_obj_port_vlan *vlan) 1019 { 1020 struct b53_device *dev = ds->priv; 1021 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1022 struct b53_vlan *vl; 1023 u16 vid; 1024 u16 pvid; 1025 1026 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1027 1028 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1029 vl = &dev->vlans[vid]; 1030 1031 b53_get_vlan_entry(dev, vid, vl); 1032 1033 vl->members &= ~BIT(port); 1034 1035 if (pvid == vid) { 1036 if (is5325(dev) || is5365(dev)) 1037 pvid = 1; 1038 else 1039 pvid = 0; 1040 } 1041 1042 if (untagged) 1043 vl->untag &= ~(BIT(port)); 1044 1045 b53_set_vlan_entry(dev, vid, vl); 1046 b53_fast_age_vlan(dev, vid); 1047 } 1048 1049 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1050 b53_fast_age_vlan(dev, pvid); 1051 1052 return 0; 1053 } 1054 EXPORT_SYMBOL(b53_vlan_del); 1055 1056 int b53_vlan_dump(struct dsa_switch *ds, int port, 1057 struct switchdev_obj_port_vlan *vlan, 1058 switchdev_obj_dump_cb_t *cb) 1059 { 1060 struct b53_device *dev = ds->priv; 1061 u16 vid, vid_start = 0, pvid; 1062 struct b53_vlan *vl; 1063 int err = 0; 1064 1065 if (is5325(dev) || is5365(dev)) 1066 vid_start = 1; 1067 1068 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1069 1070 /* Use our software cache for dumps, since we do not have any HW 1071 * operation returning only the used/valid VLANs 1072 */ 1073 for (vid = vid_start; vid < dev->num_vlans; vid++) { 1074 vl = &dev->vlans[vid]; 1075 1076 if (!vl->valid) 1077 continue; 1078 1079 if (!(vl->members & BIT(port))) 1080 continue; 1081 1082 vlan->vid_begin = vlan->vid_end = vid; 1083 vlan->flags = 0; 1084 1085 if (vl->untag & BIT(port)) 1086 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; 1087 if (pvid == vid) 1088 vlan->flags |= BRIDGE_VLAN_INFO_PVID; 1089 1090 err = cb(&vlan->obj); 1091 if (err) 1092 break; 1093 } 1094 1095 return err; 1096 } 1097 EXPORT_SYMBOL(b53_vlan_dump); 1098 1099 /* Address Resolution Logic routines */ 1100 static int b53_arl_op_wait(struct b53_device *dev) 1101 { 1102 unsigned int timeout = 10; 1103 u8 reg; 1104 1105 do { 1106 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1107 if (!(reg & ARLTBL_START_DONE)) 1108 return 0; 1109 1110 usleep_range(1000, 2000); 1111 } while (timeout--); 1112 1113 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1114 1115 return -ETIMEDOUT; 1116 } 1117 1118 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1119 { 1120 u8 reg; 1121 1122 if (op > ARLTBL_RW) 1123 return -EINVAL; 1124 1125 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1126 reg |= ARLTBL_START_DONE; 1127 if (op) 1128 reg |= ARLTBL_RW; 1129 else 1130 reg &= ~ARLTBL_RW; 1131 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1132 1133 return b53_arl_op_wait(dev); 1134 } 1135 1136 static int b53_arl_read(struct b53_device *dev, u64 mac, 1137 u16 vid, struct b53_arl_entry *ent, u8 *idx, 1138 bool is_valid) 1139 { 1140 unsigned int i; 1141 int ret; 1142 1143 ret = b53_arl_op_wait(dev); 1144 if (ret) 1145 return ret; 1146 1147 /* Read the bins */ 1148 for (i = 0; i < dev->num_arl_entries; i++) { 1149 u64 mac_vid; 1150 u32 fwd_entry; 1151 1152 b53_read64(dev, B53_ARLIO_PAGE, 1153 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1154 b53_read32(dev, B53_ARLIO_PAGE, 1155 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1156 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1157 1158 if (!(fwd_entry & ARLTBL_VALID)) 1159 continue; 1160 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1161 continue; 1162 *idx = i; 1163 } 1164 1165 return -ENOENT; 1166 } 1167 1168 static int b53_arl_op(struct b53_device *dev, int op, int port, 1169 const unsigned char *addr, u16 vid, bool is_valid) 1170 { 1171 struct b53_arl_entry ent; 1172 u32 fwd_entry; 1173 u64 mac, mac_vid = 0; 1174 u8 idx = 0; 1175 int ret; 1176 1177 /* Convert the array into a 64-bit MAC */ 1178 mac = ether_addr_to_u64(addr); 1179 1180 /* Perform a read for the given MAC and VID */ 1181 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1182 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1183 1184 /* Issue a read operation for this MAC */ 1185 ret = b53_arl_rw_op(dev, 1); 1186 if (ret) 1187 return ret; 1188 1189 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid); 1190 /* If this is a read, just finish now */ 1191 if (op) 1192 return ret; 1193 1194 /* We could not find a matching MAC, so reset to a new entry */ 1195 if (ret) { 1196 fwd_entry = 0; 1197 idx = 1; 1198 } 1199 1200 memset(&ent, 0, sizeof(ent)); 1201 ent.port = port; 1202 ent.is_valid = is_valid; 1203 ent.vid = vid; 1204 ent.is_static = true; 1205 memcpy(ent.mac, addr, ETH_ALEN); 1206 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1207 1208 b53_write64(dev, B53_ARLIO_PAGE, 1209 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1210 b53_write32(dev, B53_ARLIO_PAGE, 1211 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1212 1213 return b53_arl_rw_op(dev, 0); 1214 } 1215 1216 int b53_fdb_prepare(struct dsa_switch *ds, int port, 1217 const struct switchdev_obj_port_fdb *fdb, 1218 struct switchdev_trans *trans) 1219 { 1220 struct b53_device *priv = ds->priv; 1221 1222 /* 5325 and 5365 require some more massaging, but could 1223 * be supported eventually 1224 */ 1225 if (is5325(priv) || is5365(priv)) 1226 return -EOPNOTSUPP; 1227 1228 return 0; 1229 } 1230 EXPORT_SYMBOL(b53_fdb_prepare); 1231 1232 void b53_fdb_add(struct dsa_switch *ds, int port, 1233 const struct switchdev_obj_port_fdb *fdb, 1234 struct switchdev_trans *trans) 1235 { 1236 struct b53_device *priv = ds->priv; 1237 1238 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true)) 1239 pr_err("%s: failed to add MAC address\n", __func__); 1240 } 1241 EXPORT_SYMBOL(b53_fdb_add); 1242 1243 int b53_fdb_del(struct dsa_switch *ds, int port, 1244 const struct switchdev_obj_port_fdb *fdb) 1245 { 1246 struct b53_device *priv = ds->priv; 1247 1248 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false); 1249 } 1250 EXPORT_SYMBOL(b53_fdb_del); 1251 1252 static int b53_arl_search_wait(struct b53_device *dev) 1253 { 1254 unsigned int timeout = 1000; 1255 u8 reg; 1256 1257 do { 1258 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1259 if (!(reg & ARL_SRCH_STDN)) 1260 return 0; 1261 1262 if (reg & ARL_SRCH_VLID) 1263 return 0; 1264 1265 usleep_range(1000, 2000); 1266 } while (timeout--); 1267 1268 return -ETIMEDOUT; 1269 } 1270 1271 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1272 struct b53_arl_entry *ent) 1273 { 1274 u64 mac_vid; 1275 u32 fwd_entry; 1276 1277 b53_read64(dev, B53_ARLIO_PAGE, 1278 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1279 b53_read32(dev, B53_ARLIO_PAGE, 1280 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1281 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1282 } 1283 1284 static int b53_fdb_copy(struct net_device *dev, int port, 1285 const struct b53_arl_entry *ent, 1286 struct switchdev_obj_port_fdb *fdb, 1287 switchdev_obj_dump_cb_t *cb) 1288 { 1289 if (!ent->is_valid) 1290 return 0; 1291 1292 if (port != ent->port) 1293 return 0; 1294 1295 ether_addr_copy(fdb->addr, ent->mac); 1296 fdb->vid = ent->vid; 1297 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE; 1298 1299 return cb(&fdb->obj); 1300 } 1301 1302 int b53_fdb_dump(struct dsa_switch *ds, int port, 1303 struct switchdev_obj_port_fdb *fdb, 1304 switchdev_obj_dump_cb_t *cb) 1305 { 1306 struct b53_device *priv = ds->priv; 1307 struct net_device *dev = ds->ports[port].netdev; 1308 struct b53_arl_entry results[2]; 1309 unsigned int count = 0; 1310 int ret; 1311 u8 reg; 1312 1313 /* Start search operation */ 1314 reg = ARL_SRCH_STDN; 1315 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1316 1317 do { 1318 ret = b53_arl_search_wait(priv); 1319 if (ret) 1320 return ret; 1321 1322 b53_arl_search_rd(priv, 0, &results[0]); 1323 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb); 1324 if (ret) 1325 return ret; 1326 1327 if (priv->num_arl_entries > 2) { 1328 b53_arl_search_rd(priv, 1, &results[1]); 1329 ret = b53_fdb_copy(dev, port, &results[1], fdb, cb); 1330 if (ret) 1331 return ret; 1332 1333 if (!results[0].is_valid && !results[1].is_valid) 1334 break; 1335 } 1336 1337 } while (count++ < 1024); 1338 1339 return 0; 1340 } 1341 EXPORT_SYMBOL(b53_fdb_dump); 1342 1343 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1344 { 1345 struct b53_device *dev = ds->priv; 1346 s8 cpu_port = ds->dst->cpu_dp->index; 1347 u16 pvlan, reg; 1348 unsigned int i; 1349 1350 /* Make this port leave the all VLANs join since we will have proper 1351 * VLAN entries from now on 1352 */ 1353 if (is58xx(dev)) { 1354 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1355 reg &= ~BIT(port); 1356 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1357 reg &= ~BIT(cpu_port); 1358 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1359 } 1360 1361 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1362 1363 b53_for_each_port(dev, i) { 1364 if (ds->ports[i].bridge_dev != br) 1365 continue; 1366 1367 /* Add this local port to the remote port VLAN control 1368 * membership and update the remote port bitmask 1369 */ 1370 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1371 reg |= BIT(port); 1372 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1373 dev->ports[i].vlan_ctl_mask = reg; 1374 1375 pvlan |= BIT(i); 1376 } 1377 1378 /* Configure the local port VLAN control membership to include 1379 * remote ports and update the local port bitmask 1380 */ 1381 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1382 dev->ports[port].vlan_ctl_mask = pvlan; 1383 1384 return 0; 1385 } 1386 EXPORT_SYMBOL(b53_br_join); 1387 1388 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1389 { 1390 struct b53_device *dev = ds->priv; 1391 struct b53_vlan *vl = &dev->vlans[0]; 1392 s8 cpu_port = ds->dst->cpu_dp->index; 1393 unsigned int i; 1394 u16 pvlan, reg, pvid; 1395 1396 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1397 1398 b53_for_each_port(dev, i) { 1399 /* Don't touch the remaining ports */ 1400 if (ds->ports[i].bridge_dev != br) 1401 continue; 1402 1403 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1404 reg &= ~BIT(port); 1405 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1406 dev->ports[port].vlan_ctl_mask = reg; 1407 1408 /* Prevent self removal to preserve isolation */ 1409 if (port != i) 1410 pvlan &= ~BIT(i); 1411 } 1412 1413 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1414 dev->ports[port].vlan_ctl_mask = pvlan; 1415 1416 if (is5325(dev) || is5365(dev)) 1417 pvid = 1; 1418 else 1419 pvid = 0; 1420 1421 /* Make this port join all VLANs without VLAN entries */ 1422 if (is58xx(dev)) { 1423 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1424 reg |= BIT(port); 1425 if (!(reg & BIT(cpu_port))) 1426 reg |= BIT(cpu_port); 1427 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1428 } else { 1429 b53_get_vlan_entry(dev, pvid, vl); 1430 vl->members |= BIT(port) | BIT(dev->cpu_port); 1431 vl->untag |= BIT(port) | BIT(dev->cpu_port); 1432 b53_set_vlan_entry(dev, pvid, vl); 1433 } 1434 } 1435 EXPORT_SYMBOL(b53_br_leave); 1436 1437 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1438 { 1439 struct b53_device *dev = ds->priv; 1440 u8 hw_state; 1441 u8 reg; 1442 1443 switch (state) { 1444 case BR_STATE_DISABLED: 1445 hw_state = PORT_CTRL_DIS_STATE; 1446 break; 1447 case BR_STATE_LISTENING: 1448 hw_state = PORT_CTRL_LISTEN_STATE; 1449 break; 1450 case BR_STATE_LEARNING: 1451 hw_state = PORT_CTRL_LEARN_STATE; 1452 break; 1453 case BR_STATE_FORWARDING: 1454 hw_state = PORT_CTRL_FWD_STATE; 1455 break; 1456 case BR_STATE_BLOCKING: 1457 hw_state = PORT_CTRL_BLOCK_STATE; 1458 break; 1459 default: 1460 dev_err(ds->dev, "invalid STP state: %d\n", state); 1461 return; 1462 } 1463 1464 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1465 reg &= ~PORT_CTRL_STP_STATE_MASK; 1466 reg |= hw_state; 1467 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1468 } 1469 EXPORT_SYMBOL(b53_br_set_stp_state); 1470 1471 void b53_br_fast_age(struct dsa_switch *ds, int port) 1472 { 1473 struct b53_device *dev = ds->priv; 1474 1475 if (b53_fast_age_port(dev, port)) 1476 dev_err(ds->dev, "fast ageing failed\n"); 1477 } 1478 EXPORT_SYMBOL(b53_br_fast_age); 1479 1480 static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds) 1481 { 1482 return DSA_TAG_PROTO_NONE; 1483 } 1484 1485 int b53_mirror_add(struct dsa_switch *ds, int port, 1486 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1487 { 1488 struct b53_device *dev = ds->priv; 1489 u16 reg, loc; 1490 1491 if (ingress) 1492 loc = B53_IG_MIR_CTL; 1493 else 1494 loc = B53_EG_MIR_CTL; 1495 1496 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1497 reg &= ~MIRROR_MASK; 1498 reg |= BIT(port); 1499 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1500 1501 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1502 reg &= ~CAP_PORT_MASK; 1503 reg |= mirror->to_local_port; 1504 reg |= MIRROR_EN; 1505 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1506 1507 return 0; 1508 } 1509 EXPORT_SYMBOL(b53_mirror_add); 1510 1511 void b53_mirror_del(struct dsa_switch *ds, int port, 1512 struct dsa_mall_mirror_tc_entry *mirror) 1513 { 1514 struct b53_device *dev = ds->priv; 1515 bool loc_disable = false, other_loc_disable = false; 1516 u16 reg, loc; 1517 1518 if (mirror->ingress) 1519 loc = B53_IG_MIR_CTL; 1520 else 1521 loc = B53_EG_MIR_CTL; 1522 1523 /* Update the desired ingress/egress register */ 1524 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1525 reg &= ~BIT(port); 1526 if (!(reg & MIRROR_MASK)) 1527 loc_disable = true; 1528 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1529 1530 /* Now look at the other one to know if we can disable mirroring 1531 * entirely 1532 */ 1533 if (mirror->ingress) 1534 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 1535 else 1536 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 1537 if (!(reg & MIRROR_MASK)) 1538 other_loc_disable = true; 1539 1540 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1541 /* Both no longer have ports, let's disable mirroring */ 1542 if (loc_disable && other_loc_disable) { 1543 reg &= ~MIRROR_EN; 1544 reg &= ~mirror->to_local_port; 1545 } 1546 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1547 } 1548 EXPORT_SYMBOL(b53_mirror_del); 1549 1550 static const struct dsa_switch_ops b53_switch_ops = { 1551 .get_tag_protocol = b53_get_tag_protocol, 1552 .setup = b53_setup, 1553 .get_strings = b53_get_strings, 1554 .get_ethtool_stats = b53_get_ethtool_stats, 1555 .get_sset_count = b53_get_sset_count, 1556 .phy_read = b53_phy_read16, 1557 .phy_write = b53_phy_write16, 1558 .adjust_link = b53_adjust_link, 1559 .port_enable = b53_enable_port, 1560 .port_disable = b53_disable_port, 1561 .port_bridge_join = b53_br_join, 1562 .port_bridge_leave = b53_br_leave, 1563 .port_stp_state_set = b53_br_set_stp_state, 1564 .port_fast_age = b53_br_fast_age, 1565 .port_vlan_filtering = b53_vlan_filtering, 1566 .port_vlan_prepare = b53_vlan_prepare, 1567 .port_vlan_add = b53_vlan_add, 1568 .port_vlan_del = b53_vlan_del, 1569 .port_vlan_dump = b53_vlan_dump, 1570 .port_fdb_prepare = b53_fdb_prepare, 1571 .port_fdb_dump = b53_fdb_dump, 1572 .port_fdb_add = b53_fdb_add, 1573 .port_fdb_del = b53_fdb_del, 1574 .port_mirror_add = b53_mirror_add, 1575 .port_mirror_del = b53_mirror_del, 1576 }; 1577 1578 struct b53_chip_data { 1579 u32 chip_id; 1580 const char *dev_name; 1581 u16 vlans; 1582 u16 enabled_ports; 1583 u8 cpu_port; 1584 u8 vta_regs[3]; 1585 u8 arl_entries; 1586 u8 duplex_reg; 1587 u8 jumbo_pm_reg; 1588 u8 jumbo_size_reg; 1589 }; 1590 1591 #define B53_VTA_REGS \ 1592 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 1593 #define B53_VTA_REGS_9798 \ 1594 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 1595 #define B53_VTA_REGS_63XX \ 1596 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 1597 1598 static const struct b53_chip_data b53_switch_chips[] = { 1599 { 1600 .chip_id = BCM5325_DEVICE_ID, 1601 .dev_name = "BCM5325", 1602 .vlans = 16, 1603 .enabled_ports = 0x1f, 1604 .arl_entries = 2, 1605 .cpu_port = B53_CPU_PORT_25, 1606 .duplex_reg = B53_DUPLEX_STAT_FE, 1607 }, 1608 { 1609 .chip_id = BCM5365_DEVICE_ID, 1610 .dev_name = "BCM5365", 1611 .vlans = 256, 1612 .enabled_ports = 0x1f, 1613 .arl_entries = 2, 1614 .cpu_port = B53_CPU_PORT_25, 1615 .duplex_reg = B53_DUPLEX_STAT_FE, 1616 }, 1617 { 1618 .chip_id = BCM5395_DEVICE_ID, 1619 .dev_name = "BCM5395", 1620 .vlans = 4096, 1621 .enabled_ports = 0x1f, 1622 .arl_entries = 4, 1623 .cpu_port = B53_CPU_PORT, 1624 .vta_regs = B53_VTA_REGS, 1625 .duplex_reg = B53_DUPLEX_STAT_GE, 1626 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1627 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1628 }, 1629 { 1630 .chip_id = BCM5397_DEVICE_ID, 1631 .dev_name = "BCM5397", 1632 .vlans = 4096, 1633 .enabled_ports = 0x1f, 1634 .arl_entries = 4, 1635 .cpu_port = B53_CPU_PORT, 1636 .vta_regs = B53_VTA_REGS_9798, 1637 .duplex_reg = B53_DUPLEX_STAT_GE, 1638 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1639 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1640 }, 1641 { 1642 .chip_id = BCM5398_DEVICE_ID, 1643 .dev_name = "BCM5398", 1644 .vlans = 4096, 1645 .enabled_ports = 0x7f, 1646 .arl_entries = 4, 1647 .cpu_port = B53_CPU_PORT, 1648 .vta_regs = B53_VTA_REGS_9798, 1649 .duplex_reg = B53_DUPLEX_STAT_GE, 1650 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1651 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1652 }, 1653 { 1654 .chip_id = BCM53115_DEVICE_ID, 1655 .dev_name = "BCM53115", 1656 .vlans = 4096, 1657 .enabled_ports = 0x1f, 1658 .arl_entries = 4, 1659 .vta_regs = B53_VTA_REGS, 1660 .cpu_port = B53_CPU_PORT, 1661 .duplex_reg = B53_DUPLEX_STAT_GE, 1662 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1663 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1664 }, 1665 { 1666 .chip_id = BCM53125_DEVICE_ID, 1667 .dev_name = "BCM53125", 1668 .vlans = 4096, 1669 .enabled_ports = 0xff, 1670 .cpu_port = B53_CPU_PORT, 1671 .vta_regs = B53_VTA_REGS, 1672 .duplex_reg = B53_DUPLEX_STAT_GE, 1673 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1674 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1675 }, 1676 { 1677 .chip_id = BCM53128_DEVICE_ID, 1678 .dev_name = "BCM53128", 1679 .vlans = 4096, 1680 .enabled_ports = 0x1ff, 1681 .arl_entries = 4, 1682 .cpu_port = B53_CPU_PORT, 1683 .vta_regs = B53_VTA_REGS, 1684 .duplex_reg = B53_DUPLEX_STAT_GE, 1685 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1686 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1687 }, 1688 { 1689 .chip_id = BCM63XX_DEVICE_ID, 1690 .dev_name = "BCM63xx", 1691 .vlans = 4096, 1692 .enabled_ports = 0, /* pdata must provide them */ 1693 .arl_entries = 4, 1694 .cpu_port = B53_CPU_PORT, 1695 .vta_regs = B53_VTA_REGS_63XX, 1696 .duplex_reg = B53_DUPLEX_STAT_63XX, 1697 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 1698 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 1699 }, 1700 { 1701 .chip_id = BCM53010_DEVICE_ID, 1702 .dev_name = "BCM53010", 1703 .vlans = 4096, 1704 .enabled_ports = 0x1f, 1705 .arl_entries = 4, 1706 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1707 .vta_regs = B53_VTA_REGS, 1708 .duplex_reg = B53_DUPLEX_STAT_GE, 1709 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1710 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1711 }, 1712 { 1713 .chip_id = BCM53011_DEVICE_ID, 1714 .dev_name = "BCM53011", 1715 .vlans = 4096, 1716 .enabled_ports = 0x1bf, 1717 .arl_entries = 4, 1718 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1719 .vta_regs = B53_VTA_REGS, 1720 .duplex_reg = B53_DUPLEX_STAT_GE, 1721 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1722 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1723 }, 1724 { 1725 .chip_id = BCM53012_DEVICE_ID, 1726 .dev_name = "BCM53012", 1727 .vlans = 4096, 1728 .enabled_ports = 0x1bf, 1729 .arl_entries = 4, 1730 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1731 .vta_regs = B53_VTA_REGS, 1732 .duplex_reg = B53_DUPLEX_STAT_GE, 1733 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1734 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1735 }, 1736 { 1737 .chip_id = BCM53018_DEVICE_ID, 1738 .dev_name = "BCM53018", 1739 .vlans = 4096, 1740 .enabled_ports = 0x1f, 1741 .arl_entries = 4, 1742 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1743 .vta_regs = B53_VTA_REGS, 1744 .duplex_reg = B53_DUPLEX_STAT_GE, 1745 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1746 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1747 }, 1748 { 1749 .chip_id = BCM53019_DEVICE_ID, 1750 .dev_name = "BCM53019", 1751 .vlans = 4096, 1752 .enabled_ports = 0x1f, 1753 .arl_entries = 4, 1754 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 1755 .vta_regs = B53_VTA_REGS, 1756 .duplex_reg = B53_DUPLEX_STAT_GE, 1757 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1758 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1759 }, 1760 { 1761 .chip_id = BCM58XX_DEVICE_ID, 1762 .dev_name = "BCM585xx/586xx/88312", 1763 .vlans = 4096, 1764 .enabled_ports = 0x1ff, 1765 .arl_entries = 4, 1766 .cpu_port = B53_CPU_PORT, 1767 .vta_regs = B53_VTA_REGS, 1768 .duplex_reg = B53_DUPLEX_STAT_GE, 1769 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1770 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1771 }, 1772 { 1773 .chip_id = BCM7445_DEVICE_ID, 1774 .dev_name = "BCM7445", 1775 .vlans = 4096, 1776 .enabled_ports = 0x1ff, 1777 .arl_entries = 4, 1778 .cpu_port = B53_CPU_PORT, 1779 .vta_regs = B53_VTA_REGS, 1780 .duplex_reg = B53_DUPLEX_STAT_GE, 1781 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1782 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1783 }, 1784 { 1785 .chip_id = BCM7278_DEVICE_ID, 1786 .dev_name = "BCM7278", 1787 .vlans = 4096, 1788 .enabled_ports = 0x1ff, 1789 .arl_entries= 4, 1790 .cpu_port = B53_CPU_PORT, 1791 .vta_regs = B53_VTA_REGS, 1792 .duplex_reg = B53_DUPLEX_STAT_GE, 1793 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 1794 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 1795 }, 1796 }; 1797 1798 static int b53_switch_init(struct b53_device *dev) 1799 { 1800 unsigned int i; 1801 int ret; 1802 1803 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 1804 const struct b53_chip_data *chip = &b53_switch_chips[i]; 1805 1806 if (chip->chip_id == dev->chip_id) { 1807 if (!dev->enabled_ports) 1808 dev->enabled_ports = chip->enabled_ports; 1809 dev->name = chip->dev_name; 1810 dev->duplex_reg = chip->duplex_reg; 1811 dev->vta_regs[0] = chip->vta_regs[0]; 1812 dev->vta_regs[1] = chip->vta_regs[1]; 1813 dev->vta_regs[2] = chip->vta_regs[2]; 1814 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 1815 dev->cpu_port = chip->cpu_port; 1816 dev->num_vlans = chip->vlans; 1817 dev->num_arl_entries = chip->arl_entries; 1818 break; 1819 } 1820 } 1821 1822 /* check which BCM5325x version we have */ 1823 if (is5325(dev)) { 1824 u8 vc4; 1825 1826 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 1827 1828 /* check reserved bits */ 1829 switch (vc4 & 3) { 1830 case 1: 1831 /* BCM5325E */ 1832 break; 1833 case 3: 1834 /* BCM5325F - do not use port 4 */ 1835 dev->enabled_ports &= ~BIT(4); 1836 break; 1837 default: 1838 /* On the BCM47XX SoCs this is the supported internal switch.*/ 1839 #ifndef CONFIG_BCM47XX 1840 /* BCM5325M */ 1841 return -EINVAL; 1842 #else 1843 break; 1844 #endif 1845 } 1846 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 1847 u64 strap_value; 1848 1849 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 1850 /* use second IMP port if GMII is enabled */ 1851 if (strap_value & SV_GMII_CTRL_115) 1852 dev->cpu_port = 5; 1853 } 1854 1855 /* cpu port is always last */ 1856 dev->num_ports = dev->cpu_port + 1; 1857 dev->enabled_ports |= BIT(dev->cpu_port); 1858 1859 dev->ports = devm_kzalloc(dev->dev, 1860 sizeof(struct b53_port) * dev->num_ports, 1861 GFP_KERNEL); 1862 if (!dev->ports) 1863 return -ENOMEM; 1864 1865 dev->vlans = devm_kzalloc(dev->dev, 1866 sizeof(struct b53_vlan) * dev->num_vlans, 1867 GFP_KERNEL); 1868 if (!dev->vlans) 1869 return -ENOMEM; 1870 1871 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 1872 if (dev->reset_gpio >= 0) { 1873 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 1874 GPIOF_OUT_INIT_HIGH, "robo_reset"); 1875 if (ret) 1876 return ret; 1877 } 1878 1879 return 0; 1880 } 1881 1882 struct b53_device *b53_switch_alloc(struct device *base, 1883 const struct b53_io_ops *ops, 1884 void *priv) 1885 { 1886 struct dsa_switch *ds; 1887 struct b53_device *dev; 1888 1889 ds = dsa_switch_alloc(base, DSA_MAX_PORTS); 1890 if (!ds) 1891 return NULL; 1892 1893 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 1894 if (!dev) 1895 return NULL; 1896 1897 ds->priv = dev; 1898 dev->dev = base; 1899 1900 dev->ds = ds; 1901 dev->priv = priv; 1902 dev->ops = ops; 1903 ds->ops = &b53_switch_ops; 1904 mutex_init(&dev->reg_mutex); 1905 mutex_init(&dev->stats_mutex); 1906 1907 return dev; 1908 } 1909 EXPORT_SYMBOL(b53_switch_alloc); 1910 1911 int b53_switch_detect(struct b53_device *dev) 1912 { 1913 u32 id32; 1914 u16 tmp; 1915 u8 id8; 1916 int ret; 1917 1918 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 1919 if (ret) 1920 return ret; 1921 1922 switch (id8) { 1923 case 0: 1924 /* BCM5325 and BCM5365 do not have this register so reads 1925 * return 0. But the read operation did succeed, so assume this 1926 * is one of them. 1927 * 1928 * Next check if we can write to the 5325's VTA register; for 1929 * 5365 it is read only. 1930 */ 1931 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 1932 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 1933 1934 if (tmp == 0xf) 1935 dev->chip_id = BCM5325_DEVICE_ID; 1936 else 1937 dev->chip_id = BCM5365_DEVICE_ID; 1938 break; 1939 case BCM5395_DEVICE_ID: 1940 case BCM5397_DEVICE_ID: 1941 case BCM5398_DEVICE_ID: 1942 dev->chip_id = id8; 1943 break; 1944 default: 1945 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 1946 if (ret) 1947 return ret; 1948 1949 switch (id32) { 1950 case BCM53115_DEVICE_ID: 1951 case BCM53125_DEVICE_ID: 1952 case BCM53128_DEVICE_ID: 1953 case BCM53010_DEVICE_ID: 1954 case BCM53011_DEVICE_ID: 1955 case BCM53012_DEVICE_ID: 1956 case BCM53018_DEVICE_ID: 1957 case BCM53019_DEVICE_ID: 1958 dev->chip_id = id32; 1959 break; 1960 default: 1961 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 1962 id8, id32); 1963 return -ENODEV; 1964 } 1965 } 1966 1967 if (dev->chip_id == BCM5325_DEVICE_ID) 1968 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 1969 &dev->core_rev); 1970 else 1971 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 1972 &dev->core_rev); 1973 } 1974 EXPORT_SYMBOL(b53_switch_detect); 1975 1976 int b53_switch_register(struct b53_device *dev) 1977 { 1978 int ret; 1979 1980 if (dev->pdata) { 1981 dev->chip_id = dev->pdata->chip_id; 1982 dev->enabled_ports = dev->pdata->enabled_ports; 1983 } 1984 1985 if (!dev->chip_id && b53_switch_detect(dev)) 1986 return -EINVAL; 1987 1988 ret = b53_switch_init(dev); 1989 if (ret) 1990 return ret; 1991 1992 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 1993 1994 return dsa_register_switch(dev->ds, dev->ds->dev); 1995 } 1996 EXPORT_SYMBOL(b53_switch_register); 1997 1998 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 1999 MODULE_DESCRIPTION("B53 switch library"); 2000 MODULE_LICENSE("Dual BSD/GPL"); 2001