1 /* 2 * B53 switch driver main logic 3 * 4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/delay.h> 23 #include <linux/export.h> 24 #include <linux/gpio.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/platform_data/b53.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if_bridge.h> 32 #include <net/dsa.h> 33 34 #include "b53_regs.h" 35 #include "b53_priv.h" 36 37 struct b53_mib_desc { 38 u8 size; 39 u8 offset; 40 const char *name; 41 }; 42 43 /* BCM5365 MIB counters */ 44 static const struct b53_mib_desc b53_mibs_65[] = { 45 { 8, 0x00, "TxOctets" }, 46 { 4, 0x08, "TxDropPkts" }, 47 { 4, 0x10, "TxBroadcastPkts" }, 48 { 4, 0x14, "TxMulticastPkts" }, 49 { 4, 0x18, "TxUnicastPkts" }, 50 { 4, 0x1c, "TxCollisions" }, 51 { 4, 0x20, "TxSingleCollision" }, 52 { 4, 0x24, "TxMultipleCollision" }, 53 { 4, 0x28, "TxDeferredTransmit" }, 54 { 4, 0x2c, "TxLateCollision" }, 55 { 4, 0x30, "TxExcessiveCollision" }, 56 { 4, 0x38, "TxPausePkts" }, 57 { 8, 0x44, "RxOctets" }, 58 { 4, 0x4c, "RxUndersizePkts" }, 59 { 4, 0x50, "RxPausePkts" }, 60 { 4, 0x54, "Pkts64Octets" }, 61 { 4, 0x58, "Pkts65to127Octets" }, 62 { 4, 0x5c, "Pkts128to255Octets" }, 63 { 4, 0x60, "Pkts256to511Octets" }, 64 { 4, 0x64, "Pkts512to1023Octets" }, 65 { 4, 0x68, "Pkts1024to1522Octets" }, 66 { 4, 0x6c, "RxOversizePkts" }, 67 { 4, 0x70, "RxJabbers" }, 68 { 4, 0x74, "RxAlignmentErrors" }, 69 { 4, 0x78, "RxFCSErrors" }, 70 { 8, 0x7c, "RxGoodOctets" }, 71 { 4, 0x84, "RxDropPkts" }, 72 { 4, 0x88, "RxUnicastPkts" }, 73 { 4, 0x8c, "RxMulticastPkts" }, 74 { 4, 0x90, "RxBroadcastPkts" }, 75 { 4, 0x94, "RxSAChanges" }, 76 { 4, 0x98, "RxFragments" }, 77 }; 78 79 #define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65) 80 81 /* BCM63xx MIB counters */ 82 static const struct b53_mib_desc b53_mibs_63xx[] = { 83 { 8, 0x00, "TxOctets" }, 84 { 4, 0x08, "TxDropPkts" }, 85 { 4, 0x0c, "TxQoSPkts" }, 86 { 4, 0x10, "TxBroadcastPkts" }, 87 { 4, 0x14, "TxMulticastPkts" }, 88 { 4, 0x18, "TxUnicastPkts" }, 89 { 4, 0x1c, "TxCollisions" }, 90 { 4, 0x20, "TxSingleCollision" }, 91 { 4, 0x24, "TxMultipleCollision" }, 92 { 4, 0x28, "TxDeferredTransmit" }, 93 { 4, 0x2c, "TxLateCollision" }, 94 { 4, 0x30, "TxExcessiveCollision" }, 95 { 4, 0x38, "TxPausePkts" }, 96 { 8, 0x3c, "TxQoSOctets" }, 97 { 8, 0x44, "RxOctets" }, 98 { 4, 0x4c, "RxUndersizePkts" }, 99 { 4, 0x50, "RxPausePkts" }, 100 { 4, 0x54, "Pkts64Octets" }, 101 { 4, 0x58, "Pkts65to127Octets" }, 102 { 4, 0x5c, "Pkts128to255Octets" }, 103 { 4, 0x60, "Pkts256to511Octets" }, 104 { 4, 0x64, "Pkts512to1023Octets" }, 105 { 4, 0x68, "Pkts1024to1522Octets" }, 106 { 4, 0x6c, "RxOversizePkts" }, 107 { 4, 0x70, "RxJabbers" }, 108 { 4, 0x74, "RxAlignmentErrors" }, 109 { 4, 0x78, "RxFCSErrors" }, 110 { 8, 0x7c, "RxGoodOctets" }, 111 { 4, 0x84, "RxDropPkts" }, 112 { 4, 0x88, "RxUnicastPkts" }, 113 { 4, 0x8c, "RxMulticastPkts" }, 114 { 4, 0x90, "RxBroadcastPkts" }, 115 { 4, 0x94, "RxSAChanges" }, 116 { 4, 0x98, "RxFragments" }, 117 { 4, 0xa0, "RxSymbolErrors" }, 118 { 4, 0xa4, "RxQoSPkts" }, 119 { 8, 0xa8, "RxQoSOctets" }, 120 { 4, 0xb0, "Pkts1523to2047Octets" }, 121 { 4, 0xb4, "Pkts2048to4095Octets" }, 122 { 4, 0xb8, "Pkts4096to8191Octets" }, 123 { 4, 0xbc, "Pkts8192to9728Octets" }, 124 { 4, 0xc0, "RxDiscarded" }, 125 }; 126 127 #define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx) 128 129 /* MIB counters */ 130 static const struct b53_mib_desc b53_mibs[] = { 131 { 8, 0x00, "TxOctets" }, 132 { 4, 0x08, "TxDropPkts" }, 133 { 4, 0x10, "TxBroadcastPkts" }, 134 { 4, 0x14, "TxMulticastPkts" }, 135 { 4, 0x18, "TxUnicastPkts" }, 136 { 4, 0x1c, "TxCollisions" }, 137 { 4, 0x20, "TxSingleCollision" }, 138 { 4, 0x24, "TxMultipleCollision" }, 139 { 4, 0x28, "TxDeferredTransmit" }, 140 { 4, 0x2c, "TxLateCollision" }, 141 { 4, 0x30, "TxExcessiveCollision" }, 142 { 4, 0x38, "TxPausePkts" }, 143 { 8, 0x50, "RxOctets" }, 144 { 4, 0x58, "RxUndersizePkts" }, 145 { 4, 0x5c, "RxPausePkts" }, 146 { 4, 0x60, "Pkts64Octets" }, 147 { 4, 0x64, "Pkts65to127Octets" }, 148 { 4, 0x68, "Pkts128to255Octets" }, 149 { 4, 0x6c, "Pkts256to511Octets" }, 150 { 4, 0x70, "Pkts512to1023Octets" }, 151 { 4, 0x74, "Pkts1024to1522Octets" }, 152 { 4, 0x78, "RxOversizePkts" }, 153 { 4, 0x7c, "RxJabbers" }, 154 { 4, 0x80, "RxAlignmentErrors" }, 155 { 4, 0x84, "RxFCSErrors" }, 156 { 8, 0x88, "RxGoodOctets" }, 157 { 4, 0x90, "RxDropPkts" }, 158 { 4, 0x94, "RxUnicastPkts" }, 159 { 4, 0x98, "RxMulticastPkts" }, 160 { 4, 0x9c, "RxBroadcastPkts" }, 161 { 4, 0xa0, "RxSAChanges" }, 162 { 4, 0xa4, "RxFragments" }, 163 { 4, 0xa8, "RxJumboPkts" }, 164 { 4, 0xac, "RxSymbolErrors" }, 165 { 4, 0xc0, "RxDiscarded" }, 166 }; 167 168 #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) 169 170 static const struct b53_mib_desc b53_mibs_58xx[] = { 171 { 8, 0x00, "TxOctets" }, 172 { 4, 0x08, "TxDropPkts" }, 173 { 4, 0x0c, "TxQPKTQ0" }, 174 { 4, 0x10, "TxBroadcastPkts" }, 175 { 4, 0x14, "TxMulticastPkts" }, 176 { 4, 0x18, "TxUnicastPKts" }, 177 { 4, 0x1c, "TxCollisions" }, 178 { 4, 0x20, "TxSingleCollision" }, 179 { 4, 0x24, "TxMultipleCollision" }, 180 { 4, 0x28, "TxDeferredCollision" }, 181 { 4, 0x2c, "TxLateCollision" }, 182 { 4, 0x30, "TxExcessiveCollision" }, 183 { 4, 0x34, "TxFrameInDisc" }, 184 { 4, 0x38, "TxPausePkts" }, 185 { 4, 0x3c, "TxQPKTQ1" }, 186 { 4, 0x40, "TxQPKTQ2" }, 187 { 4, 0x44, "TxQPKTQ3" }, 188 { 4, 0x48, "TxQPKTQ4" }, 189 { 4, 0x4c, "TxQPKTQ5" }, 190 { 8, 0x50, "RxOctets" }, 191 { 4, 0x58, "RxUndersizePkts" }, 192 { 4, 0x5c, "RxPausePkts" }, 193 { 4, 0x60, "RxPkts64Octets" }, 194 { 4, 0x64, "RxPkts65to127Octets" }, 195 { 4, 0x68, "RxPkts128to255Octets" }, 196 { 4, 0x6c, "RxPkts256to511Octets" }, 197 { 4, 0x70, "RxPkts512to1023Octets" }, 198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, 199 { 4, 0x78, "RxOversizePkts" }, 200 { 4, 0x7c, "RxJabbers" }, 201 { 4, 0x80, "RxAlignmentErrors" }, 202 { 4, 0x84, "RxFCSErrors" }, 203 { 8, 0x88, "RxGoodOctets" }, 204 { 4, 0x90, "RxDropPkts" }, 205 { 4, 0x94, "RxUnicastPkts" }, 206 { 4, 0x98, "RxMulticastPkts" }, 207 { 4, 0x9c, "RxBroadcastPkts" }, 208 { 4, 0xa0, "RxSAChanges" }, 209 { 4, 0xa4, "RxFragments" }, 210 { 4, 0xa8, "RxJumboPkt" }, 211 { 4, 0xac, "RxSymblErr" }, 212 { 4, 0xb0, "InRangeErrCount" }, 213 { 4, 0xb4, "OutRangeErrCount" }, 214 { 4, 0xb8, "EEELpiEvent" }, 215 { 4, 0xbc, "EEELpiDuration" }, 216 { 4, 0xc0, "RxDiscard" }, 217 { 4, 0xc8, "TxQPKTQ6" }, 218 { 4, 0xcc, "TxQPKTQ7" }, 219 { 4, 0xd0, "TxPkts64Octets" }, 220 { 4, 0xd4, "TxPkts65to127Octets" }, 221 { 4, 0xd8, "TxPkts128to255Octets" }, 222 { 4, 0xdc, "TxPkts256to511Ocets" }, 223 { 4, 0xe0, "TxPkts512to1023Ocets" }, 224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" }, 225 }; 226 227 #define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx) 228 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op) 230 { 231 unsigned int i; 232 233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); 234 235 for (i = 0; i < 10; i++) { 236 u8 vta; 237 238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); 239 if (!(vta & VTA_START_CMD)) 240 return 0; 241 242 usleep_range(100, 200); 243 } 244 245 return -EIO; 246 } 247 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, 249 struct b53_vlan *vlan) 250 { 251 if (is5325(dev)) { 252 u32 entry = 0; 253 254 if (vlan->members) { 255 entry = ((vlan->untag & VA_UNTAG_MASK_25) << 256 VA_UNTAG_S_25) | vlan->members; 257 if (dev->core_rev >= 3) 258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; 259 else 260 entry |= VA_VALID_25; 261 } 262 263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); 264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 265 VTA_RW_STATE_WR | VTA_RW_OP_EN); 266 } else if (is5365(dev)) { 267 u16 entry = 0; 268 269 if (vlan->members) 270 entry = ((vlan->untag & VA_UNTAG_MASK_65) << 271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65; 272 273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); 274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 275 VTA_RW_STATE_WR | VTA_RW_OP_EN); 276 } else { 277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], 279 (vlan->untag << VTE_UNTAG_S) | vlan->members); 280 281 b53_do_vlan_op(dev, VTA_CMD_WRITE); 282 } 283 284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n", 285 vid, vlan->members, vlan->untag); 286 } 287 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid, 289 struct b53_vlan *vlan) 290 { 291 if (is5325(dev)) { 292 u32 entry = 0; 293 294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | 295 VTA_RW_STATE_RD | VTA_RW_OP_EN); 296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry); 297 298 if (dev->core_rev >= 3) 299 vlan->valid = !!(entry & VA_VALID_25_R4); 300 else 301 vlan->valid = !!(entry & VA_VALID_25); 302 vlan->members = entry & VA_MEMBER_MASK; 303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25; 304 305 } else if (is5365(dev)) { 306 u16 entry = 0; 307 308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | 309 VTA_RW_STATE_WR | VTA_RW_OP_EN); 310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry); 311 312 vlan->valid = !!(entry & VA_VALID_65); 313 vlan->members = entry & VA_MEMBER_MASK; 314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65; 315 } else { 316 u32 entry = 0; 317 318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); 319 b53_do_vlan_op(dev, VTA_CMD_READ); 320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry); 321 vlan->members = entry & VTE_MEMBERS; 322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS; 323 vlan->valid = true; 324 } 325 } 326 327 static void b53_set_forwarding(struct b53_device *dev, int enable) 328 { 329 u8 mgmt; 330 331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 332 333 if (enable) 334 mgmt |= SM_SW_FWD_EN; 335 else 336 mgmt &= ~SM_SW_FWD_EN; 337 338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 339 340 /* Include IMP port in dumb forwarding mode 341 */ 342 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt); 343 mgmt |= B53_MII_DUMB_FWDG_EN; 344 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt); 345 } 346 347 static void b53_enable_vlan(struct b53_device *dev, bool enable, 348 bool enable_filtering) 349 { 350 u8 mgmt, vc0, vc1, vc4 = 0, vc5; 351 352 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 353 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); 354 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); 355 356 if (is5325(dev) || is5365(dev)) { 357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); 359 } else if (is63xx(dev)) { 360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); 361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); 362 } else { 363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); 364 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); 365 } 366 367 mgmt &= ~SM_SW_FWD_MODE; 368 369 if (enable) { 370 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; 371 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; 372 vc4 &= ~VC4_ING_VID_CHECK_MASK; 373 if (enable_filtering) { 374 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; 375 vc5 |= VC5_DROP_VTABLE_MISS; 376 } else { 377 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 378 vc5 &= ~VC5_DROP_VTABLE_MISS; 379 } 380 381 if (is5325(dev)) 382 vc0 &= ~VC0_RESERVED_1; 383 384 if (is5325(dev) || is5365(dev)) 385 vc1 |= VC1_RX_MCST_TAG_EN; 386 387 } else { 388 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); 389 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); 390 vc4 &= ~VC4_ING_VID_CHECK_MASK; 391 vc5 &= ~VC5_DROP_VTABLE_MISS; 392 393 if (is5325(dev) || is5365(dev)) 394 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; 395 else 396 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; 397 398 if (is5325(dev) || is5365(dev)) 399 vc1 &= ~VC1_RX_MCST_TAG_EN; 400 } 401 402 if (!is5325(dev) && !is5365(dev)) 403 vc5 &= ~VC5_VID_FFF_EN; 404 405 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); 406 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); 407 408 if (is5325(dev) || is5365(dev)) { 409 /* enable the high 8 bit vid check on 5325 */ 410 if (is5325(dev) && enable) 411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 412 VC3_HIGH_8BIT_EN); 413 else 414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 415 416 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); 417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); 418 } else if (is63xx(dev)) { 419 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); 420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); 421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); 422 } else { 423 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); 424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); 425 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); 426 } 427 428 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 429 430 dev->vlan_enabled = enable; 431 } 432 433 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) 434 { 435 u32 port_mask = 0; 436 u16 max_size = JMS_MIN_SIZE; 437 438 if (is5325(dev) || is5365(dev)) 439 return -EINVAL; 440 441 if (enable) { 442 port_mask = dev->enabled_ports; 443 max_size = JMS_MAX_SIZE; 444 if (allow_10_100) 445 port_mask |= JPM_10_100_JUMBO_EN; 446 } 447 448 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); 449 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); 450 } 451 452 static int b53_flush_arl(struct b53_device *dev, u8 mask) 453 { 454 unsigned int i; 455 456 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 457 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); 458 459 for (i = 0; i < 10; i++) { 460 u8 fast_age_ctrl; 461 462 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, 463 &fast_age_ctrl); 464 465 if (!(fast_age_ctrl & FAST_AGE_DONE)) 466 goto out; 467 468 msleep(1); 469 } 470 471 return -ETIMEDOUT; 472 out: 473 /* Only age dynamic entries (default behavior) */ 474 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC); 475 return 0; 476 } 477 478 static int b53_fast_age_port(struct b53_device *dev, int port) 479 { 480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port); 481 482 return b53_flush_arl(dev, FAST_AGE_PORT); 483 } 484 485 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid) 486 { 487 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid); 488 489 return b53_flush_arl(dev, FAST_AGE_VLAN); 490 } 491 492 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) 493 { 494 struct b53_device *dev = ds->priv; 495 unsigned int i; 496 u16 pvlan; 497 498 /* Enable the IMP port to be in the same VLAN as the other ports 499 * on a per-port basis such that we only have Port i and IMP in 500 * the same VLAN. 501 */ 502 b53_for_each_port(dev, i) { 503 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan); 504 pvlan |= BIT(cpu_port); 505 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan); 506 } 507 } 508 EXPORT_SYMBOL(b53_imp_vlan_setup); 509 510 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 511 { 512 struct b53_device *dev = ds->priv; 513 unsigned int cpu_port = ds->ports[port].cpu_dp->index; 514 int ret = 0; 515 u16 pvlan; 516 517 if (dev->ops->irq_enable) 518 ret = dev->ops->irq_enable(dev, port); 519 if (ret) 520 return ret; 521 522 /* Clear the Rx and Tx disable bits and set to no spanning tree */ 523 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0); 524 525 /* Set this port, and only this one to be in the default VLAN, 526 * if member of a bridge, restore its membership prior to 527 * bringing down this port. 528 */ 529 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 530 pvlan &= ~0x1ff; 531 pvlan |= BIT(port); 532 pvlan |= dev->ports[port].vlan_ctl_mask; 533 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 534 535 b53_imp_vlan_setup(ds, cpu_port); 536 537 /* If EEE was enabled, restore it */ 538 if (dev->ports[port].eee.eee_enabled) 539 b53_eee_enable_set(ds, port, true); 540 541 return 0; 542 } 543 EXPORT_SYMBOL(b53_enable_port); 544 545 void b53_disable_port(struct dsa_switch *ds, int port) 546 { 547 struct b53_device *dev = ds->priv; 548 u8 reg; 549 550 /* Disable Tx/Rx for the port */ 551 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 552 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; 553 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 554 555 if (dev->ops->irq_disable) 556 dev->ops->irq_disable(dev, port); 557 } 558 EXPORT_SYMBOL(b53_disable_port); 559 560 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port) 561 { 562 bool tag_en = !(ds->ops->get_tag_protocol(ds, port) == 563 DSA_TAG_PROTO_NONE); 564 struct b53_device *dev = ds->priv; 565 u8 hdr_ctl, val; 566 u16 reg; 567 568 /* Resolve which bit controls the Broadcom tag */ 569 switch (port) { 570 case 8: 571 val = BRCM_HDR_P8_EN; 572 break; 573 case 7: 574 val = BRCM_HDR_P7_EN; 575 break; 576 case 5: 577 val = BRCM_HDR_P5_EN; 578 break; 579 default: 580 val = 0; 581 break; 582 } 583 584 /* Enable Broadcom tags for IMP port */ 585 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl); 586 if (tag_en) 587 hdr_ctl |= val; 588 else 589 hdr_ctl &= ~val; 590 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl); 591 592 /* Registers below are only accessible on newer devices */ 593 if (!is58xx(dev)) 594 return; 595 596 /* Enable reception Broadcom tag for CPU TX (switch RX) to 597 * allow us to tag outgoing frames 598 */ 599 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); 600 if (tag_en) 601 reg &= ~BIT(port); 602 else 603 reg |= BIT(port); 604 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); 605 606 /* Enable transmission of Broadcom tags from the switch (CPU RX) to 607 * allow delivering frames to the per-port net_devices 608 */ 609 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); 610 if (tag_en) 611 reg &= ~BIT(port); 612 else 613 reg |= BIT(port); 614 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); 615 } 616 EXPORT_SYMBOL(b53_brcm_hdr_setup); 617 618 static void b53_enable_cpu_port(struct b53_device *dev, int port) 619 { 620 u8 port_ctrl; 621 622 /* BCM5325 CPU port is at 8 */ 623 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25) 624 port = B53_CPU_PORT; 625 626 port_ctrl = PORT_CTRL_RX_BCST_EN | 627 PORT_CTRL_RX_MCST_EN | 628 PORT_CTRL_RX_UCST_EN; 629 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl); 630 631 b53_brcm_hdr_setup(dev->ds, port); 632 } 633 634 static void b53_enable_mib(struct b53_device *dev) 635 { 636 u8 gc; 637 638 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 639 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); 640 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); 641 } 642 643 static u16 b53_default_pvid(struct b53_device *dev) 644 { 645 if (is5325(dev) || is5365(dev)) 646 return 1; 647 else 648 return 0; 649 } 650 651 int b53_configure_vlan(struct dsa_switch *ds) 652 { 653 struct b53_device *dev = ds->priv; 654 struct b53_vlan vl = { 0 }; 655 int i, def_vid; 656 657 def_vid = b53_default_pvid(dev); 658 659 /* clear all vlan entries */ 660 if (is5325(dev) || is5365(dev)) { 661 for (i = def_vid; i < dev->num_vlans; i++) 662 b53_set_vlan_entry(dev, i, &vl); 663 } else { 664 b53_do_vlan_op(dev, VTA_CMD_CLEAR); 665 } 666 667 b53_enable_vlan(dev, false, ds->vlan_filtering); 668 669 b53_for_each_port(dev, i) 670 b53_write16(dev, B53_VLAN_PAGE, 671 B53_VLAN_PORT_DEF_TAG(i), def_vid); 672 673 if (!is5325(dev) && !is5365(dev)) 674 b53_set_jumbo(dev, dev->enable_jumbo, false); 675 676 return 0; 677 } 678 EXPORT_SYMBOL(b53_configure_vlan); 679 680 static void b53_switch_reset_gpio(struct b53_device *dev) 681 { 682 int gpio = dev->reset_gpio; 683 684 if (gpio < 0) 685 return; 686 687 /* Reset sequence: RESET low(50ms)->high(20ms) 688 */ 689 gpio_set_value(gpio, 0); 690 mdelay(50); 691 692 gpio_set_value(gpio, 1); 693 mdelay(20); 694 695 dev->current_page = 0xff; 696 } 697 698 static int b53_switch_reset(struct b53_device *dev) 699 { 700 unsigned int timeout = 1000; 701 u8 mgmt, reg; 702 703 b53_switch_reset_gpio(dev); 704 705 if (is539x(dev)) { 706 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); 707 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); 708 } 709 710 /* This is specific to 58xx devices here, do not use is58xx() which 711 * covers the larger Starfigther 2 family, including 7445/7278 which 712 * still use this driver as a library and need to perform the reset 713 * earlier. 714 */ 715 if (dev->chip_id == BCM58XX_DEVICE_ID || 716 dev->chip_id == BCM583XX_DEVICE_ID) { 717 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 718 reg |= SW_RST | EN_SW_RST | EN_CH_RST; 719 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); 720 721 do { 722 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); 723 if (!(reg & SW_RST)) 724 break; 725 726 usleep_range(1000, 2000); 727 } while (timeout-- > 0); 728 729 if (timeout == 0) 730 return -ETIMEDOUT; 731 } 732 733 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 734 735 if (!(mgmt & SM_SW_FWD_EN)) { 736 mgmt &= ~SM_SW_FWD_MODE; 737 mgmt |= SM_SW_FWD_EN; 738 739 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); 740 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); 741 742 if (!(mgmt & SM_SW_FWD_EN)) { 743 dev_err(dev->dev, "Failed to enable switch!\n"); 744 return -EINVAL; 745 } 746 } 747 748 b53_enable_mib(dev); 749 750 return b53_flush_arl(dev, FAST_AGE_STATIC); 751 } 752 753 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) 754 { 755 struct b53_device *priv = ds->priv; 756 u16 value = 0; 757 int ret; 758 759 if (priv->ops->phy_read16) 760 ret = priv->ops->phy_read16(priv, addr, reg, &value); 761 else 762 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr), 763 reg * 2, &value); 764 765 return ret ? ret : value; 766 } 767 768 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 769 { 770 struct b53_device *priv = ds->priv; 771 772 if (priv->ops->phy_write16) 773 return priv->ops->phy_write16(priv, addr, reg, val); 774 775 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); 776 } 777 778 static int b53_reset_switch(struct b53_device *priv) 779 { 780 /* reset vlans */ 781 priv->enable_jumbo = false; 782 783 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans); 784 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports); 785 786 priv->serdes_lane = B53_INVALID_LANE; 787 788 return b53_switch_reset(priv); 789 } 790 791 static int b53_apply_config(struct b53_device *priv) 792 { 793 /* disable switching */ 794 b53_set_forwarding(priv, 0); 795 796 b53_configure_vlan(priv->ds); 797 798 /* enable switching */ 799 b53_set_forwarding(priv, 1); 800 801 return 0; 802 } 803 804 static void b53_reset_mib(struct b53_device *priv) 805 { 806 u8 gc; 807 808 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); 809 810 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); 811 msleep(1); 812 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); 813 msleep(1); 814 } 815 816 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) 817 { 818 if (is5365(dev)) 819 return b53_mibs_65; 820 else if (is63xx(dev)) 821 return b53_mibs_63xx; 822 else if (is58xx(dev)) 823 return b53_mibs_58xx; 824 else 825 return b53_mibs; 826 } 827 828 static unsigned int b53_get_mib_size(struct b53_device *dev) 829 { 830 if (is5365(dev)) 831 return B53_MIBS_65_SIZE; 832 else if (is63xx(dev)) 833 return B53_MIBS_63XX_SIZE; 834 else if (is58xx(dev)) 835 return B53_MIBS_58XX_SIZE; 836 else 837 return B53_MIBS_SIZE; 838 } 839 840 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port) 841 { 842 /* These ports typically do not have built-in PHYs */ 843 switch (port) { 844 case B53_CPU_PORT_25: 845 case 7: 846 case B53_CPU_PORT: 847 return NULL; 848 } 849 850 return mdiobus_get_phy(ds->slave_mii_bus, port); 851 } 852 853 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset, 854 uint8_t *data) 855 { 856 struct b53_device *dev = ds->priv; 857 const struct b53_mib_desc *mibs = b53_get_mib(dev); 858 unsigned int mib_size = b53_get_mib_size(dev); 859 struct phy_device *phydev; 860 unsigned int i; 861 862 if (stringset == ETH_SS_STATS) { 863 for (i = 0; i < mib_size; i++) 864 strlcpy(data + i * ETH_GSTRING_LEN, 865 mibs[i].name, ETH_GSTRING_LEN); 866 } else if (stringset == ETH_SS_PHY_STATS) { 867 phydev = b53_get_phy_device(ds, port); 868 if (!phydev) 869 return; 870 871 phy_ethtool_get_strings(phydev, data); 872 } 873 } 874 EXPORT_SYMBOL(b53_get_strings); 875 876 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 877 { 878 struct b53_device *dev = ds->priv; 879 const struct b53_mib_desc *mibs = b53_get_mib(dev); 880 unsigned int mib_size = b53_get_mib_size(dev); 881 const struct b53_mib_desc *s; 882 unsigned int i; 883 u64 val = 0; 884 885 if (is5365(dev) && port == 5) 886 port = 8; 887 888 mutex_lock(&dev->stats_mutex); 889 890 for (i = 0; i < mib_size; i++) { 891 s = &mibs[i]; 892 893 if (s->size == 8) { 894 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val); 895 } else { 896 u32 val32; 897 898 b53_read32(dev, B53_MIB_PAGE(port), s->offset, 899 &val32); 900 val = val32; 901 } 902 data[i] = (u64)val; 903 } 904 905 mutex_unlock(&dev->stats_mutex); 906 } 907 EXPORT_SYMBOL(b53_get_ethtool_stats); 908 909 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data) 910 { 911 struct phy_device *phydev; 912 913 phydev = b53_get_phy_device(ds, port); 914 if (!phydev) 915 return; 916 917 phy_ethtool_get_stats(phydev, NULL, data); 918 } 919 EXPORT_SYMBOL(b53_get_ethtool_phy_stats); 920 921 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset) 922 { 923 struct b53_device *dev = ds->priv; 924 struct phy_device *phydev; 925 926 if (sset == ETH_SS_STATS) { 927 return b53_get_mib_size(dev); 928 } else if (sset == ETH_SS_PHY_STATS) { 929 phydev = b53_get_phy_device(ds, port); 930 if (!phydev) 931 return 0; 932 933 return phy_ethtool_get_sset_count(phydev); 934 } 935 936 return 0; 937 } 938 EXPORT_SYMBOL(b53_get_sset_count); 939 940 static int b53_setup(struct dsa_switch *ds) 941 { 942 struct b53_device *dev = ds->priv; 943 unsigned int port; 944 int ret; 945 946 ret = b53_reset_switch(dev); 947 if (ret) { 948 dev_err(ds->dev, "failed to reset switch\n"); 949 return ret; 950 } 951 952 b53_reset_mib(dev); 953 954 ret = b53_apply_config(dev); 955 if (ret) 956 dev_err(ds->dev, "failed to apply configuration\n"); 957 958 /* Configure IMP/CPU port, disable all other ports. Enabled 959 * ports will be configured with .port_enable 960 */ 961 for (port = 0; port < dev->num_ports; port++) { 962 if (dsa_is_cpu_port(ds, port)) 963 b53_enable_cpu_port(dev, port); 964 else 965 b53_disable_port(ds, port); 966 } 967 968 /* Let DSA handle the case were multiple bridges span the same switch 969 * device and different VLAN awareness settings are requested, which 970 * would be breaking filtering semantics for any of the other bridge 971 * devices. (not hardware supported) 972 */ 973 ds->vlan_filtering_is_global = true; 974 975 return ret; 976 } 977 978 static void b53_force_link(struct b53_device *dev, int port, int link) 979 { 980 u8 reg, val, off; 981 982 /* Override the port settings */ 983 if (port == dev->cpu_port) { 984 off = B53_PORT_OVERRIDE_CTRL; 985 val = PORT_OVERRIDE_EN; 986 } else { 987 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 988 val = GMII_PO_EN; 989 } 990 991 b53_read8(dev, B53_CTRL_PAGE, off, ®); 992 reg |= val; 993 if (link) 994 reg |= PORT_OVERRIDE_LINK; 995 else 996 reg &= ~PORT_OVERRIDE_LINK; 997 b53_write8(dev, B53_CTRL_PAGE, off, reg); 998 } 999 1000 static void b53_force_port_config(struct b53_device *dev, int port, 1001 int speed, int duplex, int pause) 1002 { 1003 u8 reg, val, off; 1004 1005 /* Override the port settings */ 1006 if (port == dev->cpu_port) { 1007 off = B53_PORT_OVERRIDE_CTRL; 1008 val = PORT_OVERRIDE_EN; 1009 } else { 1010 off = B53_GMII_PORT_OVERRIDE_CTRL(port); 1011 val = GMII_PO_EN; 1012 } 1013 1014 b53_read8(dev, B53_CTRL_PAGE, off, ®); 1015 reg |= val; 1016 if (duplex == DUPLEX_FULL) 1017 reg |= PORT_OVERRIDE_FULL_DUPLEX; 1018 else 1019 reg &= ~PORT_OVERRIDE_FULL_DUPLEX; 1020 1021 switch (speed) { 1022 case 2000: 1023 reg |= PORT_OVERRIDE_SPEED_2000M; 1024 /* fallthrough */ 1025 case SPEED_1000: 1026 reg |= PORT_OVERRIDE_SPEED_1000M; 1027 break; 1028 case SPEED_100: 1029 reg |= PORT_OVERRIDE_SPEED_100M; 1030 break; 1031 case SPEED_10: 1032 reg |= PORT_OVERRIDE_SPEED_10M; 1033 break; 1034 default: 1035 dev_err(dev->dev, "unknown speed: %d\n", speed); 1036 return; 1037 } 1038 1039 if (pause & MLO_PAUSE_RX) 1040 reg |= PORT_OVERRIDE_RX_FLOW; 1041 if (pause & MLO_PAUSE_TX) 1042 reg |= PORT_OVERRIDE_TX_FLOW; 1043 1044 b53_write8(dev, B53_CTRL_PAGE, off, reg); 1045 } 1046 1047 static void b53_adjust_link(struct dsa_switch *ds, int port, 1048 struct phy_device *phydev) 1049 { 1050 struct b53_device *dev = ds->priv; 1051 struct ethtool_eee *p = &dev->ports[port].eee; 1052 u8 rgmii_ctrl = 0, reg = 0, off; 1053 int pause = 0; 1054 1055 if (!phy_is_pseudo_fixed_link(phydev)) 1056 return; 1057 1058 /* Enable flow control on BCM5301x's CPU port */ 1059 if (is5301x(dev) && port == dev->cpu_port) 1060 pause = MLO_PAUSE_TXRX_MASK; 1061 1062 if (phydev->pause) { 1063 if (phydev->asym_pause) 1064 pause |= MLO_PAUSE_TX; 1065 pause |= MLO_PAUSE_RX; 1066 } 1067 1068 b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause); 1069 b53_force_link(dev, port, phydev->link); 1070 1071 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { 1072 if (port == 8) 1073 off = B53_RGMII_CTRL_IMP; 1074 else 1075 off = B53_RGMII_CTRL_P(port); 1076 1077 /* Configure the port RGMII clock delay by DLL disabled and 1078 * tx_clk aligned timing (restoring to reset defaults) 1079 */ 1080 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); 1081 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC | 1082 RGMII_CTRL_TIMING_SEL); 1083 1084 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make 1085 * sure that we enable the port TX clock internal delay to 1086 * account for this internal delay that is inserted, otherwise 1087 * the switch won't be able to receive correctly. 1088 * 1089 * PHY_INTERFACE_MODE_RGMII means that we are not introducing 1090 * any delay neither on transmission nor reception, so the 1091 * BCM53125 must also be configured accordingly to account for 1092 * the lack of delay and introduce 1093 * 1094 * The BCM53125 switch has its RX clock and TX clock control 1095 * swapped, hence the reason why we modify the TX clock path in 1096 * the "RGMII" case 1097 */ 1098 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1099 rgmii_ctrl |= RGMII_CTRL_DLL_TXC; 1100 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 1101 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC; 1102 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL; 1103 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); 1104 1105 dev_info(ds->dev, "Configured port %d for %s\n", port, 1106 phy_modes(phydev->interface)); 1107 } 1108 1109 /* configure MII port if necessary */ 1110 if (is5325(dev)) { 1111 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1112 ®); 1113 1114 /* reverse mii needs to be enabled */ 1115 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1116 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1117 reg | PORT_OVERRIDE_RV_MII_25); 1118 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, 1119 ®); 1120 1121 if (!(reg & PORT_OVERRIDE_RV_MII_25)) { 1122 dev_err(ds->dev, 1123 "Failed to enable reverse MII mode\n"); 1124 return; 1125 } 1126 } 1127 } else if (is5301x(dev)) { 1128 if (port != dev->cpu_port) { 1129 b53_force_port_config(dev, dev->cpu_port, 2000, 1130 DUPLEX_FULL, MLO_PAUSE_TXRX_MASK); 1131 b53_force_link(dev, dev->cpu_port, 1); 1132 } 1133 } 1134 1135 /* Re-negotiate EEE if it was enabled already */ 1136 p->eee_enabled = b53_eee_init(ds, port, phydev); 1137 } 1138 1139 void b53_port_event(struct dsa_switch *ds, int port) 1140 { 1141 struct b53_device *dev = ds->priv; 1142 bool link; 1143 u16 sts; 1144 1145 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts); 1146 link = !!(sts & BIT(port)); 1147 dsa_port_phylink_mac_change(ds, port, link); 1148 } 1149 EXPORT_SYMBOL(b53_port_event); 1150 1151 void b53_phylink_validate(struct dsa_switch *ds, int port, 1152 unsigned long *supported, 1153 struct phylink_link_state *state) 1154 { 1155 struct b53_device *dev = ds->priv; 1156 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1157 1158 if (dev->ops->serdes_phylink_validate) 1159 dev->ops->serdes_phylink_validate(dev, port, mask, state); 1160 1161 /* Allow all the expected bits */ 1162 phylink_set(mask, Autoneg); 1163 phylink_set_port_modes(mask); 1164 phylink_set(mask, Pause); 1165 phylink_set(mask, Asym_Pause); 1166 1167 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we 1168 * support Gigabit, including Half duplex. 1169 */ 1170 if (state->interface != PHY_INTERFACE_MODE_MII && 1171 state->interface != PHY_INTERFACE_MODE_REVMII && 1172 !phy_interface_mode_is_8023z(state->interface) && 1173 !(is5325(dev) || is5365(dev))) { 1174 phylink_set(mask, 1000baseT_Full); 1175 phylink_set(mask, 1000baseT_Half); 1176 } 1177 1178 if (!phy_interface_mode_is_8023z(state->interface)) { 1179 phylink_set(mask, 10baseT_Half); 1180 phylink_set(mask, 10baseT_Full); 1181 phylink_set(mask, 100baseT_Half); 1182 phylink_set(mask, 100baseT_Full); 1183 } 1184 1185 bitmap_and(supported, supported, mask, 1186 __ETHTOOL_LINK_MODE_MASK_NBITS); 1187 bitmap_and(state->advertising, state->advertising, mask, 1188 __ETHTOOL_LINK_MODE_MASK_NBITS); 1189 1190 phylink_helper_basex_speed(state); 1191 } 1192 EXPORT_SYMBOL(b53_phylink_validate); 1193 1194 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port, 1195 struct phylink_link_state *state) 1196 { 1197 struct b53_device *dev = ds->priv; 1198 int ret = -EOPNOTSUPP; 1199 1200 if ((phy_interface_mode_is_8023z(state->interface) || 1201 state->interface == PHY_INTERFACE_MODE_SGMII) && 1202 dev->ops->serdes_link_state) 1203 ret = dev->ops->serdes_link_state(dev, port, state); 1204 1205 return ret; 1206 } 1207 EXPORT_SYMBOL(b53_phylink_mac_link_state); 1208 1209 void b53_phylink_mac_config(struct dsa_switch *ds, int port, 1210 unsigned int mode, 1211 const struct phylink_link_state *state) 1212 { 1213 struct b53_device *dev = ds->priv; 1214 1215 if (mode == MLO_AN_PHY) 1216 return; 1217 1218 if (mode == MLO_AN_FIXED) { 1219 b53_force_port_config(dev, port, state->speed, 1220 state->duplex, state->pause); 1221 return; 1222 } 1223 1224 if ((phy_interface_mode_is_8023z(state->interface) || 1225 state->interface == PHY_INTERFACE_MODE_SGMII) && 1226 dev->ops->serdes_config) 1227 dev->ops->serdes_config(dev, port, mode, state); 1228 } 1229 EXPORT_SYMBOL(b53_phylink_mac_config); 1230 1231 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port) 1232 { 1233 struct b53_device *dev = ds->priv; 1234 1235 if (dev->ops->serdes_an_restart) 1236 dev->ops->serdes_an_restart(dev, port); 1237 } 1238 EXPORT_SYMBOL(b53_phylink_mac_an_restart); 1239 1240 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port, 1241 unsigned int mode, 1242 phy_interface_t interface) 1243 { 1244 struct b53_device *dev = ds->priv; 1245 1246 if (mode == MLO_AN_PHY) 1247 return; 1248 1249 if (mode == MLO_AN_FIXED) { 1250 b53_force_link(dev, port, false); 1251 return; 1252 } 1253 1254 if (phy_interface_mode_is_8023z(interface) && 1255 dev->ops->serdes_link_set) 1256 dev->ops->serdes_link_set(dev, port, mode, interface, false); 1257 } 1258 EXPORT_SYMBOL(b53_phylink_mac_link_down); 1259 1260 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port, 1261 unsigned int mode, 1262 phy_interface_t interface, 1263 struct phy_device *phydev) 1264 { 1265 struct b53_device *dev = ds->priv; 1266 1267 if (mode == MLO_AN_PHY) 1268 return; 1269 1270 if (mode == MLO_AN_FIXED) { 1271 b53_force_link(dev, port, true); 1272 return; 1273 } 1274 1275 if (phy_interface_mode_is_8023z(interface) && 1276 dev->ops->serdes_link_set) 1277 dev->ops->serdes_link_set(dev, port, mode, interface, true); 1278 } 1279 EXPORT_SYMBOL(b53_phylink_mac_link_up); 1280 1281 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering) 1282 { 1283 struct b53_device *dev = ds->priv; 1284 u16 pvid, new_pvid; 1285 1286 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1287 new_pvid = pvid; 1288 if (!vlan_filtering) { 1289 /* Filtering is currently enabled, use the default PVID since 1290 * the bridge does not expect tagging anymore 1291 */ 1292 dev->ports[port].pvid = pvid; 1293 new_pvid = b53_default_pvid(dev); 1294 } else { 1295 /* Filtering is currently disabled, restore the previous PVID */ 1296 new_pvid = dev->ports[port].pvid; 1297 } 1298 1299 if (pvid != new_pvid) 1300 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1301 new_pvid); 1302 1303 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering); 1304 1305 return 0; 1306 } 1307 EXPORT_SYMBOL(b53_vlan_filtering); 1308 1309 int b53_vlan_prepare(struct dsa_switch *ds, int port, 1310 const struct switchdev_obj_port_vlan *vlan) 1311 { 1312 struct b53_device *dev = ds->priv; 1313 1314 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0) 1315 return -EOPNOTSUPP; 1316 1317 if (vlan->vid_end > dev->num_vlans) 1318 return -ERANGE; 1319 1320 b53_enable_vlan(dev, true, ds->vlan_filtering); 1321 1322 return 0; 1323 } 1324 EXPORT_SYMBOL(b53_vlan_prepare); 1325 1326 void b53_vlan_add(struct dsa_switch *ds, int port, 1327 const struct switchdev_obj_port_vlan *vlan) 1328 { 1329 struct b53_device *dev = ds->priv; 1330 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1331 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1332 struct b53_vlan *vl; 1333 u16 vid; 1334 1335 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1336 vl = &dev->vlans[vid]; 1337 1338 b53_get_vlan_entry(dev, vid, vl); 1339 1340 vl->members |= BIT(port); 1341 if (untagged && !dsa_is_cpu_port(ds, port)) 1342 vl->untag |= BIT(port); 1343 else 1344 vl->untag &= ~BIT(port); 1345 1346 b53_set_vlan_entry(dev, vid, vl); 1347 b53_fast_age_vlan(dev, vid); 1348 } 1349 1350 if (pvid && !dsa_is_cpu_port(ds, port)) { 1351 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), 1352 vlan->vid_end); 1353 b53_fast_age_vlan(dev, vid); 1354 } 1355 } 1356 EXPORT_SYMBOL(b53_vlan_add); 1357 1358 int b53_vlan_del(struct dsa_switch *ds, int port, 1359 const struct switchdev_obj_port_vlan *vlan) 1360 { 1361 struct b53_device *dev = ds->priv; 1362 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1363 struct b53_vlan *vl; 1364 u16 vid; 1365 u16 pvid; 1366 1367 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid); 1368 1369 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1370 vl = &dev->vlans[vid]; 1371 1372 b53_get_vlan_entry(dev, vid, vl); 1373 1374 vl->members &= ~BIT(port); 1375 1376 if (pvid == vid) 1377 pvid = b53_default_pvid(dev); 1378 1379 if (untagged && !dsa_is_cpu_port(ds, port)) 1380 vl->untag &= ~(BIT(port)); 1381 1382 b53_set_vlan_entry(dev, vid, vl); 1383 b53_fast_age_vlan(dev, vid); 1384 } 1385 1386 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid); 1387 b53_fast_age_vlan(dev, pvid); 1388 1389 return 0; 1390 } 1391 EXPORT_SYMBOL(b53_vlan_del); 1392 1393 /* Address Resolution Logic routines */ 1394 static int b53_arl_op_wait(struct b53_device *dev) 1395 { 1396 unsigned int timeout = 10; 1397 u8 reg; 1398 1399 do { 1400 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1401 if (!(reg & ARLTBL_START_DONE)) 1402 return 0; 1403 1404 usleep_range(1000, 2000); 1405 } while (timeout--); 1406 1407 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); 1408 1409 return -ETIMEDOUT; 1410 } 1411 1412 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op) 1413 { 1414 u8 reg; 1415 1416 if (op > ARLTBL_RW) 1417 return -EINVAL; 1418 1419 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); 1420 reg |= ARLTBL_START_DONE; 1421 if (op) 1422 reg |= ARLTBL_RW; 1423 else 1424 reg &= ~ARLTBL_RW; 1425 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); 1426 1427 return b53_arl_op_wait(dev); 1428 } 1429 1430 static int b53_arl_read(struct b53_device *dev, u64 mac, 1431 u16 vid, struct b53_arl_entry *ent, u8 *idx, 1432 bool is_valid) 1433 { 1434 unsigned int i; 1435 int ret; 1436 1437 ret = b53_arl_op_wait(dev); 1438 if (ret) 1439 return ret; 1440 1441 /* Read the bins */ 1442 for (i = 0; i < dev->num_arl_entries; i++) { 1443 u64 mac_vid; 1444 u32 fwd_entry; 1445 1446 b53_read64(dev, B53_ARLIO_PAGE, 1447 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid); 1448 b53_read32(dev, B53_ARLIO_PAGE, 1449 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry); 1450 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1451 1452 if (!(fwd_entry & ARLTBL_VALID)) 1453 continue; 1454 if ((mac_vid & ARLTBL_MAC_MASK) != mac) 1455 continue; 1456 *idx = i; 1457 } 1458 1459 return -ENOENT; 1460 } 1461 1462 static int b53_arl_op(struct b53_device *dev, int op, int port, 1463 const unsigned char *addr, u16 vid, bool is_valid) 1464 { 1465 struct b53_arl_entry ent; 1466 u32 fwd_entry; 1467 u64 mac, mac_vid = 0; 1468 u8 idx = 0; 1469 int ret; 1470 1471 /* Convert the array into a 64-bit MAC */ 1472 mac = ether_addr_to_u64(addr); 1473 1474 /* Perform a read for the given MAC and VID */ 1475 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac); 1476 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid); 1477 1478 /* Issue a read operation for this MAC */ 1479 ret = b53_arl_rw_op(dev, 1); 1480 if (ret) 1481 return ret; 1482 1483 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid); 1484 /* If this is a read, just finish now */ 1485 if (op) 1486 return ret; 1487 1488 /* We could not find a matching MAC, so reset to a new entry */ 1489 if (ret) { 1490 fwd_entry = 0; 1491 idx = 1; 1492 } 1493 1494 memset(&ent, 0, sizeof(ent)); 1495 ent.port = port; 1496 ent.is_valid = is_valid; 1497 ent.vid = vid; 1498 ent.is_static = true; 1499 memcpy(ent.mac, addr, ETH_ALEN); 1500 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent); 1501 1502 b53_write64(dev, B53_ARLIO_PAGE, 1503 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid); 1504 b53_write32(dev, B53_ARLIO_PAGE, 1505 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry); 1506 1507 return b53_arl_rw_op(dev, 0); 1508 } 1509 1510 int b53_fdb_add(struct dsa_switch *ds, int port, 1511 const unsigned char *addr, u16 vid) 1512 { 1513 struct b53_device *priv = ds->priv; 1514 1515 /* 5325 and 5365 require some more massaging, but could 1516 * be supported eventually 1517 */ 1518 if (is5325(priv) || is5365(priv)) 1519 return -EOPNOTSUPP; 1520 1521 return b53_arl_op(priv, 0, port, addr, vid, true); 1522 } 1523 EXPORT_SYMBOL(b53_fdb_add); 1524 1525 int b53_fdb_del(struct dsa_switch *ds, int port, 1526 const unsigned char *addr, u16 vid) 1527 { 1528 struct b53_device *priv = ds->priv; 1529 1530 return b53_arl_op(priv, 0, port, addr, vid, false); 1531 } 1532 EXPORT_SYMBOL(b53_fdb_del); 1533 1534 static int b53_arl_search_wait(struct b53_device *dev) 1535 { 1536 unsigned int timeout = 1000; 1537 u8 reg; 1538 1539 do { 1540 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); 1541 if (!(reg & ARL_SRCH_STDN)) 1542 return 0; 1543 1544 if (reg & ARL_SRCH_VLID) 1545 return 0; 1546 1547 usleep_range(1000, 2000); 1548 } while (timeout--); 1549 1550 return -ETIMEDOUT; 1551 } 1552 1553 static void b53_arl_search_rd(struct b53_device *dev, u8 idx, 1554 struct b53_arl_entry *ent) 1555 { 1556 u64 mac_vid; 1557 u32 fwd_entry; 1558 1559 b53_read64(dev, B53_ARLIO_PAGE, 1560 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid); 1561 b53_read32(dev, B53_ARLIO_PAGE, 1562 B53_ARL_SRCH_RSTL(idx), &fwd_entry); 1563 b53_arl_to_entry(ent, mac_vid, fwd_entry); 1564 } 1565 1566 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent, 1567 dsa_fdb_dump_cb_t *cb, void *data) 1568 { 1569 if (!ent->is_valid) 1570 return 0; 1571 1572 if (port != ent->port) 1573 return 0; 1574 1575 return cb(ent->mac, ent->vid, ent->is_static, data); 1576 } 1577 1578 int b53_fdb_dump(struct dsa_switch *ds, int port, 1579 dsa_fdb_dump_cb_t *cb, void *data) 1580 { 1581 struct b53_device *priv = ds->priv; 1582 struct b53_arl_entry results[2]; 1583 unsigned int count = 0; 1584 int ret; 1585 u8 reg; 1586 1587 /* Start search operation */ 1588 reg = ARL_SRCH_STDN; 1589 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); 1590 1591 do { 1592 ret = b53_arl_search_wait(priv); 1593 if (ret) 1594 return ret; 1595 1596 b53_arl_search_rd(priv, 0, &results[0]); 1597 ret = b53_fdb_copy(port, &results[0], cb, data); 1598 if (ret) 1599 return ret; 1600 1601 if (priv->num_arl_entries > 2) { 1602 b53_arl_search_rd(priv, 1, &results[1]); 1603 ret = b53_fdb_copy(port, &results[1], cb, data); 1604 if (ret) 1605 return ret; 1606 1607 if (!results[0].is_valid && !results[1].is_valid) 1608 break; 1609 } 1610 1611 } while (count++ < 1024); 1612 1613 return 0; 1614 } 1615 EXPORT_SYMBOL(b53_fdb_dump); 1616 1617 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br) 1618 { 1619 struct b53_device *dev = ds->priv; 1620 s8 cpu_port = ds->ports[port].cpu_dp->index; 1621 u16 pvlan, reg; 1622 unsigned int i; 1623 1624 /* Make this port leave the all VLANs join since we will have proper 1625 * VLAN entries from now on 1626 */ 1627 if (is58xx(dev)) { 1628 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1629 reg &= ~BIT(port); 1630 if ((reg & BIT(cpu_port)) == BIT(cpu_port)) 1631 reg &= ~BIT(cpu_port); 1632 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1633 } 1634 1635 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1636 1637 b53_for_each_port(dev, i) { 1638 if (dsa_to_port(ds, i)->bridge_dev != br) 1639 continue; 1640 1641 /* Add this local port to the remote port VLAN control 1642 * membership and update the remote port bitmask 1643 */ 1644 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1645 reg |= BIT(port); 1646 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1647 dev->ports[i].vlan_ctl_mask = reg; 1648 1649 pvlan |= BIT(i); 1650 } 1651 1652 /* Configure the local port VLAN control membership to include 1653 * remote ports and update the local port bitmask 1654 */ 1655 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1656 dev->ports[port].vlan_ctl_mask = pvlan; 1657 1658 return 0; 1659 } 1660 EXPORT_SYMBOL(b53_br_join); 1661 1662 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br) 1663 { 1664 struct b53_device *dev = ds->priv; 1665 struct b53_vlan *vl = &dev->vlans[0]; 1666 s8 cpu_port = ds->ports[port].cpu_dp->index; 1667 unsigned int i; 1668 u16 pvlan, reg, pvid; 1669 1670 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); 1671 1672 b53_for_each_port(dev, i) { 1673 /* Don't touch the remaining ports */ 1674 if (dsa_to_port(ds, i)->bridge_dev != br) 1675 continue; 1676 1677 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); 1678 reg &= ~BIT(port); 1679 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); 1680 dev->ports[port].vlan_ctl_mask = reg; 1681 1682 /* Prevent self removal to preserve isolation */ 1683 if (port != i) 1684 pvlan &= ~BIT(i); 1685 } 1686 1687 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan); 1688 dev->ports[port].vlan_ctl_mask = pvlan; 1689 1690 pvid = b53_default_pvid(dev); 1691 1692 /* Make this port join all VLANs without VLAN entries */ 1693 if (is58xx(dev)) { 1694 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); 1695 reg |= BIT(port); 1696 if (!(reg & BIT(cpu_port))) 1697 reg |= BIT(cpu_port); 1698 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); 1699 } else { 1700 b53_get_vlan_entry(dev, pvid, vl); 1701 vl->members |= BIT(port) | BIT(cpu_port); 1702 vl->untag |= BIT(port) | BIT(cpu_port); 1703 b53_set_vlan_entry(dev, pvid, vl); 1704 } 1705 } 1706 EXPORT_SYMBOL(b53_br_leave); 1707 1708 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state) 1709 { 1710 struct b53_device *dev = ds->priv; 1711 u8 hw_state; 1712 u8 reg; 1713 1714 switch (state) { 1715 case BR_STATE_DISABLED: 1716 hw_state = PORT_CTRL_DIS_STATE; 1717 break; 1718 case BR_STATE_LISTENING: 1719 hw_state = PORT_CTRL_LISTEN_STATE; 1720 break; 1721 case BR_STATE_LEARNING: 1722 hw_state = PORT_CTRL_LEARN_STATE; 1723 break; 1724 case BR_STATE_FORWARDING: 1725 hw_state = PORT_CTRL_FWD_STATE; 1726 break; 1727 case BR_STATE_BLOCKING: 1728 hw_state = PORT_CTRL_BLOCK_STATE; 1729 break; 1730 default: 1731 dev_err(ds->dev, "invalid STP state: %d\n", state); 1732 return; 1733 } 1734 1735 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); 1736 reg &= ~PORT_CTRL_STP_STATE_MASK; 1737 reg |= hw_state; 1738 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); 1739 } 1740 EXPORT_SYMBOL(b53_br_set_stp_state); 1741 1742 void b53_br_fast_age(struct dsa_switch *ds, int port) 1743 { 1744 struct b53_device *dev = ds->priv; 1745 1746 if (b53_fast_age_port(dev, port)) 1747 dev_err(ds->dev, "fast ageing failed\n"); 1748 } 1749 EXPORT_SYMBOL(b53_br_fast_age); 1750 1751 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port) 1752 { 1753 /* Broadcom switches will accept enabling Broadcom tags on the 1754 * following ports: 5, 7 and 8, any other port is not supported 1755 */ 1756 switch (port) { 1757 case B53_CPU_PORT_25: 1758 case 7: 1759 case B53_CPU_PORT: 1760 return true; 1761 } 1762 1763 return false; 1764 } 1765 1766 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port) 1767 { 1768 bool ret = b53_possible_cpu_port(ds, port); 1769 1770 if (!ret) 1771 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", 1772 port); 1773 return ret; 1774 } 1775 1776 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port) 1777 { 1778 struct b53_device *dev = ds->priv; 1779 1780 /* Older models (5325, 5365) support a different tag format that we do 1781 * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed 1782 * mode to be turned on which means we need to specifically manage ARL 1783 * misses on multicast addresses (TBD). 1784 */ 1785 if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) || 1786 !b53_can_enable_brcm_tags(ds, port)) 1787 return DSA_TAG_PROTO_NONE; 1788 1789 /* Broadcom BCM58xx chips have a flow accelerator on Port 8 1790 * which requires us to use the prepended Broadcom tag type 1791 */ 1792 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) 1793 return DSA_TAG_PROTO_BRCM_PREPEND; 1794 1795 return DSA_TAG_PROTO_BRCM; 1796 } 1797 EXPORT_SYMBOL(b53_get_tag_protocol); 1798 1799 int b53_mirror_add(struct dsa_switch *ds, int port, 1800 struct dsa_mall_mirror_tc_entry *mirror, bool ingress) 1801 { 1802 struct b53_device *dev = ds->priv; 1803 u16 reg, loc; 1804 1805 if (ingress) 1806 loc = B53_IG_MIR_CTL; 1807 else 1808 loc = B53_EG_MIR_CTL; 1809 1810 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1811 reg &= ~MIRROR_MASK; 1812 reg |= BIT(port); 1813 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1814 1815 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1816 reg &= ~CAP_PORT_MASK; 1817 reg |= mirror->to_local_port; 1818 reg |= MIRROR_EN; 1819 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1820 1821 return 0; 1822 } 1823 EXPORT_SYMBOL(b53_mirror_add); 1824 1825 void b53_mirror_del(struct dsa_switch *ds, int port, 1826 struct dsa_mall_mirror_tc_entry *mirror) 1827 { 1828 struct b53_device *dev = ds->priv; 1829 bool loc_disable = false, other_loc_disable = false; 1830 u16 reg, loc; 1831 1832 if (mirror->ingress) 1833 loc = B53_IG_MIR_CTL; 1834 else 1835 loc = B53_EG_MIR_CTL; 1836 1837 /* Update the desired ingress/egress register */ 1838 b53_read16(dev, B53_MGMT_PAGE, loc, ®); 1839 reg &= ~BIT(port); 1840 if (!(reg & MIRROR_MASK)) 1841 loc_disable = true; 1842 b53_write16(dev, B53_MGMT_PAGE, loc, reg); 1843 1844 /* Now look at the other one to know if we can disable mirroring 1845 * entirely 1846 */ 1847 if (mirror->ingress) 1848 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); 1849 else 1850 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); 1851 if (!(reg & MIRROR_MASK)) 1852 other_loc_disable = true; 1853 1854 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); 1855 /* Both no longer have ports, let's disable mirroring */ 1856 if (loc_disable && other_loc_disable) { 1857 reg &= ~MIRROR_EN; 1858 reg &= ~mirror->to_local_port; 1859 } 1860 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); 1861 } 1862 EXPORT_SYMBOL(b53_mirror_del); 1863 1864 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable) 1865 { 1866 struct b53_device *dev = ds->priv; 1867 u16 reg; 1868 1869 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); 1870 if (enable) 1871 reg |= BIT(port); 1872 else 1873 reg &= ~BIT(port); 1874 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); 1875 } 1876 EXPORT_SYMBOL(b53_eee_enable_set); 1877 1878 1879 /* Returns 0 if EEE was not enabled, or 1 otherwise 1880 */ 1881 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy) 1882 { 1883 int ret; 1884 1885 ret = phy_init_eee(phy, 0); 1886 if (ret) 1887 return 0; 1888 1889 b53_eee_enable_set(ds, port, true); 1890 1891 return 1; 1892 } 1893 EXPORT_SYMBOL(b53_eee_init); 1894 1895 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1896 { 1897 struct b53_device *dev = ds->priv; 1898 struct ethtool_eee *p = &dev->ports[port].eee; 1899 u16 reg; 1900 1901 if (is5325(dev) || is5365(dev)) 1902 return -EOPNOTSUPP; 1903 1904 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); 1905 e->eee_enabled = p->eee_enabled; 1906 e->eee_active = !!(reg & BIT(port)); 1907 1908 return 0; 1909 } 1910 EXPORT_SYMBOL(b53_get_mac_eee); 1911 1912 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) 1913 { 1914 struct b53_device *dev = ds->priv; 1915 struct ethtool_eee *p = &dev->ports[port].eee; 1916 1917 if (is5325(dev) || is5365(dev)) 1918 return -EOPNOTSUPP; 1919 1920 p->eee_enabled = e->eee_enabled; 1921 b53_eee_enable_set(ds, port, e->eee_enabled); 1922 1923 return 0; 1924 } 1925 EXPORT_SYMBOL(b53_set_mac_eee); 1926 1927 static const struct dsa_switch_ops b53_switch_ops = { 1928 .get_tag_protocol = b53_get_tag_protocol, 1929 .setup = b53_setup, 1930 .get_strings = b53_get_strings, 1931 .get_ethtool_stats = b53_get_ethtool_stats, 1932 .get_sset_count = b53_get_sset_count, 1933 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats, 1934 .phy_read = b53_phy_read16, 1935 .phy_write = b53_phy_write16, 1936 .adjust_link = b53_adjust_link, 1937 .phylink_validate = b53_phylink_validate, 1938 .phylink_mac_link_state = b53_phylink_mac_link_state, 1939 .phylink_mac_config = b53_phylink_mac_config, 1940 .phylink_mac_an_restart = b53_phylink_mac_an_restart, 1941 .phylink_mac_link_down = b53_phylink_mac_link_down, 1942 .phylink_mac_link_up = b53_phylink_mac_link_up, 1943 .port_enable = b53_enable_port, 1944 .port_disable = b53_disable_port, 1945 .get_mac_eee = b53_get_mac_eee, 1946 .set_mac_eee = b53_set_mac_eee, 1947 .port_bridge_join = b53_br_join, 1948 .port_bridge_leave = b53_br_leave, 1949 .port_stp_state_set = b53_br_set_stp_state, 1950 .port_fast_age = b53_br_fast_age, 1951 .port_vlan_filtering = b53_vlan_filtering, 1952 .port_vlan_prepare = b53_vlan_prepare, 1953 .port_vlan_add = b53_vlan_add, 1954 .port_vlan_del = b53_vlan_del, 1955 .port_fdb_dump = b53_fdb_dump, 1956 .port_fdb_add = b53_fdb_add, 1957 .port_fdb_del = b53_fdb_del, 1958 .port_mirror_add = b53_mirror_add, 1959 .port_mirror_del = b53_mirror_del, 1960 }; 1961 1962 struct b53_chip_data { 1963 u32 chip_id; 1964 const char *dev_name; 1965 u16 vlans; 1966 u16 enabled_ports; 1967 u8 cpu_port; 1968 u8 vta_regs[3]; 1969 u8 arl_entries; 1970 u8 duplex_reg; 1971 u8 jumbo_pm_reg; 1972 u8 jumbo_size_reg; 1973 }; 1974 1975 #define B53_VTA_REGS \ 1976 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } 1977 #define B53_VTA_REGS_9798 \ 1978 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } 1979 #define B53_VTA_REGS_63XX \ 1980 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } 1981 1982 static const struct b53_chip_data b53_switch_chips[] = { 1983 { 1984 .chip_id = BCM5325_DEVICE_ID, 1985 .dev_name = "BCM5325", 1986 .vlans = 16, 1987 .enabled_ports = 0x1f, 1988 .arl_entries = 2, 1989 .cpu_port = B53_CPU_PORT_25, 1990 .duplex_reg = B53_DUPLEX_STAT_FE, 1991 }, 1992 { 1993 .chip_id = BCM5365_DEVICE_ID, 1994 .dev_name = "BCM5365", 1995 .vlans = 256, 1996 .enabled_ports = 0x1f, 1997 .arl_entries = 2, 1998 .cpu_port = B53_CPU_PORT_25, 1999 .duplex_reg = B53_DUPLEX_STAT_FE, 2000 }, 2001 { 2002 .chip_id = BCM5389_DEVICE_ID, 2003 .dev_name = "BCM5389", 2004 .vlans = 4096, 2005 .enabled_ports = 0x1f, 2006 .arl_entries = 4, 2007 .cpu_port = B53_CPU_PORT, 2008 .vta_regs = B53_VTA_REGS, 2009 .duplex_reg = B53_DUPLEX_STAT_GE, 2010 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2011 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2012 }, 2013 { 2014 .chip_id = BCM5395_DEVICE_ID, 2015 .dev_name = "BCM5395", 2016 .vlans = 4096, 2017 .enabled_ports = 0x1f, 2018 .arl_entries = 4, 2019 .cpu_port = B53_CPU_PORT, 2020 .vta_regs = B53_VTA_REGS, 2021 .duplex_reg = B53_DUPLEX_STAT_GE, 2022 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2023 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2024 }, 2025 { 2026 .chip_id = BCM5397_DEVICE_ID, 2027 .dev_name = "BCM5397", 2028 .vlans = 4096, 2029 .enabled_ports = 0x1f, 2030 .arl_entries = 4, 2031 .cpu_port = B53_CPU_PORT, 2032 .vta_regs = B53_VTA_REGS_9798, 2033 .duplex_reg = B53_DUPLEX_STAT_GE, 2034 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2035 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2036 }, 2037 { 2038 .chip_id = BCM5398_DEVICE_ID, 2039 .dev_name = "BCM5398", 2040 .vlans = 4096, 2041 .enabled_ports = 0x7f, 2042 .arl_entries = 4, 2043 .cpu_port = B53_CPU_PORT, 2044 .vta_regs = B53_VTA_REGS_9798, 2045 .duplex_reg = B53_DUPLEX_STAT_GE, 2046 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2047 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2048 }, 2049 { 2050 .chip_id = BCM53115_DEVICE_ID, 2051 .dev_name = "BCM53115", 2052 .vlans = 4096, 2053 .enabled_ports = 0x1f, 2054 .arl_entries = 4, 2055 .vta_regs = B53_VTA_REGS, 2056 .cpu_port = B53_CPU_PORT, 2057 .duplex_reg = B53_DUPLEX_STAT_GE, 2058 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2059 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2060 }, 2061 { 2062 .chip_id = BCM53125_DEVICE_ID, 2063 .dev_name = "BCM53125", 2064 .vlans = 4096, 2065 .enabled_ports = 0xff, 2066 .arl_entries = 4, 2067 .cpu_port = B53_CPU_PORT, 2068 .vta_regs = B53_VTA_REGS, 2069 .duplex_reg = B53_DUPLEX_STAT_GE, 2070 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2071 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2072 }, 2073 { 2074 .chip_id = BCM53128_DEVICE_ID, 2075 .dev_name = "BCM53128", 2076 .vlans = 4096, 2077 .enabled_ports = 0x1ff, 2078 .arl_entries = 4, 2079 .cpu_port = B53_CPU_PORT, 2080 .vta_regs = B53_VTA_REGS, 2081 .duplex_reg = B53_DUPLEX_STAT_GE, 2082 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2083 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2084 }, 2085 { 2086 .chip_id = BCM63XX_DEVICE_ID, 2087 .dev_name = "BCM63xx", 2088 .vlans = 4096, 2089 .enabled_ports = 0, /* pdata must provide them */ 2090 .arl_entries = 4, 2091 .cpu_port = B53_CPU_PORT, 2092 .vta_regs = B53_VTA_REGS_63XX, 2093 .duplex_reg = B53_DUPLEX_STAT_63XX, 2094 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, 2095 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, 2096 }, 2097 { 2098 .chip_id = BCM53010_DEVICE_ID, 2099 .dev_name = "BCM53010", 2100 .vlans = 4096, 2101 .enabled_ports = 0x1f, 2102 .arl_entries = 4, 2103 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2104 .vta_regs = B53_VTA_REGS, 2105 .duplex_reg = B53_DUPLEX_STAT_GE, 2106 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2107 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2108 }, 2109 { 2110 .chip_id = BCM53011_DEVICE_ID, 2111 .dev_name = "BCM53011", 2112 .vlans = 4096, 2113 .enabled_ports = 0x1bf, 2114 .arl_entries = 4, 2115 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2116 .vta_regs = B53_VTA_REGS, 2117 .duplex_reg = B53_DUPLEX_STAT_GE, 2118 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2119 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2120 }, 2121 { 2122 .chip_id = BCM53012_DEVICE_ID, 2123 .dev_name = "BCM53012", 2124 .vlans = 4096, 2125 .enabled_ports = 0x1bf, 2126 .arl_entries = 4, 2127 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2128 .vta_regs = B53_VTA_REGS, 2129 .duplex_reg = B53_DUPLEX_STAT_GE, 2130 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2131 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2132 }, 2133 { 2134 .chip_id = BCM53018_DEVICE_ID, 2135 .dev_name = "BCM53018", 2136 .vlans = 4096, 2137 .enabled_ports = 0x1f, 2138 .arl_entries = 4, 2139 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2140 .vta_regs = B53_VTA_REGS, 2141 .duplex_reg = B53_DUPLEX_STAT_GE, 2142 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2143 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2144 }, 2145 { 2146 .chip_id = BCM53019_DEVICE_ID, 2147 .dev_name = "BCM53019", 2148 .vlans = 4096, 2149 .enabled_ports = 0x1f, 2150 .arl_entries = 4, 2151 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ 2152 .vta_regs = B53_VTA_REGS, 2153 .duplex_reg = B53_DUPLEX_STAT_GE, 2154 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2155 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2156 }, 2157 { 2158 .chip_id = BCM58XX_DEVICE_ID, 2159 .dev_name = "BCM585xx/586xx/88312", 2160 .vlans = 4096, 2161 .enabled_ports = 0x1ff, 2162 .arl_entries = 4, 2163 .cpu_port = B53_CPU_PORT, 2164 .vta_regs = B53_VTA_REGS, 2165 .duplex_reg = B53_DUPLEX_STAT_GE, 2166 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2167 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2168 }, 2169 { 2170 .chip_id = BCM583XX_DEVICE_ID, 2171 .dev_name = "BCM583xx/11360", 2172 .vlans = 4096, 2173 .enabled_ports = 0x103, 2174 .arl_entries = 4, 2175 .cpu_port = B53_CPU_PORT, 2176 .vta_regs = B53_VTA_REGS, 2177 .duplex_reg = B53_DUPLEX_STAT_GE, 2178 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2179 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2180 }, 2181 { 2182 .chip_id = BCM7445_DEVICE_ID, 2183 .dev_name = "BCM7445", 2184 .vlans = 4096, 2185 .enabled_ports = 0x1ff, 2186 .arl_entries = 4, 2187 .cpu_port = B53_CPU_PORT, 2188 .vta_regs = B53_VTA_REGS, 2189 .duplex_reg = B53_DUPLEX_STAT_GE, 2190 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2191 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2192 }, 2193 { 2194 .chip_id = BCM7278_DEVICE_ID, 2195 .dev_name = "BCM7278", 2196 .vlans = 4096, 2197 .enabled_ports = 0x1ff, 2198 .arl_entries= 4, 2199 .cpu_port = B53_CPU_PORT, 2200 .vta_regs = B53_VTA_REGS, 2201 .duplex_reg = B53_DUPLEX_STAT_GE, 2202 .jumbo_pm_reg = B53_JUMBO_PORT_MASK, 2203 .jumbo_size_reg = B53_JUMBO_MAX_SIZE, 2204 }, 2205 }; 2206 2207 static int b53_switch_init(struct b53_device *dev) 2208 { 2209 unsigned int i; 2210 int ret; 2211 2212 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { 2213 const struct b53_chip_data *chip = &b53_switch_chips[i]; 2214 2215 if (chip->chip_id == dev->chip_id) { 2216 if (!dev->enabled_ports) 2217 dev->enabled_ports = chip->enabled_ports; 2218 dev->name = chip->dev_name; 2219 dev->duplex_reg = chip->duplex_reg; 2220 dev->vta_regs[0] = chip->vta_regs[0]; 2221 dev->vta_regs[1] = chip->vta_regs[1]; 2222 dev->vta_regs[2] = chip->vta_regs[2]; 2223 dev->jumbo_pm_reg = chip->jumbo_pm_reg; 2224 dev->cpu_port = chip->cpu_port; 2225 dev->num_vlans = chip->vlans; 2226 dev->num_arl_entries = chip->arl_entries; 2227 break; 2228 } 2229 } 2230 2231 /* check which BCM5325x version we have */ 2232 if (is5325(dev)) { 2233 u8 vc4; 2234 2235 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); 2236 2237 /* check reserved bits */ 2238 switch (vc4 & 3) { 2239 case 1: 2240 /* BCM5325E */ 2241 break; 2242 case 3: 2243 /* BCM5325F - do not use port 4 */ 2244 dev->enabled_ports &= ~BIT(4); 2245 break; 2246 default: 2247 /* On the BCM47XX SoCs this is the supported internal switch.*/ 2248 #ifndef CONFIG_BCM47XX 2249 /* BCM5325M */ 2250 return -EINVAL; 2251 #else 2252 break; 2253 #endif 2254 } 2255 } else if (dev->chip_id == BCM53115_DEVICE_ID) { 2256 u64 strap_value; 2257 2258 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); 2259 /* use second IMP port if GMII is enabled */ 2260 if (strap_value & SV_GMII_CTRL_115) 2261 dev->cpu_port = 5; 2262 } 2263 2264 /* cpu port is always last */ 2265 dev->num_ports = dev->cpu_port + 1; 2266 dev->enabled_ports |= BIT(dev->cpu_port); 2267 2268 /* Include non standard CPU port built-in PHYs to be probed */ 2269 if (is539x(dev) || is531x5(dev)) { 2270 for (i = 0; i < dev->num_ports; i++) { 2271 if (!(dev->ds->phys_mii_mask & BIT(i)) && 2272 !b53_possible_cpu_port(dev->ds, i)) 2273 dev->ds->phys_mii_mask |= BIT(i); 2274 } 2275 } 2276 2277 dev->ports = devm_kcalloc(dev->dev, 2278 dev->num_ports, sizeof(struct b53_port), 2279 GFP_KERNEL); 2280 if (!dev->ports) 2281 return -ENOMEM; 2282 2283 dev->vlans = devm_kcalloc(dev->dev, 2284 dev->num_vlans, sizeof(struct b53_vlan), 2285 GFP_KERNEL); 2286 if (!dev->vlans) 2287 return -ENOMEM; 2288 2289 dev->reset_gpio = b53_switch_get_reset_gpio(dev); 2290 if (dev->reset_gpio >= 0) { 2291 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, 2292 GPIOF_OUT_INIT_HIGH, "robo_reset"); 2293 if (ret) 2294 return ret; 2295 } 2296 2297 return 0; 2298 } 2299 2300 struct b53_device *b53_switch_alloc(struct device *base, 2301 const struct b53_io_ops *ops, 2302 void *priv) 2303 { 2304 struct dsa_switch *ds; 2305 struct b53_device *dev; 2306 2307 ds = dsa_switch_alloc(base, DSA_MAX_PORTS); 2308 if (!ds) 2309 return NULL; 2310 2311 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); 2312 if (!dev) 2313 return NULL; 2314 2315 ds->priv = dev; 2316 dev->dev = base; 2317 2318 dev->ds = ds; 2319 dev->priv = priv; 2320 dev->ops = ops; 2321 ds->ops = &b53_switch_ops; 2322 mutex_init(&dev->reg_mutex); 2323 mutex_init(&dev->stats_mutex); 2324 2325 return dev; 2326 } 2327 EXPORT_SYMBOL(b53_switch_alloc); 2328 2329 int b53_switch_detect(struct b53_device *dev) 2330 { 2331 u32 id32; 2332 u16 tmp; 2333 u8 id8; 2334 int ret; 2335 2336 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); 2337 if (ret) 2338 return ret; 2339 2340 switch (id8) { 2341 case 0: 2342 /* BCM5325 and BCM5365 do not have this register so reads 2343 * return 0. But the read operation did succeed, so assume this 2344 * is one of them. 2345 * 2346 * Next check if we can write to the 5325's VTA register; for 2347 * 5365 it is read only. 2348 */ 2349 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); 2350 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); 2351 2352 if (tmp == 0xf) 2353 dev->chip_id = BCM5325_DEVICE_ID; 2354 else 2355 dev->chip_id = BCM5365_DEVICE_ID; 2356 break; 2357 case BCM5389_DEVICE_ID: 2358 case BCM5395_DEVICE_ID: 2359 case BCM5397_DEVICE_ID: 2360 case BCM5398_DEVICE_ID: 2361 dev->chip_id = id8; 2362 break; 2363 default: 2364 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); 2365 if (ret) 2366 return ret; 2367 2368 switch (id32) { 2369 case BCM53115_DEVICE_ID: 2370 case BCM53125_DEVICE_ID: 2371 case BCM53128_DEVICE_ID: 2372 case BCM53010_DEVICE_ID: 2373 case BCM53011_DEVICE_ID: 2374 case BCM53012_DEVICE_ID: 2375 case BCM53018_DEVICE_ID: 2376 case BCM53019_DEVICE_ID: 2377 dev->chip_id = id32; 2378 break; 2379 default: 2380 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", 2381 id8, id32); 2382 return -ENODEV; 2383 } 2384 } 2385 2386 if (dev->chip_id == BCM5325_DEVICE_ID) 2387 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, 2388 &dev->core_rev); 2389 else 2390 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, 2391 &dev->core_rev); 2392 } 2393 EXPORT_SYMBOL(b53_switch_detect); 2394 2395 int b53_switch_register(struct b53_device *dev) 2396 { 2397 int ret; 2398 2399 if (dev->pdata) { 2400 dev->chip_id = dev->pdata->chip_id; 2401 dev->enabled_ports = dev->pdata->enabled_ports; 2402 } 2403 2404 if (!dev->chip_id && b53_switch_detect(dev)) 2405 return -EINVAL; 2406 2407 ret = b53_switch_init(dev); 2408 if (ret) 2409 return ret; 2410 2411 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev); 2412 2413 return dsa_register_switch(dev->ds); 2414 } 2415 EXPORT_SYMBOL(b53_switch_register); 2416 2417 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>"); 2418 MODULE_DESCRIPTION("B53 switch library"); 2419 MODULE_LICENSE("Dual BSD/GPL"); 2420